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Revert "UBUNTU: SAUCE: change power control driver to acpi driver"
[mirror_ubuntu-jammy-kernel.git] / drivers / media / i2c / ov01a1s.c
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020-2021 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include "power_ctrl_logic.h"
14
15 #define OV01A1S_LINK_FREQ_400MHZ 400000000ULL
16 #define OV01A1S_SCLK 40000000LL
17 #define OV01A1S_MCLK 19200000
18 #define OV01A1S_DATA_LANES 1
19 #define OV01A1S_RGB_DEPTH 10
20
21 #define OV01A1S_REG_CHIP_ID 0x300a
22 #define OV01A1S_CHIP_ID 0x560141
23
24 #define OV01A1S_REG_MODE_SELECT 0x0100
25 #define OV01A1S_MODE_STANDBY 0x00
26 #define OV01A1S_MODE_STREAMING 0x01
27
28 /* vertical-timings from sensor */
29 #define OV01A1S_REG_VTS 0x380e
30 #define OV01A1S_VTS_DEF 0x0380
31 #define OV01A1S_VTS_MIN 0x0380
32 #define OV01A1S_VTS_MAX 0xffff
33
34 /* Exposure controls from sensor */
35 #define OV01A1S_REG_EXPOSURE 0x3501
36 #define OV01A1S_EXPOSURE_MIN 4
37 #define OV01A1S_EXPOSURE_MAX_MARGIN 8
38 #define OV01A1S_EXPOSURE_STEP 1
39
40 /* Analog gain controls from sensor */
41 #define OV01A1S_REG_ANALOG_GAIN 0x3508
42 #define OV01A1S_ANAL_GAIN_MIN 0x100
43 #define OV01A1S_ANAL_GAIN_MAX 0xffff
44 #define OV01A1S_ANAL_GAIN_STEP 1
45
46 /* Digital gain controls from sensor */
47 #define OV01A1S_REG_DIGILAL_GAIN_B 0x350A
48 #define OV01A1S_REG_DIGITAL_GAIN_GB 0x3510
49 #define OV01A1S_REG_DIGITAL_GAIN_GR 0x3513
50 #define OV01A1S_REG_DIGITAL_GAIN_R 0x3516
51 #define OV01A1S_DGTL_GAIN_MIN 0
52 #define OV01A1S_DGTL_GAIN_MAX 0x3ffff
53 #define OV01A1S_DGTL_GAIN_STEP 1
54 #define OV01A1S_DGTL_GAIN_DEFAULT 1024
55
56 /* Test Pattern Control */
57 #define OV01A1S_REG_TEST_PATTERN 0x4503
58 #define OV01A1S_TEST_PATTERN_ENABLE BIT(7)
59 #define OV01A1S_TEST_PATTERN_BAR_SHIFT 0
60
61 enum {
62 OV01A1S_LINK_FREQ_400MHZ_INDEX,
63 };
64
65 struct ov01a1s_reg {
66 u16 address;
67 u8 val;
68 };
69
70 struct ov01a1s_reg_list {
71 u32 num_of_regs;
72 const struct ov01a1s_reg *regs;
73 };
74
75 struct ov01a1s_link_freq_config {
76 const struct ov01a1s_reg_list reg_list;
77 };
78
79 struct ov01a1s_mode {
80 /* Frame width in pixels */
81 u32 width;
82
83 /* Frame height in pixels */
84 u32 height;
85
86 /* Horizontal timining size */
87 u32 hts;
88
89 /* Default vertical timining size */
90 u32 vts_def;
91
92 /* Min vertical timining size */
93 u32 vts_min;
94
95 /* Link frequency needed for this resolution */
96 u32 link_freq_index;
97
98 /* Sensor register settings for this resolution */
99 const struct ov01a1s_reg_list reg_list;
100 };
101
102 static const struct ov01a1s_reg mipi_data_rate_720mbps[] = {
103 };
104
105 static const struct ov01a1s_reg sensor_1296x800_setting[] = {
106 {0x0103, 0x01},
107 {0x0302, 0x00},
108 {0x0303, 0x06},
109 {0x0304, 0x01},
110 {0x0305, 0x90},
111 {0x0306, 0x00},
112 {0x0308, 0x01},
113 {0x0309, 0x00},
114 {0x030c, 0x01},
115 {0x0322, 0x01},
116 {0x0323, 0x06},
117 {0x0324, 0x01},
118 {0x0325, 0x68},
119 {0x3002, 0xa1},
120 {0x301e, 0xf0},
121 {0x3022, 0x01},
122 {0x3501, 0x03},
123 {0x3502, 0x78},
124 {0x3504, 0x0c},
125 {0x3508, 0x01},
126 {0x3509, 0x00},
127 {0x3601, 0xc0},
128 {0x3603, 0x71},
129 {0x3610, 0x68},
130 {0x3611, 0x86},
131 {0x3640, 0x10},
132 {0x3641, 0x80},
133 {0x3642, 0xdc},
134 {0x3646, 0x55},
135 {0x3647, 0x57},
136 {0x364b, 0x00},
137 {0x3653, 0x10},
138 {0x3655, 0x00},
139 {0x3656, 0x00},
140 {0x365f, 0x0f},
141 {0x3661, 0x45},
142 {0x3662, 0x24},
143 {0x3663, 0x11},
144 {0x3664, 0x07},
145 {0x3709, 0x34},
146 {0x370b, 0x6f},
147 {0x3714, 0x22},
148 {0x371b, 0x27},
149 {0x371c, 0x67},
150 {0x371d, 0xa7},
151 {0x371e, 0xe7},
152 {0x3730, 0x81},
153 {0x3733, 0x10},
154 {0x3734, 0x40},
155 {0x3737, 0x04},
156 {0x3739, 0x1c},
157 {0x3767, 0x00},
158 {0x376c, 0x81},
159 {0x3772, 0x14},
160 {0x37c2, 0x04},
161 {0x37d8, 0x03},
162 {0x37d9, 0x0c},
163 {0x37e0, 0x00},
164 {0x37e1, 0x08},
165 {0x37e2, 0x10},
166 {0x37e3, 0x04},
167 {0x37e4, 0x04},
168 {0x37e5, 0x03},
169 {0x37e6, 0x04},
170 {0x3800, 0x00},
171 {0x3801, 0x00},
172 {0x3802, 0x00},
173 {0x3803, 0x00},
174 {0x3804, 0x05},
175 {0x3805, 0x0f},
176 {0x3806, 0x03},
177 {0x3807, 0x2f},
178 {0x3808, 0x05},
179 {0x3809, 0x00},
180 {0x380a, 0x03},
181 {0x380b, 0x1e},
182 {0x380c, 0x05},
183 {0x380d, 0xd0},
184 {0x380e, 0x03},
185 {0x380f, 0x80},
186 {0x3810, 0x00},
187 {0x3811, 0x09},
188 {0x3812, 0x00},
189 {0x3813, 0x08},
190 {0x3814, 0x01},
191 {0x3815, 0x01},
192 {0x3816, 0x01},
193 {0x3817, 0x01},
194 {0x3820, 0xa8},
195 {0x3822, 0x03},
196 {0x3832, 0x28},
197 {0x3833, 0x10},
198 {0x3b00, 0x00},
199 {0x3c80, 0x00},
200 {0x3c88, 0x02},
201 {0x3c8c, 0x07},
202 {0x3c8d, 0x40},
203 {0x3cc7, 0x80},
204 {0x4000, 0xc3},
205 {0x4001, 0xe0},
206 {0x4003, 0x40},
207 {0x4008, 0x02},
208 {0x4009, 0x19},
209 {0x400a, 0x01},
210 {0x400b, 0x6c},
211 {0x4011, 0x00},
212 {0x4041, 0x00},
213 {0x4300, 0xff},
214 {0x4301, 0x00},
215 {0x4302, 0x0f},
216 {0x4503, 0x00},
217 {0x4601, 0x50},
218 {0x481f, 0x34},
219 {0x4825, 0x33},
220 {0x4837, 0x14},
221 {0x4881, 0x40},
222 {0x4883, 0x01},
223 {0x4890, 0x00},
224 {0x4901, 0x00},
225 {0x4902, 0x00},
226 {0x4b00, 0x2a},
227 {0x4b0d, 0x00},
228 {0x450a, 0x04},
229 {0x450b, 0x00},
230 {0x5000, 0x65},
231 {0x5004, 0x00},
232 {0x5080, 0x40},
233 {0x5200, 0x18},
234 {0x4837, 0x14},
235 {0x0305, 0xf4},
236 {0x0325, 0xc2},
237 {0x3808, 0x05},
238 {0x3809, 0x10},
239 {0x380a, 0x03},
240 {0x380b, 0x1e},
241 {0x3810, 0x00},
242 {0x3811, 0x00},
243 {0x3812, 0x00},
244 {0x3813, 0x09},
245 {0x3820, 0x88},
246 {0x373d, 0x24},
247 };
248
249 static const char * const ov01a1s_test_pattern_menu[] = {
250 "Disabled",
251 "Color Bar",
252 "Top-Bottom Darker Color Bar",
253 "Right-Left Darker Color Bar",
254 "Color Bar type 4",
255 };
256
257 static const s64 link_freq_menu_items[] = {
258 OV01A1S_LINK_FREQ_400MHZ,
259 };
260
261 static const struct ov01a1s_link_freq_config link_freq_configs[] = {
262 [OV01A1S_LINK_FREQ_400MHZ_INDEX] = {
263 .reg_list = {
264 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
265 .regs = mipi_data_rate_720mbps,
266 }
267 },
268 };
269
270 static const struct ov01a1s_mode supported_modes[] = {
271 {
272 .width = 1296,
273 .height = 798,
274 .hts = 1488,
275 .vts_def = OV01A1S_VTS_DEF,
276 .vts_min = OV01A1S_VTS_MIN,
277 .reg_list = {
278 .num_of_regs = ARRAY_SIZE(sensor_1296x800_setting),
279 .regs = sensor_1296x800_setting,
280 },
281 .link_freq_index = OV01A1S_LINK_FREQ_400MHZ_INDEX,
282 },
283 };
284
285 struct ov01a1s {
286 struct v4l2_subdev sd;
287 struct media_pad pad;
288 struct v4l2_ctrl_handler ctrl_handler;
289
290 /* V4L2 Controls */
291 struct v4l2_ctrl *link_freq;
292 struct v4l2_ctrl *pixel_rate;
293 struct v4l2_ctrl *vblank;
294 struct v4l2_ctrl *hblank;
295 struct v4l2_ctrl *exposure;
296
297 /* Current mode */
298 const struct ov01a1s_mode *cur_mode;
299
300 /* To serialize asynchronus callbacks */
301 struct mutex mutex;
302
303 /* Streaming on/off */
304 bool streaming;
305 };
306
307 static inline struct ov01a1s *to_ov01a1s(struct v4l2_subdev *subdev)
308 {
309 return container_of(subdev, struct ov01a1s, sd);
310 }
311
312 static int ov01a1s_read_reg(struct ov01a1s *ov01a1s, u16 reg, u16 len, u32 *val)
313 {
314 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
315 struct i2c_msg msgs[2];
316 u8 addr_buf[2];
317 u8 data_buf[4] = {0};
318 int ret = 0;
319
320 if (len > sizeof(data_buf))
321 return -EINVAL;
322
323 put_unaligned_be16(reg, addr_buf);
324 msgs[0].addr = client->addr;
325 msgs[0].flags = 0;
326 msgs[0].len = sizeof(addr_buf);
327 msgs[0].buf = addr_buf;
328 msgs[1].addr = client->addr;
329 msgs[1].flags = I2C_M_RD;
330 msgs[1].len = len;
331 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
332
333 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
334 if (ret != ARRAY_SIZE(msgs))
335 return ret < 0 ? ret : -EIO;
336
337 *val = get_unaligned_be32(data_buf);
338
339 return 0;
340 }
341
342 static int ov01a1s_write_reg(struct ov01a1s *ov01a1s, u16 reg, u16 len, u32 val)
343 {
344 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
345 u8 buf[6];
346 int ret = 0;
347
348 if (len > 4)
349 return -EINVAL;
350
351 put_unaligned_be16(reg, buf);
352 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
353
354 ret = i2c_master_send(client, buf, len + 2);
355 if (ret != len + 2)
356 return ret < 0 ? ret : -EIO;
357
358 return 0;
359 }
360
361 static int ov01a1s_write_reg_list(struct ov01a1s *ov01a1s,
362 const struct ov01a1s_reg_list *r_list)
363 {
364 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
365 unsigned int i;
366 int ret = 0;
367
368 for (i = 0; i < r_list->num_of_regs; i++) {
369 ret = ov01a1s_write_reg(ov01a1s, r_list->regs[i].address, 1,
370 r_list->regs[i].val);
371 if (ret) {
372 dev_err_ratelimited(&client->dev,
373 "write reg 0x%4.4x return err = %d",
374 r_list->regs[i].address, ret);
375 return ret;
376 }
377 }
378
379 return 0;
380 }
381
382 static int ov01a1s_update_digital_gain(struct ov01a1s *ov01a1s, u32 d_gain)
383 {
384 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
385 u32 real = d_gain << 6;
386 int ret = 0;
387
388 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGILAL_GAIN_B, 3, real);
389 if (ret) {
390 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_B");
391 return ret;
392 }
393 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGITAL_GAIN_GB, 3, real);
394 if (ret) {
395 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_GB");
396 return ret;
397 }
398 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGITAL_GAIN_GR, 3, real);
399 if (ret) {
400 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_GR");
401 return ret;
402 }
403
404 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_DIGITAL_GAIN_R, 3, real);
405 if (ret) {
406 dev_err(&client->dev, "failed to set OV01A1S_REG_DIGITAL_GAIN_R");
407 return ret;
408 }
409 return ret;
410 }
411
412 static int ov01a1s_test_pattern(struct ov01a1s *ov01a1s, u32 pattern)
413 {
414 if (pattern)
415 pattern = (pattern - 1) << OV01A1S_TEST_PATTERN_BAR_SHIFT |
416 OV01A1S_TEST_PATTERN_ENABLE;
417
418 return ov01a1s_write_reg(ov01a1s, OV01A1S_REG_TEST_PATTERN, 1, pattern);
419 }
420
421 static int ov01a1s_set_ctrl(struct v4l2_ctrl *ctrl)
422 {
423 struct ov01a1s *ov01a1s = container_of(ctrl->handler,
424 struct ov01a1s, ctrl_handler);
425 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
426 s64 exposure_max;
427 int ret = 0;
428
429 /* Propagate change of current control to all related controls */
430 if (ctrl->id == V4L2_CID_VBLANK) {
431 /* Update max exposure while meeting expected vblanking */
432 exposure_max = ov01a1s->cur_mode->height + ctrl->val -
433 OV01A1S_EXPOSURE_MAX_MARGIN;
434 __v4l2_ctrl_modify_range(ov01a1s->exposure,
435 ov01a1s->exposure->minimum,
436 exposure_max, ov01a1s->exposure->step,
437 exposure_max);
438 }
439
440 /* V4L2 controls values will be applied only when power is already up */
441 if (!pm_runtime_get_if_in_use(&client->dev))
442 return 0;
443
444 switch (ctrl->id) {
445 case V4L2_CID_ANALOGUE_GAIN:
446 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_ANALOG_GAIN, 2,
447 ctrl->val);
448 break;
449
450 case V4L2_CID_DIGITAL_GAIN:
451 ret = ov01a1s_update_digital_gain(ov01a1s, ctrl->val);
452 break;
453
454 case V4L2_CID_EXPOSURE:
455 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_EXPOSURE, 2,
456 ctrl->val);
457 break;
458
459 case V4L2_CID_VBLANK:
460 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_VTS, 2,
461 ov01a1s->cur_mode->height + ctrl->val);
462 break;
463
464 case V4L2_CID_TEST_PATTERN:
465 ret = ov01a1s_test_pattern(ov01a1s, ctrl->val);
466 break;
467
468 default:
469 ret = -EINVAL;
470 break;
471 }
472
473 pm_runtime_put(&client->dev);
474
475 return ret;
476 }
477
478 static const struct v4l2_ctrl_ops ov01a1s_ctrl_ops = {
479 .s_ctrl = ov01a1s_set_ctrl,
480 };
481
482 static int ov01a1s_init_controls(struct ov01a1s *ov01a1s)
483 {
484 struct v4l2_ctrl_handler *ctrl_hdlr;
485 const struct ov01a1s_mode *cur_mode;
486 s64 exposure_max, h_blank;
487 u32 vblank_min, vblank_max, vblank_default;
488 int size;
489 int ret = 0;
490
491 ctrl_hdlr = &ov01a1s->ctrl_handler;
492 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
493 if (ret)
494 return ret;
495
496 ctrl_hdlr->lock = &ov01a1s->mutex;
497 cur_mode = ov01a1s->cur_mode;
498 size = ARRAY_SIZE(link_freq_menu_items);
499
500 ov01a1s->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
501 &ov01a1s_ctrl_ops,
502 V4L2_CID_LINK_FREQ,
503 size - 1, 0,
504 link_freq_menu_items);
505 if (ov01a1s->link_freq)
506 ov01a1s->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
507
508 ov01a1s->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
509 V4L2_CID_PIXEL_RATE, 0,
510 OV01A1S_SCLK, 1, OV01A1S_SCLK);
511
512 vblank_min = cur_mode->vts_min - cur_mode->height;
513 vblank_max = OV01A1S_VTS_MAX - cur_mode->height;
514 vblank_default = cur_mode->vts_def - cur_mode->height;
515 ov01a1s->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
516 V4L2_CID_VBLANK, vblank_min,
517 vblank_max, 1, vblank_default);
518
519 h_blank = cur_mode->hts - cur_mode->width;
520 ov01a1s->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
521 V4L2_CID_HBLANK, h_blank, h_blank,
522 1, h_blank);
523 if (ov01a1s->hblank)
524 ov01a1s->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
525
526 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
527 OV01A1S_ANAL_GAIN_MIN, OV01A1S_ANAL_GAIN_MAX,
528 OV01A1S_ANAL_GAIN_STEP, OV01A1S_ANAL_GAIN_MIN);
529 v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
530 OV01A1S_DGTL_GAIN_MIN, OV01A1S_DGTL_GAIN_MAX,
531 OV01A1S_DGTL_GAIN_STEP, OV01A1S_DGTL_GAIN_DEFAULT);
532 exposure_max = cur_mode->vts_def - OV01A1S_EXPOSURE_MAX_MARGIN;
533 ov01a1s->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov01a1s_ctrl_ops,
534 V4L2_CID_EXPOSURE,
535 OV01A1S_EXPOSURE_MIN,
536 exposure_max,
537 OV01A1S_EXPOSURE_STEP,
538 exposure_max);
539 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov01a1s_ctrl_ops,
540 V4L2_CID_TEST_PATTERN,
541 ARRAY_SIZE(ov01a1s_test_pattern_menu) - 1,
542 0, 0, ov01a1s_test_pattern_menu);
543 if (ctrl_hdlr->error)
544 return ctrl_hdlr->error;
545
546 ov01a1s->sd.ctrl_handler = ctrl_hdlr;
547
548 return 0;
549 }
550
551 static void ov01a1s_update_pad_format(const struct ov01a1s_mode *mode,
552 struct v4l2_mbus_framefmt *fmt)
553 {
554 fmt->width = mode->width;
555 fmt->height = mode->height;
556 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
557 fmt->field = V4L2_FIELD_NONE;
558 }
559
560 static int ov01a1s_start_streaming(struct ov01a1s *ov01a1s)
561 {
562 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
563 const struct ov01a1s_reg_list *reg_list;
564 int link_freq_index;
565 int ret = 0;
566
567 power_ctrl_logic_set_power(1);
568 link_freq_index = ov01a1s->cur_mode->link_freq_index;
569 reg_list = &link_freq_configs[link_freq_index].reg_list;
570 ret = ov01a1s_write_reg_list(ov01a1s, reg_list);
571 if (ret) {
572 dev_err(&client->dev, "failed to set plls");
573 return ret;
574 }
575
576 reg_list = &ov01a1s->cur_mode->reg_list;
577 ret = ov01a1s_write_reg_list(ov01a1s, reg_list);
578 if (ret) {
579 dev_err(&client->dev, "failed to set mode");
580 return ret;
581 }
582
583 ret = __v4l2_ctrl_handler_setup(ov01a1s->sd.ctrl_handler);
584 if (ret)
585 return ret;
586
587 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_MODE_SELECT, 1,
588 OV01A1S_MODE_STREAMING);
589 if (ret)
590 dev_err(&client->dev, "failed to start streaming");
591
592 return ret;
593 }
594
595 static void ov01a1s_stop_streaming(struct ov01a1s *ov01a1s)
596 {
597 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
598 int ret = 0;
599
600 ret = ov01a1s_write_reg(ov01a1s, OV01A1S_REG_MODE_SELECT, 1,
601 OV01A1S_MODE_STANDBY);
602 if (ret)
603 dev_err(&client->dev, "failed to stop streaming");
604 power_ctrl_logic_set_power(0);
605 }
606
607 static int ov01a1s_set_stream(struct v4l2_subdev *sd, int enable)
608 {
609 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
610 struct i2c_client *client = v4l2_get_subdevdata(sd);
611 int ret = 0;
612
613 if (ov01a1s->streaming == enable)
614 return 0;
615
616 mutex_lock(&ov01a1s->mutex);
617 if (enable) {
618 ret = pm_runtime_get_sync(&client->dev);
619 if (ret < 0) {
620 pm_runtime_put_noidle(&client->dev);
621 mutex_unlock(&ov01a1s->mutex);
622 return ret;
623 }
624
625 ret = ov01a1s_start_streaming(ov01a1s);
626 if (ret) {
627 enable = 0;
628 ov01a1s_stop_streaming(ov01a1s);
629 pm_runtime_put(&client->dev);
630 }
631 } else {
632 ov01a1s_stop_streaming(ov01a1s);
633 pm_runtime_put(&client->dev);
634 }
635
636 ov01a1s->streaming = enable;
637 mutex_unlock(&ov01a1s->mutex);
638
639 return ret;
640 }
641
642 static int __maybe_unused ov01a1s_suspend(struct device *dev)
643 {
644 struct i2c_client *client = to_i2c_client(dev);
645 struct v4l2_subdev *sd = i2c_get_clientdata(client);
646 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
647
648 mutex_lock(&ov01a1s->mutex);
649 if (ov01a1s->streaming)
650 ov01a1s_stop_streaming(ov01a1s);
651
652 mutex_unlock(&ov01a1s->mutex);
653
654 return 0;
655 }
656
657 static int __maybe_unused ov01a1s_resume(struct device *dev)
658 {
659 struct i2c_client *client = to_i2c_client(dev);
660 struct v4l2_subdev *sd = i2c_get_clientdata(client);
661 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
662 int ret = 0;
663
664 mutex_lock(&ov01a1s->mutex);
665 if (!ov01a1s->streaming)
666 goto exit;
667
668 ret = ov01a1s_start_streaming(ov01a1s);
669 if (ret) {
670 ov01a1s->streaming = false;
671 ov01a1s_stop_streaming(ov01a1s);
672 }
673
674 exit:
675 mutex_unlock(&ov01a1s->mutex);
676 return ret;
677 }
678
679 static int ov01a1s_set_format(struct v4l2_subdev *sd,
680 struct v4l2_subdev_pad_config *cfg,
681 struct v4l2_subdev_format *fmt)
682 {
683 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
684 const struct ov01a1s_mode *mode;
685 s32 vblank_def, h_blank;
686
687 mode = v4l2_find_nearest_size(supported_modes,
688 ARRAY_SIZE(supported_modes), width,
689 height, fmt->format.width,
690 fmt->format.height);
691
692 mutex_lock(&ov01a1s->mutex);
693 ov01a1s_update_pad_format(mode, &fmt->format);
694 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
695 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
696 } else {
697 ov01a1s->cur_mode = mode;
698 __v4l2_ctrl_s_ctrl(ov01a1s->link_freq, mode->link_freq_index);
699 __v4l2_ctrl_s_ctrl_int64(ov01a1s->pixel_rate, OV01A1S_SCLK);
700
701 /* Update limits and set FPS to default */
702 vblank_def = mode->vts_def - mode->height;
703 __v4l2_ctrl_modify_range(ov01a1s->vblank,
704 mode->vts_min - mode->height,
705 OV01A1S_VTS_MAX - mode->height, 1,
706 vblank_def);
707 __v4l2_ctrl_s_ctrl(ov01a1s->vblank, vblank_def);
708 h_blank = mode->hts - mode->width;
709 __v4l2_ctrl_modify_range(ov01a1s->hblank, h_blank, h_blank, 1,
710 h_blank);
711 }
712 mutex_unlock(&ov01a1s->mutex);
713
714 return 0;
715 }
716
717 static int ov01a1s_get_format(struct v4l2_subdev *sd,
718 struct v4l2_subdev_pad_config *cfg,
719 struct v4l2_subdev_format *fmt)
720 {
721 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
722
723 mutex_lock(&ov01a1s->mutex);
724 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
725 fmt->format = *v4l2_subdev_get_try_format(&ov01a1s->sd, cfg,
726 fmt->pad);
727 else
728 ov01a1s_update_pad_format(ov01a1s->cur_mode, &fmt->format);
729
730 mutex_unlock(&ov01a1s->mutex);
731
732 return 0;
733 }
734
735 static int ov01a1s_enum_mbus_code(struct v4l2_subdev *sd,
736 struct v4l2_subdev_pad_config *cfg,
737 struct v4l2_subdev_mbus_code_enum *code)
738 {
739 if (code->index > 0)
740 return -EINVAL;
741
742 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
743
744 return 0;
745 }
746
747 static int ov01a1s_enum_frame_size(struct v4l2_subdev *sd,
748 struct v4l2_subdev_pad_config *cfg,
749 struct v4l2_subdev_frame_size_enum *fse)
750 {
751 if (fse->index >= ARRAY_SIZE(supported_modes))
752 return -EINVAL;
753
754 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
755 return -EINVAL;
756
757 fse->min_width = supported_modes[fse->index].width;
758 fse->max_width = fse->min_width;
759 fse->min_height = supported_modes[fse->index].height;
760 fse->max_height = fse->min_height;
761
762 return 0;
763 }
764
765 static int ov01a1s_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
766 {
767 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
768
769 mutex_lock(&ov01a1s->mutex);
770 ov01a1s_update_pad_format(&supported_modes[0],
771 v4l2_subdev_get_try_format(sd, fh->pad, 0));
772 mutex_unlock(&ov01a1s->mutex);
773
774 return 0;
775 }
776
777 static const struct v4l2_subdev_video_ops ov01a1s_video_ops = {
778 .s_stream = ov01a1s_set_stream,
779 };
780
781 static const struct v4l2_subdev_pad_ops ov01a1s_pad_ops = {
782 .set_fmt = ov01a1s_set_format,
783 .get_fmt = ov01a1s_get_format,
784 .enum_mbus_code = ov01a1s_enum_mbus_code,
785 .enum_frame_size = ov01a1s_enum_frame_size,
786 };
787
788 static const struct v4l2_subdev_ops ov01a1s_subdev_ops = {
789 .video = &ov01a1s_video_ops,
790 .pad = &ov01a1s_pad_ops,
791 };
792
793 static const struct media_entity_operations ov01a1s_subdev_entity_ops = {
794 .link_validate = v4l2_subdev_link_validate,
795 };
796
797 static const struct v4l2_subdev_internal_ops ov01a1s_internal_ops = {
798 .open = ov01a1s_open,
799 };
800
801 static int ov01a1s_identify_module(struct ov01a1s *ov01a1s)
802 {
803 struct i2c_client *client = v4l2_get_subdevdata(&ov01a1s->sd);
804 int ret;
805 u32 val;
806
807 ret = ov01a1s_read_reg(ov01a1s, OV01A1S_REG_CHIP_ID, 3, &val);
808 if (ret)
809 return ret;
810
811 if (val != OV01A1S_CHIP_ID) {
812 dev_err(&client->dev, "chip id mismatch: %x!=%x",
813 OV01A1S_CHIP_ID, val);
814 return -ENXIO;
815 }
816
817 return 0;
818 }
819
820 static int ov01a1s_remove(struct i2c_client *client)
821 {
822 struct v4l2_subdev *sd = i2c_get_clientdata(client);
823 struct ov01a1s *ov01a1s = to_ov01a1s(sd);
824
825 v4l2_async_unregister_subdev(sd);
826 media_entity_cleanup(&sd->entity);
827 v4l2_ctrl_handler_free(sd->ctrl_handler);
828 pm_runtime_disable(&client->dev);
829 mutex_destroy(&ov01a1s->mutex);
830
831 return 0;
832 }
833
834 static int ov01a1s_probe(struct i2c_client *client)
835 {
836 struct ov01a1s *ov01a1s;
837 int ret = 0;
838
839 ov01a1s = devm_kzalloc(&client->dev, sizeof(*ov01a1s), GFP_KERNEL);
840 if (!ov01a1s)
841 return -ENOMEM;
842
843 v4l2_i2c_subdev_init(&ov01a1s->sd, client, &ov01a1s_subdev_ops);
844 power_ctrl_logic_set_power(0);
845 power_ctrl_logic_set_power(1);
846 ret = ov01a1s_identify_module(ov01a1s);
847 if (ret) {
848 dev_err(&client->dev, "failed to find sensor: %d", ret);
849 return ret;
850 }
851
852 mutex_init(&ov01a1s->mutex);
853 ov01a1s->cur_mode = &supported_modes[0];
854 ret = ov01a1s_init_controls(ov01a1s);
855 if (ret) {
856 dev_err(&client->dev, "failed to init controls: %d", ret);
857 goto probe_error_v4l2_ctrl_handler_free;
858 }
859
860 ov01a1s->sd.internal_ops = &ov01a1s_internal_ops;
861 ov01a1s->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
862 ov01a1s->sd.entity.ops = &ov01a1s_subdev_entity_ops;
863 ov01a1s->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
864 ov01a1s->pad.flags = MEDIA_PAD_FL_SOURCE;
865 ret = media_entity_pads_init(&ov01a1s->sd.entity, 1, &ov01a1s->pad);
866 if (ret) {
867 dev_err(&client->dev, "failed to init entity pads: %d", ret);
868 goto probe_error_v4l2_ctrl_handler_free;
869 }
870
871 ret = v4l2_async_register_subdev_sensor_common(&ov01a1s->sd);
872 if (ret < 0) {
873 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
874 ret);
875 goto probe_error_media_entity_cleanup;
876 }
877
878 /*
879 * Device is already turned on by i2c-core with ACPI domain PM.
880 * Enable runtime PM and turn off the device.
881 */
882 pm_runtime_set_active(&client->dev);
883 pm_runtime_enable(&client->dev);
884 pm_runtime_idle(&client->dev);
885
886 power_ctrl_logic_set_power(0);
887 return 0;
888
889 probe_error_media_entity_cleanup:
890 media_entity_cleanup(&ov01a1s->sd.entity);
891
892 probe_error_v4l2_ctrl_handler_free:
893 v4l2_ctrl_handler_free(ov01a1s->sd.ctrl_handler);
894 mutex_destroy(&ov01a1s->mutex);
895
896 return ret;
897 }
898
899 static const struct dev_pm_ops ov01a1s_pm_ops = {
900 SET_SYSTEM_SLEEP_PM_OPS(ov01a1s_suspend, ov01a1s_resume)
901 };
902
903 #ifdef CONFIG_ACPI
904 static const struct acpi_device_id ov01a1s_acpi_ids[] = {
905 { "OVTI01AS" },
906 {}
907 };
908
909 MODULE_DEVICE_TABLE(acpi, ov01a1s_acpi_ids);
910 #endif
911
912 static struct i2c_driver ov01a1s_i2c_driver = {
913 .driver = {
914 .name = "ov01a1s",
915 .pm = &ov01a1s_pm_ops,
916 .acpi_match_table = ACPI_PTR(ov01a1s_acpi_ids),
917 },
918 .probe_new = ov01a1s_probe,
919 .remove = ov01a1s_remove,
920 };
921
922 module_i2c_driver(ov01a1s_i2c_driver);
923
924 MODULE_AUTHOR("Xu, Chongyang <chongyang.xu@intel.com>");
925 MODULE_AUTHOR("Lai, Jim <jim.lai@intel.com>");
926 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
927 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
928 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
929 MODULE_DESCRIPTION("OmniVision OV01A1S sensor driver");
930 MODULE_LICENSE("GPL v2");
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