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UBUNTU: SAUCE: IPU6: 2022-03-11 alpha release for Andrews MLK
[mirror_ubuntu-jammy-kernel.git] / drivers / media / i2c / ov02c10.c
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/version.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-fwnode.h>
14 #include <linux/vsc.h>
15
16 #define OV02C10_LINK_FREQ_400MHZ 400000000ULL
17 #define OV02C10_SCLK 80000000LL
18 #define OV02C10_MCLK 19200000
19 #define OV02C10_DATA_LANES 1
20 #define OV02C10_RGB_DEPTH 10
21
22 #define OV02C10_REG_CHIP_ID 0x300a
23 #define OV02C10_CHIP_ID 0x560243
24
25 #define OV02C10_REG_MODE_SELECT 0x0100
26 #define OV02C10_MODE_STANDBY 0x00
27 #define OV02C10_MODE_STREAMING 0x01
28
29 /* vertical-timings from sensor */
30 #define OV02C10_REG_VTS 0x380e
31 #define OV02C10_VTS_DEF 0x048c
32 #define OV02C10_VTS_MIN 0x048c
33 #define OV02C10_VTS_MAX 0x7fff
34
35 /* Exposure controls from sensor */
36 #define OV02C10_REG_EXPOSURE 0x3501
37 #define OV02C10_EXPOSURE_MIN 4
38 #define OV02C10_EXPOSURE_MAX_MARGIN 8
39 #define OV02C10_EXPOSURE_STEP 1
40
41 /* Analog gain controls from sensor */
42 #define OV02C10_REG_ANALOG_GAIN 0x3508
43 #define OV02C10_ANAL_GAIN_MIN 0x10
44 #define OV02C10_ANAL_GAIN_MAX 0xf8
45 #define OV02C10_ANAL_GAIN_STEP 1
46 #define OV02C10_ANAL_GAIN_DEFAULT 0x80
47
48 /* Digital gain controls from sensor */
49 #define OV02C10_REG_DIGILAL_GAIN 0x350a
50 #define OV02C10_DGTL_GAIN_MIN 0x0400
51 #define OV02C10_DGTL_GAIN_MAX 0x3fff
52 #define OV02C10_DGTL_GAIN_STEP 1
53 #define OV02C10_DGTL_GAIN_DEFAULT 0x0400
54
55 /* Test Pattern Control */
56 #define OV02C10_REG_TEST_PATTERN 0x4503
57 #define OV02C10_TEST_PATTERN_ENABLE BIT(7)
58 #define OV02C10_TEST_PATTERN_BAR_SHIFT 0
59
60 enum {
61 OV02C10_LINK_FREQ_400MHZ_INDEX,
62 };
63
64 struct ov02c10_reg {
65 u16 address;
66 u8 val;
67 };
68
69 struct ov02c10_reg_list {
70 u32 num_of_regs;
71 const struct ov02c10_reg *regs;
72 };
73
74 struct ov02c10_link_freq_config {
75 const struct ov02c10_reg_list reg_list;
76 };
77
78 struct ov02c10_mode {
79 /* Frame width in pixels */
80 u32 width;
81
82 /* Frame height in pixels */
83 u32 height;
84
85 /* Horizontal timining size */
86 u32 hts;
87
88 /* Default vertical timining size */
89 u32 vts_def;
90
91 /* Min vertical timining size */
92 u32 vts_min;
93
94 /* Link frequency needed for this resolution */
95 u32 link_freq_index;
96
97 /* Sensor register settings for this resolution */
98 const struct ov02c10_reg_list reg_list;
99 };
100
101 static const struct ov02c10_reg mipi_data_rate_960mbps[] = {
102 };
103
104 static const struct ov02c10_reg sensor_1932x1092_1lane_30fps_setting[] = {
105 // 1932x1092_GRBG_MIPI_MCLK19.2MHz_30fps_1Lane
106 {0x0301, 0x08},
107 // {0x0303, 0x06},
108 {0x0304, 0x01},
109 // {0x0305, 0xe0},
110 {0x0313, 0x40},
111 {0x031c, 0x4f},
112 {0x301b, 0xd2},
113 {0x3020, 0x97},
114 {0x3022, 0x01},
115 {0x3026, 0xb4},
116 {0x3027, 0xe1},
117 {0x303b, 0x00},
118 {0x303c, 0x4f},
119 {0x303d, 0xe6},
120 {0x303e, 0x00},
121 {0x303f, 0x03},
122 {0x3021, 0x23},
123 {0x3501, 0x04},
124 {0x3502, 0x6c},
125 {0x3504, 0x0c},
126 {0x3507, 0x00},
127 {0x3508, 0x08},
128 {0x3509, 0x00},
129 {0x350a, 0x01},
130 {0x350b, 0x00},
131 {0x350c, 0x41},
132 {0x3600, 0x84},
133 {0x3611, 0x1b},
134 {0x3613, 0x78},
135 {0x3623, 0x00},
136 {0x3632, 0xa0},
137 {0x3642, 0xe8},
138 {0x364c, 0x70},
139 {0x365f, 0x0f},
140 {0x3708, 0x30},
141 {0x3714, 0x24},
142 {0x3725, 0x02},
143 {0x3737, 0x08},
144 {0x3739, 0x28},
145 {0x3749, 0x32},
146 {0x374a, 0x32},
147 {0x374b, 0x32},
148 {0x374c, 0x32},
149 {0x374d, 0x81},
150 {0x374e, 0x81},
151 {0x374f, 0x81},
152 {0x3752, 0x36},
153 {0x3753, 0x36},
154 {0x3754, 0x36},
155 {0x3761, 0x00},
156 {0x376c, 0x81},
157 {0x377c, 0x81},
158 {0x377d, 0x81},
159 {0x377e, 0x81},
160 {0x37a0, 0x44},
161 {0x37a6, 0x44},
162 {0x37aa, 0x0d},
163 {0x37ae, 0x00},
164 {0x37cb, 0x03},
165 {0x37cc, 0x01},
166 {0x37d8, 0x02},
167 {0x37d9, 0x10},
168 {0x37e1, 0x10},
169 {0x37e2, 0x18},
170 {0x37e3, 0x08},
171 {0x37e4, 0x08},
172 {0x37e5, 0x02},
173 {0x37e6, 0x08},
174 {0x3800, 0x00},
175 {0x3801, 0x00},
176 {0x3802, 0x00},
177 // {0x3803, 0x04},
178 // {0x3804, 0x07},
179 // {0x3805, 0x8f},
180 // {0x3806, 0x04},
181 // {0x3807, 0x43},
182 // {0x3808, 0x07},
183 // {0x3809, 0x80},
184 // {0x380a, 0x04},
185 // {0x380b, 0x38},
186 // {0x380c, 0x04},
187 // {0x380d, 0x74},
188 // {0x380e, 0x04},
189 // {0x380f, 0x8c},
190 // {0x3810, 0x00},
191 // {0x3811, 0x07},
192 // {0x3812, 0x00},
193 // {0x3813, 0x04},
194 {0x3814, 0x01},
195 {0x3815, 0x01},
196 {0x3816, 0x01},
197 {0x3817, 0x01},
198 {0x3820, 0xa8},
199 {0x3821, 0x00},
200 {0x3822, 0x80},
201 {0x3823, 0x08},
202 {0x3824, 0x00},
203 {0x3825, 0x20},
204 {0x3826, 0x00},
205 {0x3827, 0x08},
206 {0x382a, 0x00},
207 {0x382b, 0x08},
208 {0x382d, 0x00},
209 {0x382e, 0x00},
210 {0x382f, 0x23},
211 {0x3834, 0x00},
212 {0x3839, 0x00},
213 {0x383a, 0xd1},
214 {0x383e, 0x03},
215 {0x393d, 0x29},
216 {0x393f, 0x6e},
217 {0x394b, 0x01},
218 {0x394c, 0x01},
219 {0x394d, 0x01},
220 {0x394e, 0x01},
221 {0x394f, 0x01},
222 {0x3950, 0x01},
223 {0x3951, 0x01},
224 {0x3952, 0x01},
225 {0x3953, 0x01},
226 {0x3954, 0x01},
227 {0x3955, 0x01},
228 {0x3956, 0x01},
229 {0x3957, 0x0e},
230 {0x3958, 0x08},
231 {0x3959, 0x08},
232 {0x395a, 0x08},
233 {0x395b, 0x00},
234 {0x395c, 0x00},
235 {0x395d, 0x00},
236 {0x395e, 0x00},
237 {0x395f, 0x00},
238 {0x395f, 0x00},
239 {0x3960, 0x00},
240 {0x3961, 0x00},
241 {0x3962, 0x00},
242 {0x3963, 0x00},
243 {0x3964, 0x00},
244 {0x3965, 0x00},
245 {0x3966, 0x00},
246 {0x3967, 0x00},
247 {0x3968, 0x01},
248 {0x3969, 0x01},
249 {0x396a, 0x01},
250 {0x396b, 0x01},
251 {0x396c, 0x00},
252 {0x396d, 0xf0},
253 {0x396e, 0x11},
254 {0x396f, 0x00},
255 {0x3970, 0x37},
256 {0x3971, 0x37},
257 {0x3972, 0x37},
258 {0x3973, 0x37},
259 {0x3974, 0x00},
260 {0x3975, 0x3c},
261 {0x3976, 0x3c},
262 {0x3977, 0x3c},
263 {0x3978, 0x3c},
264 {0x3c00, 0x0f},
265 {0x3c20, 0x01},
266 {0x3c21, 0x08},
267 {0x3f00, 0x8b},
268 {0x3f02, 0x0f},
269 {0x4000, 0xc3},
270 {0x4001, 0xe0},
271 {0x4002, 0x00},
272 {0x4003, 0x40},
273 {0x4008, 0x04},
274 {0x4009, 0x23},
275 {0x400a, 0x04},
276 {0x400b, 0x01},
277 {0x4077, 0x06},
278 {0x4078, 0x00},
279 {0x4079, 0x1a},
280 {0x407a, 0x7f},
281 {0x407b, 0x01},
282 {0x4080, 0x03},
283 {0x4081, 0x84},
284 {0x4308, 0x03},
285 {0x4309, 0xff},
286 {0x430d, 0x00},
287 {0x4806, 0x00},
288 {0x4813, 0x00},
289 {0x4837, 0x10},
290 {0x4857, 0x05},
291 {0x4500, 0x07},
292 {0x4501, 0x00},
293 {0x4503, 0x00},
294 {0x450a, 0x04},
295 {0x450e, 0x00},
296 {0x450f, 0x00},
297 {0x4800, 0x24},
298 {0x4900, 0x00},
299 {0x4901, 0x00},
300 {0x4902, 0x01},
301 {0x5000, 0xf5},
302 {0x5001, 0x50},
303 {0x5006, 0x00},
304 {0x5080, 0x40},
305 {0x5181, 0x2b},
306 {0x5202, 0xa3},
307 {0x5206, 0x01},
308 {0x5207, 0x00},
309 {0x520a, 0x01},
310 {0x520b, 0x00},
311 // {0x3016, 0x32},
312 {0x365d, 0x00},
313 {0x4815, 0x40},
314 {0x4816, 0x12},
315 {0x4f00, 0x01},
316 {0x396c, 0x10},
317 {0x3603, 0x08},
318 {0x395b, 0x13},
319 {0x395c, 0x09},
320 {0x395d, 0x05},
321 {0x395e, 0x02},
322 {0x3610, 0x57},
323 {0x394e, 0x0b},
324 {0x394d, 0x08},
325 {0x394c, 0x06},
326 {0x394b, 0x06},
327 // key setting for MCLK=19.2MCLK 1932x1092 GRBG 1 lane 30fps
328 {0x0303, 0x05},
329 {0x0305, 0x90},
330 {0x0316, 0x90},
331 {0x3016, 0x12},
332 {0x3803, 0x00},
333 {0x3804, 0x07},
334 {0x3805, 0x8f},
335 {0x3806, 0x04},
336 {0x3807, 0x47},
337 {0x3808, 0x07},
338 {0x3809, 0x8c},
339 {0x380a, 0x04},
340 {0x380b, 0x44},
341 {0x380c, 0x08},
342 {0x380d, 0xe8},
343 {0x380e, 0x04},
344 {0x380f, 0x8c},
345 {0x3810, 0x00},
346 {0x3811, 0x03},
347 {0x3812, 0x00},
348 {0x3813, 0x03},
349 };
350
351 static const char * const ov02c10_test_pattern_menu[] = {
352 "Disabled",
353 "Color Bar",
354 "Top-Bottom Darker Color Bar",
355 "Right-Left Darker Color Bar",
356 "Color Bar type 4",
357 };
358
359 static const s64 link_freq_menu_items[] = {
360 OV02C10_LINK_FREQ_400MHZ,
361 };
362
363 static const struct ov02c10_link_freq_config link_freq_configs[] = {
364 [OV02C10_LINK_FREQ_400MHZ_INDEX] = {
365 .reg_list = {
366 .num_of_regs = ARRAY_SIZE(mipi_data_rate_960mbps),
367 .regs = mipi_data_rate_960mbps,
368 }
369 },
370 };
371
372 static const struct ov02c10_mode supported_modes[] = {
373 {
374 .width = 1932,
375 .height = 1092,
376 .hts = 2280,
377 .vts_def = OV02C10_VTS_DEF,
378 .vts_min = OV02C10_VTS_MIN,
379 .reg_list = {
380 .num_of_regs = ARRAY_SIZE(sensor_1932x1092_1lane_30fps_setting),
381 .regs = sensor_1932x1092_1lane_30fps_setting,
382 },
383 .link_freq_index = OV02C10_LINK_FREQ_400MHZ_INDEX,
384 },
385 };
386
387 struct ov02c10 {
388 struct v4l2_subdev sd;
389 struct media_pad pad;
390 struct v4l2_ctrl_handler ctrl_handler;
391
392 /* V4L2 Controls */
393 struct v4l2_ctrl *link_freq;
394 struct v4l2_ctrl *pixel_rate;
395 struct v4l2_ctrl *vblank;
396 struct v4l2_ctrl *hblank;
397 struct v4l2_ctrl *exposure;
398 struct v4l2_ctrl *privacy_status;
399 /* Current mode */
400 const struct ov02c10_mode *cur_mode;
401
402 /* To serialize asynchronus callbacks */
403 struct mutex mutex;
404
405 /* Streaming on/off */
406 bool streaming;
407 };
408
409 static inline struct ov02c10 *to_ov02c10(struct v4l2_subdev *subdev)
410 {
411 return container_of(subdev, struct ov02c10, sd);
412 }
413
414 static int ov02c10_read_reg(struct ov02c10 *ov02c10, u16 reg, u16 len, u32 *val)
415 {
416 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
417 struct i2c_msg msgs[2];
418 u8 addr_buf[2];
419 u8 data_buf[4] = {0};
420 int ret = 0;
421
422 if (len > sizeof(data_buf))
423 return -EINVAL;
424
425 put_unaligned_be16(reg, addr_buf);
426 msgs[0].addr = client->addr;
427 msgs[0].flags = 0;
428 msgs[0].len = sizeof(addr_buf);
429 msgs[0].buf = addr_buf;
430 msgs[1].addr = client->addr;
431 msgs[1].flags = I2C_M_RD;
432 msgs[1].len = len;
433 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
434
435 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
436
437 if (ret != ARRAY_SIZE(msgs))
438 return ret < 0 ? ret : -EIO;
439
440 *val = get_unaligned_be32(data_buf);
441
442 return 0;
443 }
444
445 static int ov02c10_write_reg(struct ov02c10 *ov02c10, u16 reg, u16 len, u32 val)
446 {
447 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
448 u8 buf[6];
449 int ret = 0;
450
451 if (len > 4)
452 return -EINVAL;
453
454 put_unaligned_be16(reg, buf);
455 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
456
457 ret = i2c_master_send(client, buf, len + 2);
458 if (ret != len + 2)
459 return ret < 0 ? ret : -EIO;
460
461 return 0;
462 }
463
464 static int ov02c10_write_reg_list(struct ov02c10 *ov02c10,
465 const struct ov02c10_reg_list *r_list)
466 {
467 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
468 unsigned int i;
469 int ret = 0;
470
471 for (i = 0; i < r_list->num_of_regs; i++) {
472 ret = ov02c10_write_reg(ov02c10, r_list->regs[i].address, 1,
473 r_list->regs[i].val);
474 if (ret) {
475 dev_err_ratelimited(&client->dev,
476 "write reg 0x%4.4x return err = %d",
477 r_list->regs[i].address, ret);
478 return ret;
479 }
480 }
481
482 return 0;
483 }
484
485 static int ov02c10_test_pattern(struct ov02c10 *ov02c10, u32 pattern)
486 {
487 if (pattern)
488 pattern = (pattern - 1) << OV02C10_TEST_PATTERN_BAR_SHIFT |
489 OV02C10_TEST_PATTERN_ENABLE;
490
491 return ov02c10_write_reg(ov02c10, OV02C10_REG_TEST_PATTERN, 1, pattern);
492 }
493
494 static int ov02c10_set_ctrl(struct v4l2_ctrl *ctrl)
495 {
496 struct ov02c10 *ov02c10 = container_of(ctrl->handler,
497 struct ov02c10, ctrl_handler);
498 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
499 s64 exposure_max;
500 int ret = 0;
501
502 /* Propagate change of current control to all related controls */
503 if (ctrl->id == V4L2_CID_VBLANK) {
504 /* Update max exposure while meeting expected vblanking */
505 exposure_max = ov02c10->cur_mode->height + ctrl->val -
506 OV02C10_EXPOSURE_MAX_MARGIN;
507 __v4l2_ctrl_modify_range(ov02c10->exposure,
508 ov02c10->exposure->minimum,
509 exposure_max, ov02c10->exposure->step,
510 exposure_max);
511 }
512
513 /* V4L2 controls values will be applied only when power is already up */
514 if (!pm_runtime_get_if_in_use(&client->dev))
515 return 0;
516
517 switch (ctrl->id) {
518 case V4L2_CID_ANALOGUE_GAIN:
519 ret = ov02c10_write_reg(ov02c10, OV02C10_REG_ANALOG_GAIN, 2,
520 ctrl->val << 4);
521 break;
522
523 case V4L2_CID_DIGITAL_GAIN:
524 ret = ov02c10_write_reg(ov02c10, OV02C10_REG_DIGILAL_GAIN, 3,
525 ctrl->val << 6);
526 break;
527
528 case V4L2_CID_EXPOSURE:
529 ret = ov02c10_write_reg(ov02c10, OV02C10_REG_EXPOSURE, 2,
530 ctrl->val);
531 break;
532
533 case V4L2_CID_VBLANK:
534 ret = ov02c10_write_reg(ov02c10, OV02C10_REG_VTS, 2,
535 ov02c10->cur_mode->height + ctrl->val);
536 break;
537
538 case V4L2_CID_TEST_PATTERN:
539 ret = ov02c10_test_pattern(ov02c10, ctrl->val);
540 break;
541
542 case V4L2_CID_PRIVACY:
543 dev_dbg(&client->dev, "set privacy to %d", ctrl->val);
544 break;
545
546 default:
547 ret = -EINVAL;
548 break;
549 }
550
551 pm_runtime_put(&client->dev);
552
553 return ret;
554 }
555
556 static const struct v4l2_ctrl_ops ov02c10_ctrl_ops = {
557 .s_ctrl = ov02c10_set_ctrl,
558 };
559
560 static int ov02c10_init_controls(struct ov02c10 *ov02c10)
561 {
562 struct v4l2_ctrl_handler *ctrl_hdlr;
563 const struct ov02c10_mode *cur_mode;
564 s64 exposure_max, h_blank;
565 u32 vblank_min, vblank_max, vblank_default;
566 int size;
567 int ret = 0;
568
569 ctrl_hdlr = &ov02c10->ctrl_handler;
570 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 9);
571 if (ret)
572 return ret;
573
574 ctrl_hdlr->lock = &ov02c10->mutex;
575 cur_mode = ov02c10->cur_mode;
576 size = ARRAY_SIZE(link_freq_menu_items);
577
578 ov02c10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
579 &ov02c10_ctrl_ops,
580 V4L2_CID_LINK_FREQ,
581 size - 1, 0,
582 link_freq_menu_items);
583 if (ov02c10->link_freq)
584 ov02c10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
585
586 ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
587 V4L2_CID_PIXEL_RATE, 0,
588 OV02C10_SCLK, 1, OV02C10_SCLK);
589
590 vblank_min = cur_mode->vts_min - cur_mode->height;
591 vblank_max = OV02C10_VTS_MAX - cur_mode->height;
592 vblank_default = cur_mode->vts_def - cur_mode->height;
593 ov02c10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
594 V4L2_CID_VBLANK, vblank_min,
595 vblank_max, 1, vblank_default);
596
597 h_blank = cur_mode->hts - cur_mode->width;
598 ov02c10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
599 V4L2_CID_HBLANK, h_blank, h_blank,
600 1, h_blank);
601 if (ov02c10->hblank)
602 ov02c10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
603 ov02c10->privacy_status = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
604 V4L2_CID_PRIVACY, 0, 1, 1, 0);
605
606 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
607 OV02C10_ANAL_GAIN_MIN, OV02C10_ANAL_GAIN_MAX,
608 OV02C10_ANAL_GAIN_STEP, OV02C10_ANAL_GAIN_DEFAULT);
609 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
610 OV02C10_DGTL_GAIN_MIN, OV02C10_DGTL_GAIN_MAX,
611 OV02C10_DGTL_GAIN_STEP, OV02C10_DGTL_GAIN_DEFAULT);
612 exposure_max = cur_mode->vts_def - OV02C10_EXPOSURE_MAX_MARGIN;
613 ov02c10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
614 V4L2_CID_EXPOSURE,
615 OV02C10_EXPOSURE_MIN,
616 exposure_max,
617 OV02C10_EXPOSURE_STEP,
618 exposure_max);
619 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02c10_ctrl_ops,
620 V4L2_CID_TEST_PATTERN,
621 ARRAY_SIZE(ov02c10_test_pattern_menu) - 1,
622 0, 0, ov02c10_test_pattern_menu);
623 if (ctrl_hdlr->error)
624 return ctrl_hdlr->error;
625
626 ov02c10->sd.ctrl_handler = ctrl_hdlr;
627
628 return 0;
629 }
630
631 static void ov02c10_update_pad_format(const struct ov02c10_mode *mode,
632 struct v4l2_mbus_framefmt *fmt)
633 {
634 fmt->width = mode->width;
635 fmt->height = mode->height;
636 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
637 fmt->field = V4L2_FIELD_NONE;
638 }
639
640 static void ov02c10_vsc_privacy_callback(void *handle,
641 enum vsc_privacy_status status)
642 {
643 struct ov02c10 *ov02c10 = handle;
644
645 v4l2_ctrl_s_ctrl(ov02c10->privacy_status, !status);
646 }
647
648 static int ov02c10_start_streaming(struct ov02c10 *ov02c10)
649 {
650 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
651 const struct ov02c10_reg_list *reg_list;
652 int link_freq_index;
653 int ret = 0;
654 struct vsc_mipi_config conf;
655 struct vsc_camera_status status;
656
657 conf.lane_num = OV02C10_DATA_LANES;
658 /* frequency unit 100k */
659 conf.freq = OV02C10_LINK_FREQ_400MHZ / 100000;
660 ret = vsc_acquire_camera_sensor(&conf, ov02c10_vsc_privacy_callback,
661 ov02c10, &status);
662 if (ret) {
663 dev_err(&client->dev, "Acquire VSC failed");
664 return ret;
665 }
666 __v4l2_ctrl_s_ctrl(ov02c10->privacy_status, !(status.status));
667 link_freq_index = ov02c10->cur_mode->link_freq_index;
668 reg_list = &link_freq_configs[link_freq_index].reg_list;
669 ret = ov02c10_write_reg_list(ov02c10, reg_list);
670 if (ret) {
671 dev_err(&client->dev, "failed to set plls");
672 return ret;
673 }
674
675 reg_list = &ov02c10->cur_mode->reg_list;
676 ret = ov02c10_write_reg_list(ov02c10, reg_list);
677 if (ret) {
678 dev_err(&client->dev, "failed to set mode");
679 return ret;
680 }
681
682 ret = __v4l2_ctrl_handler_setup(ov02c10->sd.ctrl_handler);
683 if (ret)
684 return ret;
685
686 ret = ov02c10_write_reg(ov02c10, OV02C10_REG_MODE_SELECT, 1,
687 OV02C10_MODE_STREAMING);
688 if (ret)
689 dev_err(&client->dev, "failed to start streaming");
690
691 return ret;
692 }
693
694 static void ov02c10_stop_streaming(struct ov02c10 *ov02c10)
695 {
696 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
697 int ret = 0;
698 struct vsc_camera_status status;
699
700 ret = ov02c10_write_reg(ov02c10, OV02C10_REG_MODE_SELECT, 1,
701 OV02C10_MODE_STANDBY);
702 if (ret)
703 dev_err(&client->dev, "failed to stop streaming");
704 ret = vsc_release_camera_sensor(&status);
705 if (ret)
706 dev_err(&client->dev, "Release VSC failed");
707 }
708
709 static int ov02c10_set_stream(struct v4l2_subdev *sd, int enable)
710 {
711 struct ov02c10 *ov02c10 = to_ov02c10(sd);
712 struct i2c_client *client = v4l2_get_subdevdata(sd);
713 int ret = 0;
714
715 if (ov02c10->streaming == enable)
716 return 0;
717
718 mutex_lock(&ov02c10->mutex);
719 if (enable) {
720 ret = pm_runtime_get_sync(&client->dev);
721 if (ret < 0) {
722 pm_runtime_put_noidle(&client->dev);
723 mutex_unlock(&ov02c10->mutex);
724 return ret;
725 }
726
727 ret = ov02c10_start_streaming(ov02c10);
728 if (ret) {
729 enable = 0;
730 ov02c10_stop_streaming(ov02c10);
731 pm_runtime_put(&client->dev);
732 }
733 } else {
734 ov02c10_stop_streaming(ov02c10);
735 pm_runtime_put(&client->dev);
736 }
737
738 ov02c10->streaming = enable;
739 mutex_unlock(&ov02c10->mutex);
740
741 return ret;
742 }
743
744 static int __maybe_unused ov02c10_suspend(struct device *dev)
745 {
746 struct i2c_client *client = to_i2c_client(dev);
747 struct v4l2_subdev *sd = i2c_get_clientdata(client);
748 struct ov02c10 *ov02c10 = to_ov02c10(sd);
749
750 mutex_lock(&ov02c10->mutex);
751 if (ov02c10->streaming)
752 ov02c10_stop_streaming(ov02c10);
753
754 mutex_unlock(&ov02c10->mutex);
755
756 return 0;
757 }
758
759 static int __maybe_unused ov02c10_resume(struct device *dev)
760 {
761 struct i2c_client *client = to_i2c_client(dev);
762 struct v4l2_subdev *sd = i2c_get_clientdata(client);
763 struct ov02c10 *ov02c10 = to_ov02c10(sd);
764 int ret = 0;
765
766 mutex_lock(&ov02c10->mutex);
767 if (!ov02c10->streaming)
768 goto exit;
769
770 ret = ov02c10_start_streaming(ov02c10);
771 if (ret) {
772 ov02c10->streaming = false;
773 ov02c10_stop_streaming(ov02c10);
774 }
775
776 exit:
777 mutex_unlock(&ov02c10->mutex);
778 return ret;
779 }
780
781 static int ov02c10_set_format(struct v4l2_subdev *sd,
782 struct v4l2_subdev_state *sd_state,
783 struct v4l2_subdev_format *fmt)
784 {
785 struct ov02c10 *ov02c10 = to_ov02c10(sd);
786 const struct ov02c10_mode *mode;
787 s32 vblank_def, h_blank;
788
789 mode = v4l2_find_nearest_size(supported_modes,
790 ARRAY_SIZE(supported_modes), width,
791 height, fmt->format.width,
792 fmt->format.height);
793
794 mutex_lock(&ov02c10->mutex);
795 ov02c10_update_pad_format(mode, &fmt->format);
796 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
797 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
798 } else {
799 ov02c10->cur_mode = mode;
800 __v4l2_ctrl_s_ctrl(ov02c10->link_freq, mode->link_freq_index);
801 __v4l2_ctrl_s_ctrl_int64(ov02c10->pixel_rate, OV02C10_SCLK);
802
803 /* Update limits and set FPS to default */
804 vblank_def = mode->vts_def - mode->height;
805 __v4l2_ctrl_modify_range(ov02c10->vblank,
806 mode->vts_min - mode->height,
807 OV02C10_VTS_MAX - mode->height, 1,
808 vblank_def);
809 __v4l2_ctrl_s_ctrl(ov02c10->vblank, vblank_def);
810 h_blank = mode->hts - mode->width;
811 __v4l2_ctrl_modify_range(ov02c10->hblank, h_blank, h_blank, 1,
812 h_blank);
813 }
814 mutex_unlock(&ov02c10->mutex);
815
816 return 0;
817 }
818
819 static int ov02c10_get_format(struct v4l2_subdev *sd,
820 struct v4l2_subdev_state *sd_state,
821 struct v4l2_subdev_format *fmt)
822 {
823 struct ov02c10 *ov02c10 = to_ov02c10(sd);
824
825 mutex_lock(&ov02c10->mutex);
826 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
827 fmt->format = *v4l2_subdev_get_try_format(&ov02c10->sd,
828 sd_state, fmt->pad);
829 else
830 ov02c10_update_pad_format(ov02c10->cur_mode, &fmt->format);
831
832 mutex_unlock(&ov02c10->mutex);
833
834 return 0;
835 }
836
837 static int ov02c10_enum_mbus_code(struct v4l2_subdev *sd,
838 struct v4l2_subdev_state *sd_state,
839 struct v4l2_subdev_mbus_code_enum *code)
840 {
841 if (code->index > 0)
842 return -EINVAL;
843
844 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
845
846 return 0;
847 }
848
849 static int ov02c10_enum_frame_size(struct v4l2_subdev *sd,
850 struct v4l2_subdev_state *sd_state,
851 struct v4l2_subdev_frame_size_enum *fse)
852 {
853 if (fse->index >= ARRAY_SIZE(supported_modes))
854 return -EINVAL;
855
856 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
857 return -EINVAL;
858
859 fse->min_width = supported_modes[fse->index].width;
860 fse->max_width = fse->min_width;
861 fse->min_height = supported_modes[fse->index].height;
862 fse->max_height = fse->min_height;
863
864 return 0;
865 }
866
867 static int ov02c10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
868 {
869 struct ov02c10 *ov02c10 = to_ov02c10(sd);
870
871 mutex_lock(&ov02c10->mutex);
872 ov02c10_update_pad_format(&supported_modes[0],
873 v4l2_subdev_get_try_format(sd, fh->state, 0));
874 mutex_unlock(&ov02c10->mutex);
875
876 return 0;
877 }
878
879 static const struct v4l2_subdev_video_ops ov02c10_video_ops = {
880 .s_stream = ov02c10_set_stream,
881 };
882
883 static const struct v4l2_subdev_pad_ops ov02c10_pad_ops = {
884 .set_fmt = ov02c10_set_format,
885 .get_fmt = ov02c10_get_format,
886 .enum_mbus_code = ov02c10_enum_mbus_code,
887 .enum_frame_size = ov02c10_enum_frame_size,
888 };
889
890 static const struct v4l2_subdev_ops ov02c10_subdev_ops = {
891 .video = &ov02c10_video_ops,
892 .pad = &ov02c10_pad_ops,
893 };
894
895 static const struct media_entity_operations ov02c10_subdev_entity_ops = {
896 .link_validate = v4l2_subdev_link_validate,
897 };
898
899 static const struct v4l2_subdev_internal_ops ov02c10_internal_ops = {
900 .open = ov02c10_open,
901 };
902
903 static int ov02c10_identify_module(struct ov02c10 *ov02c10)
904 {
905 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
906 int ret;
907 u32 val;
908
909 ret = ov02c10_read_reg(ov02c10, OV02C10_REG_CHIP_ID, 3, &val);
910 if (ret)
911 return ret;
912
913 if (val != OV02C10_CHIP_ID) {
914 dev_err(&client->dev, "chip id mismatch: %x!=%x",
915 OV02C10_CHIP_ID, val);
916 return -ENXIO;
917 }
918
919 return 0;
920 }
921
922 static int ov02c10_remove(struct i2c_client *client)
923 {
924 struct v4l2_subdev *sd = i2c_get_clientdata(client);
925 struct ov02c10 *ov02c10 = to_ov02c10(sd);
926
927 v4l2_async_unregister_subdev(sd);
928 media_entity_cleanup(&sd->entity);
929 v4l2_ctrl_handler_free(sd->ctrl_handler);
930 pm_runtime_disable(&client->dev);
931 mutex_destroy(&ov02c10->mutex);
932
933 return 0;
934 }
935
936 static int ov02c10_probe(struct i2c_client *client)
937 {
938 struct ov02c10 *ov02c10;
939 int ret = 0;
940 struct vsc_mipi_config conf;
941 struct vsc_camera_status status;
942
943 conf.lane_num = OV02C10_DATA_LANES;
944 /* frequency unit 100k */
945 conf.freq = OV02C10_LINK_FREQ_400MHZ / 100000;
946 ret = vsc_acquire_camera_sensor(&conf, NULL, NULL, &status);
947 if (ret == -EAGAIN) {
948 dev_dbg(&client->dev, "VSC not ready, will re-probe");
949 return -EPROBE_DEFER;
950 } else if (ret) {
951 dev_err(&client->dev, "Acquire VSC failed");
952 return ret;
953 }
954 ov02c10 = devm_kzalloc(&client->dev, sizeof(*ov02c10), GFP_KERNEL);
955 if (!ov02c10) {
956 ret = -ENOMEM;
957 goto probe_error_ret;
958 }
959
960 v4l2_i2c_subdev_init(&ov02c10->sd, client, &ov02c10_subdev_ops);
961
962 ret = ov02c10_identify_module(ov02c10);
963 if (ret) {
964 dev_err(&client->dev, "failed to find sensor: %d", ret);
965 goto probe_error_ret;
966 }
967
968 mutex_init(&ov02c10->mutex);
969 ov02c10->cur_mode = &supported_modes[0];
970 ret = ov02c10_init_controls(ov02c10);
971 if (ret) {
972 dev_err(&client->dev, "failed to init controls: %d", ret);
973 goto probe_error_v4l2_ctrl_handler_free;
974 }
975
976 ov02c10->sd.internal_ops = &ov02c10_internal_ops;
977 ov02c10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
978 ov02c10->sd.entity.ops = &ov02c10_subdev_entity_ops;
979 ov02c10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
980 ov02c10->pad.flags = MEDIA_PAD_FL_SOURCE;
981 ret = media_entity_pads_init(&ov02c10->sd.entity, 1, &ov02c10->pad);
982 if (ret) {
983 dev_err(&client->dev, "failed to init entity pads: %d", ret);
984 goto probe_error_v4l2_ctrl_handler_free;
985 }
986
987 ret = v4l2_async_register_subdev_sensor(&ov02c10->sd);
988 if (ret < 0) {
989 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
990 ret);
991 goto probe_error_media_entity_cleanup;
992 }
993
994 vsc_release_camera_sensor(&status);
995 /*
996 * Device is already turned on by i2c-core with ACPI domain PM.
997 * Enable runtime PM and turn off the device.
998 */
999 pm_runtime_set_active(&client->dev);
1000 pm_runtime_enable(&client->dev);
1001 pm_runtime_idle(&client->dev);
1002
1003 return 0;
1004
1005 probe_error_media_entity_cleanup:
1006 media_entity_cleanup(&ov02c10->sd.entity);
1007
1008 probe_error_v4l2_ctrl_handler_free:
1009 v4l2_ctrl_handler_free(ov02c10->sd.ctrl_handler);
1010 mutex_destroy(&ov02c10->mutex);
1011
1012 probe_error_ret:
1013 vsc_release_camera_sensor(&status);
1014 return ret;
1015 }
1016
1017 static const struct dev_pm_ops ov02c10_pm_ops = {
1018 SET_SYSTEM_SLEEP_PM_OPS(ov02c10_suspend, ov02c10_resume)
1019 };
1020
1021 #ifdef CONFIG_ACPI
1022 static const struct acpi_device_id ov02c10_acpi_ids[] = {
1023 {"OVTI02C1"},
1024 {}
1025 };
1026
1027 MODULE_DEVICE_TABLE(acpi, ov02c10_acpi_ids);
1028 #endif
1029
1030 static struct i2c_driver ov02c10_i2c_driver = {
1031 .driver = {
1032 .name = "ov02c10",
1033 .pm = &ov02c10_pm_ops,
1034 .acpi_match_table = ACPI_PTR(ov02c10_acpi_ids),
1035 },
1036 .probe_new = ov02c10_probe,
1037 .remove = ov02c10_remove,
1038 };
1039
1040 module_i2c_driver(ov02c10_i2c_driver);
1041
1042 MODULE_AUTHOR("Hao Yao <hao.yao@intel.com>");
1043 MODULE_DESCRIPTION("OmniVision OV02C10 sensor driver");
1044 MODULE_LICENSE("GPL v2");
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