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Merge branch 'core-rcu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / soc_camera / ov6650.c
1 /*
2 * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/v4l2-mediabus.h>
32 #include <linux/module.h>
33
34 #include <media/soc_camera.h>
35 #include <media/v4l2-chip-ident.h>
36 #include <media/v4l2-ctrls.h>
37
38 /* Register definitions */
39 #define REG_GAIN 0x00 /* range 00 - 3F */
40 #define REG_BLUE 0x01
41 #define REG_RED 0x02
42 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
43 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
44
45 #define REG_BRT 0x06
46
47 #define REG_PIDH 0x0a
48 #define REG_PIDL 0x0b
49
50 #define REG_AECH 0x10
51 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
52 /* [7:6] Input system clock (MHz)*/
53 /* 00=8, 01=12, 10=16, 11=24 */
54 /* [5:0]: Internal Clock Pre-Scaler */
55 #define REG_COMA 0x12 /* [7] Reset */
56 #define REG_COMB 0x13
57 #define REG_COMC 0x14
58 #define REG_COMD 0x15
59 #define REG_COML 0x16
60 #define REG_HSTRT 0x17
61 #define REG_HSTOP 0x18
62 #define REG_VSTRT 0x19
63 #define REG_VSTOP 0x1a
64 #define REG_PSHFT 0x1b
65 #define REG_MIDH 0x1c
66 #define REG_MIDL 0x1d
67 #define REG_HSYNS 0x1e
68 #define REG_HSYNE 0x1f
69 #define REG_COME 0x20
70 #define REG_YOFF 0x21
71 #define REG_UOFF 0x22
72 #define REG_VOFF 0x23
73 #define REG_AEW 0x24
74 #define REG_AEB 0x25
75 #define REG_COMF 0x26
76 #define REG_COMG 0x27
77 #define REG_COMH 0x28
78 #define REG_COMI 0x29
79
80 #define REG_FRARL 0x2b
81 #define REG_COMJ 0x2c
82 #define REG_COMK 0x2d
83 #define REG_AVGY 0x2e
84 #define REG_REF0 0x2f
85 #define REG_REF1 0x30
86 #define REG_REF2 0x31
87 #define REG_FRAJH 0x32
88 #define REG_FRAJL 0x33
89 #define REG_FACT 0x34
90 #define REG_L1AEC 0x35
91 #define REG_AVGU 0x36
92 #define REG_AVGV 0x37
93
94 #define REG_SPCB 0x60
95 #define REG_SPCC 0x61
96 #define REG_GAM1 0x62
97 #define REG_GAM2 0x63
98 #define REG_GAM3 0x64
99 #define REG_SPCD 0x65
100
101 #define REG_SPCE 0x68
102 #define REG_ADCL 0x69
103
104 #define REG_RMCO 0x6c
105 #define REG_GMCO 0x6d
106 #define REG_BMCO 0x6e
107
108
109 /* Register bits, values, etc. */
110 #define OV6650_PIDH 0x66 /* high byte of product ID number */
111 #define OV6650_PIDL 0x50 /* low byte of product ID number */
112 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
113 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
114
115 #define DEF_GAIN 0x00
116 #define DEF_BLUE 0x80
117 #define DEF_RED 0x80
118
119 #define SAT_SHIFT 4
120 #define SAT_MASK (0xf << SAT_SHIFT)
121 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
122
123 #define HUE_EN BIT(5)
124 #define HUE_MASK 0x1f
125 #define DEF_HUE 0x10
126 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
127
128 #define DEF_AECH 0x4D
129
130 #define CLKRC_6MHz 0x00
131 #define CLKRC_12MHz 0x40
132 #define CLKRC_16MHz 0x80
133 #define CLKRC_24MHz 0xc0
134 #define CLKRC_DIV_MASK 0x3f
135 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
136
137 #define COMA_RESET BIT(7)
138 #define COMA_QCIF BIT(5)
139 #define COMA_RAW_RGB BIT(4)
140 #define COMA_RGB BIT(3)
141 #define COMA_BW BIT(2)
142 #define COMA_WORD_SWAP BIT(1)
143 #define COMA_BYTE_SWAP BIT(0)
144 #define DEF_COMA 0x00
145
146 #define COMB_FLIP_V BIT(7)
147 #define COMB_FLIP_H BIT(5)
148 #define COMB_BAND_FILTER BIT(4)
149 #define COMB_AWB BIT(2)
150 #define COMB_AGC BIT(1)
151 #define COMB_AEC BIT(0)
152 #define DEF_COMB 0x5f
153
154 #define COML_ONE_CHANNEL BIT(7)
155
156 #define DEF_HSTRT 0x24
157 #define DEF_HSTOP 0xd4
158 #define DEF_VSTRT 0x04
159 #define DEF_VSTOP 0x94
160
161 #define COMF_HREF_LOW BIT(4)
162
163 #define COMJ_PCLK_RISING BIT(4)
164 #define COMJ_VSYNC_HIGH BIT(0)
165
166 /* supported resolutions */
167 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
168 #define W_CIF (W_QCIF << 1)
169 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
170 #define H_CIF (H_QCIF << 1)
171
172 #define FRAME_RATE_MAX 30
173
174
175 struct ov6650_reg {
176 u8 reg;
177 u8 val;
178 };
179
180 struct ov6650 {
181 struct v4l2_subdev subdev;
182 struct v4l2_ctrl_handler hdl;
183 struct {
184 /* exposure/autoexposure cluster */
185 struct v4l2_ctrl *autoexposure;
186 struct v4l2_ctrl *exposure;
187 };
188 struct {
189 /* gain/autogain cluster */
190 struct v4l2_ctrl *autogain;
191 struct v4l2_ctrl *gain;
192 };
193 struct {
194 /* blue/red/autowhitebalance cluster */
195 struct v4l2_ctrl *autowb;
196 struct v4l2_ctrl *blue;
197 struct v4l2_ctrl *red;
198 };
199 bool half_scale; /* scale down output by 2 */
200 struct v4l2_rect rect; /* sensor cropping window */
201 unsigned long pclk_limit; /* from host */
202 unsigned long pclk_max; /* from resolution and format */
203 struct v4l2_fract tpf; /* as requested with s_parm */
204 enum v4l2_mbus_pixelcode code;
205 enum v4l2_colorspace colorspace;
206 };
207
208
209 static enum v4l2_mbus_pixelcode ov6650_codes[] = {
210 V4L2_MBUS_FMT_YUYV8_2X8,
211 V4L2_MBUS_FMT_UYVY8_2X8,
212 V4L2_MBUS_FMT_YVYU8_2X8,
213 V4L2_MBUS_FMT_VYUY8_2X8,
214 V4L2_MBUS_FMT_SBGGR8_1X8,
215 V4L2_MBUS_FMT_Y8_1X8,
216 };
217
218 /* read a register */
219 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
220 {
221 int ret;
222 u8 data = reg;
223 struct i2c_msg msg = {
224 .addr = client->addr,
225 .flags = 0,
226 .len = 1,
227 .buf = &data,
228 };
229
230 ret = i2c_transfer(client->adapter, &msg, 1);
231 if (ret < 0)
232 goto err;
233
234 msg.flags = I2C_M_RD;
235 ret = i2c_transfer(client->adapter, &msg, 1);
236 if (ret < 0)
237 goto err;
238
239 *val = data;
240 return 0;
241
242 err:
243 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
244 return ret;
245 }
246
247 /* write a register */
248 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
249 {
250 int ret;
251 unsigned char data[2] = { reg, val };
252 struct i2c_msg msg = {
253 .addr = client->addr,
254 .flags = 0,
255 .len = 2,
256 .buf = data,
257 };
258
259 ret = i2c_transfer(client->adapter, &msg, 1);
260 udelay(100);
261
262 if (ret < 0) {
263 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
264 return ret;
265 }
266 return 0;
267 }
268
269
270 /* Read a register, alter its bits, write it back */
271 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
272 {
273 u8 val;
274 int ret;
275
276 ret = ov6650_reg_read(client, reg, &val);
277 if (ret) {
278 dev_err(&client->dev,
279 "[Read]-Modify-Write of register 0x%02x failed!\n",
280 reg);
281 return ret;
282 }
283
284 val &= ~mask;
285 val |= set;
286
287 ret = ov6650_reg_write(client, reg, val);
288 if (ret)
289 dev_err(&client->dev,
290 "Read-Modify-[Write] of register 0x%02x failed!\n",
291 reg);
292
293 return ret;
294 }
295
296 static struct ov6650 *to_ov6650(const struct i2c_client *client)
297 {
298 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
299 }
300
301 /* Start/Stop streaming from the device */
302 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
303 {
304 return 0;
305 }
306
307 /* Get status of additional camera capabilities */
308 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
309 {
310 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
311 struct v4l2_subdev *sd = &priv->subdev;
312 struct i2c_client *client = v4l2_get_subdevdata(sd);
313 uint8_t reg, reg2;
314 int ret;
315
316 switch (ctrl->id) {
317 case V4L2_CID_AUTOGAIN:
318 ret = ov6650_reg_read(client, REG_GAIN, &reg);
319 if (!ret)
320 priv->gain->val = reg;
321 return ret;
322 case V4L2_CID_AUTO_WHITE_BALANCE:
323 ret = ov6650_reg_read(client, REG_BLUE, &reg);
324 if (!ret)
325 ret = ov6650_reg_read(client, REG_RED, &reg2);
326 if (!ret) {
327 priv->blue->val = reg;
328 priv->red->val = reg2;
329 }
330 return ret;
331 case V4L2_CID_EXPOSURE_AUTO:
332 ret = ov6650_reg_read(client, REG_AECH, &reg);
333 if (!ret)
334 priv->exposure->val = reg;
335 return ret;
336 }
337 return -EINVAL;
338 }
339
340 /* Set status of additional camera capabilities */
341 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
342 {
343 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
344 struct v4l2_subdev *sd = &priv->subdev;
345 struct i2c_client *client = v4l2_get_subdevdata(sd);
346 int ret;
347
348 switch (ctrl->id) {
349 case V4L2_CID_AUTOGAIN:
350 ret = ov6650_reg_rmw(client, REG_COMB,
351 ctrl->val ? COMB_AGC : 0, COMB_AGC);
352 if (!ret && !ctrl->val)
353 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
354 return ret;
355 case V4L2_CID_AUTO_WHITE_BALANCE:
356 ret = ov6650_reg_rmw(client, REG_COMB,
357 ctrl->val ? COMB_AWB : 0, COMB_AWB);
358 if (!ret && !ctrl->val) {
359 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
360 if (!ret)
361 ret = ov6650_reg_write(client, REG_RED,
362 priv->red->val);
363 }
364 return ret;
365 case V4L2_CID_SATURATION:
366 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
367 SAT_MASK);
368 case V4L2_CID_HUE:
369 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
370 HUE_MASK);
371 case V4L2_CID_BRIGHTNESS:
372 return ov6650_reg_write(client, REG_BRT, ctrl->val);
373 case V4L2_CID_EXPOSURE_AUTO:
374 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
375 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
376 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
377 ret = ov6650_reg_write(client, REG_AECH,
378 priv->exposure->val);
379 return ret;
380 case V4L2_CID_GAMMA:
381 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
382 case V4L2_CID_VFLIP:
383 return ov6650_reg_rmw(client, REG_COMB,
384 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
385 case V4L2_CID_HFLIP:
386 return ov6650_reg_rmw(client, REG_COMB,
387 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
388 }
389
390 return -EINVAL;
391 }
392
393 /* Get chip identification */
394 static int ov6650_g_chip_ident(struct v4l2_subdev *sd,
395 struct v4l2_dbg_chip_ident *id)
396 {
397 id->ident = V4L2_IDENT_OV6650;
398 id->revision = 0;
399
400 return 0;
401 }
402
403 #ifdef CONFIG_VIDEO_ADV_DEBUG
404 static int ov6650_get_register(struct v4l2_subdev *sd,
405 struct v4l2_dbg_register *reg)
406 {
407 struct i2c_client *client = v4l2_get_subdevdata(sd);
408 int ret;
409 u8 val;
410
411 if (reg->reg & ~0xff)
412 return -EINVAL;
413
414 reg->size = 1;
415
416 ret = ov6650_reg_read(client, reg->reg, &val);
417 if (!ret)
418 reg->val = (__u64)val;
419
420 return ret;
421 }
422
423 static int ov6650_set_register(struct v4l2_subdev *sd,
424 struct v4l2_dbg_register *reg)
425 {
426 struct i2c_client *client = v4l2_get_subdevdata(sd);
427
428 if (reg->reg & ~0xff || reg->val & ~0xff)
429 return -EINVAL;
430
431 return ov6650_reg_write(client, reg->reg, reg->val);
432 }
433 #endif
434
435 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
436 {
437 struct i2c_client *client = v4l2_get_subdevdata(sd);
438 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
439
440 return soc_camera_set_power(&client->dev, icl, on);
441 }
442
443 static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
444 {
445 struct i2c_client *client = v4l2_get_subdevdata(sd);
446 struct ov6650 *priv = to_ov6650(client);
447
448 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
449 a->c = priv->rect;
450
451 return 0;
452 }
453
454 static int ov6650_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
455 {
456 struct i2c_client *client = v4l2_get_subdevdata(sd);
457 struct ov6650 *priv = to_ov6650(client);
458 struct v4l2_rect rect = a->c;
459 int ret;
460
461 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
462 return -EINVAL;
463
464 rect.left = ALIGN(rect.left, 2);
465 rect.width = ALIGN(rect.width, 2);
466 rect.top = ALIGN(rect.top, 2);
467 rect.height = ALIGN(rect.height, 2);
468 soc_camera_limit_side(&rect.left, &rect.width,
469 DEF_HSTRT << 1, 2, W_CIF);
470 soc_camera_limit_side(&rect.top, &rect.height,
471 DEF_VSTRT << 1, 2, H_CIF);
472
473 ret = ov6650_reg_write(client, REG_HSTRT, rect.left >> 1);
474 if (!ret) {
475 priv->rect.left = rect.left;
476 ret = ov6650_reg_write(client, REG_HSTOP,
477 (rect.left + rect.width) >> 1);
478 }
479 if (!ret) {
480 priv->rect.width = rect.width;
481 ret = ov6650_reg_write(client, REG_VSTRT, rect.top >> 1);
482 }
483 if (!ret) {
484 priv->rect.top = rect.top;
485 ret = ov6650_reg_write(client, REG_VSTOP,
486 (rect.top + rect.height) >> 1);
487 }
488 if (!ret)
489 priv->rect.height = rect.height;
490
491 return ret;
492 }
493
494 static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
495 {
496 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
497 return -EINVAL;
498
499 a->bounds.left = DEF_HSTRT << 1;
500 a->bounds.top = DEF_VSTRT << 1;
501 a->bounds.width = W_CIF;
502 a->bounds.height = H_CIF;
503 a->defrect = a->bounds;
504 a->pixelaspect.numerator = 1;
505 a->pixelaspect.denominator = 1;
506
507 return 0;
508 }
509
510 static int ov6650_g_fmt(struct v4l2_subdev *sd,
511 struct v4l2_mbus_framefmt *mf)
512 {
513 struct i2c_client *client = v4l2_get_subdevdata(sd);
514 struct ov6650 *priv = to_ov6650(client);
515
516 mf->width = priv->rect.width >> priv->half_scale;
517 mf->height = priv->rect.height >> priv->half_scale;
518 mf->code = priv->code;
519 mf->colorspace = priv->colorspace;
520 mf->field = V4L2_FIELD_NONE;
521
522 return 0;
523 }
524
525 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
526 {
527 return width > rect->width >> 1 || height > rect->height >> 1;
528 }
529
530 static u8 to_clkrc(struct v4l2_fract *timeperframe,
531 unsigned long pclk_limit, unsigned long pclk_max)
532 {
533 unsigned long pclk;
534
535 if (timeperframe->numerator && timeperframe->denominator)
536 pclk = pclk_max * timeperframe->denominator /
537 (FRAME_RATE_MAX * timeperframe->numerator);
538 else
539 pclk = pclk_max;
540
541 if (pclk_limit && pclk_limit < pclk)
542 pclk = pclk_limit;
543
544 return (pclk_max - 1) / pclk;
545 }
546
547 /* set the format we will capture in */
548 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
549 {
550 struct i2c_client *client = v4l2_get_subdevdata(sd);
551 struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
552 struct soc_camera_sense *sense = icd->sense;
553 struct ov6650 *priv = to_ov6650(client);
554 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
555 struct v4l2_crop a = {
556 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
557 .c = {
558 .left = priv->rect.left + (priv->rect.width >> 1) -
559 (mf->width >> (1 - half_scale)),
560 .top = priv->rect.top + (priv->rect.height >> 1) -
561 (mf->height >> (1 - half_scale)),
562 .width = mf->width << half_scale,
563 .height = mf->height << half_scale,
564 },
565 };
566 enum v4l2_mbus_pixelcode code = mf->code;
567 unsigned long mclk, pclk;
568 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
569 int ret;
570
571 /* select color matrix configuration for given color encoding */
572 switch (code) {
573 case V4L2_MBUS_FMT_Y8_1X8:
574 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
575 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
576 coma_set |= COMA_BW;
577 break;
578 case V4L2_MBUS_FMT_YUYV8_2X8:
579 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
580 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
581 coma_set |= COMA_WORD_SWAP;
582 break;
583 case V4L2_MBUS_FMT_YVYU8_2X8:
584 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
585 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
586 COMA_BYTE_SWAP;
587 break;
588 case V4L2_MBUS_FMT_UYVY8_2X8:
589 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
590 if (half_scale) {
591 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
592 coma_set |= COMA_BYTE_SWAP;
593 } else {
594 coma_mask |= COMA_RGB | COMA_BW;
595 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
596 }
597 break;
598 case V4L2_MBUS_FMT_VYUY8_2X8:
599 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
600 if (half_scale) {
601 coma_mask |= COMA_RGB | COMA_BW;
602 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
603 } else {
604 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
605 coma_set |= COMA_BYTE_SWAP;
606 }
607 break;
608 case V4L2_MBUS_FMT_SBGGR8_1X8:
609 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
610 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
611 coma_set |= COMA_RAW_RGB | COMA_RGB;
612 break;
613 default:
614 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
615 return -EINVAL;
616 }
617 priv->code = code;
618
619 if (code == V4L2_MBUS_FMT_Y8_1X8 ||
620 code == V4L2_MBUS_FMT_SBGGR8_1X8) {
621 coml_mask = COML_ONE_CHANNEL;
622 coml_set = 0;
623 priv->pclk_max = 4000000;
624 } else {
625 coml_mask = 0;
626 coml_set = COML_ONE_CHANNEL;
627 priv->pclk_max = 8000000;
628 }
629
630 if (code == V4L2_MBUS_FMT_SBGGR8_1X8)
631 priv->colorspace = V4L2_COLORSPACE_SRGB;
632 else if (code != 0)
633 priv->colorspace = V4L2_COLORSPACE_JPEG;
634
635 if (half_scale) {
636 dev_dbg(&client->dev, "max resolution: QCIF\n");
637 coma_set |= COMA_QCIF;
638 priv->pclk_max /= 2;
639 } else {
640 dev_dbg(&client->dev, "max resolution: CIF\n");
641 coma_mask |= COMA_QCIF;
642 }
643 priv->half_scale = half_scale;
644
645 if (sense) {
646 if (sense->master_clock == 8000000) {
647 dev_dbg(&client->dev, "8MHz input clock\n");
648 clkrc = CLKRC_6MHz;
649 } else if (sense->master_clock == 12000000) {
650 dev_dbg(&client->dev, "12MHz input clock\n");
651 clkrc = CLKRC_12MHz;
652 } else if (sense->master_clock == 16000000) {
653 dev_dbg(&client->dev, "16MHz input clock\n");
654 clkrc = CLKRC_16MHz;
655 } else if (sense->master_clock == 24000000) {
656 dev_dbg(&client->dev, "24MHz input clock\n");
657 clkrc = CLKRC_24MHz;
658 } else {
659 dev_err(&client->dev,
660 "unsupported input clock, check platform data\n");
661 return -EINVAL;
662 }
663 mclk = sense->master_clock;
664 priv->pclk_limit = sense->pixel_clock_max;
665 } else {
666 clkrc = CLKRC_24MHz;
667 mclk = 24000000;
668 priv->pclk_limit = 0;
669 dev_dbg(&client->dev, "using default 24MHz input clock\n");
670 }
671
672 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
673
674 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
675 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
676 mclk / pclk, 10 * mclk % pclk / pclk);
677
678 ret = ov6650_s_crop(sd, &a);
679 if (!ret)
680 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
681 if (!ret)
682 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
683 if (!ret)
684 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
685
686 if (!ret) {
687 mf->colorspace = priv->colorspace;
688 mf->width = priv->rect.width >> half_scale;
689 mf->height = priv->rect.height >> half_scale;
690 }
691
692 return ret;
693 }
694
695 static int ov6650_try_fmt(struct v4l2_subdev *sd,
696 struct v4l2_mbus_framefmt *mf)
697 {
698 struct i2c_client *client = v4l2_get_subdevdata(sd);
699 struct ov6650 *priv = to_ov6650(client);
700
701 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
702 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
703 &mf->height, 2, H_CIF, 1, 0);
704
705 mf->field = V4L2_FIELD_NONE;
706
707 switch (mf->code) {
708 case V4L2_MBUS_FMT_Y10_1X10:
709 mf->code = V4L2_MBUS_FMT_Y8_1X8;
710 case V4L2_MBUS_FMT_Y8_1X8:
711 case V4L2_MBUS_FMT_YVYU8_2X8:
712 case V4L2_MBUS_FMT_YUYV8_2X8:
713 case V4L2_MBUS_FMT_VYUY8_2X8:
714 case V4L2_MBUS_FMT_UYVY8_2X8:
715 mf->colorspace = V4L2_COLORSPACE_JPEG;
716 break;
717 default:
718 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
719 case V4L2_MBUS_FMT_SBGGR8_1X8:
720 mf->colorspace = V4L2_COLORSPACE_SRGB;
721 break;
722 }
723
724 return 0;
725 }
726
727 static int ov6650_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
728 enum v4l2_mbus_pixelcode *code)
729 {
730 if (index >= ARRAY_SIZE(ov6650_codes))
731 return -EINVAL;
732
733 *code = ov6650_codes[index];
734 return 0;
735 }
736
737 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
738 {
739 struct i2c_client *client = v4l2_get_subdevdata(sd);
740 struct ov6650 *priv = to_ov6650(client);
741 struct v4l2_captureparm *cp = &parms->parm.capture;
742
743 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
744 return -EINVAL;
745
746 memset(cp, 0, sizeof(*cp));
747 cp->capability = V4L2_CAP_TIMEPERFRAME;
748 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
749 priv->pclk_limit, priv->pclk_max));
750 cp->timeperframe.denominator = FRAME_RATE_MAX;
751
752 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
753 cp->timeperframe.numerator, cp->timeperframe.denominator);
754
755 return 0;
756 }
757
758 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
759 {
760 struct i2c_client *client = v4l2_get_subdevdata(sd);
761 struct ov6650 *priv = to_ov6650(client);
762 struct v4l2_captureparm *cp = &parms->parm.capture;
763 struct v4l2_fract *tpf = &cp->timeperframe;
764 int div, ret;
765 u8 clkrc;
766
767 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
768 return -EINVAL;
769
770 if (cp->extendedmode != 0)
771 return -EINVAL;
772
773 if (tpf->numerator == 0 || tpf->denominator == 0)
774 div = 1; /* Reset to full rate */
775 else
776 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
777
778 if (div == 0)
779 div = 1;
780 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
781 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
782
783 /*
784 * Keep result to be used as tpf limit
785 * for subseqent clock divider calculations
786 */
787 priv->tpf.numerator = div;
788 priv->tpf.denominator = FRAME_RATE_MAX;
789
790 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
791
792 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
793 if (!ret) {
794 tpf->numerator = GET_CLKRC_DIV(clkrc);
795 tpf->denominator = FRAME_RATE_MAX;
796 }
797
798 return ret;
799 }
800
801 /* Soft reset the camera. This has nothing to do with the RESET pin! */
802 static int ov6650_reset(struct i2c_client *client)
803 {
804 int ret;
805
806 dev_dbg(&client->dev, "reset\n");
807
808 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
809 if (ret)
810 dev_err(&client->dev,
811 "An error occurred while entering soft reset!\n");
812
813 return ret;
814 }
815
816 /* program default register values */
817 static int ov6650_prog_dflt(struct i2c_client *client)
818 {
819 int ret;
820
821 dev_dbg(&client->dev, "initializing\n");
822
823 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
824 if (!ret)
825 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
826
827 return ret;
828 }
829
830 static int ov6650_video_probe(struct i2c_client *client)
831 {
832 struct ov6650 *priv = to_ov6650(client);
833 u8 pidh, pidl, midh, midl;
834 int ret;
835
836 ret = ov6650_s_power(&priv->subdev, 1);
837 if (ret < 0)
838 return ret;
839
840 /*
841 * check and show product ID and manufacturer ID
842 */
843 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
844 if (!ret)
845 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
846 if (!ret)
847 ret = ov6650_reg_read(client, REG_MIDH, &midh);
848 if (!ret)
849 ret = ov6650_reg_read(client, REG_MIDL, &midl);
850
851 if (ret)
852 goto done;
853
854 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
855 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
856 pidh, pidl);
857 ret = -ENODEV;
858 goto done;
859 }
860
861 dev_info(&client->dev,
862 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
863 pidh, pidl, midh, midl);
864
865 ret = ov6650_reset(client);
866 if (!ret)
867 ret = ov6650_prog_dflt(client);
868 if (!ret)
869 ret = v4l2_ctrl_handler_setup(&priv->hdl);
870
871 done:
872 ov6650_s_power(&priv->subdev, 0);
873 return ret;
874 }
875
876 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
877 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
878 .s_ctrl = ov6550_s_ctrl,
879 };
880
881 static struct v4l2_subdev_core_ops ov6650_core_ops = {
882 .g_chip_ident = ov6650_g_chip_ident,
883 #ifdef CONFIG_VIDEO_ADV_DEBUG
884 .g_register = ov6650_get_register,
885 .s_register = ov6650_set_register,
886 #endif
887 .s_power = ov6650_s_power,
888 };
889
890 /* Request bus settings on camera side */
891 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
892 struct v4l2_mbus_config *cfg)
893 {
894 struct i2c_client *client = v4l2_get_subdevdata(sd);
895 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
896
897 cfg->flags = V4L2_MBUS_MASTER |
898 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
899 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
900 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
901 V4L2_MBUS_DATA_ACTIVE_HIGH;
902 cfg->type = V4L2_MBUS_PARALLEL;
903 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
904
905 return 0;
906 }
907
908 /* Alter bus settings on camera side */
909 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
910 const struct v4l2_mbus_config *cfg)
911 {
912 struct i2c_client *client = v4l2_get_subdevdata(sd);
913 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
914 unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
915 int ret;
916
917 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
918 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
919 else
920 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
921 if (ret)
922 return ret;
923
924 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
925 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
926 else
927 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
928 if (ret)
929 return ret;
930
931 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
932 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
933 else
934 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
935
936 return ret;
937 }
938
939 static struct v4l2_subdev_video_ops ov6650_video_ops = {
940 .s_stream = ov6650_s_stream,
941 .g_mbus_fmt = ov6650_g_fmt,
942 .s_mbus_fmt = ov6650_s_fmt,
943 .try_mbus_fmt = ov6650_try_fmt,
944 .enum_mbus_fmt = ov6650_enum_fmt,
945 .cropcap = ov6650_cropcap,
946 .g_crop = ov6650_g_crop,
947 .s_crop = ov6650_s_crop,
948 .g_parm = ov6650_g_parm,
949 .s_parm = ov6650_s_parm,
950 .g_mbus_config = ov6650_g_mbus_config,
951 .s_mbus_config = ov6650_s_mbus_config,
952 };
953
954 static struct v4l2_subdev_ops ov6650_subdev_ops = {
955 .core = &ov6650_core_ops,
956 .video = &ov6650_video_ops,
957 };
958
959 /*
960 * i2c_driver function
961 */
962 static int ov6650_probe(struct i2c_client *client,
963 const struct i2c_device_id *did)
964 {
965 struct ov6650 *priv;
966 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
967 int ret;
968
969 if (!icl) {
970 dev_err(&client->dev, "Missing platform_data for driver\n");
971 return -EINVAL;
972 }
973
974 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
975 if (!priv) {
976 dev_err(&client->dev,
977 "Failed to allocate memory for private data!\n");
978 return -ENOMEM;
979 }
980
981 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
982 v4l2_ctrl_handler_init(&priv->hdl, 13);
983 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
984 V4L2_CID_VFLIP, 0, 1, 1, 0);
985 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
986 V4L2_CID_HFLIP, 0, 1, 1, 0);
987 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
988 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
989 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
990 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
991 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
992 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
993 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
994 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
995 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
996 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
997 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
998 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
999 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1000 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1001 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1002 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1003 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1004 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1005 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1006 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1007 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1008 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1009 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1010
1011 priv->subdev.ctrl_handler = &priv->hdl;
1012 if (priv->hdl.error) {
1013 int err = priv->hdl.error;
1014
1015 kfree(priv);
1016 return err;
1017 }
1018 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1019 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1020 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1021 V4L2_EXPOSURE_MANUAL, true);
1022
1023 priv->rect.left = DEF_HSTRT << 1;
1024 priv->rect.top = DEF_VSTRT << 1;
1025 priv->rect.width = W_CIF;
1026 priv->rect.height = H_CIF;
1027 priv->half_scale = false;
1028 priv->code = V4L2_MBUS_FMT_YUYV8_2X8;
1029 priv->colorspace = V4L2_COLORSPACE_JPEG;
1030
1031 ret = ov6650_video_probe(client);
1032 if (ret) {
1033 v4l2_ctrl_handler_free(&priv->hdl);
1034 kfree(priv);
1035 }
1036
1037 return ret;
1038 }
1039
1040 static int ov6650_remove(struct i2c_client *client)
1041 {
1042 struct ov6650 *priv = to_ov6650(client);
1043
1044 v4l2_device_unregister_subdev(&priv->subdev);
1045 v4l2_ctrl_handler_free(&priv->hdl);
1046 kfree(priv);
1047 return 0;
1048 }
1049
1050 static const struct i2c_device_id ov6650_id[] = {
1051 { "ov6650", 0 },
1052 { }
1053 };
1054 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1055
1056 static struct i2c_driver ov6650_i2c_driver = {
1057 .driver = {
1058 .name = "ov6650",
1059 },
1060 .probe = ov6650_probe,
1061 .remove = ov6650_remove,
1062 .id_table = ov6650_id,
1063 };
1064
1065 module_i2c_driver(ov6650_i2c_driver);
1066
1067 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1068 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1069 MODULE_LICENSE("GPL v2");
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