drivers/media/pci/cx25821/cx25821-video-upstream.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *
  16  *  GNU General Public License for more details.
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include "cx25821-video.h"
  22 #include "cx25821-video-upstream.h"
  23
  24 #include <linux/errno.h>
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/module.h>
  28 #include <linux/slab.h>
  29
  30 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
  31 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
  32 MODULE_LICENSE("GPL");
  33
  34 static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC |
  35                         FLD_VID_SRC_OPC_ERR;
  36
  37 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
  38                                         const struct sram_channel *ch,
  39                                         unsigned int bpl, u32 risc)
  40 {
  41         unsigned int i, lines;
  42         u32 cdt;
  43
  44         if (ch->cmds_start == 0) {
  45                 cx_write(ch->ptr1_reg, 0);
  46                 cx_write(ch->ptr2_reg, 0);
  47                 cx_write(ch->cnt2_reg, 0);
  48                 cx_write(ch->cnt1_reg, 0);
  49                 return 0;
  50         }
  51
  52         bpl = (bpl + 7) & ~7;   /* alignment */
  53         cdt = ch->cdt;
  54         lines = ch->fifo_size / bpl;
  55
  56         if (lines > 4)
  57                 lines = 4;
  58
  59         BUG_ON(lines < 2);
  60
  61         /* write CDT */
  62         for (i = 0; i < lines; i++) {
  63                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
  64                 cx_write(cdt + 16 * i + 4, 0);
  65                 cx_write(cdt + 16 * i + 8, 0);
  66                 cx_write(cdt + 16 * i + 12, 0);
  67         }
  68
  69         /* write CMDS */
  70         cx_write(ch->cmds_start + 0, risc);
  71
  72         cx_write(ch->cmds_start + 4, 0);
  73         cx_write(ch->cmds_start + 8, cdt);
  74         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
  75         cx_write(ch->cmds_start + 16, ch->ctrl_start);
  76
  77         cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
  78
  79         for (i = 24; i < 80; i += 4)
  80                 cx_write(ch->cmds_start + i, 0);
  81
  82         /* fill registers */
  83         cx_write(ch->ptr1_reg, ch->fifo_start);
  84         cx_write(ch->ptr2_reg, cdt);
  85         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
  86         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
  87
  88         return 0;
  89 }
  90
  91 static __le32 *cx25821_update_riscprogram(struct cx25821_channel *chan,
  92                                           __le32 *rp, unsigned int offset,
  93                                           unsigned int bpl, u32 sync_line,
  94                                           unsigned int lines, int fifo_enable,
  95                                           int field_type)
  96 {
  97         struct cx25821_video_out_data *out = chan->out;
  98         unsigned int line, i;
  99         int dist_betwn_starts = bpl * 2;
 100
 101         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 102
 103         if (USE_RISC_NOOP_VIDEO) {
 104                 for (i = 0; i < NUM_NO_OPS; i++)
 105                         *(rp++) = cpu_to_le32(RISC_NOOP);
 106         }
 107
 108         /* scan lines */
 109         for (line = 0; line < lines; line++) {
 110                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 111                 *(rp++) = cpu_to_le32(out->_data_buf_phys_addr + offset);
 112                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 113
 114                 if ((lines <= NTSC_FIELD_HEIGHT)
 115                     || (line < (NTSC_FIELD_HEIGHT - 1)) || !(out->is_60hz)) {
 116                         offset += dist_betwn_starts;
 117                 }
 118         }
 119
 120         return rp;
 121 }
 122
 123 static __le32 *cx25821_risc_field_upstream(struct cx25821_channel *chan, __le32 *rp,
 124                                            dma_addr_t databuf_phys_addr,
 125                                            unsigned int offset, u32 sync_line,
 126                                            unsigned int bpl, unsigned int lines,
 127                                            int fifo_enable, int field_type)
 128 {
 129         struct cx25821_video_out_data *out = chan->out;
 130         unsigned int line, i;
 131         const struct sram_channel *sram_ch = chan->sram_channels;
 132         int dist_betwn_starts = bpl * 2;
 133
 134         /* sync instruction */
 135         if (sync_line != NO_SYNC_LINE)
 136                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 137
 138         if (USE_RISC_NOOP_VIDEO) {
 139                 for (i = 0; i < NUM_NO_OPS; i++)
 140                         *(rp++) = cpu_to_le32(RISC_NOOP);
 141         }
 142
 143         /* scan lines */
 144         for (line = 0; line < lines; line++) {
 145                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 146                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
 147                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 148
 149                 if ((lines <= NTSC_FIELD_HEIGHT)
 150                     || (line < (NTSC_FIELD_HEIGHT - 1)) || !(out->is_60hz))
 151                         /* to skip the other field line */
 152                         offset += dist_betwn_starts;
 153
 154                 /* check if we need to enable the FIFO after the first 4 lines
 155                  * For the upstream video channel, the risc engine will enable
 156                  * the FIFO. */
 157                 if (fifo_enable && line == 3) {
 158                         *(rp++) = cpu_to_le32(RISC_WRITECR);
 159                         *(rp++) = cpu_to_le32(sram_ch->dma_ctl);
 160                         *(rp++) = cpu_to_le32(FLD_VID_FIFO_EN);
 161                         *(rp++) = cpu_to_le32(0x00000001);
 162                 }
 163         }
 164
 165         return rp;
 166 }
 167
 168 static int cx25821_risc_buffer_upstream(struct cx25821_channel *chan,
 169                                         struct pci_dev *pci,
 170                                         unsigned int top_offset,
 171                                         unsigned int bpl, unsigned int lines)
 172 {
 173         struct cx25821_video_out_data *out = chan->out;
 174         __le32 *rp;
 175         int fifo_enable = 0;
 176         /* get line count for single field */
 177         int singlefield_lines = lines >> 1;
 178         int odd_num_lines = singlefield_lines;
 179         int frame = 0;
 180         int frame_size = 0;
 181         int databuf_offset = 0;
 182         int risc_program_size = 0;
 183         int risc_flag = RISC_CNT_RESET;
 184         unsigned int bottom_offset = bpl;
 185         dma_addr_t risc_phys_jump_addr;
 186
 187         if (out->is_60hz) {
 188                 odd_num_lines = singlefield_lines + 1;
 189                 risc_program_size = FRAME1_VID_PROG_SIZE;
 190                 frame_size = (bpl == Y411_LINE_SZ) ?
 191                         FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
 192         } else {
 193                 risc_program_size = PAL_VID_PROG_SIZE;
 194                 frame_size = (bpl == Y411_LINE_SZ) ?
 195                         FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 196         }
 197
 198         /* Virtual address of Risc buffer program */
 199         rp = out->_dma_virt_addr;
 200
 201         for (frame = 0; frame < NUM_FRAMES; frame++) {
 202                 databuf_offset = frame_size * frame;
 203
 204                 if (UNSET != top_offset) {
 205                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
 206                         rp = cx25821_risc_field_upstream(chan, rp,
 207                                         out->_data_buf_phys_addr +
 208                                         databuf_offset, top_offset, 0, bpl,
 209                                         odd_num_lines, fifo_enable, ODD_FIELD);
 210                 }
 211
 212                 fifo_enable = FIFO_DISABLE;
 213
 214                 /* Even Field */
 215                 rp = cx25821_risc_field_upstream(chan, rp,
 216                                                  out->_data_buf_phys_addr +
 217                                                  databuf_offset, bottom_offset,
 218                                                  0x200, bpl, singlefield_lines,
 219                                                  fifo_enable, EVEN_FIELD);
 220
 221                 if (frame == 0) {
 222                         risc_flag = RISC_CNT_RESET;
 223                         risc_phys_jump_addr = out->_dma_phys_start_addr +
 224                                 risc_program_size;
 225                 } else {
 226                         risc_phys_jump_addr = out->_dma_phys_start_addr;
 227                         risc_flag = RISC_CNT_INC;
 228                 }
 229
 230                 /* Loop to 2ndFrameRISC or to Start of Risc
 231                  * program & generate IRQ
 232                  */
 233                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
 234                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 235                 *(rp++) = cpu_to_le32(0);
 236         }
 237
 238         return 0;
 239 }
 240
 241 void cx25821_stop_upstream_video(struct cx25821_channel *chan)
 242 {
 243         struct cx25821_video_out_data *out = chan->out;
 244         struct cx25821_dev *dev = chan->dev;
 245         const struct sram_channel *sram_ch = chan->sram_channels;
 246         u32 tmp = 0;
 247
 248         if (!out->_is_running) {
 249                 pr_info("No video file is currently running so return!\n");
 250                 return;
 251         }
 252
 253         /* Set the interrupt mask register, disable irq. */
 254         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) & ~(1 << sram_ch->irq_bit));
 255
 256         /* Disable RISC interrupts */
 257         tmp = cx_read(sram_ch->int_msk);
 258         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
 259
 260         /* Turn OFF risc and fifo enable */
 261         tmp = cx_read(sram_ch->dma_ctl);
 262         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
 263
 264         free_irq(dev->pci->irq, chan);
 265
 266         /* Clear data buffer memory */
 267         if (out->_data_buf_virt_addr)
 268                 memset(out->_data_buf_virt_addr, 0, out->_data_buf_size);
 269
 270         out->_is_running = 0;
 271         out->_is_first_frame = 0;
 272         out->_frame_count = 0;
 273         out->_file_status = END_OF_FILE;
 274
 275         tmp = cx_read(VID_CH_MODE_SEL);
 276         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 277 }
 278
 279 void cx25821_free_mem_upstream(struct cx25821_channel *chan)
 280 {
 281         struct cx25821_video_out_data *out = chan->out;
 282         struct cx25821_dev *dev = chan->dev;
 283
 284         if (out->_is_running)
 285                 cx25821_stop_upstream_video(chan);
 286
 287         if (out->_dma_virt_addr) {
 288                 pci_free_consistent(dev->pci, out->_risc_size,
 289                                     out->_dma_virt_addr, out->_dma_phys_addr);
 290                 out->_dma_virt_addr = NULL;
 291         }
 292
 293         if (out->_data_buf_virt_addr) {
 294                 pci_free_consistent(dev->pci, out->_data_buf_size,
 295                                     out->_data_buf_virt_addr,
 296                                     out->_data_buf_phys_addr);
 297                 out->_data_buf_virt_addr = NULL;
 298         }
 299 }
 300
 301 int cx25821_write_frame(struct cx25821_channel *chan,
 302                 const char __user *data, size_t count)
 303 {
 304         struct cx25821_video_out_data *out = chan->out;
 305         int line_size = (out->_pixel_format == PIXEL_FRMT_411) ?
 306                 Y411_LINE_SZ : Y422_LINE_SZ;
 307         int frame_size = 0;
 308         int frame_offset = 0;
 309         int curpos = out->curpos;
 310
 311         if (out->is_60hz)
 312                 frame_size = (line_size == Y411_LINE_SZ) ?
 313                         FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
 314         else
 315                 frame_size = (line_size == Y411_LINE_SZ) ?
 316                         FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 317
 318         if (curpos == 0) {
 319                 out->cur_frame_index = out->_frame_index;
 320                 if (wait_event_interruptible(out->waitq, out->cur_frame_index != out->_frame_index))
 321                         return -EINTR;
 322                 out->cur_frame_index = out->_frame_index;
 323         }
 324
 325         frame_offset = out->cur_frame_index ? frame_size : 0;
 326
 327         if (frame_size - curpos < count)
 328                 count = frame_size - curpos;
 329         if (copy_from_user((__force char *)out->_data_buf_virt_addr + frame_offset + curpos,
 330                                 data, count))
 331                 return -EFAULT;
 332         curpos += count;
 333         if (curpos == frame_size) {
 334                 out->_frame_count++;
 335                 curpos = 0;
 336         }
 337         out->curpos = curpos;
 338
 339         return count;
 340 }
 341
 342 static int cx25821_upstream_buffer_prepare(struct cx25821_channel *chan,
 343                                            const struct sram_channel *sram_ch,
 344                                            int bpl)
 345 {
 346         struct cx25821_video_out_data *out = chan->out;
 347         struct cx25821_dev *dev = chan->dev;
 348         int ret = 0;
 349         dma_addr_t dma_addr;
 350         dma_addr_t data_dma_addr;
 351
 352         if (out->_dma_virt_addr != NULL)
 353                 pci_free_consistent(dev->pci, out->upstream_riscbuf_size,
 354                                 out->_dma_virt_addr, out->_dma_phys_addr);
 355
 356         out->_dma_virt_addr = pci_alloc_consistent(dev->pci,
 357                         out->upstream_riscbuf_size, &dma_addr);
 358         out->_dma_virt_start_addr = out->_dma_virt_addr;
 359         out->_dma_phys_start_addr = dma_addr;
 360         out->_dma_phys_addr = dma_addr;
 361         out->_risc_size = out->upstream_riscbuf_size;
 362
 363         if (!out->_dma_virt_addr) {
 364                 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
 365                 return -ENOMEM;
 366         }
 367
 368         /* Clear memory at address */
 369         memset(out->_dma_virt_addr, 0, out->_risc_size);
 370
 371         if (out->_data_buf_virt_addr != NULL)
 372                 pci_free_consistent(dev->pci, out->upstream_databuf_size,
 373                                 out->_data_buf_virt_addr,
 374                                 out->_data_buf_phys_addr);
 375         /* For Video Data buffer allocation */
 376         out->_data_buf_virt_addr = pci_alloc_consistent(dev->pci,
 377                         out->upstream_databuf_size, &data_dma_addr);
 378         out->_data_buf_phys_addr = data_dma_addr;
 379         out->_data_buf_size = out->upstream_databuf_size;
 380
 381         if (!out->_data_buf_virt_addr) {
 382                 pr_err("FAILED to allocate memory for data buffer! Returning\n");
 383                 return -ENOMEM;
 384         }
 385
 386         /* Clear memory at address */
 387         memset(out->_data_buf_virt_addr, 0, out->_data_buf_size);
 388
 389         /* Create RISC programs */
 390         ret = cx25821_risc_buffer_upstream(chan, dev->pci, 0, bpl,
 391                         out->_lines_count);
 392         if (ret < 0) {
 393                 pr_info("Failed creating Video Upstream Risc programs!\n");
 394                 goto error;
 395         }
 396
 397         return 0;
 398
 399 error:
 400         return ret;
 401 }
 402
 403 static int cx25821_video_upstream_irq(struct cx25821_channel *chan, u32 status)
 404 {
 405         struct cx25821_video_out_data *out = chan->out;
 406         struct cx25821_dev *dev = chan->dev;
 407         u32 int_msk_tmp;
 408         const struct sram_channel *channel = chan->sram_channels;
 409         int singlefield_lines = NTSC_FIELD_HEIGHT;
 410         int line_size_in_bytes = Y422_LINE_SZ;
 411         int odd_risc_prog_size = 0;
 412         dma_addr_t risc_phys_jump_addr;
 413         __le32 *rp;
 414
 415         if (status & FLD_VID_SRC_RISC1) {
 416                 /* We should only process one program per call */
 417                 u32 prog_cnt = cx_read(channel->gpcnt);
 418
 419                 /* Since we've identified our IRQ, clear our bits from the
 420                  * interrupt mask and interrupt status registers */
 421                 int_msk_tmp = cx_read(channel->int_msk);
 422                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
 423                 cx_write(channel->int_stat, _intr_msk);
 424
 425                 wake_up(&out->waitq);
 426
 427                 spin_lock(&dev->slock);
 428
 429                 out->_frame_index = prog_cnt;
 430
 431                 if (out->_is_first_frame) {
 432                         out->_is_first_frame = 0;
 433
 434                         if (out->is_60hz) {
 435                                 singlefield_lines += 1;
 436                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
 437                         } else {
 438                                 singlefield_lines = PAL_FIELD_HEIGHT;
 439                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
 440                         }
 441
 442                         if (out->_dma_virt_start_addr != NULL) {
 443                                 line_size_in_bytes =
 444                                     (out->_pixel_format ==
 445                                      PIXEL_FRMT_411) ? Y411_LINE_SZ :
 446                                     Y422_LINE_SZ;
 447                                 risc_phys_jump_addr =
 448                                     out->_dma_phys_start_addr +
 449                                     odd_risc_prog_size;
 450
 451                                 rp = cx25821_update_riscprogram(chan,
 452                                         out->_dma_virt_start_addr, TOP_OFFSET,
 453                                         line_size_in_bytes, 0x0,
 454                                         singlefield_lines, FIFO_DISABLE,
 455                                         ODD_FIELD);
 456
 457                                 /* Jump to Even Risc program of 1st Frame */
 458                                 *(rp++) = cpu_to_le32(RISC_JUMP);
 459                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 460                                 *(rp++) = cpu_to_le32(0);
 461                         }
 462                 }
 463
 464                 spin_unlock(&dev->slock);
 465         } else {
 466                 if (status & FLD_VID_SRC_UF)
 467                         pr_err("%s(): Video Received Underflow Error Interrupt!\n",
 468                                __func__);
 469
 470                 if (status & FLD_VID_SRC_SYNC)
 471                         pr_err("%s(): Video Received Sync Error Interrupt!\n",
 472                                __func__);
 473
 474                 if (status & FLD_VID_SRC_OPC_ERR)
 475                         pr_err("%s(): Video Received OpCode Error Interrupt!\n",
 476                                __func__);
 477         }
 478
 479         if (out->_file_status == END_OF_FILE) {
 480                 pr_err("EOF Channel 1 Framecount = %d\n", out->_frame_count);
 481                 return -1;
 482         }
 483         /* ElSE, set the interrupt mask register, re-enable irq. */
 484         int_msk_tmp = cx_read(channel->int_msk);
 485         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
 486
 487         return 0;
 488 }
 489
 490 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
 491 {
 492         struct cx25821_channel *chan = dev_id;
 493         struct cx25821_dev *dev = chan->dev;
 494         u32 vid_status;
 495         int handled = 0;
 496         const struct sram_channel *sram_ch;
 497
 498         if (!dev)
 499                 return -1;
 500
 501         sram_ch = chan->sram_channels;
 502
 503         vid_status = cx_read(sram_ch->int_stat);
 504
 505         /* Only deal with our interrupt */
 506         if (vid_status)
 507                 handled = cx25821_video_upstream_irq(chan, vid_status);
 508
 509         return IRQ_RETVAL(handled);
 510 }
 511
 512 static void cx25821_set_pixelengine(struct cx25821_channel *chan,
 513                                     const struct sram_channel *ch,
 514                                     int pix_format)
 515 {
 516         struct cx25821_video_out_data *out = chan->out;
 517         struct cx25821_dev *dev = chan->dev;
 518         int width = WIDTH_D1;
 519         int height = out->_lines_count;
 520         int num_lines, odd_num_lines;
 521         u32 value;
 522         int vip_mode = OUTPUT_FRMT_656;
 523
 524         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
 525         value &= 0xFFFFFFEF;
 526         value |= out->is_60hz ? 0 : 0x10;
 527         cx_write(ch->vid_fmt_ctl, value);
 528
 529         /* set number of active pixels in each line.
 530          * Default is 720 pixels in both NTSC and PAL format */
 531         cx_write(ch->vid_active_ctl1, width);
 532
 533         num_lines = (height / 2) & 0x3FF;
 534         odd_num_lines = num_lines;
 535
 536         if (out->is_60hz)
 537                 odd_num_lines += 1;
 538
 539         value = (num_lines << 16) | odd_num_lines;
 540
 541         /* set number of active lines in field 0 (top) and field 1 (bottom) */
 542         cx_write(ch->vid_active_ctl2, value);
 543
 544         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
 545 }
 546
 547 static int cx25821_start_video_dma_upstream(struct cx25821_channel *chan,
 548                                             const struct sram_channel *sram_ch)
 549 {
 550         struct cx25821_video_out_data *out = chan->out;
 551         struct cx25821_dev *dev = chan->dev;
 552         u32 tmp = 0;
 553         int err = 0;
 554
 555         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
 556          * channel A-C
 557          */
 558         tmp = cx_read(VID_CH_MODE_SEL);
 559         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 560
 561         /* Set the physical start address of the RISC program in the initial
 562          * program counter(IPC) member of the cmds.
 563          */
 564         cx_write(sram_ch->cmds_start + 0, out->_dma_phys_addr);
 565         /* Risc IPC High 64 bits 63-32 */
 566         cx_write(sram_ch->cmds_start + 4, 0);
 567
 568         /* reset counter */
 569         cx_write(sram_ch->gpcnt_ctl, 3);
 570
 571         /* Clear our bits from the interrupt status register. */
 572         cx_write(sram_ch->int_stat, _intr_msk);
 573
 574         /* Set the interrupt mask register, enable irq. */
 575         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
 576         tmp = cx_read(sram_ch->int_msk);
 577         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
 578
 579         err = request_irq(dev->pci->irq, cx25821_upstream_irq,
 580                         IRQF_SHARED, dev->name, chan);
 581         if (err < 0) {
 582                 pr_err("%s: can't get upstream IRQ %d\n",
 583                        dev->name, dev->pci->irq);
 584                 goto fail_irq;
 585         }
 586
 587         /* Start the DMA  engine */
 588         tmp = cx_read(sram_ch->dma_ctl);
 589         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
 590
 591         out->_is_running = 1;
 592         out->_is_first_frame = 1;
 593
 594         return 0;
 595
 596 fail_irq:
 597         cx25821_dev_unregister(dev);
 598         return err;
 599 }
 600
 601 int cx25821_vidupstream_init(struct cx25821_channel *chan,
 602                                  int pixel_format)
 603 {
 604         struct cx25821_video_out_data *out = chan->out;
 605         struct cx25821_dev *dev = chan->dev;
 606         const struct sram_channel *sram_ch;
 607         u32 tmp;
 608         int err = 0;
 609         int data_frame_size = 0;
 610         int risc_buffer_size = 0;
 611
 612         if (out->_is_running) {
 613                 pr_info("Video Channel is still running so return!\n");
 614                 return 0;
 615         }
 616
 617         sram_ch = chan->sram_channels;
 618
 619         out->is_60hz = dev->tvnorm & V4L2_STD_525_60;
 620
 621         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
 622          * channel A-C
 623          */
 624         tmp = cx_read(VID_CH_MODE_SEL);
 625         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 626
 627         out->_is_running = 0;
 628         out->_frame_count = 0;
 629         out->_file_status = RESET_STATUS;
 630         out->_lines_count = out->is_60hz ? 480 : 576;
 631         out->_pixel_format = pixel_format;
 632         out->_line_size = (out->_pixel_format == PIXEL_FRMT_422) ?
 633                 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 634         data_frame_size = out->is_60hz ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
 635         risc_buffer_size = out->is_60hz ?
 636                 NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
 637
 638         out->_is_running = 0;
 639         out->_frame_count = 0;
 640         out->_file_status = RESET_STATUS;
 641         out->_lines_count = out->is_60hz ? 480 : 576;
 642         out->_pixel_format = pixel_format;
 643         out->_line_size = (out->_pixel_format == PIXEL_FRMT_422) ?
 644                 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 645         out->curpos = 0;
 646         init_waitqueue_head(&out->waitq);
 647
 648         err = cx25821_sram_channel_setup_upstream(dev, sram_ch,
 649                         out->_line_size, 0);
 650
 651         /* setup fifo + format */
 652         cx25821_set_pixelengine(chan, sram_ch, out->_pixel_format);
 653
 654         out->upstream_riscbuf_size = risc_buffer_size * 2;
 655         out->upstream_databuf_size = data_frame_size * 2;
 656
 657         /* Allocating buffers and prepare RISC program */
 658         err = cx25821_upstream_buffer_prepare(chan, sram_ch, out->_line_size);
 659         if (err < 0) {
 660                 pr_err("%s: Failed to set up Video upstream buffers!\n",
 661                        dev->name);
 662                 goto error;
 663         }
 664
 665         cx25821_start_video_dma_upstream(chan, sram_ch);
 666
 667         return 0;
 668
 669 error:
 670         cx25821_dev_unregister(dev);
 671
 672         return err;
 673 }