1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013 - 2020 Intel Corporation
5 #include <linux/clkdev.h>
6 #include <linux/clk-provider.h>
7 #include <linux/completion.h>
8 #include <linux/debugfs.h>
9 #include <linux/device.h>
10 #include <linux/delay.h>
11 #include <linux/elf.h>
12 #include <linux/errno.h>
13 #include <linux/firmware.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/pm_runtime.h>
19 #include <media/ipu-isys.h>
23 #include "ipu-buttress.h"
24 #include "ipu-platform-buttress-regs.h"
27 #define BOOTLOADER_STATUS_OFFSET 0x15c
29 #define BOOTLOADER_MAGIC_KEY 0xb00710ad
31 #define ENTRY BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE1
32 #define EXIT BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE2
33 #define QUERY BUTTRESS_IU2CSECSR_IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE
35 #define BUTTRESS_TSC_SYNC_RESET_TRIAL_MAX 10
37 #define BUTTRESS_CSE_BOOTLOAD_TIMEOUT 5000000
38 #define BUTTRESS_CSE_AUTHENTICATE_TIMEOUT 10000000
39 #define BUTTRESS_CSE_FWRESET_TIMEOUT 100000
41 #define BUTTRESS_IPC_TX_TIMEOUT 1000
42 #define BUTTRESS_IPC_RESET_TIMEOUT 2000
43 #define BUTTRESS_IPC_RX_TIMEOUT 1000
44 #define BUTTRESS_IPC_VALIDITY_TIMEOUT 1000000
45 #define BUTTRESS_TSC_SYNC_TIMEOUT 5000
47 #define IPU_BUTTRESS_TSC_LIMIT 500 /* 26 us @ 19.2 MHz */
48 #define IPU_BUTTRESS_TSC_RETRY 10
50 #define BUTTRESS_CSE_IPC_RESET_RETRY 4
52 #define BUTTRESS_IPC_CMD_SEND_RETRY 1
54 static const u32 ipu_adev_irq_mask
[] = {
55 BUTTRESS_ISR_IS_IRQ
, BUTTRESS_ISR_PS_IRQ
58 int ipu_buttress_ipc_reset(struct ipu_device
*isp
, struct ipu_buttress_ipc
*ipc
)
60 struct ipu_buttress
*b
= &isp
->buttress
;
61 unsigned int retries
= BUTTRESS_IPC_RESET_TIMEOUT
;
62 u32 val
= 0, csr_in_clr
;
64 if (!isp
->secure_mode
) {
65 dev_info(&isp
->pdev
->dev
, "Skip ipc reset for non-secure mode");
69 mutex_lock(&b
->ipc_mutex
);
71 /* Clear-by-1 CSR (all bits), corresponding internal states. */
72 val
= readl(isp
->base
+ ipc
->csr_in
);
73 writel(val
, isp
->base
+ ipc
->csr_in
);
75 /* Set peer CSR bit IPC_PEER_COMP_ACTIONS_RST_PHASE1 */
76 writel(ENTRY
, isp
->base
+ ipc
->csr_out
);
78 * Clear-by-1 all CSR bits EXCEPT following
80 * A. IPC_PEER_COMP_ACTIONS_RST_PHASE1.
81 * B. IPC_PEER_COMP_ACTIONS_RST_PHASE2.
82 * C. Possibly custom bits, depending on
85 csr_in_clr
= BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ
|
86 BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID
|
87 BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ
| QUERY
;
90 usleep_range(400, 500);
91 val
= readl(isp
->base
+ ipc
->csr_in
);
94 case (ENTRY
| EXIT
| QUERY
):
95 dev_dbg(&isp
->pdev
->dev
,
96 "%s:%s & %s\n", __func__
,
97 "IPC_PEER_COMP_ACTIONS_RST_PHASE1",
98 "IPC_PEER_COMP_ACTIONS_RST_PHASE2");
100 * 1) Clear-by-1 CSR bits
101 * (IPC_PEER_COMP_ACTIONS_RST_PHASE1,
102 * IPC_PEER_COMP_ACTIONS_RST_PHASE2).
103 * 2) Set peer CSR bit
104 * IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE.
106 writel(ENTRY
| EXIT
, isp
->base
+ ipc
->csr_in
);
107 writel(QUERY
, isp
->base
+ ipc
->csr_out
);
110 case (ENTRY
| QUERY
):
111 dev_dbg(&isp
->pdev
->dev
,
112 "%s:IPC_PEER_COMP_ACTIONS_RST_PHASE1\n",
115 * 1) Clear-by-1 CSR bits
116 * (IPC_PEER_COMP_ACTIONS_RST_PHASE1,
117 * IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE).
118 * 2) Set peer CSR bit
119 * IPC_PEER_COMP_ACTIONS_RST_PHASE1.
121 writel(ENTRY
| QUERY
, isp
->base
+ ipc
->csr_in
);
122 writel(ENTRY
, isp
->base
+ ipc
->csr_out
);
126 dev_dbg(&isp
->pdev
->dev
,
127 "%s: IPC_PEER_COMP_ACTIONS_RST_PHASE2\n",
131 * IPC_PEER_COMP_ACTIONS_RST_PHASE2.
132 * 1) Clear incoming doorbell.
133 * 2) Clear-by-1 all CSR bits EXCEPT following
135 * A. IPC_PEER_COMP_ACTIONS_RST_PHASE1.
136 * B. IPC_PEER_COMP_ACTIONS_RST_PHASE2.
137 * C. Possibly custom bits, depending on
139 * 3) Set peer CSR bit
140 * IPC_PEER_COMP_ACTIONS_RST_PHASE2.
142 writel(EXIT
, isp
->base
+ ipc
->csr_in
);
143 writel(0, isp
->base
+ ipc
->db0_in
);
144 writel(csr_in_clr
, isp
->base
+ ipc
->csr_in
);
145 writel(EXIT
, isp
->base
+ ipc
->csr_out
);
148 * Read csr_in again to make sure if RST_PHASE2 is done.
149 * If csr_in is QUERY, it should be handled again.
151 usleep_range(200, 300);
152 val
= readl(isp
->base
+ ipc
->csr_in
);
154 dev_dbg(&isp
->pdev
->dev
,
155 "%s: RST_PHASE2 retry csr_in = %x\n",
159 mutex_unlock(&b
->ipc_mutex
);
162 dev_dbg(&isp
->pdev
->dev
,
163 "%s: %s\n", __func__
,
164 "IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE");
166 * 1) Clear-by-1 CSR bit
167 * IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE.
168 * 2) Set peer CSR bit
169 * IPC_PEER_COMP_ACTIONS_RST_PHASE1
171 writel(QUERY
, isp
->base
+ ipc
->csr_in
);
172 writel(ENTRY
, isp
->base
+ ipc
->csr_out
);
175 dev_dbg_ratelimited(&isp
->pdev
->dev
,
176 "%s: unexpected CSR 0x%x\n",
182 mutex_unlock(&b
->ipc_mutex
);
183 dev_err(&isp
->pdev
->dev
, "Timed out while waiting for CSE\n");
189 ipu_buttress_ipc_validity_close(struct ipu_device
*isp
,
190 struct ipu_buttress_ipc
*ipc
)
192 /* Set bit 5 in CSE CSR */
193 writel(BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ
,
194 isp
->base
+ ipc
->csr_out
);
198 ipu_buttress_ipc_validity_open(struct ipu_device
*isp
,
199 struct ipu_buttress_ipc
*ipc
)
201 unsigned int mask
= BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID
;
202 unsigned int tout
= BUTTRESS_IPC_VALIDITY_TIMEOUT
;
207 /* Set bit 3 in CSE CSR */
208 writel(BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ
,
209 isp
->base
+ ipc
->csr_out
);
211 addr
= isp
->base
+ ipc
->csr_in
;
212 ret
= readl_poll_timeout(addr
, val
, val
& mask
, 200, tout
);
215 dev_err(&isp
->pdev
->dev
, "CSE validity timeout 0x%x\n", val
);
216 ipu_buttress_ipc_validity_close(isp
, ipc
);
222 static void ipu_buttress_ipc_recv(struct ipu_device
*isp
,
223 struct ipu_buttress_ipc
*ipc
, u32
*ipc_msg
)
226 *ipc_msg
= readl(isp
->base
+ ipc
->data0_in
);
227 writel(0, isp
->base
+ ipc
->db0_in
);
230 static int ipu_buttress_ipc_send_bulk(struct ipu_device
*isp
,
231 enum ipu_buttress_ipc_domain ipc_domain
,
232 struct ipu_ipc_buttress_bulk_msg
*msgs
,
235 struct ipu_buttress
*b
= &isp
->buttress
;
236 struct ipu_buttress_ipc
*ipc
;
237 unsigned long tx_timeout_jiffies
, rx_timeout_jiffies
;
241 unsigned int i
, retry
= BUTTRESS_IPC_CMD_SEND_RETRY
;
243 ipc
= ipc_domain
== IPU_BUTTRESS_IPC_CSE
? &b
->cse
: &b
->ish
;
245 mutex_lock(&b
->ipc_mutex
);
247 ret
= ipu_buttress_ipc_validity_open(isp
, ipc
);
249 dev_err(&isp
->pdev
->dev
, "IPC validity open failed\n");
253 tx_timeout_jiffies
= msecs_to_jiffies(BUTTRESS_IPC_TX_TIMEOUT
);
254 rx_timeout_jiffies
= msecs_to_jiffies(BUTTRESS_IPC_RX_TIMEOUT
);
256 for (i
= 0; i
< size
; i
++) {
257 reinit_completion(&ipc
->send_complete
);
258 if (msgs
[i
].require_resp
)
259 reinit_completion(&ipc
->recv_complete
);
261 dev_dbg(&isp
->pdev
->dev
, "bulk IPC command: 0x%x\n",
263 writel(msgs
[i
].cmd
, isp
->base
+ ipc
->data0_out
);
265 val
= BUTTRESS_IU2CSEDB0_BUSY
| msgs
[i
].cmd_size
;
267 writel(val
, isp
->base
+ ipc
->db0_out
);
269 tout
= wait_for_completion_timeout(&ipc
->send_complete
,
272 dev_err(&isp
->pdev
->dev
, "send IPC response timeout\n");
279 * WORKAROUND: Sometimes CSE is not
280 * responding on first try, try again.
282 writel(0, isp
->base
+ ipc
->db0_out
);
287 retry
= BUTTRESS_IPC_CMD_SEND_RETRY
;
289 if (!msgs
[i
].require_resp
)
292 tout
= wait_for_completion_timeout(&ipc
->recv_complete
,
295 dev_err(&isp
->pdev
->dev
, "recv IPC response timeout\n");
300 if (ipc
->nack_mask
&&
301 (ipc
->recv_data
& ipc
->nack_mask
) == ipc
->nack
) {
302 dev_err(&isp
->pdev
->dev
,
303 "IPC NACK for cmd 0x%x\n", msgs
[i
].cmd
);
308 if (ipc
->recv_data
!= msgs
[i
].expected_resp
) {
309 dev_err(&isp
->pdev
->dev
,
310 "expected resp: 0x%x, IPC response: 0x%x ",
311 msgs
[i
].expected_resp
, ipc
->recv_data
);
317 dev_dbg(&isp
->pdev
->dev
, "bulk IPC commands done\n");
320 ipu_buttress_ipc_validity_close(isp
, ipc
);
321 mutex_unlock(&b
->ipc_mutex
);
326 ipu_buttress_ipc_send(struct ipu_device
*isp
,
327 enum ipu_buttress_ipc_domain ipc_domain
,
328 u32 ipc_msg
, u32 size
, bool require_resp
,
331 struct ipu_ipc_buttress_bulk_msg msg
= {
334 .require_resp
= require_resp
,
335 .expected_resp
= expected_resp
,
338 return ipu_buttress_ipc_send_bulk(isp
, ipc_domain
, &msg
, 1);
341 static irqreturn_t
ipu_buttress_call_isr(struct ipu_bus_device
*adev
)
343 irqreturn_t ret
= IRQ_WAKE_THREAD
;
345 if (!adev
|| !adev
->adrv
)
349 ret
= adev
->adrv
->isr(adev
);
351 if (ret
== IRQ_WAKE_THREAD
&& !adev
->adrv
->isr_threaded
)
354 adev
->adrv
->wake_isr_thread
= (ret
== IRQ_WAKE_THREAD
);
359 irqreturn_t
ipu_buttress_isr(int irq
, void *isp_ptr
)
361 struct ipu_device
*isp
= isp_ptr
;
362 struct ipu_bus_device
*adev
[] = { isp
->isys
, isp
->psys
};
363 struct ipu_buttress
*b
= &isp
->buttress
;
364 irqreturn_t ret
= IRQ_NONE
;
365 u32 disable_irqs
= 0;
367 u32 reg_irq_sts
= BUTTRESS_REG_ISR_STATUS
;
370 pm_runtime_get(&isp
->pdev
->dev
);
372 if (!pm_runtime_active(&isp
->pdev
->dev
)) {
373 irq_status
= readl(isp
->base
+ reg_irq_sts
);
374 writel(irq_status
, isp
->base
+ BUTTRESS_REG_ISR_CLEAR
);
375 pm_runtime_put(&isp
->pdev
->dev
);
379 irq_status
= readl(isp
->base
+ reg_irq_sts
);
381 pm_runtime_put(&isp
->pdev
->dev
);
386 writel(irq_status
, isp
->base
+ BUTTRESS_REG_ISR_CLEAR
);
388 for (i
= 0; i
< ARRAY_SIZE(ipu_adev_irq_mask
); i
++) {
389 if (irq_status
& ipu_adev_irq_mask
[i
]) {
390 irqreturn_t r
= ipu_buttress_call_isr(adev
[i
]);
392 if (r
== IRQ_WAKE_THREAD
) {
393 ret
= IRQ_WAKE_THREAD
;
394 disable_irqs
|= ipu_adev_irq_mask
[i
];
395 } else if (ret
== IRQ_NONE
&&
402 if (irq_status
& (BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING
|
403 BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING
|
404 BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE
|
405 BUTTRESS_ISR_IPC_EXEC_DONE_BY_ISH
|
406 BUTTRESS_ISR_SAI_VIOLATION
) &&
410 if (irq_status
& BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING
) {
411 dev_dbg(&isp
->pdev
->dev
,
412 "BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING\n");
413 ipu_buttress_ipc_recv(isp
, &b
->cse
, &b
->cse
.recv_data
);
414 complete(&b
->cse
.recv_complete
);
417 if (irq_status
& BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING
) {
418 dev_dbg(&isp
->pdev
->dev
,
419 "BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING\n");
420 ipu_buttress_ipc_recv(isp
, &b
->ish
, &b
->ish
.recv_data
);
421 complete(&b
->ish
.recv_complete
);
424 if (irq_status
& BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE
) {
425 dev_dbg(&isp
->pdev
->dev
,
426 "BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE\n");
427 complete(&b
->cse
.send_complete
);
430 if (irq_status
& BUTTRESS_ISR_IPC_EXEC_DONE_BY_ISH
) {
431 dev_dbg(&isp
->pdev
->dev
,
432 "BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE\n");
433 complete(&b
->ish
.send_complete
);
436 if (irq_status
& BUTTRESS_ISR_SAI_VIOLATION
&&
437 ipu_buttress_get_secure_mode(isp
)) {
438 dev_err(&isp
->pdev
->dev
,
439 "BUTTRESS_ISR_SAI_VIOLATION\n");
443 irq_status
= readl(isp
->base
+ reg_irq_sts
);
444 } while (irq_status
&& !isp
->flr_done
);
447 writel(BUTTRESS_IRQS
& ~disable_irqs
,
448 isp
->base
+ BUTTRESS_REG_ISR_ENABLE
);
450 pm_runtime_put(&isp
->pdev
->dev
);
455 irqreturn_t
ipu_buttress_isr_threaded(int irq
, void *isp_ptr
)
457 struct ipu_device
*isp
= isp_ptr
;
458 struct ipu_bus_device
*adev
[] = { isp
->isys
, isp
->psys
};
459 irqreturn_t ret
= IRQ_NONE
;
462 dev_dbg(&isp
->pdev
->dev
, "isr: Buttress threaded interrupt handler\n");
464 for (i
= 0; i
< ARRAY_SIZE(ipu_adev_irq_mask
); i
++) {
465 if (adev
[i
] && adev
[i
]->adrv
&&
466 adev
[i
]->adrv
->wake_isr_thread
&&
467 adev
[i
]->adrv
->isr_threaded(adev
[i
]) == IRQ_HANDLED
)
471 writel(BUTTRESS_IRQS
, isp
->base
+ BUTTRESS_REG_ISR_ENABLE
);
476 int ipu_buttress_power(struct device
*dev
,
477 struct ipu_buttress_ctrl
*ctrl
, bool on
)
479 struct ipu_device
*isp
= to_ipu_bus_device(dev
)->isp
;
486 /* Until FLR completion nothing is expected to work */
490 mutex_lock(&isp
->buttress
.power_mutex
);
494 pwr_sts
= ctrl
->pwr_sts_off
<< ctrl
->pwr_sts_shift
;
496 val
= BUTTRESS_FREQ_CTL_START
|
497 ctrl
->divisor
<< ctrl
->divisor_shift
|
498 ctrl
->qos_floor
<< BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT
|
499 BUTTRESS_FREQ_CTL_ICCMAX_LEVEL
;
501 pwr_sts
= ctrl
->pwr_sts_on
<< ctrl
->pwr_sts_shift
;
504 writel(val
, isp
->base
+ ctrl
->freq_ctl
);
506 ret
= readl_poll_timeout(isp
->base
+ BUTTRESS_REG_PWR_STATE
,
507 val
, ((val
& ctrl
->pwr_sts_mask
) == pwr_sts
),
508 100, BUTTRESS_POWER_TIMEOUT
);
510 dev_err(&isp
->pdev
->dev
,
511 "Change power status timeout with 0x%x\n", val
);
513 ctrl
->started
= !ret
&& on
;
515 mutex_unlock(&isp
->buttress
.power_mutex
);
520 static bool secure_mode_enable
= 1;
521 module_param(secure_mode_enable
, bool, 0660);
522 MODULE_PARM_DESC(secure_mode
, "IPU secure mode enable");
524 void ipu_buttress_set_secure_mode(struct ipu_device
*isp
)
530 * HACK to disable possible secure mode. This can be
531 * reverted when CSE is disabling the secure mode
533 read
= readl(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
535 if (secure_mode_enable
)
536 val
= read
|= BUTTRESS_SECURITY_CTL_FW_SECURE_MODE
;
538 val
= read
& ~BUTTRESS_SECURITY_CTL_FW_SECURE_MODE
;
543 writel(val
, isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
545 /* In B0, for some registers in buttress, because of a hw bug, write
546 * might not succeed at first attempt. Write twice until the
547 * write is successful
549 writel(val
, isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
552 read
= readl(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
556 writel(val
, isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
559 dev_err(&isp
->pdev
->dev
,
560 "update security control register failed\n");
564 bool ipu_buttress_get_secure_mode(struct ipu_device
*isp
)
568 val
= readl(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
570 return val
& BUTTRESS_SECURITY_CTL_FW_SECURE_MODE
;
573 bool ipu_buttress_auth_done(struct ipu_device
*isp
)
577 if (!isp
->secure_mode
)
580 val
= readl(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
);
582 return (val
& BUTTRESS_SECURITY_CTL_FW_SETUP_MASK
) ==
583 BUTTRESS_SECURITY_CTL_AUTH_DONE
;
585 EXPORT_SYMBOL(ipu_buttress_auth_done
);
587 static void ipu_buttress_set_psys_ratio(struct ipu_device
*isp
,
588 unsigned int psys_divisor
,
589 unsigned int psys_qos_floor
)
591 struct ipu_buttress_ctrl
*ctrl
= isp
->psys
->ctrl
;
593 mutex_lock(&isp
->buttress
.power_mutex
);
595 if (ctrl
->divisor
== psys_divisor
&& ctrl
->qos_floor
== psys_qos_floor
)
596 goto out_mutex_unlock
;
598 ctrl
->divisor
= psys_divisor
;
599 ctrl
->qos_floor
= psys_qos_floor
;
603 * According to documentation driver initiates DVFS
604 * transition by writing wanted ratio, floor ratio and start
605 * bit. No need to stop PS first
607 writel(BUTTRESS_FREQ_CTL_START
|
608 ctrl
->qos_floor
<< BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT
|
609 psys_divisor
, isp
->base
+ BUTTRESS_REG_PS_FREQ_CTL
);
613 mutex_unlock(&isp
->buttress
.power_mutex
);
616 static void ipu_buttress_set_isys_ratio(struct ipu_device
*isp
,
617 unsigned int isys_divisor
)
619 struct ipu_buttress_ctrl
*ctrl
= isp
->isys
->ctrl
;
621 mutex_lock(&isp
->buttress
.power_mutex
);
623 if (ctrl
->divisor
== isys_divisor
)
624 goto out_mutex_unlock
;
626 ctrl
->divisor
= isys_divisor
;
629 writel(BUTTRESS_FREQ_CTL_START
|
630 ctrl
->qos_floor
<< BUTTRESS_FREQ_CTL_QOS_FLOOR_SHIFT
|
631 isys_divisor
, isp
->base
+ BUTTRESS_REG_IS_FREQ_CTL
);
635 mutex_unlock(&isp
->buttress
.power_mutex
);
638 static void ipu_buttress_set_psys_freq(struct ipu_device
*isp
,
641 unsigned int psys_ratio
= freq
/ BUTTRESS_PS_FREQ_STEP
;
643 if (isp
->buttress
.psys_force_ratio
)
646 ipu_buttress_set_psys_ratio(isp
, psys_ratio
, psys_ratio
);
650 ipu_buttress_add_psys_constraint(struct ipu_device
*isp
,
651 struct ipu_buttress_constraint
*constraint
)
653 struct ipu_buttress
*b
= &isp
->buttress
;
655 mutex_lock(&b
->cons_mutex
);
656 list_add(&constraint
->list
, &b
->constraints
);
658 if (constraint
->min_freq
> b
->psys_min_freq
) {
659 isp
->buttress
.psys_min_freq
= min(constraint
->min_freq
,
660 b
->psys_fused_freqs
.max_freq
);
661 ipu_buttress_set_psys_freq(isp
, b
->psys_min_freq
);
663 mutex_unlock(&b
->cons_mutex
);
665 EXPORT_SYMBOL_GPL(ipu_buttress_add_psys_constraint
);
668 ipu_buttress_remove_psys_constraint(struct ipu_device
*isp
,
669 struct ipu_buttress_constraint
*constraint
)
671 struct ipu_buttress
*b
= &isp
->buttress
;
672 struct ipu_buttress_constraint
*c
;
673 unsigned int min_freq
= 0;
675 mutex_lock(&b
->cons_mutex
);
676 list_del(&constraint
->list
);
678 if (constraint
->min_freq
>= b
->psys_min_freq
) {
679 list_for_each_entry(c
, &b
->constraints
, list
)
680 if (c
->min_freq
> min_freq
)
681 min_freq
= c
->min_freq
;
683 b
->psys_min_freq
= clamp(min_freq
,
684 b
->psys_fused_freqs
.efficient_freq
,
685 b
->psys_fused_freqs
.max_freq
);
686 ipu_buttress_set_psys_freq(isp
, b
->psys_min_freq
);
688 mutex_unlock(&b
->cons_mutex
);
690 EXPORT_SYMBOL_GPL(ipu_buttress_remove_psys_constraint
);
692 int ipu_buttress_reset_authentication(struct ipu_device
*isp
)
697 if (!isp
->secure_mode
) {
698 dev_dbg(&isp
->pdev
->dev
,
699 "Non-secure mode -> skip authentication\n");
703 writel(BUTTRESS_FW_RESET_CTL_START
, isp
->base
+
704 BUTTRESS_REG_FW_RESET_CTL
);
706 ret
= readl_poll_timeout(isp
->base
+ BUTTRESS_REG_FW_RESET_CTL
, val
,
707 val
& BUTTRESS_FW_RESET_CTL_DONE
, 500,
708 BUTTRESS_CSE_FWRESET_TIMEOUT
);
710 dev_err(&isp
->pdev
->dev
,
711 "Time out while resetting authentication state\n");
713 dev_info(&isp
->pdev
->dev
,
714 "FW reset for authentication done\n");
715 writel(0, isp
->base
+ BUTTRESS_REG_FW_RESET_CTL
);
716 /* leave some time for HW restore */
717 usleep_range(800, 1000);
723 int ipu_buttress_map_fw_image(struct ipu_bus_device
*sys
,
724 const struct firmware
*fw
, struct sg_table
*sgt
)
728 unsigned long n_pages
, i
;
731 n_pages
= PAGE_ALIGN(fw
->size
) >> PAGE_SHIFT
;
733 pages
= kmalloc_array(n_pages
, sizeof(*pages
), GFP_KERNEL
);
738 for (i
= 0; i
< n_pages
; i
++) {
739 struct page
*p
= vmalloc_to_page(addr
);
749 rval
= sg_alloc_table_from_pages(sgt
, pages
, n_pages
, 0, fw
->size
,
756 n_pages
= dma_map_sg(&sys
->dev
, sgt
->sgl
, sgt
->nents
, DMA_TO_DEVICE
);
757 if (n_pages
!= sgt
->nents
) {
763 dma_sync_sg_for_device(&sys
->dev
, sgt
->sgl
, sgt
->nents
, DMA_TO_DEVICE
);
770 EXPORT_SYMBOL_GPL(ipu_buttress_map_fw_image
);
772 int ipu_buttress_unmap_fw_image(struct ipu_bus_device
*sys
,
773 struct sg_table
*sgt
)
775 dma_unmap_sg(&sys
->dev
, sgt
->sgl
, sgt
->nents
, DMA_TO_DEVICE
);
780 EXPORT_SYMBOL_GPL(ipu_buttress_unmap_fw_image
);
782 int ipu_buttress_authenticate(struct ipu_device
*isp
)
784 struct ipu_psys_pdata
*psys_pdata
;
785 struct ipu_buttress
*b
= &isp
->buttress
;
786 u32 data
, mask
, done
, fail
;
789 if (!isp
->secure_mode
) {
790 dev_dbg(&isp
->pdev
->dev
,
791 "Non-secure mode -> skip authentication\n");
795 psys_pdata
= isp
->psys
->pdata
;
797 mutex_lock(&b
->auth_mutex
);
799 if (ipu_buttress_auth_done(isp
)) {
801 goto iunit_power_off
;
805 * Write address of FIT table to FW_SOURCE register
806 * Let's use fw address. I.e. not using FIT table yet
808 data
= lower_32_bits(isp
->pkg_dir_dma_addr
);
809 writel(data
, isp
->base
+ BUTTRESS_REG_FW_SOURCE_BASE_LO
);
811 data
= upper_32_bits(isp
->pkg_dir_dma_addr
);
812 writel(data
, isp
->base
+ BUTTRESS_REG_FW_SOURCE_BASE_HI
);
815 * Write boot_load into IU2CSEDATA0
816 * Write sizeof(boot_load) | 0x2 << CLIENT_ID to
817 * IU2CSEDB.IU2CSECMD and set IU2CSEDB.IU2CSEBUSY as
819 dev_info(&isp
->pdev
->dev
, "Sending BOOT_LOAD to CSE\n");
820 rval
= ipu_buttress_ipc_send(isp
, IPU_BUTTRESS_IPC_CSE
,
821 BUTTRESS_IU2CSEDATA0_IPC_BOOT_LOAD
,
823 BUTTRESS_CSE2IUDATA0_IPC_BOOT_LOAD_DONE
);
825 dev_err(&isp
->pdev
->dev
, "CSE boot_load failed\n");
826 goto iunit_power_off
;
829 mask
= BUTTRESS_SECURITY_CTL_FW_SETUP_MASK
;
830 done
= BUTTRESS_SECURITY_CTL_FW_SETUP_DONE
;
831 fail
= BUTTRESS_SECURITY_CTL_AUTH_FAILED
;
832 rval
= readl_poll_timeout(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
, data
,
833 ((data
& mask
) == done
||
834 (data
& mask
) == fail
), 500,
835 BUTTRESS_CSE_BOOTLOAD_TIMEOUT
);
837 dev_err(&isp
->pdev
->dev
, "CSE boot_load timeout\n");
838 goto iunit_power_off
;
841 data
= readl(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
) & mask
;
843 dev_err(&isp
->pdev
->dev
, "CSE auth failed\n");
845 goto iunit_power_off
;
848 rval
= readl_poll_timeout(psys_pdata
->base
+ BOOTLOADER_STATUS_OFFSET
,
849 data
, data
== BOOTLOADER_MAGIC_KEY
, 500,
850 BUTTRESS_CSE_BOOTLOAD_TIMEOUT
);
852 dev_err(&isp
->pdev
->dev
, "Expect magic number timeout 0x%x\n",
854 goto iunit_power_off
;
858 * Write authenticate_run into IU2CSEDATA0
859 * Write sizeof(boot_load) | 0x2 << CLIENT_ID to
860 * IU2CSEDB.IU2CSECMD and set IU2CSEDB.IU2CSEBUSY as
862 dev_info(&isp
->pdev
->dev
, "Sending AUTHENTICATE_RUN to CSE\n");
863 rval
= ipu_buttress_ipc_send(isp
, IPU_BUTTRESS_IPC_CSE
,
864 BUTTRESS_IU2CSEDATA0_IPC_AUTH_RUN
,
866 BUTTRESS_CSE2IUDATA0_IPC_AUTH_RUN_DONE
);
868 dev_err(&isp
->pdev
->dev
, "CSE authenticate_run failed\n");
869 goto iunit_power_off
;
872 done
= BUTTRESS_SECURITY_CTL_AUTH_DONE
;
873 rval
= readl_poll_timeout(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
, data
,
874 ((data
& mask
) == done
||
875 (data
& mask
) == fail
), 500,
876 BUTTRESS_CSE_AUTHENTICATE_TIMEOUT
);
878 dev_err(&isp
->pdev
->dev
, "CSE authenticate timeout\n");
879 goto iunit_power_off
;
882 data
= readl(isp
->base
+ BUTTRESS_REG_SECURITY_CTL
) & mask
;
884 dev_err(&isp
->pdev
->dev
, "CSE boot_load failed\n");
886 goto iunit_power_off
;
889 dev_info(&isp
->pdev
->dev
, "CSE authenticate_run done\n");
892 mutex_unlock(&b
->auth_mutex
);
897 static int ipu_buttress_send_tsc_request(struct ipu_device
*isp
)
899 u32 val
, mask
, shift
, done
;
902 mask
= BUTTRESS_PWR_STATE_HH_STATUS_MASK
;
903 shift
= BUTTRESS_PWR_STATE_HH_STATUS_SHIFT
;
905 writel(BUTTRESS_FABRIC_CMD_START_TSC_SYNC
,
906 isp
->base
+ BUTTRESS_REG_FABRIC_CMD
);
908 val
= readl(isp
->base
+ BUTTRESS_REG_PWR_STATE
);
909 val
= (val
& mask
) >> shift
;
910 if (val
== BUTTRESS_PWR_STATE_HH_STATE_ERR
) {
911 dev_err(&isp
->pdev
->dev
, "Start tsc sync failed\n");
915 done
= BUTTRESS_PWR_STATE_HH_STATE_DONE
;
916 ret
= readl_poll_timeout(isp
->base
+ BUTTRESS_REG_PWR_STATE
, val
,
917 ((val
& mask
) >> shift
== done
), 500,
918 BUTTRESS_TSC_SYNC_TIMEOUT
);
920 dev_err(&isp
->pdev
->dev
, "Start tsc sync timeout\n");
925 int ipu_buttress_start_tsc_sync(struct ipu_device
*isp
)
929 for (i
= 0; i
< BUTTRESS_TSC_SYNC_RESET_TRIAL_MAX
; i
++) {
932 ret
= ipu_buttress_send_tsc_request(isp
);
933 if (ret
== -ETIMEDOUT
) {
935 /* set tsw soft reset */
936 val
= readl(isp
->base
+ BUTTRESS_REG_TSW_CTL
);
937 val
= val
| BUTTRESS_TSW_CTL_SOFT_RESET
;
938 writel(val
, isp
->base
+ BUTTRESS_REG_TSW_CTL
);
939 /* clear tsw soft reset */
940 val
= val
& (~BUTTRESS_TSW_CTL_SOFT_RESET
);
941 writel(val
, isp
->base
+ BUTTRESS_REG_TSW_CTL
);
948 dev_err(&isp
->pdev
->dev
, "TSC sync failed(timeout)\n");
952 EXPORT_SYMBOL(ipu_buttress_start_tsc_sync
);
954 struct clk_ipu_sensor
{
955 struct ipu_device
*isp
;
961 #define to_clk_ipu_sensor(_hw) container_of(_hw, struct clk_ipu_sensor, hw)
963 int ipu_buttress_tsc_read(struct ipu_device
*isp
, u64
*val
)
965 u32 tsc_hi_1
, tsc_hi_2
, tsc_lo
;
968 local_irq_save(flags
);
969 tsc_hi_1
= readl(isp
->base
+ BUTTRESS_REG_TSC_HI
);
970 tsc_lo
= readl(isp
->base
+ BUTTRESS_REG_TSC_LO
);
971 tsc_hi_2
= readl(isp
->base
+ BUTTRESS_REG_TSC_HI
);
972 if (tsc_hi_1
== tsc_hi_2
) {
973 *val
= (u64
)tsc_hi_1
<< 32 | tsc_lo
;
975 /* Check if TSC has rolled over */
976 if (tsc_lo
& BIT(31))
977 *val
= (u64
)tsc_hi_1
<< 32 | tsc_lo
;
979 *val
= (u64
)tsc_hi_2
<< 32 | tsc_lo
;
981 local_irq_restore(flags
);
985 EXPORT_SYMBOL_GPL(ipu_buttress_tsc_read
);
987 #ifdef CONFIG_DEBUG_FS
989 static int ipu_buttress_reg_open(struct inode
*inode
, struct file
*file
)
991 if (!inode
->i_private
)
994 file
->private_data
= inode
->i_private
;
998 static ssize_t
ipu_buttress_reg_read(struct file
*file
, char __user
*buf
,
999 size_t count
, loff_t
*ppos
)
1001 struct debugfs_reg32
*reg
= file
->private_data
;
1003 u32 val
= readl((void __iomem
*)reg
->offset
);
1004 int len
= scnprintf(tmp
, sizeof(tmp
), "0x%08x", val
);
1006 return simple_read_from_buffer(buf
, len
, ppos
, &tmp
, len
);
1009 static ssize_t
ipu_buttress_reg_write(struct file
*file
,
1010 const char __user
*buf
,
1011 size_t count
, loff_t
*ppos
)
1013 struct debugfs_reg32
*reg
= file
->private_data
;
1017 rval
= kstrtou32_from_user(buf
, count
, 0, &val
);
1021 writel(val
, (void __iomem
*)reg
->offset
);
1026 static struct debugfs_reg32 buttress_regs
[] = {
1027 {"IU2CSEDB0", BUTTRESS_REG_IU2CSEDB0
},
1028 {"IU2CSEDATA0", BUTTRESS_REG_IU2CSEDATA0
},
1029 {"CSE2IUDB0", BUTTRESS_REG_CSE2IUDB0
},
1030 {"CSE2IUDATA0", BUTTRESS_REG_CSE2IUDATA0
},
1031 {"CSE2IUCSR", BUTTRESS_REG_CSE2IUCSR
},
1032 {"IU2CSECSR", BUTTRESS_REG_IU2CSECSR
},
1035 static const struct file_operations ipu_buttress_reg_fops
= {
1036 .owner
= THIS_MODULE
,
1037 .open
= ipu_buttress_reg_open
,
1038 .read
= ipu_buttress_reg_read
,
1039 .write
= ipu_buttress_reg_write
,
1042 static int ipu_buttress_start_tsc_sync_set(void *data
, u64 val
)
1044 struct ipu_device
*isp
= data
;
1046 return ipu_buttress_start_tsc_sync(isp
);
1049 DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_start_tsc_sync_fops
, NULL
,
1050 ipu_buttress_start_tsc_sync_set
, "%llu\n");
1052 static int ipu_buttress_tsc_get(void *data
, u64
*val
)
1054 return ipu_buttress_tsc_read(data
, val
);
1056 DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_tsc_fops
, ipu_buttress_tsc_get
,
1059 static int ipu_buttress_psys_force_freq_get(void *data
, u64
*val
)
1061 struct ipu_device
*isp
= data
;
1063 *val
= isp
->buttress
.psys_force_ratio
* BUTTRESS_PS_FREQ_STEP
;
1068 static int ipu_buttress_psys_force_freq_set(void *data
, u64 val
)
1070 struct ipu_device
*isp
= data
;
1072 if (val
&& (val
< BUTTRESS_MIN_FORCE_PS_FREQ
||
1073 val
> BUTTRESS_MAX_FORCE_PS_FREQ
))
1076 do_div(val
, BUTTRESS_PS_FREQ_STEP
);
1077 isp
->buttress
.psys_force_ratio
= val
;
1079 if (isp
->buttress
.psys_force_ratio
)
1080 ipu_buttress_set_psys_ratio(isp
,
1081 isp
->buttress
.psys_force_ratio
,
1082 isp
->buttress
.psys_force_ratio
);
1084 ipu_buttress_set_psys_freq(isp
, isp
->buttress
.psys_min_freq
);
1089 static int ipu_buttress_isys_freq_get(void *data
, u64
*val
)
1091 struct ipu_device
*isp
= data
;
1095 rval
= pm_runtime_get_sync(&isp
->isys
->dev
);
1097 pm_runtime_put(&isp
->isys
->dev
);
1098 dev_err(&isp
->pdev
->dev
, "Runtime PM failed (%d)\n", rval
);
1102 reg_val
= readl(isp
->base
+ BUTTRESS_REG_IS_FREQ_CTL
);
1104 pm_runtime_put(&isp
->isys
->dev
);
1106 *val
= IPU_IS_FREQ_RATIO_BASE
*
1107 (reg_val
& IPU_BUTTRESS_IS_FREQ_CTL_DIVISOR_MASK
);
1112 static int ipu_buttress_isys_freq_set(void *data
, u64 val
)
1114 struct ipu_device
*isp
= data
;
1117 if (val
< BUTTRESS_MIN_FORCE_IS_FREQ
||
1118 val
> BUTTRESS_MAX_FORCE_IS_FREQ
)
1121 rval
= pm_runtime_get_sync(&isp
->isys
->dev
);
1123 pm_runtime_put(&isp
->isys
->dev
);
1124 dev_err(&isp
->pdev
->dev
, "Runtime PM failed (%d)\n", rval
);
1128 do_div(val
, BUTTRESS_IS_FREQ_STEP
);
1130 ipu_buttress_set_isys_ratio(isp
, val
);
1132 pm_runtime_put(&isp
->isys
->dev
);
1137 DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_psys_force_freq_fops
,
1138 ipu_buttress_psys_force_freq_get
,
1139 ipu_buttress_psys_force_freq_set
, "%llu\n");
1141 DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_psys_freq_fops
,
1142 ipu_buttress_psys_freq_get
, NULL
, "%llu\n");
1144 DEFINE_SIMPLE_ATTRIBUTE(ipu_buttress_isys_freq_fops
,
1145 ipu_buttress_isys_freq_get
,
1146 ipu_buttress_isys_freq_set
, "%llu\n");
1148 int ipu_buttress_debugfs_init(struct ipu_device
*isp
)
1150 struct debugfs_reg32
*reg
=
1151 devm_kcalloc(&isp
->pdev
->dev
, ARRAY_SIZE(buttress_regs
),
1152 sizeof(*reg
), GFP_KERNEL
);
1153 struct dentry
*dir
, *file
;
1159 dir
= debugfs_create_dir("buttress", isp
->ipu_dir
);
1163 for (i
= 0; i
< ARRAY_SIZE(buttress_regs
); i
++, reg
++) {
1164 reg
->offset
= (unsigned long)isp
->base
+
1165 buttress_regs
[i
].offset
;
1166 reg
->name
= buttress_regs
[i
].name
;
1167 file
= debugfs_create_file(reg
->name
, 0700,
1168 dir
, reg
, &ipu_buttress_reg_fops
);
1173 file
= debugfs_create_file("start_tsc_sync", 0200, dir
, isp
,
1174 &ipu_buttress_start_tsc_sync_fops
);
1177 file
= debugfs_create_file("tsc", 0400, dir
, isp
,
1178 &ipu_buttress_tsc_fops
);
1181 file
= debugfs_create_file("psys_force_freq", 0700, dir
, isp
,
1182 &ipu_buttress_psys_force_freq_fops
);
1186 file
= debugfs_create_file("psys_freq", 0400, dir
, isp
,
1187 &ipu_buttress_psys_freq_fops
);
1191 file
= debugfs_create_file("isys_freq", 0700, dir
, isp
,
1192 &ipu_buttress_isys_freq_fops
);
1198 debugfs_remove_recursive(dir
);
1202 #endif /* CONFIG_DEBUG_FS */
1204 u64
ipu_buttress_tsc_ticks_to_ns(u64 ticks
)
1206 u64 ns
= ticks
* 10000;
1208 * TSC clock frequency is 19.2MHz,
1209 * converting TSC tick count to ns is calculated by:
1210 * ns = ticks * 1000 000 000 / 19.2Mhz
1211 * = ticks * 1000 000 000 / 19200000Hz
1212 * = ticks * 10000 / 192 ns
1218 EXPORT_SYMBOL_GPL(ipu_buttress_tsc_ticks_to_ns
);
1220 static ssize_t
psys_fused_min_freq_show(struct device
*dev
,
1221 struct device_attribute
*attr
,
1224 struct ipu_device
*isp
= pci_get_drvdata(to_pci_dev(dev
));
1226 return snprintf(buf
, PAGE_SIZE
, "%u\n",
1227 isp
->buttress
.psys_fused_freqs
.min_freq
);
1230 static DEVICE_ATTR_RO(psys_fused_min_freq
);
1232 static ssize_t
psys_fused_max_freq_show(struct device
*dev
,
1233 struct device_attribute
*attr
,
1236 struct ipu_device
*isp
= pci_get_drvdata(to_pci_dev(dev
));
1238 return snprintf(buf
, PAGE_SIZE
, "%u\n",
1239 isp
->buttress
.psys_fused_freqs
.max_freq
);
1242 static DEVICE_ATTR_RO(psys_fused_max_freq
);
1244 static ssize_t
psys_fused_efficient_freq_show(struct device
*dev
,
1245 struct device_attribute
*attr
,
1248 struct ipu_device
*isp
= pci_get_drvdata(to_pci_dev(dev
));
1250 return snprintf(buf
, PAGE_SIZE
, "%u\n",
1251 isp
->buttress
.psys_fused_freqs
.efficient_freq
);
1254 static DEVICE_ATTR_RO(psys_fused_efficient_freq
);
1256 int ipu_buttress_restore(struct ipu_device
*isp
)
1258 struct ipu_buttress
*b
= &isp
->buttress
;
1260 writel(BUTTRESS_IRQS
, isp
->base
+ BUTTRESS_REG_ISR_CLEAR
);
1261 writel(BUTTRESS_IRQS
, isp
->base
+ BUTTRESS_REG_ISR_ENABLE
);
1262 writel(b
->wdt_cached_value
, isp
->base
+ BUTTRESS_REG_WDT
);
1267 int ipu_buttress_init(struct ipu_device
*isp
)
1269 struct ipu_buttress
*b
= &isp
->buttress
;
1270 int rval
, ipc_reset_retry
= BUTTRESS_CSE_IPC_RESET_RETRY
;
1272 mutex_init(&b
->power_mutex
);
1273 mutex_init(&b
->auth_mutex
);
1274 mutex_init(&b
->cons_mutex
);
1275 mutex_init(&b
->ipc_mutex
);
1276 init_completion(&b
->ish
.send_complete
);
1277 init_completion(&b
->cse
.send_complete
);
1278 init_completion(&b
->ish
.recv_complete
);
1279 init_completion(&b
->cse
.recv_complete
);
1281 b
->cse
.nack
= BUTTRESS_CSE2IUDATA0_IPC_NACK
;
1282 b
->cse
.nack_mask
= BUTTRESS_CSE2IUDATA0_IPC_NACK_MASK
;
1283 b
->cse
.csr_in
= BUTTRESS_REG_CSE2IUCSR
;
1284 b
->cse
.csr_out
= BUTTRESS_REG_IU2CSECSR
;
1285 b
->cse
.db0_in
= BUTTRESS_REG_CSE2IUDB0
;
1286 b
->cse
.db0_out
= BUTTRESS_REG_IU2CSEDB0
;
1287 b
->cse
.data0_in
= BUTTRESS_REG_CSE2IUDATA0
;
1288 b
->cse
.data0_out
= BUTTRESS_REG_IU2CSEDATA0
;
1290 /* no ISH on IPU6 */
1291 memset(&b
->ish
, 0, sizeof(b
->ish
));
1292 INIT_LIST_HEAD(&b
->constraints
);
1294 ipu_buttress_set_secure_mode(isp
);
1295 isp
->secure_mode
= ipu_buttress_get_secure_mode(isp
);
1296 if (isp
->secure_mode
!= secure_mode_enable
)
1297 dev_warn(&isp
->pdev
->dev
, "Unable to set secure mode\n");
1299 dev_info(&isp
->pdev
->dev
, "IPU in %s mode\n",
1300 isp
->secure_mode
? "secure" : "non-secure");
1302 b
->wdt_cached_value
= readl(isp
->base
+ BUTTRESS_REG_WDT
);
1303 writel(BUTTRESS_IRQS
, isp
->base
+ BUTTRESS_REG_ISR_CLEAR
);
1304 writel(BUTTRESS_IRQS
, isp
->base
+ BUTTRESS_REG_ISR_ENABLE
);
1306 rval
= device_create_file(&isp
->pdev
->dev
,
1307 &dev_attr_psys_fused_min_freq
);
1309 dev_err(&isp
->pdev
->dev
, "Create min freq file failed\n");
1310 goto err_mutex_destroy
;
1313 rval
= device_create_file(&isp
->pdev
->dev
,
1314 &dev_attr_psys_fused_max_freq
);
1316 dev_err(&isp
->pdev
->dev
, "Create max freq file failed\n");
1317 goto err_remove_min_freq_file
;
1320 rval
= device_create_file(&isp
->pdev
->dev
,
1321 &dev_attr_psys_fused_efficient_freq
);
1323 dev_err(&isp
->pdev
->dev
, "Create efficient freq file failed\n");
1324 goto err_remove_max_freq_file
;
1328 * We want to retry couple of time in case CSE initialization
1329 * is delayed for reason or another.
1332 rval
= ipu_buttress_ipc_reset(isp
, &b
->cse
);
1334 dev_warn(&isp
->pdev
->dev
,
1335 "IPC reset protocol failed, retrying\n");
1337 dev_info(&isp
->pdev
->dev
, "IPC reset done\n");
1340 } while (ipc_reset_retry
--);
1342 dev_err(&isp
->pdev
->dev
, "IPC reset protocol failed\n");
1344 err_remove_max_freq_file
:
1345 device_remove_file(&isp
->pdev
->dev
, &dev_attr_psys_fused_max_freq
);
1346 err_remove_min_freq_file
:
1347 device_remove_file(&isp
->pdev
->dev
, &dev_attr_psys_fused_min_freq
);
1349 mutex_destroy(&b
->power_mutex
);
1350 mutex_destroy(&b
->auth_mutex
);
1351 mutex_destroy(&b
->cons_mutex
);
1352 mutex_destroy(&b
->ipc_mutex
);
1357 void ipu_buttress_exit(struct ipu_device
*isp
)
1359 struct ipu_buttress
*b
= &isp
->buttress
;
1361 writel(0, isp
->base
+ BUTTRESS_REG_ISR_ENABLE
);
1363 device_remove_file(&isp
->pdev
->dev
,
1364 &dev_attr_psys_fused_efficient_freq
);
1365 device_remove_file(&isp
->pdev
->dev
, &dev_attr_psys_fused_max_freq
);
1366 device_remove_file(&isp
->pdev
->dev
, &dev_attr_psys_fused_min_freq
);
1368 mutex_destroy(&b
->power_mutex
);
1369 mutex_destroy(&b
->auth_mutex
);
1370 mutex_destroy(&b
->cons_mutex
);
1371 mutex_destroy(&b
->ipc_mutex
);