1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2013 - 2020 Intel Corporation */
7 #define IPU_MMU_NAME IPU_NAME "-mmu"
8 #define IPU_ISYS_CSI2_NAME IPU_NAME "-csi2"
9 #define IPU_ISYS_NAME IPU_NAME "-isys"
10 #define IPU_PSYS_NAME IPU_NAME "-psys"
11 #define IPU_BUTTRESS_NAME IPU_NAME "-buttress"
13 #define IPU_MMU_MAX_DEVICES 4
14 #define IPU_MMU_ADDRESS_BITS 32
15 /* The firmware is accessible within the first 2 GiB only in non-secure mode. */
16 #define IPU_MMU_ADDRESS_BITS_NON_SECURE 31
18 #define IPU_MMU_MAX_TLB_L1_STREAMS 32
19 #define IPU_MMU_MAX_TLB_L2_STREAMS 32
20 #define IPU_MAX_LI_BLOCK_ADDR 128
21 #define IPU_MAX_L2_BLOCK_ADDR 64
23 #define IPU_ISYS_MAX_CSI2_LEGACY_PORTS 4
24 #define IPU_ISYS_MAX_CSI2_COMBO_PORTS 2
26 #define IPU_MAX_FRAME_COUNTER 0xff
29 * To maximize the IOSF utlization, IPU need to send requests in bursts.
30 * At the DMA interface with the buttress, there are CDC FIFOs with burst
31 * collection capability. CDC FIFO burst collectors have a configurable
32 * threshold and is configured based on the outcome of performance measurements.
34 * isys has 3 ports with IOSF interface for VC0, VC1 and VC2
35 * psys has 4 ports with IOSF interface for VC0, VC1w, VC1r and VC2
37 * Threshold values are pre-defined and are arrived at after performance
38 * evaluations on a type of IPU
40 #define IPU_MAX_VC_IOSF_PORTS 4
43 * IPU must configure correct arbitration mechanism related to the IOSF VC
44 * requests. There are two options per VC0 and VC1 - > 0 means rearbitrate on
45 * stall and 1 means stall until the request is completed.
47 #define IPU_BTRS_ARB_MODE_TYPE_REARB 0
48 #define IPU_BTRS_ARB_MODE_TYPE_STALL 1
50 /* Currently chosen arbitration mechanism for VC0 */
51 #define IPU_BTRS_ARB_STALL_MODE_VC0 \
52 IPU_BTRS_ARB_MODE_TYPE_REARB
54 /* Currently chosen arbitration mechanism for VC1 */
55 #define IPU_BTRS_ARB_STALL_MODE_VC1 \
56 IPU_BTRS_ARB_MODE_TYPE_REARB
58 struct ipu_isys_subdev_pdata
;
61 * MMU Invalidation HW bug workaround by ZLW mechanism
63 * Old IPU MMUV2 has a bug in the invalidation mechanism which might result in
64 * wrong translation or replication of the translation. This will cause data
65 * corruption. So we cannot directly use the MMU V2 invalidation registers
66 * to invalidate the MMU. Instead, whenever an invalidate is called, we need to
67 * clear the TLB by evicting all the valid translations by filling it with trash
68 * buffer (which is guaranteed not to be used by any other processes). ZLW is
69 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW
70 * or Zero length write, is pre-fetch mechanism to pre-fetch the pages in
71 * advance to the L1 and L2 caches without triggering any memory operations.
73 * In MMU V2, L1 -> 16 streams and 64 blocks, maximum 16 blocks per stream
74 * One L1 block has 16 entries, hence points to 16 * 4K pages
75 * L2 -> 16 streams and 32 blocks. 2 blocks per streams
76 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range
77 * 2 blocks per L2 stream means, 1 stream points to 8MB range
79 * As we need to clear the caches and 8MB being the biggest cache size, we need
80 * to have trash buffer which points to 8MB address range. As these trash
81 * buffers are not used for any memory transactions, we need only the least
82 * amount of physical memory. So we reserve 8MB IOVA address range but only
83 * one page is reserved from physical memory. Each of this 8MB IOVA address
84 * range is then mapped to the same physical memory page.
86 /* One L2 entry maps 1024 L1 entries and one L1 entry per page */
87 #define IPU_MMUV2_L2_RANGE (1024 * PAGE_SIZE)
88 /* Max L2 blocks per stream */
89 #define IPU_MMUV2_MAX_L2_BLOCKS 2
90 /* Max L1 blocks per stream */
91 #define IPU_MMUV2_MAX_L1_BLOCKS 16
92 #define IPU_MMUV2_TRASH_RANGE (IPU_MMUV2_L2_RANGE * \
93 IPU_MMUV2_MAX_L2_BLOCKS)
94 /* Entries per L1 block */
95 #define MMUV2_ENTRIES_PER_L1_BLOCK 16
96 #define MMUV2_TRASH_L1_BLOCK_OFFSET (MMUV2_ENTRIES_PER_L1_BLOCK * \
98 #define MMUV2_TRASH_L2_BLOCK_OFFSET IPU_MMUV2_L2_RANGE
101 * In some of the IPU MMUs, there is provision to configure L1 and L2 page
102 * table caches. Both these L1 and L2 caches are divided into multiple sections
103 * called streams. There is maximum 16 streams for both caches. Each of these
104 * sections are subdivided into multiple blocks. When nr_l1streams = 0 and
105 * nr_l2streams = 0, means the MMU is of type MMU_V1 and do not support
106 * L1/L2 page table caches.
108 * L1 stream per block sizes are configurable and varies per usecase.
109 * L2 has constant block sizes - 2 blocks per stream.
111 * MMU1 support pre-fetching of the pages to have less cache lookup misses. To
112 * enable the pre-fetching, MMU1 AT (Address Translator) device registers
113 * need to be configured.
115 * There are four types of memory accesses which requires ZLW configuration.
116 * ZLW(Zero Length Write) is a mechanism to enable VT-d pre-fetching on IOMMU.
118 * 1. Sequential Access or 1D mode
120 * set ZLW_PAGE_CROSS_1D -> 1
121 * Set ZLW_N to "N" pages so that ZLW will be inserte N pages ahead where
122 * N is pre-defined and hardcoded in the platform data
127 * set ZLW_PAGE_CROSS_1D -> 1,
131 * 3. ZLW Enable (no 1D or 2D mode)
133 * set ZLW_PAGE_CROSS_1D -> 0,
139 * set ZLW_PAGE_CROSS_1D -> 0,
143 * To configure the ZLW for the above memory access, four registers are
144 * available. Hence to track these four settings, we have the following entries
145 * in the struct ipu_mmu_hw. Each of these entries are per stream and
146 * available only for the L1 streams.
148 * a. l1_zlw_en -> To track zlw enabled per stream (ZLW_EN)
149 * b. l1_zlw_1d_mode -> Track 1D mode per stream. ZLW inserted at page boundary
150 * c. l1_ins_zlw_ahead_pages -> to track how advance the ZLW need to be inserted
151 * Insert ZLW request N pages ahead address.
152 * d. l1_zlw_2d_mode -> To track 2D mode per stream (ZLW_2D)
155 * Currently L1/L2 streams, blocks, AT ZLW configurations etc. are pre-defined
156 * as per the usecase specific calculations. Any change to this pre-defined
157 * table has to happen in sync with IPU FW.
161 unsigned long offset
;
164 unsigned int info_bits
;
167 * L1 has variable blocks per stream - total of 64 blocks and maximum of
168 * 16 blocks per stream. Configurable by using the block start address
169 * per stream. Block start address is calculated from the block size
171 u8 l1_block_sz
[IPU_MMU_MAX_TLB_L1_STREAMS
];
172 /* Is ZLW is enabled in each stream */
173 bool l1_zlw_en
[IPU_MMU_MAX_TLB_L1_STREAMS
];
174 bool l1_zlw_1d_mode
[IPU_MMU_MAX_TLB_L1_STREAMS
];
175 u8 l1_ins_zlw_ahead_pages
[IPU_MMU_MAX_TLB_L1_STREAMS
];
176 bool l1_zlw_2d_mode
[IPU_MMU_MAX_TLB_L1_STREAMS
];
178 u32 l1_stream_id_reg_offset
;
179 u32 l2_stream_id_reg_offset
;
183 * L2 has fixed 2 blocks per stream. Block address is calculated
184 * from the block size
186 u8 l2_block_sz
[IPU_MMU_MAX_TLB_L2_STREAMS
];
187 /* flag to track if WA is needed for successive invalidate HW bug */
188 bool insert_read_before_invalidate
;
189 /* flag to track if zlw based mmu invalidation is needed */
193 struct ipu_mmu_pdata
{
194 unsigned int nr_mmus
;
195 struct ipu_mmu_hw mmu_hw
[IPU_MMU_MAX_DEVICES
];
199 struct ipu_isys_csi2_pdata
{
203 #define IPU_EV_AUTO 0xff
205 struct ipu_isys_internal_csi2_pdata
{
207 unsigned int *offsets
;
211 * One place to handle all the IPU HW variations
213 struct ipu_hw_variants
{
214 unsigned long offset
;
215 unsigned int nr_mmus
;
216 struct ipu_mmu_hw mmu_hw
[IPU_MMU_MAX_DEVICES
];
218 u8 cdc_fifo_threshold
[IPU_MAX_VC_IOSF_PORTS
];
220 u32 spc_offset
; /* SPC offset from psys base */
223 struct ipu_isys_internal_pdata
{
224 struct ipu_isys_internal_csi2_pdata csi2
;
225 struct ipu_hw_variants hw_variant
;
226 u32 num_parallel_streams
;
227 u32 isys_dma_overshoot
;
230 struct ipu_isys_pdata
{
232 const struct ipu_isys_internal_pdata
*ipdata
;
235 struct ipu_psys_internal_pdata
{
236 struct ipu_hw_variants hw_variant
;
239 struct ipu_psys_pdata
{
241 const struct ipu_psys_internal_pdata
*ipdata
;