drivers/media/pci/tw686x/tw686x-regs.h

   1 /* DMA controller registers */
   2 #define REG8_1(a0) ((const u16[8]) { a0, a0 + 1, a0 + 2, a0 + 3, \
   3                                      a0 + 4, a0 + 5, a0 + 6, a0 + 7})
   4 #define REG8_2(a0) ((const u16[8]) { a0, a0 + 2, a0 + 4, a0 + 6,        \
   5                                      a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe})
   6 #define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \
   7                                      a0 + 0x20, a0 + 0x28, a0 + 0x30, \
   8                                      a0 + 0x38})
   9 #define INT_STATUS              0x00
  10 #define PB_STATUS               0x01
  11 #define DMA_CMD                 0x02
  12 #define VIDEO_FIFO_STATUS       0x03
  13 #define VIDEO_CHANNEL_ID        0x04
  14 #define VIDEO_PARSER_STATUS     0x05
  15 #define SYS_SOFT_RST            0x06
  16 #define DMA_PAGE_TABLE0_ADDR    ((const u16[8]) { 0x08, 0xd0, 0xd2, 0xd4, \
  17                                                   0xd6, 0xd8, 0xda, 0xdc })
  18 #define DMA_PAGE_TABLE1_ADDR    ((const u16[8]) { 0x09, 0xd1, 0xd3, 0xd5, \
  19                                                   0xd7, 0xd9, 0xdb, 0xdd })
  20 #define DMA_CHANNEL_ENABLE      0x0a
  21 #define DMA_CONFIG              0x0b
  22 #define DMA_TIMER_INTERVAL      0x0c
  23 #define DMA_CHANNEL_TIMEOUT     0x0d
  24 #define VDMA_CHANNEL_CONFIG     REG8_1(0x10)
  25 #define ADMA_P_ADDR             REG8_2(0x18)
  26 #define ADMA_B_ADDR             REG8_2(0x19)
  27 #define DMA10_P_ADDR            0x28
  28 #define DMA10_B_ADDR            0x29
  29 #define VIDEO_CONTROL1          0x2a
  30 #define VIDEO_CONTROL2          0x2b
  31 #define AUDIO_CONTROL1          0x2c
  32 #define AUDIO_CONTROL2          0x2d
  33 #define PHASE_REF               0x2e
  34 #define GPIO_REG                0x2f
  35 #define INTL_HBAR_CTRL          REG8_1(0x30)
  36 #define AUDIO_CONTROL3          0x38
  37 #define VIDEO_FIELD_CTRL        REG8_1(0x39)
  38 #define HSCALER_CTRL            REG8_1(0x42)
  39 #define VIDEO_SIZE              REG8_1(0x4A)
  40 #define VIDEO_SIZE_F2           REG8_1(0x52)
  41 #define MD_CONF                 REG8_1(0x60)
  42 #define MD_INIT                 REG8_1(0x68)
  43 #define MD_MAP0                 REG8_1(0x70)
  44 #define VDMA_P_ADDR             REG8_8(0x80) /* not used in DMA SG mode */
  45 #define VDMA_WHP                REG8_8(0x81)
  46 #define VDMA_B_ADDR             REG8_8(0x82)
  47 #define VDMA_F2_P_ADDR          REG8_8(0x84)
  48 #define VDMA_F2_WHP             REG8_8(0x85)
  49 #define VDMA_F2_B_ADDR          REG8_8(0x86)
  50 #define EP_REG_ADDR             0xfe
  51 #define EP_REG_DATA             0xff
  52
  53 /* Video decoder registers */
  54 #define VDREG8(a0) ((const u16[8]) { \
  55         a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \
  56         a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130})
  57 #define VIDSTAT                 VDREG8(0x100)
  58 #define BRIGHT                  VDREG8(0x101)
  59 #define CONTRAST                VDREG8(0x102)
  60 #define SHARPNESS               VDREG8(0x103)
  61 #define SAT_U                   VDREG8(0x104)
  62 #define SAT_V                   VDREG8(0x105)
  63 #define HUE                     VDREG8(0x106)
  64 #define CROP_HI                 VDREG8(0x107)
  65 #define VDELAY_LO               VDREG8(0x108)
  66 #define VACTIVE_LO              VDREG8(0x109)
  67 #define HDELAY_LO               VDREG8(0x10a)
  68 #define HACTIVE_LO              VDREG8(0x10b)
  69 #define MVSN                    VDREG8(0x10c)
  70 #define STATUS2                 VDREG8(0x10d)
  71 #define SDT                     VDREG8(0x10e)
  72 #define SDT_EN                  VDREG8(0x10f)
  73
  74 #define VSCALE_LO               VDREG8(0x144)
  75 #define SCALE_HI                VDREG8(0x145)
  76 #define HSCALE_LO               VDREG8(0x146)
  77 #define F2CROP_HI               VDREG8(0x147)
  78 #define F2VDELAY_LO             VDREG8(0x148)
  79 #define F2VACTIVE_LO            VDREG8(0x149)
  80 #define F2HDELAY_LO             VDREG8(0x14a)
  81 #define F2HACTIVE_LO            VDREG8(0x14b)
  82 #define F2VSCALE_LO             VDREG8(0x14c)
  83 #define F2SCALE_HI              VDREG8(0x14d)
  84 #define F2HSCALE_LO             VDREG8(0x14e)
  85 #define F2CNT                   VDREG8(0x14f)
  86
  87 #define VDREG2(a0) ((const u16[2]) { a0, a0 + 0x100 })
  88 #define SRST                    VDREG2(0x180)
  89 #define ACNTL                   VDREG2(0x181)
  90 #define ACNTL2                  VDREG2(0x182)
  91 #define CNTRL1                  VDREG2(0x183)
  92 #define CKHY                    VDREG2(0x184)
  93 #define SHCOR                   VDREG2(0x185)
  94 #define CORING                  VDREG2(0x186)
  95 #define CLMPG                   VDREG2(0x187)
  96 #define IAGC                    VDREG2(0x188)
  97 #define VCTRL1                  VDREG2(0x18f)
  98 #define MISC1                   VDREG2(0x194)
  99 #define LOOP                    VDREG2(0x195)
 100 #define MISC2                   VDREG2(0x196)
 101
 102 #define CLMD                    VDREG2(0x197)
 103 #define ANPWRDOWN               VDREG2(0x1ce)
 104 #define AIGAIN                  ((const u16[8]) { 0x1d0, 0x1d1, 0x1d2, 0x1d3, \
 105                                                   0x2d0, 0x2d1, 0x2d2, 0x2d3 })
 106
 107 #define SYS_MODE_DMA_SHIFT      13
 108
 109 #define DMA_CMD_ENABLE          BIT(31)
 110 #define INT_STATUS_DMA_TOUT     BIT(17)
 111 #define TW686X_VIDSTAT_HLOCK    BIT(6)
 112 #define TW686X_VIDSTAT_VDLOSS   BIT(7)
 113
 114 #define TW686X_STD_NTSC_M       0
 115 #define TW686X_STD_PAL          1
 116 #define TW686X_STD_SECAM        2
 117 #define TW686X_STD_NTSC_443     3
 118 #define TW686X_STD_PAL_M        4
 119 #define TW686X_STD_PAL_CN       5
 120 #define TW686X_STD_PAL_60       6
 121
 122 #define TW686X_FIFO_ERROR(x)    (x & ~(0xff))