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[mirror_ubuntu-eoan-kernel.git] / drivers / media / platform / coda / coda-bit.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Coda multi-standard codec IP - BIT processor functions
4 *
5 * Copyright (C) 2012 Vista Silicon S.L.
6 * Javier Martin, <javier.martin@vista-silicon.com>
7 * Xavier Duret
8 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
9 */
10
11 #include <linux/clk.h>
12 #include <linux/irqreturn.h>
13 #include <linux/kernel.h>
14 #include <linux/log2.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/slab.h>
18 #include <linux/videodev2.h>
19
20 #include <media/v4l2-common.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fh.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/videobuf2-v4l2.h>
25 #include <media/videobuf2-dma-contig.h>
26 #include <media/videobuf2-vmalloc.h>
27
28 #include "coda.h"
29 #include "imx-vdoa.h"
30 #define CREATE_TRACE_POINTS
31 #include "trace.h"
32
33 #define CODA_PARA_BUF_SIZE (10 * 1024)
34 #define CODA7_PS_BUF_SIZE 0x28000
35 #define CODA9_PS_SAVE_SIZE (512 * 1024)
36
37 #define CODA_DEFAULT_GAMMA 4096
38 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
39
40 static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
41
42 static inline int coda_is_initialized(struct coda_dev *dev)
43 {
44 return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
45 }
46
47 static inline unsigned long coda_isbusy(struct coda_dev *dev)
48 {
49 return coda_read(dev, CODA_REG_BIT_BUSY);
50 }
51
52 static int coda_wait_timeout(struct coda_dev *dev)
53 {
54 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
55
56 while (coda_isbusy(dev)) {
57 if (time_after(jiffies, timeout))
58 return -ETIMEDOUT;
59 }
60 return 0;
61 }
62
63 static void coda_command_async(struct coda_ctx *ctx, int cmd)
64 {
65 struct coda_dev *dev = ctx->dev;
66
67 if (dev->devtype->product == CODA_HX4 ||
68 dev->devtype->product == CODA_7541 ||
69 dev->devtype->product == CODA_960) {
70 /* Restore context related registers to CODA */
71 coda_write(dev, ctx->bit_stream_param,
72 CODA_REG_BIT_BIT_STREAM_PARAM);
73 coda_write(dev, ctx->frm_dis_flg,
74 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
75 coda_write(dev, ctx->frame_mem_ctrl,
76 CODA_REG_BIT_FRAME_MEM_CTRL);
77 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
78 }
79
80 if (dev->devtype->product == CODA_960) {
81 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
82 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
83 }
84
85 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
86
87 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
88 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
89 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
90
91 trace_coda_bit_run(ctx, cmd);
92
93 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
94 }
95
96 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
97 {
98 struct coda_dev *dev = ctx->dev;
99 int ret;
100
101 coda_command_async(ctx, cmd);
102 ret = coda_wait_timeout(dev);
103 trace_coda_bit_done(ctx);
104
105 return ret;
106 }
107
108 int coda_hw_reset(struct coda_ctx *ctx)
109 {
110 struct coda_dev *dev = ctx->dev;
111 unsigned long timeout;
112 unsigned int idx;
113 int ret;
114
115 if (!dev->rstc)
116 return -ENOENT;
117
118 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
119
120 if (dev->devtype->product == CODA_960) {
121 timeout = jiffies + msecs_to_jiffies(100);
122 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
123 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
124 if (time_after(jiffies, timeout))
125 return -ETIME;
126 cpu_relax();
127 }
128 }
129
130 ret = reset_control_reset(dev->rstc);
131 if (ret < 0)
132 return ret;
133
134 if (dev->devtype->product == CODA_960)
135 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
136 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
137 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
138 ret = coda_wait_timeout(dev);
139 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
140
141 return ret;
142 }
143
144 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
145 {
146 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
147 struct coda_dev *dev = ctx->dev;
148 u32 rd_ptr;
149
150 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
151 kfifo->out = (kfifo->in & ~kfifo->mask) |
152 (rd_ptr - ctx->bitstream.paddr);
153 if (kfifo->out > kfifo->in)
154 kfifo->out -= kfifo->mask + 1;
155 }
156
157 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
158 {
159 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
160 struct coda_dev *dev = ctx->dev;
161 u32 rd_ptr, wr_ptr;
162
163 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
164 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
165 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
166 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
167 }
168
169 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
170 {
171 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
172 struct coda_dev *dev = ctx->dev;
173 u32 wr_ptr;
174
175 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
176 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
177 }
178
179 static int coda_bitstream_pad(struct coda_ctx *ctx, u32 size)
180 {
181 unsigned char *buf;
182 u32 n;
183
184 if (size < 6)
185 size = 6;
186
187 buf = kmalloc(size, GFP_KERNEL);
188 if (!buf)
189 return -ENOMEM;
190
191 coda_h264_filler_nal(size, buf);
192 n = kfifo_in(&ctx->bitstream_fifo, buf, size);
193 kfree(buf);
194
195 return (n < size) ? -ENOSPC : 0;
196 }
197
198 static int coda_bitstream_queue(struct coda_ctx *ctx,
199 struct vb2_v4l2_buffer *src_buf)
200 {
201 u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
202 u32 n;
203
204 n = kfifo_in(&ctx->bitstream_fifo,
205 vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
206 if (n < src_size)
207 return -ENOSPC;
208
209 src_buf->sequence = ctx->qsequence++;
210
211 return 0;
212 }
213
214 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
215 struct vb2_v4l2_buffer *src_buf)
216 {
217 unsigned long payload = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
218 int ret;
219
220 if (coda_get_bitstream_payload(ctx) + payload + 512 >=
221 ctx->bitstream.size)
222 return false;
223
224 if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
225 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
226 return true;
227 }
228
229 /* Add zero padding before the first H.264 buffer, if it is too small */
230 if (ctx->qsequence == 0 && payload < 512 &&
231 ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
232 coda_bitstream_pad(ctx, 512 - payload);
233
234 ret = coda_bitstream_queue(ctx, src_buf);
235 if (ret < 0) {
236 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
237 return false;
238 }
239 /* Sync read pointer to device */
240 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
241 coda_kfifo_sync_to_device_write(ctx);
242
243 ctx->hold = false;
244
245 return true;
246 }
247
248 void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list)
249 {
250 struct vb2_v4l2_buffer *src_buf;
251 struct coda_buffer_meta *meta;
252 u32 start;
253
254 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
255 return;
256
257 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
258 /*
259 * Only queue two JPEGs into the bitstream buffer to keep
260 * latency low. We need at least one complete buffer and the
261 * header of another buffer (for prescan) in the bitstream.
262 */
263 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
264 ctx->num_metas > 1)
265 break;
266
267 if (ctx->num_internal_frames &&
268 ctx->num_metas >= ctx->num_internal_frames) {
269 meta = list_first_entry(&ctx->buffer_meta_list,
270 struct coda_buffer_meta, list);
271
272 /*
273 * If we managed to fill in at least a full reorder
274 * window of buffers (num_internal_frames is a
275 * conservative estimate for this) and the bitstream
276 * prefetcher has at least 2 256 bytes periods beyond
277 * the first buffer to fetch, we can safely stop queuing
278 * in order to limit the decoder drain latency.
279 */
280 if (coda_bitstream_can_fetch_past(ctx, meta->end))
281 break;
282 }
283
284 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
285
286 /* Drop frames that do not start/end with a SOI/EOI markers */
287 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
288 !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
289 v4l2_err(&ctx->dev->v4l2_dev,
290 "dropping invalid JPEG frame %d\n",
291 ctx->qsequence);
292 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
293 if (buffer_list) {
294 struct v4l2_m2m_buffer *m2m_buf;
295
296 m2m_buf = container_of(src_buf,
297 struct v4l2_m2m_buffer,
298 vb);
299 list_add_tail(&m2m_buf->list, buffer_list);
300 } else {
301 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
302 }
303 continue;
304 }
305
306 /* Dump empty buffers */
307 if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
308 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
309 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
310 continue;
311 }
312
313 /* Buffer start position */
314 start = ctx->bitstream_fifo.kfifo.in;
315
316 if (coda_bitstream_try_queue(ctx, src_buf)) {
317 /*
318 * Source buffer is queued in the bitstream ringbuffer;
319 * queue the timestamp and mark source buffer as done
320 */
321 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
322
323 meta = kmalloc(sizeof(*meta), GFP_KERNEL);
324 if (meta) {
325 meta->sequence = src_buf->sequence;
326 meta->timecode = src_buf->timecode;
327 meta->timestamp = src_buf->vb2_buf.timestamp;
328 meta->start = start;
329 meta->end = ctx->bitstream_fifo.kfifo.in;
330 spin_lock(&ctx->buffer_meta_lock);
331 list_add_tail(&meta->list,
332 &ctx->buffer_meta_list);
333 ctx->num_metas++;
334 spin_unlock(&ctx->buffer_meta_lock);
335
336 trace_coda_bit_queue(ctx, src_buf, meta);
337 }
338
339 if (buffer_list) {
340 struct v4l2_m2m_buffer *m2m_buf;
341
342 m2m_buf = container_of(src_buf,
343 struct v4l2_m2m_buffer,
344 vb);
345 list_add_tail(&m2m_buf->list, buffer_list);
346 } else {
347 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
348 }
349 } else {
350 break;
351 }
352 }
353 }
354
355 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
356 {
357 struct coda_dev *dev = ctx->dev;
358
359 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
360
361 /* If this context is currently running, update the hardware flag */
362 if ((dev->devtype->product == CODA_960) &&
363 coda_isbusy(dev) &&
364 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
365 coda_write(dev, ctx->bit_stream_param,
366 CODA_REG_BIT_BIT_STREAM_PARAM);
367 }
368 }
369
370 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
371 {
372 struct coda_dev *dev = ctx->dev;
373 u32 *p = ctx->parabuf.vaddr;
374
375 if (dev->devtype->product == CODA_DX6)
376 p[index] = value;
377 else
378 p[index ^ 1] = value;
379 }
380
381 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
382 struct coda_aux_buf *buf, size_t size,
383 const char *name)
384 {
385 return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
386 }
387
388
389 static void coda_free_framebuffers(struct coda_ctx *ctx)
390 {
391 int i;
392
393 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
394 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
395 }
396
397 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
398 struct coda_q_data *q_data, u32 fourcc)
399 {
400 struct coda_dev *dev = ctx->dev;
401 unsigned int ysize, ycbcr_size;
402 int ret;
403 int i;
404
405 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
406 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 ||
407 ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 ||
408 ctx->codec->dst_fourcc == V4L2_PIX_FMT_MPEG4)
409 ysize = round_up(q_data->rect.width, 16) *
410 round_up(q_data->rect.height, 16);
411 else
412 ysize = round_up(q_data->rect.width, 8) * q_data->rect.height;
413
414 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
415 ycbcr_size = round_up(ysize, 4096) + ysize / 2;
416 else
417 ycbcr_size = ysize + ysize / 2;
418
419 /* Allocate frame buffers */
420 for (i = 0; i < ctx->num_internal_frames; i++) {
421 size_t size = ycbcr_size;
422 char *name;
423
424 /* Add space for mvcol buffers */
425 if (dev->devtype->product != CODA_DX6 &&
426 (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
427 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)))
428 size += ysize / 4;
429 name = kasprintf(GFP_KERNEL, "fb%d", i);
430 if (!name) {
431 coda_free_framebuffers(ctx);
432 return -ENOMEM;
433 }
434 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
435 size, name);
436 kfree(name);
437 if (ret < 0) {
438 coda_free_framebuffers(ctx);
439 return ret;
440 }
441 }
442
443 /* Register frame buffers in the parameter buffer */
444 for (i = 0; i < ctx->num_internal_frames; i++) {
445 u32 y, cb, cr, mvcol;
446
447 /* Start addresses of Y, Cb, Cr planes */
448 y = ctx->internal_frames[i].paddr;
449 cb = y + ysize;
450 cr = y + ysize + ysize/4;
451 mvcol = y + ysize + ysize/4 + ysize/4;
452 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
453 cb = round_up(cb, 4096);
454 mvcol = cb + ysize/2;
455 cr = 0;
456 /* Packed 20-bit MSB of base addresses */
457 /* YYYYYCCC, CCyyyyyc, cccc.... */
458 y = (y & 0xfffff000) | cb >> 20;
459 cb = (cb & 0x000ff000) << 12;
460 }
461 coda_parabuf_write(ctx, i * 3 + 0, y);
462 coda_parabuf_write(ctx, i * 3 + 1, cb);
463 coda_parabuf_write(ctx, i * 3 + 2, cr);
464
465 if (dev->devtype->product == CODA_DX6)
466 continue;
467
468 /* mvcol buffer for h.264 and mpeg4 */
469 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
470 coda_parabuf_write(ctx, 96 + i, mvcol);
471 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)
472 coda_parabuf_write(ctx, 97, mvcol);
473 }
474
475 return 0;
476 }
477
478 static void coda_free_context_buffers(struct coda_ctx *ctx)
479 {
480 struct coda_dev *dev = ctx->dev;
481
482 coda_free_aux_buf(dev, &ctx->slicebuf);
483 coda_free_aux_buf(dev, &ctx->psbuf);
484 if (dev->devtype->product != CODA_DX6)
485 coda_free_aux_buf(dev, &ctx->workbuf);
486 coda_free_aux_buf(dev, &ctx->parabuf);
487 }
488
489 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
490 struct coda_q_data *q_data)
491 {
492 struct coda_dev *dev = ctx->dev;
493 size_t size;
494 int ret;
495
496 if (!ctx->parabuf.vaddr) {
497 ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
498 CODA_PARA_BUF_SIZE, "parabuf");
499 if (ret < 0)
500 return ret;
501 }
502
503 if (dev->devtype->product == CODA_DX6)
504 return 0;
505
506 if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
507 /* worst case slice size */
508 size = (DIV_ROUND_UP(q_data->rect.width, 16) *
509 DIV_ROUND_UP(q_data->rect.height, 16)) * 3200 / 8 + 512;
510 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
511 "slicebuf");
512 if (ret < 0)
513 goto err;
514 }
515
516 if (!ctx->psbuf.vaddr && (dev->devtype->product == CODA_HX4 ||
517 dev->devtype->product == CODA_7541)) {
518 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
519 CODA7_PS_BUF_SIZE, "psbuf");
520 if (ret < 0)
521 goto err;
522 }
523
524 if (!ctx->workbuf.vaddr) {
525 size = dev->devtype->workbuf_size;
526 if (dev->devtype->product == CODA_960 &&
527 q_data->fourcc == V4L2_PIX_FMT_H264)
528 size += CODA9_PS_SAVE_SIZE;
529 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
530 "workbuf");
531 if (ret < 0)
532 goto err;
533 }
534
535 return 0;
536
537 err:
538 coda_free_context_buffers(ctx);
539 return ret;
540 }
541
542 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
543 int header_code, u8 *header, int *size)
544 {
545 struct vb2_buffer *vb = &buf->vb2_buf;
546 struct coda_dev *dev = ctx->dev;
547 struct coda_q_data *q_data_src;
548 struct v4l2_rect *r;
549 size_t bufsize;
550 int ret;
551 int i;
552
553 if (dev->devtype->product == CODA_960)
554 memset(vb2_plane_vaddr(vb, 0), 0, 64);
555
556 coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
557 CODA_CMD_ENC_HEADER_BB_START);
558 bufsize = vb2_plane_size(vb, 0);
559 if (dev->devtype->product == CODA_960)
560 bufsize /= 1024;
561 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
562 if (dev->devtype->product == CODA_960 &&
563 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 &&
564 header_code == CODA_HEADER_H264_SPS) {
565 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
566 r = &q_data_src->rect;
567
568 if (r->width % 16 || r->height % 16) {
569 u32 crop_right = round_up(r->width, 16) - r->width;
570 u32 crop_bottom = round_up(r->height, 16) - r->height;
571
572 coda_write(dev, crop_right,
573 CODA9_CMD_ENC_HEADER_FRAME_CROP_H);
574 coda_write(dev, crop_bottom,
575 CODA9_CMD_ENC_HEADER_FRAME_CROP_V);
576 header_code |= CODA9_HEADER_FRAME_CROP;
577 }
578 }
579 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
580 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
581 if (ret < 0) {
582 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
583 return ret;
584 }
585
586 if (dev->devtype->product == CODA_960) {
587 for (i = 63; i > 0; i--)
588 if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
589 break;
590 *size = i + 1;
591 } else {
592 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
593 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
594 }
595 memcpy(header, vb2_plane_vaddr(vb, 0), *size);
596
597 return 0;
598 }
599
600 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
601 {
602 phys_addr_t ret;
603
604 size = round_up(size, 1024);
605 if (size > iram->remaining)
606 return 0;
607 iram->remaining -= size;
608
609 ret = iram->next_paddr;
610 iram->next_paddr += size;
611
612 return ret;
613 }
614
615 static void coda_setup_iram(struct coda_ctx *ctx)
616 {
617 struct coda_iram_info *iram_info = &ctx->iram_info;
618 struct coda_dev *dev = ctx->dev;
619 int w64, w128;
620 int mb_width;
621 int dbk_bits;
622 int bit_bits;
623 int ip_bits;
624 int me_bits;
625
626 memset(iram_info, 0, sizeof(*iram_info));
627 iram_info->next_paddr = dev->iram.paddr;
628 iram_info->remaining = dev->iram.size;
629
630 if (!dev->iram.vaddr)
631 return;
632
633 switch (dev->devtype->product) {
634 case CODA_HX4:
635 dbk_bits = CODA7_USE_HOST_DBK_ENABLE;
636 bit_bits = CODA7_USE_HOST_BIT_ENABLE;
637 ip_bits = CODA7_USE_HOST_IP_ENABLE;
638 me_bits = CODA7_USE_HOST_ME_ENABLE;
639 break;
640 case CODA_7541:
641 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
642 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
643 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
644 me_bits = CODA7_USE_HOST_ME_ENABLE | CODA7_USE_ME_ENABLE;
645 break;
646 case CODA_960:
647 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
648 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
649 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
650 me_bits = 0;
651 break;
652 default: /* CODA_DX6 */
653 return;
654 }
655
656 if (ctx->inst_type == CODA_INST_ENCODER) {
657 struct coda_q_data *q_data_src;
658
659 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
660 mb_width = DIV_ROUND_UP(q_data_src->rect.width, 16);
661 w128 = mb_width * 128;
662 w64 = mb_width * 64;
663
664 /* Prioritize in case IRAM is too small for everything */
665 if (dev->devtype->product == CODA_HX4 ||
666 dev->devtype->product == CODA_7541) {
667 iram_info->search_ram_size = round_up(mb_width * 16 *
668 36 + 2048, 1024);
669 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
670 iram_info->search_ram_size);
671 if (!iram_info->search_ram_paddr) {
672 pr_err("IRAM is smaller than the search ram size\n");
673 goto out;
674 }
675 iram_info->axi_sram_use |= me_bits;
676 }
677
678 /* Only H.264BP and H.263P3 are considered */
679 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
680 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
681 if (!iram_info->buf_dbk_c_use)
682 goto out;
683 iram_info->axi_sram_use |= dbk_bits;
684
685 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
686 if (!iram_info->buf_bit_use)
687 goto out;
688 iram_info->axi_sram_use |= bit_bits;
689
690 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
691 if (!iram_info->buf_ip_ac_dc_use)
692 goto out;
693 iram_info->axi_sram_use |= ip_bits;
694
695 /* OVL and BTP disabled for encoder */
696 } else if (ctx->inst_type == CODA_INST_DECODER) {
697 struct coda_q_data *q_data_dst;
698
699 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
700 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
701 w128 = mb_width * 128;
702
703 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
704 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
705 if (!iram_info->buf_dbk_c_use)
706 goto out;
707 iram_info->axi_sram_use |= dbk_bits;
708
709 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
710 if (!iram_info->buf_bit_use)
711 goto out;
712 iram_info->axi_sram_use |= bit_bits;
713
714 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
715 if (!iram_info->buf_ip_ac_dc_use)
716 goto out;
717 iram_info->axi_sram_use |= ip_bits;
718
719 /* OVL and BTP unused as there is no VC1 support yet */
720 }
721
722 out:
723 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
724 coda_dbg(1, ctx, "IRAM smaller than needed\n");
725
726 if (dev->devtype->product == CODA_HX4 ||
727 dev->devtype->product == CODA_7541) {
728 /* TODO - Enabling these causes picture errors on CODA7541 */
729 if (ctx->inst_type == CODA_INST_DECODER) {
730 /* fw 1.4.50 */
731 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
732 CODA7_USE_IP_ENABLE);
733 } else {
734 /* fw 13.4.29 */
735 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
736 CODA7_USE_HOST_DBK_ENABLE |
737 CODA7_USE_IP_ENABLE |
738 CODA7_USE_DBK_ENABLE);
739 }
740 }
741 }
742
743 static u32 coda_supported_firmwares[] = {
744 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
745 CODA_FIRMWARE_VERNUM(CODA_HX4, 1, 4, 50),
746 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
747 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
748 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 9),
749 CODA_FIRMWARE_VERNUM(CODA_960, 2, 3, 10),
750 CODA_FIRMWARE_VERNUM(CODA_960, 3, 1, 1),
751 };
752
753 static bool coda_firmware_supported(u32 vernum)
754 {
755 int i;
756
757 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
758 if (vernum == coda_supported_firmwares[i])
759 return true;
760 return false;
761 }
762
763 int coda_check_firmware(struct coda_dev *dev)
764 {
765 u16 product, major, minor, release;
766 u32 data;
767 int ret;
768
769 ret = clk_prepare_enable(dev->clk_per);
770 if (ret)
771 goto err_clk_per;
772
773 ret = clk_prepare_enable(dev->clk_ahb);
774 if (ret)
775 goto err_clk_ahb;
776
777 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
778 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
779 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
780 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
781 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
782 if (coda_wait_timeout(dev)) {
783 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
784 ret = -EIO;
785 goto err_run_cmd;
786 }
787
788 if (dev->devtype->product == CODA_960) {
789 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
790 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
791 data);
792 }
793
794 /* Check we are compatible with the loaded firmware */
795 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
796 product = CODA_FIRMWARE_PRODUCT(data);
797 major = CODA_FIRMWARE_MAJOR(data);
798 minor = CODA_FIRMWARE_MINOR(data);
799 release = CODA_FIRMWARE_RELEASE(data);
800
801 clk_disable_unprepare(dev->clk_per);
802 clk_disable_unprepare(dev->clk_ahb);
803
804 if (product != dev->devtype->product) {
805 v4l2_err(&dev->v4l2_dev,
806 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
807 coda_product_name(dev->devtype->product),
808 coda_product_name(product), major, minor, release);
809 return -EINVAL;
810 }
811
812 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
813 coda_product_name(product));
814
815 if (coda_firmware_supported(data)) {
816 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
817 major, minor, release);
818 } else {
819 v4l2_warn(&dev->v4l2_dev,
820 "Unsupported firmware version: %u.%u.%u\n",
821 major, minor, release);
822 }
823
824 return 0;
825
826 err_run_cmd:
827 clk_disable_unprepare(dev->clk_ahb);
828 err_clk_ahb:
829 clk_disable_unprepare(dev->clk_per);
830 err_clk_per:
831 return ret;
832 }
833
834 static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
835 {
836 u32 cache_size, cache_config;
837
838 if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
839 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
840 cache_size = 0x20262024;
841 cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
842 } else {
843 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
844 cache_size = 0x02440243;
845 cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
846 }
847 coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
848 if (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {
849 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
850 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
851 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
852 } else {
853 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
854 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
855 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
856 }
857 coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
858 }
859
860 /*
861 * Encoder context operations
862 */
863
864 static int coda_encoder_reqbufs(struct coda_ctx *ctx,
865 struct v4l2_requestbuffers *rb)
866 {
867 struct coda_q_data *q_data_src;
868 int ret;
869
870 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
871 return 0;
872
873 if (rb->count) {
874 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
875 ret = coda_alloc_context_buffers(ctx, q_data_src);
876 if (ret < 0)
877 return ret;
878 } else {
879 coda_free_context_buffers(ctx);
880 }
881
882 return 0;
883 }
884
885 static int coda_start_encoding(struct coda_ctx *ctx)
886 {
887 struct coda_dev *dev = ctx->dev;
888 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
889 struct coda_q_data *q_data_src, *q_data_dst;
890 u32 bitstream_buf, bitstream_size;
891 struct vb2_v4l2_buffer *buf;
892 int gamma, ret, value;
893 u32 dst_fourcc;
894 int num_fb;
895 u32 stride;
896
897 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
898 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
899 dst_fourcc = q_data_dst->fourcc;
900
901 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
902 bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
903 bitstream_size = q_data_dst->sizeimage;
904
905 if (!coda_is_initialized(dev)) {
906 v4l2_err(v4l2_dev, "coda is not initialized.\n");
907 return -EFAULT;
908 }
909
910 if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
911 if (!ctx->params.jpeg_qmat_tab[0])
912 ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
913 if (!ctx->params.jpeg_qmat_tab[1])
914 ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
915 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
916 }
917
918 mutex_lock(&dev->coda_mutex);
919
920 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
921 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
922 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
923 switch (dev->devtype->product) {
924 case CODA_DX6:
925 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
926 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
927 break;
928 case CODA_960:
929 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
930 /* fallthrough */
931 case CODA_HX4:
932 case CODA_7541:
933 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
934 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
935 break;
936 }
937
938 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
939 CODA9_FRAME_TILED2LINEAR);
940 if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
941 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
942 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
943 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
944 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
945
946 if (dev->devtype->product == CODA_DX6) {
947 /* Configure the coda */
948 coda_write(dev, dev->iram.paddr,
949 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
950 }
951
952 /* Could set rotation here if needed */
953 value = 0;
954 switch (dev->devtype->product) {
955 case CODA_DX6:
956 value = (q_data_src->rect.width & CODADX6_PICWIDTH_MASK)
957 << CODADX6_PICWIDTH_OFFSET;
958 value |= (q_data_src->rect.height & CODADX6_PICHEIGHT_MASK)
959 << CODA_PICHEIGHT_OFFSET;
960 break;
961 case CODA_HX4:
962 case CODA_7541:
963 if (dst_fourcc == V4L2_PIX_FMT_H264) {
964 value = (round_up(q_data_src->rect.width, 16) &
965 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
966 value |= (round_up(q_data_src->rect.height, 16) &
967 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
968 break;
969 }
970 /* fallthrough */
971 case CODA_960:
972 value = (q_data_src->rect.width & CODA7_PICWIDTH_MASK)
973 << CODA7_PICWIDTH_OFFSET;
974 value |= (q_data_src->rect.height & CODA7_PICHEIGHT_MASK)
975 << CODA_PICHEIGHT_OFFSET;
976 }
977 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
978 if (dst_fourcc == V4L2_PIX_FMT_JPEG)
979 ctx->params.framerate = 0;
980 coda_write(dev, ctx->params.framerate,
981 CODA_CMD_ENC_SEQ_SRC_F_RATE);
982
983 ctx->params.codec_mode = ctx->codec->mode;
984 switch (dst_fourcc) {
985 case V4L2_PIX_FMT_MPEG4:
986 if (dev->devtype->product == CODA_960)
987 coda_write(dev, CODA9_STD_MPEG4,
988 CODA_CMD_ENC_SEQ_COD_STD);
989 else
990 coda_write(dev, CODA_STD_MPEG4,
991 CODA_CMD_ENC_SEQ_COD_STD);
992 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
993 break;
994 case V4L2_PIX_FMT_H264:
995 if (dev->devtype->product == CODA_960)
996 coda_write(dev, CODA9_STD_H264,
997 CODA_CMD_ENC_SEQ_COD_STD);
998 else
999 coda_write(dev, CODA_STD_H264,
1000 CODA_CMD_ENC_SEQ_COD_STD);
1001 value = ((ctx->params.h264_disable_deblocking_filter_idc &
1002 CODA_264PARAM_DISABLEDEBLK_MASK) <<
1003 CODA_264PARAM_DISABLEDEBLK_OFFSET) |
1004 ((ctx->params.h264_slice_alpha_c0_offset_div2 &
1005 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
1006 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
1007 ((ctx->params.h264_slice_beta_offset_div2 &
1008 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
1009 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET) |
1010 (ctx->params.h264_constrained_intra_pred_flag <<
1011 CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_OFFSET) |
1012 (ctx->params.h264_chroma_qp_index_offset &
1013 CODA_264PARAM_CHROMAQPOFFSET_MASK);
1014 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
1015 break;
1016 case V4L2_PIX_FMT_JPEG:
1017 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
1018 coda_write(dev, ctx->params.jpeg_restart_interval,
1019 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
1020 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
1021 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
1022 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
1023
1024 coda_jpeg_write_tables(ctx);
1025 break;
1026 default:
1027 v4l2_err(v4l2_dev,
1028 "dst format (0x%08x) invalid.\n", dst_fourcc);
1029 ret = -EINVAL;
1030 goto out;
1031 }
1032
1033 /*
1034 * slice mode and GOP size registers are used for thumb size/offset
1035 * in JPEG mode
1036 */
1037 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1038 switch (ctx->params.slice_mode) {
1039 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
1040 value = 0;
1041 break;
1042 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
1043 value = (ctx->params.slice_max_mb &
1044 CODA_SLICING_SIZE_MASK)
1045 << CODA_SLICING_SIZE_OFFSET;
1046 value |= (1 & CODA_SLICING_UNIT_MASK)
1047 << CODA_SLICING_UNIT_OFFSET;
1048 value |= 1 & CODA_SLICING_MODE_MASK;
1049 break;
1050 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
1051 value = (ctx->params.slice_max_bits &
1052 CODA_SLICING_SIZE_MASK)
1053 << CODA_SLICING_SIZE_OFFSET;
1054 value |= (0 & CODA_SLICING_UNIT_MASK)
1055 << CODA_SLICING_UNIT_OFFSET;
1056 value |= 1 & CODA_SLICING_MODE_MASK;
1057 break;
1058 }
1059 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
1060 value = ctx->params.gop_size;
1061 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
1062 }
1063
1064 if (ctx->params.bitrate) {
1065 /* Rate control enabled */
1066 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
1067 << CODA_RATECONTROL_BITRATE_OFFSET;
1068 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
1069 value |= (ctx->params.vbv_delay &
1070 CODA_RATECONTROL_INITIALDELAY_MASK)
1071 << CODA_RATECONTROL_INITIALDELAY_OFFSET;
1072 if (dev->devtype->product == CODA_960)
1073 value |= BIT(31); /* disable autoskip */
1074 } else {
1075 value = 0;
1076 }
1077 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
1078
1079 coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
1080 coda_write(dev, ctx->params.intra_refresh,
1081 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
1082
1083 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
1084 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
1085
1086
1087 value = 0;
1088 if (dev->devtype->product == CODA_960)
1089 gamma = CODA9_DEFAULT_GAMMA;
1090 else
1091 gamma = CODA_DEFAULT_GAMMA;
1092 if (gamma > 0) {
1093 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
1094 CODA_CMD_ENC_SEQ_RC_GAMMA);
1095 }
1096
1097 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
1098 coda_write(dev,
1099 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
1100 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
1101 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
1102 }
1103 if (dev->devtype->product == CODA_960) {
1104 if (ctx->params.h264_max_qp)
1105 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
1106 if (CODA_DEFAULT_GAMMA > 0)
1107 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
1108 } else {
1109 if (CODA_DEFAULT_GAMMA > 0) {
1110 if (dev->devtype->product == CODA_DX6)
1111 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
1112 else
1113 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
1114 }
1115 if (ctx->params.h264_min_qp)
1116 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
1117 if (ctx->params.h264_max_qp)
1118 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
1119 }
1120 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1121
1122 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
1123
1124 coda_setup_iram(ctx);
1125
1126 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1127 switch (dev->devtype->product) {
1128 case CODA_DX6:
1129 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
1130 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1131 break;
1132 case CODA_HX4:
1133 case CODA_7541:
1134 coda_write(dev, ctx->iram_info.search_ram_paddr,
1135 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1136 coda_write(dev, ctx->iram_info.search_ram_size,
1137 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1138 break;
1139 case CODA_960:
1140 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
1141 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
1142 }
1143 }
1144
1145 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1146 if (ret < 0) {
1147 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1148 goto out;
1149 }
1150
1151 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1152 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1153 ret = -EFAULT;
1154 goto out;
1155 }
1156 ctx->initialized = 1;
1157
1158 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1159 if (dev->devtype->product == CODA_960)
1160 ctx->num_internal_frames = 4;
1161 else
1162 ctx->num_internal_frames = 2;
1163 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1164 if (ret < 0) {
1165 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1166 goto out;
1167 }
1168 num_fb = 2;
1169 stride = q_data_src->bytesperline;
1170 } else {
1171 ctx->num_internal_frames = 0;
1172 num_fb = 0;
1173 stride = 0;
1174 }
1175 coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
1176 coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
1177
1178 if (dev->devtype->product == CODA_HX4 ||
1179 dev->devtype->product == CODA_7541) {
1180 coda_write(dev, q_data_src->bytesperline,
1181 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1182 }
1183 if (dev->devtype->product != CODA_DX6) {
1184 coda_write(dev, ctx->iram_info.buf_bit_use,
1185 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1186 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1187 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1188 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1189 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1190 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1191 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1192 coda_write(dev, ctx->iram_info.buf_ovl_use,
1193 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1194 if (dev->devtype->product == CODA_960) {
1195 coda_write(dev, ctx->iram_info.buf_btp_use,
1196 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1197
1198 coda9_set_frame_cache(ctx, q_data_src->fourcc);
1199
1200 /* FIXME */
1201 coda_write(dev, ctx->internal_frames[2].paddr,
1202 CODA9_CMD_SET_FRAME_SUBSAMP_A);
1203 coda_write(dev, ctx->internal_frames[3].paddr,
1204 CODA9_CMD_SET_FRAME_SUBSAMP_B);
1205 }
1206 }
1207
1208 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1209 if (ret < 0) {
1210 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1211 goto out;
1212 }
1213
1214 coda_dbg(1, ctx, "start encoding %dx%d %4.4s->%4.4s @ %d/%d Hz\n",
1215 q_data_src->rect.width, q_data_src->rect.height,
1216 (char *)&ctx->codec->src_fourcc, (char *)&dst_fourcc,
1217 ctx->params.framerate & 0xffff,
1218 (ctx->params.framerate >> 16) + 1);
1219
1220 /* Save stream headers */
1221 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1222 switch (dst_fourcc) {
1223 case V4L2_PIX_FMT_H264:
1224 /*
1225 * Get SPS in the first frame and copy it to an
1226 * intermediate buffer.
1227 */
1228 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1229 &ctx->vpu_header[0][0],
1230 &ctx->vpu_header_size[0]);
1231 if (ret < 0)
1232 goto out;
1233
1234 /*
1235 * If visible width or height are not aligned to macroblock
1236 * size, the crop_right and crop_bottom SPS fields must be set
1237 * to the difference between visible and coded size. This is
1238 * only supported by CODA960 firmware. All others do not allow
1239 * writing frame cropping parameters, so we have to manually
1240 * fix up the SPS RBSP (Sequence Parameter Set Raw Byte
1241 * Sequence Payload) ourselves.
1242 */
1243 if (ctx->dev->devtype->product != CODA_960 &&
1244 ((q_data_src->rect.width % 16) ||
1245 (q_data_src->rect.height % 16))) {
1246 ret = coda_h264_sps_fixup(ctx, q_data_src->rect.width,
1247 q_data_src->rect.height,
1248 &ctx->vpu_header[0][0],
1249 &ctx->vpu_header_size[0],
1250 sizeof(ctx->vpu_header[0]));
1251 if (ret < 0)
1252 goto out;
1253 }
1254
1255 /*
1256 * Get PPS in the first frame and copy it to an
1257 * intermediate buffer.
1258 */
1259 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1260 &ctx->vpu_header[1][0],
1261 &ctx->vpu_header_size[1]);
1262 if (ret < 0)
1263 goto out;
1264
1265 /*
1266 * Length of H.264 headers is variable and thus it might not be
1267 * aligned for the coda to append the encoded frame. In that is
1268 * the case a filler NAL must be added to header 2.
1269 */
1270 ctx->vpu_header_size[2] = coda_h264_padding(
1271 (ctx->vpu_header_size[0] +
1272 ctx->vpu_header_size[1]),
1273 ctx->vpu_header[2]);
1274 break;
1275 case V4L2_PIX_FMT_MPEG4:
1276 /*
1277 * Get VOS in the first frame and copy it to an
1278 * intermediate buffer
1279 */
1280 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1281 &ctx->vpu_header[0][0],
1282 &ctx->vpu_header_size[0]);
1283 if (ret < 0)
1284 goto out;
1285
1286 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1287 &ctx->vpu_header[1][0],
1288 &ctx->vpu_header_size[1]);
1289 if (ret < 0)
1290 goto out;
1291
1292 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1293 &ctx->vpu_header[2][0],
1294 &ctx->vpu_header_size[2]);
1295 if (ret < 0)
1296 goto out;
1297 break;
1298 default:
1299 /* No more formats need to save headers at the moment */
1300 break;
1301 }
1302
1303 out:
1304 mutex_unlock(&dev->coda_mutex);
1305 return ret;
1306 }
1307
1308 static int coda_prepare_encode(struct coda_ctx *ctx)
1309 {
1310 struct coda_q_data *q_data_src, *q_data_dst;
1311 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1312 struct coda_dev *dev = ctx->dev;
1313 int force_ipicture;
1314 int quant_param = 0;
1315 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1316 u32 rot_mode = 0;
1317 u32 dst_fourcc;
1318 u32 reg;
1319
1320 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1321 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1322 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1323 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1324 dst_fourcc = q_data_dst->fourcc;
1325
1326 src_buf->sequence = ctx->osequence;
1327 dst_buf->sequence = ctx->osequence;
1328 ctx->osequence++;
1329
1330 force_ipicture = ctx->params.force_ipicture;
1331 if (force_ipicture)
1332 ctx->params.force_ipicture = false;
1333 else if (ctx->params.gop_size != 0 &&
1334 (src_buf->sequence % ctx->params.gop_size) == 0)
1335 force_ipicture = 1;
1336
1337 /*
1338 * Workaround coda firmware BUG that only marks the first
1339 * frame as IDR. This is a problem for some decoders that can't
1340 * recover when a frame is lost.
1341 */
1342 if (!force_ipicture) {
1343 src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1344 src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1345 } else {
1346 src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1347 src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1348 }
1349
1350 if (dev->devtype->product == CODA_960)
1351 coda_set_gdi_regs(ctx);
1352
1353 /*
1354 * Copy headers in front of the first frame and forced I frames for
1355 * H.264 only. In MPEG4 they are already copied by the CODA.
1356 */
1357 if (src_buf->sequence == 0 || force_ipicture) {
1358 pic_stream_buffer_addr =
1359 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
1360 ctx->vpu_header_size[0] +
1361 ctx->vpu_header_size[1] +
1362 ctx->vpu_header_size[2];
1363 pic_stream_buffer_size = q_data_dst->sizeimage -
1364 ctx->vpu_header_size[0] -
1365 ctx->vpu_header_size[1] -
1366 ctx->vpu_header_size[2];
1367 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
1368 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1369 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1370 + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
1371 ctx->vpu_header_size[1]);
1372 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1373 + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
1374 &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
1375 } else {
1376 pic_stream_buffer_addr =
1377 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1378 pic_stream_buffer_size = q_data_dst->sizeimage;
1379 }
1380
1381 if (force_ipicture) {
1382 switch (dst_fourcc) {
1383 case V4L2_PIX_FMT_H264:
1384 quant_param = ctx->params.h264_intra_qp;
1385 break;
1386 case V4L2_PIX_FMT_MPEG4:
1387 quant_param = ctx->params.mpeg4_intra_qp;
1388 break;
1389 case V4L2_PIX_FMT_JPEG:
1390 quant_param = 30;
1391 break;
1392 default:
1393 v4l2_warn(&ctx->dev->v4l2_dev,
1394 "cannot set intra qp, fmt not supported\n");
1395 break;
1396 }
1397 } else {
1398 switch (dst_fourcc) {
1399 case V4L2_PIX_FMT_H264:
1400 quant_param = ctx->params.h264_inter_qp;
1401 break;
1402 case V4L2_PIX_FMT_MPEG4:
1403 quant_param = ctx->params.mpeg4_inter_qp;
1404 break;
1405 default:
1406 v4l2_warn(&ctx->dev->v4l2_dev,
1407 "cannot set inter qp, fmt not supported\n");
1408 break;
1409 }
1410 }
1411
1412 /* submit */
1413 if (ctx->params.rot_mode)
1414 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1415 coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1416 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1417
1418 if (dev->devtype->product == CODA_960) {
1419 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1420 coda_write(dev, q_data_src->bytesperline,
1421 CODA9_CMD_ENC_PIC_SRC_STRIDE);
1422 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1423
1424 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1425 } else {
1426 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1427 }
1428 coda_write_base(ctx, q_data_src, src_buf, reg);
1429
1430 coda_write(dev, force_ipicture << 1 & 0x2,
1431 CODA_CMD_ENC_PIC_OPTION);
1432
1433 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1434 coda_write(dev, pic_stream_buffer_size / 1024,
1435 CODA_CMD_ENC_PIC_BB_SIZE);
1436
1437 if (!ctx->streamon_out) {
1438 /* After streamoff on the output side, set stream end flag */
1439 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1440 coda_write(dev, ctx->bit_stream_param,
1441 CODA_REG_BIT_BIT_STREAM_PARAM);
1442 }
1443
1444 if (dev->devtype->product != CODA_DX6)
1445 coda_write(dev, ctx->iram_info.axi_sram_use,
1446 CODA7_REG_BIT_AXI_SRAM_USE);
1447
1448 trace_coda_enc_pic_run(ctx, src_buf);
1449
1450 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1451
1452 return 0;
1453 }
1454
1455 static void coda_finish_encode(struct coda_ctx *ctx)
1456 {
1457 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1458 struct coda_dev *dev = ctx->dev;
1459 u32 wr_ptr, start_ptr;
1460
1461 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1462 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1463
1464 trace_coda_enc_pic_done(ctx, dst_buf);
1465
1466 /* Get results from the coda */
1467 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1468 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1469
1470 /* Calculate bytesused field */
1471 if (dst_buf->sequence == 0 ||
1472 src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
1473 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
1474 ctx->vpu_header_size[0] +
1475 ctx->vpu_header_size[1] +
1476 ctx->vpu_header_size[2]);
1477 } else {
1478 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
1479 }
1480
1481 coda_dbg(1, ctx, "frame size = %u\n", wr_ptr - start_ptr);
1482
1483 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1484 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1485
1486 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1487 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1488 dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1489 } else {
1490 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1491 dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1492 }
1493
1494 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
1495 dst_buf->field = src_buf->field;
1496 dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1497 dst_buf->flags |=
1498 src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1499 dst_buf->timecode = src_buf->timecode;
1500
1501 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1502
1503 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1504 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
1505
1506 ctx->gopcounter--;
1507 if (ctx->gopcounter < 0)
1508 ctx->gopcounter = ctx->params.gop_size - 1;
1509
1510 coda_dbg(1, ctx, "job finished: encoded %c frame (%d)\n",
1511 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ? 'I' : 'P',
1512 dst_buf->sequence);
1513 }
1514
1515 static void coda_seq_end_work(struct work_struct *work)
1516 {
1517 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1518 struct coda_dev *dev = ctx->dev;
1519
1520 mutex_lock(&ctx->buffer_mutex);
1521 mutex_lock(&dev->coda_mutex);
1522
1523 if (ctx->initialized == 0)
1524 goto out;
1525
1526 coda_dbg(1, ctx, "%s: sent command 'SEQ_END' to coda\n", __func__);
1527 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1528 v4l2_err(&dev->v4l2_dev,
1529 "CODA_COMMAND_SEQ_END failed\n");
1530 }
1531
1532 /*
1533 * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1534 * from the output stream after the h.264 decoder has run. Resetting the
1535 * hardware after the decoder has finished seems to help.
1536 */
1537 if (dev->devtype->product == CODA_960)
1538 coda_hw_reset(ctx);
1539
1540 kfifo_init(&ctx->bitstream_fifo,
1541 ctx->bitstream.vaddr, ctx->bitstream.size);
1542
1543 coda_free_framebuffers(ctx);
1544
1545 ctx->initialized = 0;
1546
1547 out:
1548 mutex_unlock(&dev->coda_mutex);
1549 mutex_unlock(&ctx->buffer_mutex);
1550 }
1551
1552 static void coda_bit_release(struct coda_ctx *ctx)
1553 {
1554 mutex_lock(&ctx->buffer_mutex);
1555 coda_free_framebuffers(ctx);
1556 coda_free_context_buffers(ctx);
1557 coda_free_bitstream_buffer(ctx);
1558 mutex_unlock(&ctx->buffer_mutex);
1559 }
1560
1561 const struct coda_context_ops coda_bit_encode_ops = {
1562 .queue_init = coda_encoder_queue_init,
1563 .reqbufs = coda_encoder_reqbufs,
1564 .start_streaming = coda_start_encoding,
1565 .prepare_run = coda_prepare_encode,
1566 .finish_run = coda_finish_encode,
1567 .seq_end_work = coda_seq_end_work,
1568 .release = coda_bit_release,
1569 };
1570
1571 /*
1572 * Decoder context operations
1573 */
1574
1575 static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
1576 struct coda_q_data *q_data)
1577 {
1578 if (ctx->bitstream.vaddr)
1579 return 0;
1580
1581 ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
1582 ctx->bitstream.vaddr = dma_alloc_wc(&ctx->dev->plat_dev->dev,
1583 ctx->bitstream.size,
1584 &ctx->bitstream.paddr, GFP_KERNEL);
1585 if (!ctx->bitstream.vaddr) {
1586 v4l2_err(&ctx->dev->v4l2_dev,
1587 "failed to allocate bitstream ringbuffer");
1588 return -ENOMEM;
1589 }
1590 kfifo_init(&ctx->bitstream_fifo,
1591 ctx->bitstream.vaddr, ctx->bitstream.size);
1592
1593 return 0;
1594 }
1595
1596 static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
1597 {
1598 if (ctx->bitstream.vaddr == NULL)
1599 return;
1600
1601 dma_free_wc(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
1602 ctx->bitstream.vaddr, ctx->bitstream.paddr);
1603 ctx->bitstream.vaddr = NULL;
1604 kfifo_init(&ctx->bitstream_fifo, NULL, 0);
1605 }
1606
1607 static int coda_decoder_reqbufs(struct coda_ctx *ctx,
1608 struct v4l2_requestbuffers *rb)
1609 {
1610 struct coda_q_data *q_data_src;
1611 int ret;
1612
1613 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
1614 return 0;
1615
1616 if (rb->count) {
1617 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1618 ret = coda_alloc_context_buffers(ctx, q_data_src);
1619 if (ret < 0)
1620 return ret;
1621 ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
1622 if (ret < 0) {
1623 coda_free_context_buffers(ctx);
1624 return ret;
1625 }
1626 } else {
1627 coda_free_bitstream_buffer(ctx);
1628 coda_free_context_buffers(ctx);
1629 }
1630
1631 return 0;
1632 }
1633
1634 static bool coda_reorder_enable(struct coda_ctx *ctx)
1635 {
1636 struct coda_dev *dev = ctx->dev;
1637 int profile;
1638
1639 if (dev->devtype->product != CODA_HX4 &&
1640 dev->devtype->product != CODA_7541 &&
1641 dev->devtype->product != CODA_960)
1642 return false;
1643
1644 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1645 return false;
1646
1647 if (ctx->codec->src_fourcc != V4L2_PIX_FMT_H264)
1648 return true;
1649
1650 profile = coda_h264_profile(ctx->params.h264_profile_idc);
1651 if (profile < 0)
1652 v4l2_warn(&dev->v4l2_dev, "Unknown H264 Profile: %u\n",
1653 ctx->params.h264_profile_idc);
1654
1655 /* Baseline profile does not support reordering */
1656 return profile > V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
1657 }
1658
1659 static int __coda_start_decoding(struct coda_ctx *ctx)
1660 {
1661 struct coda_q_data *q_data_src, *q_data_dst;
1662 u32 bitstream_buf, bitstream_size;
1663 struct coda_dev *dev = ctx->dev;
1664 int width, height;
1665 u32 src_fourcc, dst_fourcc;
1666 u32 val;
1667 int ret;
1668
1669 coda_dbg(1, ctx, "Video Data Order Adapter: %s\n",
1670 ctx->use_vdoa ? "Enabled" : "Disabled");
1671
1672 /* Start decoding */
1673 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1674 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1675 bitstream_buf = ctx->bitstream.paddr;
1676 bitstream_size = ctx->bitstream.size;
1677 src_fourcc = q_data_src->fourcc;
1678 dst_fourcc = q_data_dst->fourcc;
1679
1680 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1681
1682 /* Update coda bitstream read and write pointers from kfifo */
1683 coda_kfifo_sync_to_device_full(ctx);
1684
1685 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
1686 CODA9_FRAME_TILED2LINEAR);
1687 if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
1688 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1689 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
1690 ctx->frame_mem_ctrl |= (0x3 << 9) |
1691 ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
1692 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1693
1694 ctx->display_idx = -1;
1695 ctx->frm_dis_flg = 0;
1696 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1697
1698 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1699 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1700 val = 0;
1701 if (coda_reorder_enable(ctx))
1702 val |= CODA_REORDER_ENABLE;
1703 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1704 val |= CODA_NO_INT_ENABLE;
1705 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1706
1707 ctx->params.codec_mode = ctx->codec->mode;
1708 if (dev->devtype->product == CODA_960 &&
1709 src_fourcc == V4L2_PIX_FMT_MPEG4)
1710 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1711 else
1712 ctx->params.codec_mode_aux = 0;
1713 if (src_fourcc == V4L2_PIX_FMT_MPEG4) {
1714 coda_write(dev, CODA_MP4_CLASS_MPEG4,
1715 CODA_CMD_DEC_SEQ_MP4_ASP_CLASS);
1716 }
1717 if (src_fourcc == V4L2_PIX_FMT_H264) {
1718 if (dev->devtype->product == CODA_HX4 ||
1719 dev->devtype->product == CODA_7541) {
1720 coda_write(dev, ctx->psbuf.paddr,
1721 CODA_CMD_DEC_SEQ_PS_BB_START);
1722 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1723 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1724 }
1725 if (dev->devtype->product == CODA_960) {
1726 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1727 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1728 }
1729 }
1730 if (src_fourcc == V4L2_PIX_FMT_JPEG)
1731 coda_write(dev, 0, CODA_CMD_DEC_SEQ_JPG_THUMB_EN);
1732 if (dev->devtype->product != CODA_960)
1733 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1734
1735 ctx->bit_stream_param = CODA_BIT_DEC_SEQ_INIT_ESCAPE;
1736 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1737 ctx->bit_stream_param = 0;
1738 if (ret) {
1739 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1740 return ret;
1741 }
1742 ctx->initialized = 1;
1743
1744 /* Update kfifo out pointer from coda bitstream read pointer */
1745 coda_kfifo_sync_from_device(ctx);
1746
1747 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1748 v4l2_err(&dev->v4l2_dev,
1749 "CODA_COMMAND_SEQ_INIT failed, error code = 0x%x\n",
1750 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1751 return -EAGAIN;
1752 }
1753
1754 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1755 if (dev->devtype->product == CODA_DX6) {
1756 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1757 height = val & CODADX6_PICHEIGHT_MASK;
1758 } else {
1759 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1760 height = val & CODA7_PICHEIGHT_MASK;
1761 }
1762
1763 if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
1764 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1765 width, height, q_data_dst->bytesperline,
1766 q_data_dst->height);
1767 return -EINVAL;
1768 }
1769
1770 width = round_up(width, 16);
1771 height = round_up(height, 16);
1772
1773 coda_dbg(1, ctx, "start decoding: %dx%d\n", width, height);
1774
1775 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1776 /*
1777 * If the VDOA is used, the decoder needs one additional frame,
1778 * because the frames are freed when the next frame is decoded.
1779 * Otherwise there are visible errors in the decoded frames (green
1780 * regions in displayed frames) and a broken order of frames (earlier
1781 * frames are sporadically displayed after later frames).
1782 */
1783 if (ctx->use_vdoa)
1784 ctx->num_internal_frames += 1;
1785 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1786 v4l2_err(&dev->v4l2_dev,
1787 "not enough framebuffers to decode (%d < %d)\n",
1788 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1789 return -EINVAL;
1790 }
1791
1792 if (src_fourcc == V4L2_PIX_FMT_H264) {
1793 u32 left_right;
1794 u32 top_bottom;
1795
1796 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1797 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1798
1799 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1800 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1801 q_data_dst->rect.width = width - q_data_dst->rect.left -
1802 (left_right & 0x3ff);
1803 q_data_dst->rect.height = height - q_data_dst->rect.top -
1804 (top_bottom & 0x3ff);
1805 }
1806
1807 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1808 if (ret < 0) {
1809 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1810 return ret;
1811 }
1812
1813 /* Tell the decoder how many frame buffers we allocated. */
1814 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1815 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1816
1817 if (dev->devtype->product != CODA_DX6) {
1818 /* Set secondary AXI IRAM */
1819 coda_setup_iram(ctx);
1820
1821 coda_write(dev, ctx->iram_info.buf_bit_use,
1822 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1823 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1824 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1825 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1826 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1827 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1828 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1829 coda_write(dev, ctx->iram_info.buf_ovl_use,
1830 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1831 if (dev->devtype->product == CODA_960) {
1832 coda_write(dev, ctx->iram_info.buf_btp_use,
1833 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1834
1835 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1836 coda9_set_frame_cache(ctx, dst_fourcc);
1837 }
1838 }
1839
1840 if (src_fourcc == V4L2_PIX_FMT_H264) {
1841 coda_write(dev, ctx->slicebuf.paddr,
1842 CODA_CMD_SET_FRAME_SLICE_BB_START);
1843 coda_write(dev, ctx->slicebuf.size / 1024,
1844 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1845 }
1846
1847 if (dev->devtype->product == CODA_HX4 ||
1848 dev->devtype->product == CODA_7541) {
1849 int max_mb_x = 1920 / 16;
1850 int max_mb_y = 1088 / 16;
1851 int max_mb_num = max_mb_x * max_mb_y;
1852
1853 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1854 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1855 } else if (dev->devtype->product == CODA_960) {
1856 int max_mb_x = 1920 / 16;
1857 int max_mb_y = 1088 / 16;
1858 int max_mb_num = max_mb_x * max_mb_y;
1859
1860 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1861 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1862 }
1863
1864 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1865 v4l2_err(&ctx->dev->v4l2_dev,
1866 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1867 return -ETIMEDOUT;
1868 }
1869
1870 return 0;
1871 }
1872
1873 static int coda_start_decoding(struct coda_ctx *ctx)
1874 {
1875 struct coda_dev *dev = ctx->dev;
1876 int ret;
1877
1878 mutex_lock(&dev->coda_mutex);
1879 ret = __coda_start_decoding(ctx);
1880 mutex_unlock(&dev->coda_mutex);
1881
1882 return ret;
1883 }
1884
1885 static int coda_prepare_decode(struct coda_ctx *ctx)
1886 {
1887 struct vb2_v4l2_buffer *dst_buf;
1888 struct coda_dev *dev = ctx->dev;
1889 struct coda_q_data *q_data_dst;
1890 struct coda_buffer_meta *meta;
1891 u32 rot_mode = 0;
1892 u32 reg_addr, reg_stride;
1893
1894 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1895 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1896
1897 /* Try to copy source buffer contents into the bitstream ringbuffer */
1898 mutex_lock(&ctx->bitstream_mutex);
1899 coda_fill_bitstream(ctx, NULL);
1900 mutex_unlock(&ctx->bitstream_mutex);
1901
1902 if (coda_get_bitstream_payload(ctx) < 512 &&
1903 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1904 coda_dbg(1, ctx, "bitstream payload: %d, skipping\n",
1905 coda_get_bitstream_payload(ctx));
1906 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1907 return -EAGAIN;
1908 }
1909
1910 /* Run coda_start_decoding (again) if not yet initialized */
1911 if (!ctx->initialized) {
1912 int ret = __coda_start_decoding(ctx);
1913
1914 if (ret < 0) {
1915 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1916 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1917 return -EAGAIN;
1918 } else {
1919 ctx->initialized = 1;
1920 }
1921 }
1922
1923 if (dev->devtype->product == CODA_960)
1924 coda_set_gdi_regs(ctx);
1925
1926 if (ctx->use_vdoa &&
1927 ctx->display_idx >= 0 &&
1928 ctx->display_idx < ctx->num_internal_frames) {
1929 vdoa_device_run(ctx->vdoa,
1930 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0),
1931 ctx->internal_frames[ctx->display_idx].paddr);
1932 } else {
1933 if (dev->devtype->product == CODA_960) {
1934 /*
1935 * The CODA960 seems to have an internal list of
1936 * buffers with 64 entries that includes the
1937 * registered frame buffers as well as the rotator
1938 * buffer output.
1939 *
1940 * ROT_INDEX needs to be < 0x40, but >
1941 * ctx->num_internal_frames.
1942 */
1943 coda_write(dev,
1944 CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
1945 CODA9_CMD_DEC_PIC_ROT_INDEX);
1946
1947 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1948 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1949 } else {
1950 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1951 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1952 }
1953 coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1954 coda_write(dev, q_data_dst->bytesperline, reg_stride);
1955
1956 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1957 }
1958
1959 coda_write(dev, rot_mode, CODA_CMD_DEC_PIC_ROT_MODE);
1960
1961 switch (dev->devtype->product) {
1962 case CODA_DX6:
1963 /* TBD */
1964 case CODA_HX4:
1965 case CODA_7541:
1966 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1967 break;
1968 case CODA_960:
1969 /* 'hardcode to use interrupt disable mode'? */
1970 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1971 break;
1972 }
1973
1974 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1975
1976 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1977 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1978
1979 if (dev->devtype->product != CODA_DX6)
1980 coda_write(dev, ctx->iram_info.axi_sram_use,
1981 CODA7_REG_BIT_AXI_SRAM_USE);
1982
1983 spin_lock(&ctx->buffer_meta_lock);
1984 meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1985 struct coda_buffer_meta, list);
1986
1987 if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1988
1989 /* If this is the last buffer in the bitstream, add padding */
1990 if (meta->end == ctx->bitstream_fifo.kfifo.in) {
1991 static unsigned char buf[512];
1992 unsigned int pad;
1993
1994 /* Pad to multiple of 256 and then add 256 more */
1995 pad = ((0 - meta->end) & 0xff) + 256;
1996
1997 memset(buf, 0xff, sizeof(buf));
1998
1999 kfifo_in(&ctx->bitstream_fifo, buf, pad);
2000 }
2001 }
2002 spin_unlock(&ctx->buffer_meta_lock);
2003
2004 coda_kfifo_sync_to_device_full(ctx);
2005
2006 /* Clear decode success flag */
2007 coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
2008
2009 /* Clear error return value */
2010 coda_write(dev, 0, CODA_RET_DEC_PIC_ERR_MB);
2011
2012 trace_coda_dec_pic_run(ctx, meta);
2013
2014 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
2015
2016 return 0;
2017 }
2018
2019 static void coda_finish_decode(struct coda_ctx *ctx)
2020 {
2021 struct coda_dev *dev = ctx->dev;
2022 struct coda_q_data *q_data_src;
2023 struct coda_q_data *q_data_dst;
2024 struct vb2_v4l2_buffer *dst_buf;
2025 struct coda_buffer_meta *meta;
2026 int width, height;
2027 int decoded_idx;
2028 int display_idx;
2029 u32 src_fourcc;
2030 int success;
2031 u32 err_mb;
2032 int err_vdoa = 0;
2033 u32 val;
2034
2035 /* Update kfifo out pointer from coda bitstream read pointer */
2036 coda_kfifo_sync_from_device(ctx);
2037
2038 /*
2039 * in stream-end mode, the read pointer can overshoot the write pointer
2040 * by up to 512 bytes
2041 */
2042 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
2043 if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
2044 kfifo_init(&ctx->bitstream_fifo,
2045 ctx->bitstream.vaddr, ctx->bitstream.size);
2046 }
2047
2048 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
2049 src_fourcc = q_data_src->fourcc;
2050
2051 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
2052 if (val != 1)
2053 pr_err("DEC_PIC_SUCCESS = %d\n", val);
2054
2055 success = val & 0x1;
2056 if (!success)
2057 v4l2_err(&dev->v4l2_dev, "decode failed\n");
2058
2059 if (src_fourcc == V4L2_PIX_FMT_H264) {
2060 if (val & (1 << 3))
2061 v4l2_err(&dev->v4l2_dev,
2062 "insufficient PS buffer space (%d bytes)\n",
2063 ctx->psbuf.size);
2064 if (val & (1 << 2))
2065 v4l2_err(&dev->v4l2_dev,
2066 "insufficient slice buffer space (%d bytes)\n",
2067 ctx->slicebuf.size);
2068 }
2069
2070 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
2071 width = (val >> 16) & 0xffff;
2072 height = val & 0xffff;
2073
2074 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
2075
2076 /* frame crop information */
2077 if (src_fourcc == V4L2_PIX_FMT_H264) {
2078 u32 left_right;
2079 u32 top_bottom;
2080
2081 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
2082 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
2083
2084 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
2085 /* Keep current crop information */
2086 } else {
2087 struct v4l2_rect *rect = &q_data_dst->rect;
2088
2089 rect->left = left_right >> 16 & 0xffff;
2090 rect->top = top_bottom >> 16 & 0xffff;
2091 rect->width = width - rect->left -
2092 (left_right & 0xffff);
2093 rect->height = height - rect->top -
2094 (top_bottom & 0xffff);
2095 }
2096 } else {
2097 /* no cropping */
2098 }
2099
2100 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
2101 if (err_mb > 0)
2102 v4l2_err(&dev->v4l2_dev,
2103 "errors in %d macroblocks\n", err_mb);
2104
2105 if (dev->devtype->product == CODA_HX4 ||
2106 dev->devtype->product == CODA_7541) {
2107 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
2108 if (val == 0) {
2109 /* not enough bitstream data */
2110 coda_dbg(1, ctx, "prescan failed: %d\n", val);
2111 ctx->hold = true;
2112 return;
2113 }
2114 }
2115
2116 /* Wait until the VDOA finished writing the previous display frame */
2117 if (ctx->use_vdoa &&
2118 ctx->display_idx >= 0 &&
2119 ctx->display_idx < ctx->num_internal_frames) {
2120 err_vdoa = vdoa_wait_for_completion(ctx->vdoa);
2121 }
2122
2123 ctx->frm_dis_flg = coda_read(dev,
2124 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
2125
2126 /* The previous display frame was copied out and can be overwritten */
2127 if (ctx->display_idx >= 0 &&
2128 ctx->display_idx < ctx->num_internal_frames) {
2129 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
2130 coda_write(dev, ctx->frm_dis_flg,
2131 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
2132 }
2133
2134 /*
2135 * The index of the last decoded frame, not necessarily in
2136 * display order, and the index of the next display frame.
2137 * The latter could have been decoded in a previous run.
2138 */
2139 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
2140 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
2141
2142 if (decoded_idx == -1) {
2143 /* no frame was decoded, but we might have a display frame */
2144 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
2145 ctx->sequence_offset++;
2146 else if (ctx->display_idx < 0)
2147 ctx->hold = true;
2148 } else if (decoded_idx == -2) {
2149 /* no frame was decoded, we still return remaining buffers */
2150 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
2151 v4l2_err(&dev->v4l2_dev,
2152 "decoded frame index out of range: %d\n", decoded_idx);
2153 } else {
2154 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
2155 val -= ctx->sequence_offset;
2156 spin_lock(&ctx->buffer_meta_lock);
2157 if (!list_empty(&ctx->buffer_meta_list)) {
2158 meta = list_first_entry(&ctx->buffer_meta_list,
2159 struct coda_buffer_meta, list);
2160 list_del(&meta->list);
2161 ctx->num_metas--;
2162 spin_unlock(&ctx->buffer_meta_lock);
2163 /*
2164 * Clamp counters to 16 bits for comparison, as the HW
2165 * counter rolls over at this point for h.264. This
2166 * may be different for other formats, but using 16 bits
2167 * should be enough to detect most errors and saves us
2168 * from doing different things based on the format.
2169 */
2170 if ((val & 0xffff) != (meta->sequence & 0xffff)) {
2171 v4l2_err(&dev->v4l2_dev,
2172 "sequence number mismatch (%d(%d) != %d)\n",
2173 val, ctx->sequence_offset,
2174 meta->sequence);
2175 }
2176 ctx->frame_metas[decoded_idx] = *meta;
2177 kfree(meta);
2178 } else {
2179 spin_unlock(&ctx->buffer_meta_lock);
2180 v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
2181 memset(&ctx->frame_metas[decoded_idx], 0,
2182 sizeof(struct coda_buffer_meta));
2183 ctx->frame_metas[decoded_idx].sequence = val;
2184 ctx->sequence_offset++;
2185 }
2186
2187 trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
2188
2189 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
2190 if (val == 0)
2191 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
2192 else if (val == 1)
2193 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
2194 else
2195 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
2196
2197 ctx->frame_errors[decoded_idx] = err_mb;
2198 }
2199
2200 if (display_idx == -1) {
2201 /*
2202 * no more frames to be decoded, but there could still
2203 * be rotator output to dequeue
2204 */
2205 ctx->hold = true;
2206 } else if (display_idx == -3) {
2207 /* possibly prescan failure */
2208 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
2209 v4l2_err(&dev->v4l2_dev,
2210 "presentation frame index out of range: %d\n",
2211 display_idx);
2212 }
2213
2214 /* If a frame was copied out, return it */
2215 if (ctx->display_idx >= 0 &&
2216 ctx->display_idx < ctx->num_internal_frames) {
2217 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2218 dst_buf->sequence = ctx->osequence++;
2219
2220 dst_buf->field = V4L2_FIELD_NONE;
2221 dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
2222 V4L2_BUF_FLAG_PFRAME |
2223 V4L2_BUF_FLAG_BFRAME);
2224 dst_buf->flags |= ctx->frame_types[ctx->display_idx];
2225 meta = &ctx->frame_metas[ctx->display_idx];
2226 dst_buf->timecode = meta->timecode;
2227 dst_buf->vb2_buf.timestamp = meta->timestamp;
2228
2229 trace_coda_dec_rot_done(ctx, dst_buf, meta);
2230
2231 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
2232 q_data_dst->sizeimage);
2233
2234 if (ctx->frame_errors[ctx->display_idx] || err_vdoa)
2235 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2236 else
2237 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
2238
2239 coda_dbg(1, ctx, "job finished: decoded %c frame (%u/%u)\n",
2240 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ? 'I' :
2241 ((dst_buf->flags & V4L2_BUF_FLAG_PFRAME) ? 'P' : 'B'),
2242 dst_buf->sequence, ctx->qsequence);
2243 } else {
2244 coda_dbg(1, ctx, "job finished: no frame decoded (%u/%u)\n",
2245 ctx->osequence, ctx->qsequence);
2246 }
2247
2248 /* The rotator will copy the current display frame next time */
2249 ctx->display_idx = display_idx;
2250
2251 /*
2252 * The current decode run might have brought the bitstream fill level
2253 * below the size where we can start the next decode run. As userspace
2254 * might have filled the output queue completely and might thus be
2255 * blocked, we can't rely on the next qbuf to trigger the bitstream
2256 * refill. Check if we have data to refill the bitstream now.
2257 */
2258 mutex_lock(&ctx->bitstream_mutex);
2259 coda_fill_bitstream(ctx, NULL);
2260 mutex_unlock(&ctx->bitstream_mutex);
2261 }
2262
2263 static void coda_decode_timeout(struct coda_ctx *ctx)
2264 {
2265 struct vb2_v4l2_buffer *dst_buf;
2266
2267 /*
2268 * For now this only handles the case where we would deadlock with
2269 * userspace, i.e. userspace issued DEC_CMD_STOP and waits for EOS,
2270 * but after a failed decode run we would hold the context and wait for
2271 * userspace to queue more buffers.
2272 */
2273 if (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))
2274 return;
2275
2276 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2277 dst_buf->sequence = ctx->qsequence - 1;
2278
2279 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2280 }
2281
2282 const struct coda_context_ops coda_bit_decode_ops = {
2283 .queue_init = coda_decoder_queue_init,
2284 .reqbufs = coda_decoder_reqbufs,
2285 .start_streaming = coda_start_decoding,
2286 .prepare_run = coda_prepare_decode,
2287 .finish_run = coda_finish_decode,
2288 .run_timeout = coda_decode_timeout,
2289 .seq_end_work = coda_seq_end_work,
2290 .release = coda_bit_release,
2291 };
2292
2293 irqreturn_t coda_irq_handler(int irq, void *data)
2294 {
2295 struct coda_dev *dev = data;
2296 struct coda_ctx *ctx;
2297
2298 /* read status register to attend the IRQ */
2299 coda_read(dev, CODA_REG_BIT_INT_STATUS);
2300 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2301 CODA_REG_BIT_INT_CLEAR);
2302
2303 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2304 if (ctx == NULL) {
2305 v4l2_err(&dev->v4l2_dev,
2306 "Instance released before the end of transaction\n");
2307 mutex_unlock(&dev->coda_mutex);
2308 return IRQ_HANDLED;
2309 }
2310
2311 trace_coda_bit_done(ctx);
2312
2313 if (ctx->aborting) {
2314 coda_dbg(1, ctx, "task has been aborted\n");
2315 }
2316
2317 if (coda_isbusy(ctx->dev)) {
2318 coda_dbg(1, ctx, "coda is still busy!!!!\n");
2319 return IRQ_NONE;
2320 }
2321
2322 complete(&ctx->completion);
2323
2324 return IRQ_HANDLED;
2325 }
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