2 * Coda multi-standard codec IP - BIT processor functions
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/clk.h>
16 #include <linux/irqreturn.h>
17 #include <linux/kernel.h>
18 #include <linux/log2.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-mem2mem.h>
28 #include <media/videobuf2-v4l2.h>
29 #include <media/videobuf2-dma-contig.h>
30 #include <media/videobuf2-vmalloc.h>
34 #define CREATE_TRACE_POINTS
37 #define CODA_PARA_BUF_SIZE (10 * 1024)
38 #define CODA7_PS_BUF_SIZE 0x28000
39 #define CODA9_PS_SAVE_SIZE (512 * 1024)
41 #define CODA_DEFAULT_GAMMA 4096
42 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
44 static void coda_free_bitstream_buffer(struct coda_ctx
*ctx
);
46 static inline int coda_is_initialized(struct coda_dev
*dev
)
48 return coda_read(dev
, CODA_REG_BIT_CUR_PC
) != 0;
51 static inline unsigned long coda_isbusy(struct coda_dev
*dev
)
53 return coda_read(dev
, CODA_REG_BIT_BUSY
);
56 static int coda_wait_timeout(struct coda_dev
*dev
)
58 unsigned long timeout
= jiffies
+ msecs_to_jiffies(1000);
60 while (coda_isbusy(dev
)) {
61 if (time_after(jiffies
, timeout
))
67 static void coda_command_async(struct coda_ctx
*ctx
, int cmd
)
69 struct coda_dev
*dev
= ctx
->dev
;
71 if (dev
->devtype
->product
== CODA_HX4
||
72 dev
->devtype
->product
== CODA_7541
||
73 dev
->devtype
->product
== CODA_960
) {
74 /* Restore context related registers to CODA */
75 coda_write(dev
, ctx
->bit_stream_param
,
76 CODA_REG_BIT_BIT_STREAM_PARAM
);
77 coda_write(dev
, ctx
->frm_dis_flg
,
78 CODA_REG_BIT_FRM_DIS_FLG(ctx
->reg_idx
));
79 coda_write(dev
, ctx
->frame_mem_ctrl
,
80 CODA_REG_BIT_FRAME_MEM_CTRL
);
81 coda_write(dev
, ctx
->workbuf
.paddr
, CODA_REG_BIT_WORK_BUF_ADDR
);
84 if (dev
->devtype
->product
== CODA_960
) {
85 coda_write(dev
, 1, CODA9_GDI_WPROT_ERR_CLR
);
86 coda_write(dev
, 0, CODA9_GDI_WPROT_RGN_EN
);
89 coda_write(dev
, CODA_REG_BIT_BUSY_FLAG
, CODA_REG_BIT_BUSY
);
91 coda_write(dev
, ctx
->idx
, CODA_REG_BIT_RUN_INDEX
);
92 coda_write(dev
, ctx
->params
.codec_mode
, CODA_REG_BIT_RUN_COD_STD
);
93 coda_write(dev
, ctx
->params
.codec_mode_aux
, CODA7_REG_BIT_RUN_AUX_STD
);
95 trace_coda_bit_run(ctx
, cmd
);
97 coda_write(dev
, cmd
, CODA_REG_BIT_RUN_COMMAND
);
100 static int coda_command_sync(struct coda_ctx
*ctx
, int cmd
)
102 struct coda_dev
*dev
= ctx
->dev
;
105 coda_command_async(ctx
, cmd
);
106 ret
= coda_wait_timeout(dev
);
107 trace_coda_bit_done(ctx
);
112 int coda_hw_reset(struct coda_ctx
*ctx
)
114 struct coda_dev
*dev
= ctx
->dev
;
115 unsigned long timeout
;
122 idx
= coda_read(dev
, CODA_REG_BIT_RUN_INDEX
);
124 if (dev
->devtype
->product
== CODA_960
) {
125 timeout
= jiffies
+ msecs_to_jiffies(100);
126 coda_write(dev
, 0x11, CODA9_GDI_BUS_CTRL
);
127 while (coda_read(dev
, CODA9_GDI_BUS_STATUS
) != 0x77) {
128 if (time_after(jiffies
, timeout
))
134 ret
= reset_control_reset(dev
->rstc
);
138 if (dev
->devtype
->product
== CODA_960
)
139 coda_write(dev
, 0x00, CODA9_GDI_BUS_CTRL
);
140 coda_write(dev
, CODA_REG_BIT_BUSY_FLAG
, CODA_REG_BIT_BUSY
);
141 coda_write(dev
, CODA_REG_RUN_ENABLE
, CODA_REG_BIT_CODE_RUN
);
142 ret
= coda_wait_timeout(dev
);
143 coda_write(dev
, idx
, CODA_REG_BIT_RUN_INDEX
);
148 static void coda_kfifo_sync_from_device(struct coda_ctx
*ctx
)
150 struct __kfifo
*kfifo
= &ctx
->bitstream_fifo
.kfifo
;
151 struct coda_dev
*dev
= ctx
->dev
;
154 rd_ptr
= coda_read(dev
, CODA_REG_BIT_RD_PTR(ctx
->reg_idx
));
155 kfifo
->out
= (kfifo
->in
& ~kfifo
->mask
) |
156 (rd_ptr
- ctx
->bitstream
.paddr
);
157 if (kfifo
->out
> kfifo
->in
)
158 kfifo
->out
-= kfifo
->mask
+ 1;
161 static void coda_kfifo_sync_to_device_full(struct coda_ctx
*ctx
)
163 struct __kfifo
*kfifo
= &ctx
->bitstream_fifo
.kfifo
;
164 struct coda_dev
*dev
= ctx
->dev
;
167 rd_ptr
= ctx
->bitstream
.paddr
+ (kfifo
->out
& kfifo
->mask
);
168 coda_write(dev
, rd_ptr
, CODA_REG_BIT_RD_PTR(ctx
->reg_idx
));
169 wr_ptr
= ctx
->bitstream
.paddr
+ (kfifo
->in
& kfifo
->mask
);
170 coda_write(dev
, wr_ptr
, CODA_REG_BIT_WR_PTR(ctx
->reg_idx
));
173 static void coda_kfifo_sync_to_device_write(struct coda_ctx
*ctx
)
175 struct __kfifo
*kfifo
= &ctx
->bitstream_fifo
.kfifo
;
176 struct coda_dev
*dev
= ctx
->dev
;
179 wr_ptr
= ctx
->bitstream
.paddr
+ (kfifo
->in
& kfifo
->mask
);
180 coda_write(dev
, wr_ptr
, CODA_REG_BIT_WR_PTR(ctx
->reg_idx
));
183 static int coda_bitstream_pad(struct coda_ctx
*ctx
, u32 size
)
191 buf
= kmalloc(size
, GFP_KERNEL
);
195 coda_h264_filler_nal(size
, buf
);
196 n
= kfifo_in(&ctx
->bitstream_fifo
, buf
, size
);
199 return (n
< size
) ? -ENOSPC
: 0;
202 static int coda_bitstream_queue(struct coda_ctx
*ctx
,
203 struct vb2_v4l2_buffer
*src_buf
)
205 u32 src_size
= vb2_get_plane_payload(&src_buf
->vb2_buf
, 0);
208 n
= kfifo_in(&ctx
->bitstream_fifo
,
209 vb2_plane_vaddr(&src_buf
->vb2_buf
, 0), src_size
);
213 src_buf
->sequence
= ctx
->qsequence
++;
218 static bool coda_bitstream_try_queue(struct coda_ctx
*ctx
,
219 struct vb2_v4l2_buffer
*src_buf
)
221 unsigned long payload
= vb2_get_plane_payload(&src_buf
->vb2_buf
, 0);
224 if (coda_get_bitstream_payload(ctx
) + payload
+ 512 >=
228 if (vb2_plane_vaddr(&src_buf
->vb2_buf
, 0) == NULL
) {
229 v4l2_err(&ctx
->dev
->v4l2_dev
, "trying to queue empty buffer\n");
233 /* Add zero padding before the first H.264 buffer, if it is too small */
234 if (ctx
->qsequence
== 0 && payload
< 512 &&
235 ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_H264
)
236 coda_bitstream_pad(ctx
, 512 - payload
);
238 ret
= coda_bitstream_queue(ctx
, src_buf
);
240 v4l2_err(&ctx
->dev
->v4l2_dev
, "bitstream buffer overflow\n");
243 /* Sync read pointer to device */
244 if (ctx
== v4l2_m2m_get_curr_priv(ctx
->dev
->m2m_dev
))
245 coda_kfifo_sync_to_device_write(ctx
);
252 void coda_fill_bitstream(struct coda_ctx
*ctx
, struct list_head
*buffer_list
)
254 struct vb2_v4l2_buffer
*src_buf
;
255 struct coda_buffer_meta
*meta
;
258 if (ctx
->bit_stream_param
& CODA_BIT_STREAM_END_FLAG
)
261 while (v4l2_m2m_num_src_bufs_ready(ctx
->fh
.m2m_ctx
) > 0) {
263 * Only queue two JPEGs into the bitstream buffer to keep
264 * latency low. We need at least one complete buffer and the
265 * header of another buffer (for prescan) in the bitstream.
267 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_JPEG
&&
271 if (ctx
->num_internal_frames
&&
272 ctx
->num_metas
>= ctx
->num_internal_frames
) {
273 meta
= list_first_entry(&ctx
->buffer_meta_list
,
274 struct coda_buffer_meta
, list
);
277 * If we managed to fill in at least a full reorder
278 * window of buffers (num_internal_frames is a
279 * conservative estimate for this) and the bitstream
280 * prefetcher has at least 2 256 bytes periods beyond
281 * the first buffer to fetch, we can safely stop queuing
282 * in order to limit the decoder drain latency.
284 if (coda_bitstream_can_fetch_past(ctx
, meta
->end
))
288 src_buf
= v4l2_m2m_next_src_buf(ctx
->fh
.m2m_ctx
);
290 /* Drop frames that do not start/end with a SOI/EOI markers */
291 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_JPEG
&&
292 !coda_jpeg_check_buffer(ctx
, &src_buf
->vb2_buf
)) {
293 v4l2_err(&ctx
->dev
->v4l2_dev
,
294 "dropping invalid JPEG frame %d\n",
296 src_buf
= v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
298 struct v4l2_m2m_buffer
*m2m_buf
;
300 m2m_buf
= container_of(src_buf
,
301 struct v4l2_m2m_buffer
,
303 list_add_tail(&m2m_buf
->list
, buffer_list
);
305 v4l2_m2m_buf_done(src_buf
, VB2_BUF_STATE_ERROR
);
310 /* Dump empty buffers */
311 if (!vb2_get_plane_payload(&src_buf
->vb2_buf
, 0)) {
312 src_buf
= v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
313 v4l2_m2m_buf_done(src_buf
, VB2_BUF_STATE_DONE
);
317 /* Buffer start position */
318 start
= ctx
->bitstream_fifo
.kfifo
.in
;
320 if (coda_bitstream_try_queue(ctx
, src_buf
)) {
322 * Source buffer is queued in the bitstream ringbuffer;
323 * queue the timestamp and mark source buffer as done
325 src_buf
= v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
327 meta
= kmalloc(sizeof(*meta
), GFP_KERNEL
);
329 meta
->sequence
= src_buf
->sequence
;
330 meta
->timecode
= src_buf
->timecode
;
331 meta
->timestamp
= src_buf
->vb2_buf
.timestamp
;
333 meta
->end
= ctx
->bitstream_fifo
.kfifo
.in
;
334 spin_lock(&ctx
->buffer_meta_lock
);
335 list_add_tail(&meta
->list
,
336 &ctx
->buffer_meta_list
);
338 spin_unlock(&ctx
->buffer_meta_lock
);
340 trace_coda_bit_queue(ctx
, src_buf
, meta
);
344 struct v4l2_m2m_buffer
*m2m_buf
;
346 m2m_buf
= container_of(src_buf
,
347 struct v4l2_m2m_buffer
,
349 list_add_tail(&m2m_buf
->list
, buffer_list
);
351 v4l2_m2m_buf_done(src_buf
, VB2_BUF_STATE_DONE
);
359 void coda_bit_stream_end_flag(struct coda_ctx
*ctx
)
361 struct coda_dev
*dev
= ctx
->dev
;
363 ctx
->bit_stream_param
|= CODA_BIT_STREAM_END_FLAG
;
365 /* If this context is currently running, update the hardware flag */
366 if ((dev
->devtype
->product
== CODA_960
) &&
368 (ctx
->idx
== coda_read(dev
, CODA_REG_BIT_RUN_INDEX
))) {
369 coda_write(dev
, ctx
->bit_stream_param
,
370 CODA_REG_BIT_BIT_STREAM_PARAM
);
374 static void coda_parabuf_write(struct coda_ctx
*ctx
, int index
, u32 value
)
376 struct coda_dev
*dev
= ctx
->dev
;
377 u32
*p
= ctx
->parabuf
.vaddr
;
379 if (dev
->devtype
->product
== CODA_DX6
)
382 p
[index
^ 1] = value
;
385 static inline int coda_alloc_context_buf(struct coda_ctx
*ctx
,
386 struct coda_aux_buf
*buf
, size_t size
,
389 return coda_alloc_aux_buf(ctx
->dev
, buf
, size
, name
, ctx
->debugfs_entry
);
393 static void coda_free_framebuffers(struct coda_ctx
*ctx
)
397 for (i
= 0; i
< CODA_MAX_FRAMEBUFFERS
; i
++)
398 coda_free_aux_buf(ctx
->dev
, &ctx
->internal_frames
[i
]);
401 static int coda_alloc_framebuffers(struct coda_ctx
*ctx
,
402 struct coda_q_data
*q_data
, u32 fourcc
)
404 struct coda_dev
*dev
= ctx
->dev
;
405 unsigned int ysize
, ycbcr_size
;
409 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_H264
||
410 ctx
->codec
->dst_fourcc
== V4L2_PIX_FMT_H264
||
411 ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_MPEG4
||
412 ctx
->codec
->dst_fourcc
== V4L2_PIX_FMT_MPEG4
)
413 ysize
= round_up(q_data
->rect
.width
, 16) *
414 round_up(q_data
->rect
.height
, 16);
416 ysize
= round_up(q_data
->rect
.width
, 8) * q_data
->rect
.height
;
418 if (ctx
->tiled_map_type
== GDI_TILED_FRAME_MB_RASTER_MAP
)
419 ycbcr_size
= round_up(ysize
, 4096) + ysize
/ 2;
421 ycbcr_size
= ysize
+ ysize
/ 2;
423 /* Allocate frame buffers */
424 for (i
= 0; i
< ctx
->num_internal_frames
; i
++) {
425 size_t size
= ycbcr_size
;
428 /* Add space for mvcol buffers */
429 if (dev
->devtype
->product
!= CODA_DX6
&&
430 (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_H264
||
431 (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_MPEG4
&& i
== 0)))
433 name
= kasprintf(GFP_KERNEL
, "fb%d", i
);
435 coda_free_framebuffers(ctx
);
438 ret
= coda_alloc_context_buf(ctx
, &ctx
->internal_frames
[i
],
442 coda_free_framebuffers(ctx
);
447 /* Register frame buffers in the parameter buffer */
448 for (i
= 0; i
< ctx
->num_internal_frames
; i
++) {
449 u32 y
, cb
, cr
, mvcol
;
451 /* Start addresses of Y, Cb, Cr planes */
452 y
= ctx
->internal_frames
[i
].paddr
;
454 cr
= y
+ ysize
+ ysize
/4;
455 mvcol
= y
+ ysize
+ ysize
/4 + ysize
/4;
456 if (ctx
->tiled_map_type
== GDI_TILED_FRAME_MB_RASTER_MAP
) {
457 cb
= round_up(cb
, 4096);
458 mvcol
= cb
+ ysize
/2;
460 /* Packed 20-bit MSB of base addresses */
461 /* YYYYYCCC, CCyyyyyc, cccc.... */
462 y
= (y
& 0xfffff000) | cb
>> 20;
463 cb
= (cb
& 0x000ff000) << 12;
465 coda_parabuf_write(ctx
, i
* 3 + 0, y
);
466 coda_parabuf_write(ctx
, i
* 3 + 1, cb
);
467 coda_parabuf_write(ctx
, i
* 3 + 2, cr
);
469 if (dev
->devtype
->product
== CODA_DX6
)
472 /* mvcol buffer for h.264 and mpeg4 */
473 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_H264
)
474 coda_parabuf_write(ctx
, 96 + i
, mvcol
);
475 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_MPEG4
&& i
== 0)
476 coda_parabuf_write(ctx
, 97, mvcol
);
482 static void coda_free_context_buffers(struct coda_ctx
*ctx
)
484 struct coda_dev
*dev
= ctx
->dev
;
486 coda_free_aux_buf(dev
, &ctx
->slicebuf
);
487 coda_free_aux_buf(dev
, &ctx
->psbuf
);
488 if (dev
->devtype
->product
!= CODA_DX6
)
489 coda_free_aux_buf(dev
, &ctx
->workbuf
);
490 coda_free_aux_buf(dev
, &ctx
->parabuf
);
493 static int coda_alloc_context_buffers(struct coda_ctx
*ctx
,
494 struct coda_q_data
*q_data
)
496 struct coda_dev
*dev
= ctx
->dev
;
500 if (!ctx
->parabuf
.vaddr
) {
501 ret
= coda_alloc_context_buf(ctx
, &ctx
->parabuf
,
502 CODA_PARA_BUF_SIZE
, "parabuf");
507 if (dev
->devtype
->product
== CODA_DX6
)
510 if (!ctx
->slicebuf
.vaddr
&& q_data
->fourcc
== V4L2_PIX_FMT_H264
) {
511 /* worst case slice size */
512 size
= (DIV_ROUND_UP(q_data
->rect
.width
, 16) *
513 DIV_ROUND_UP(q_data
->rect
.height
, 16)) * 3200 / 8 + 512;
514 ret
= coda_alloc_context_buf(ctx
, &ctx
->slicebuf
, size
,
520 if (!ctx
->psbuf
.vaddr
&& (dev
->devtype
->product
== CODA_HX4
||
521 dev
->devtype
->product
== CODA_7541
)) {
522 ret
= coda_alloc_context_buf(ctx
, &ctx
->psbuf
,
523 CODA7_PS_BUF_SIZE
, "psbuf");
528 if (!ctx
->workbuf
.vaddr
) {
529 size
= dev
->devtype
->workbuf_size
;
530 if (dev
->devtype
->product
== CODA_960
&&
531 q_data
->fourcc
== V4L2_PIX_FMT_H264
)
532 size
+= CODA9_PS_SAVE_SIZE
;
533 ret
= coda_alloc_context_buf(ctx
, &ctx
->workbuf
, size
,
542 coda_free_context_buffers(ctx
);
546 static int coda_encode_header(struct coda_ctx
*ctx
, struct vb2_v4l2_buffer
*buf
,
547 int header_code
, u8
*header
, int *size
)
549 struct vb2_buffer
*vb
= &buf
->vb2_buf
;
550 struct coda_dev
*dev
= ctx
->dev
;
551 struct coda_q_data
*q_data_src
;
557 if (dev
->devtype
->product
== CODA_960
)
558 memset(vb2_plane_vaddr(vb
, 0), 0, 64);
560 coda_write(dev
, vb2_dma_contig_plane_dma_addr(vb
, 0),
561 CODA_CMD_ENC_HEADER_BB_START
);
562 bufsize
= vb2_plane_size(vb
, 0);
563 if (dev
->devtype
->product
== CODA_960
)
565 coda_write(dev
, bufsize
, CODA_CMD_ENC_HEADER_BB_SIZE
);
566 if (dev
->devtype
->product
== CODA_960
&&
567 ctx
->codec
->dst_fourcc
== V4L2_PIX_FMT_H264
&&
568 header_code
== CODA_HEADER_H264_SPS
) {
569 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
570 r
= &q_data_src
->rect
;
572 if (r
->width
% 16 || r
->height
% 16) {
573 u32 crop_right
= round_up(r
->width
, 16) - r
->width
;
574 u32 crop_bottom
= round_up(r
->height
, 16) - r
->height
;
576 coda_write(dev
, crop_right
,
577 CODA9_CMD_ENC_HEADER_FRAME_CROP_H
);
578 coda_write(dev
, crop_bottom
,
579 CODA9_CMD_ENC_HEADER_FRAME_CROP_V
);
580 header_code
|= CODA9_HEADER_FRAME_CROP
;
583 coda_write(dev
, header_code
, CODA_CMD_ENC_HEADER_CODE
);
584 ret
= coda_command_sync(ctx
, CODA_COMMAND_ENCODE_HEADER
);
586 v4l2_err(&dev
->v4l2_dev
, "CODA_COMMAND_ENCODE_HEADER timeout\n");
590 if (dev
->devtype
->product
== CODA_960
) {
591 for (i
= 63; i
> 0; i
--)
592 if (((char *)vb2_plane_vaddr(vb
, 0))[i
] != 0)
596 *size
= coda_read(dev
, CODA_REG_BIT_WR_PTR(ctx
->reg_idx
)) -
597 coda_read(dev
, CODA_CMD_ENC_HEADER_BB_START
);
599 memcpy(header
, vb2_plane_vaddr(vb
, 0), *size
);
604 static phys_addr_t
coda_iram_alloc(struct coda_iram_info
*iram
, size_t size
)
608 size
= round_up(size
, 1024);
609 if (size
> iram
->remaining
)
611 iram
->remaining
-= size
;
613 ret
= iram
->next_paddr
;
614 iram
->next_paddr
+= size
;
619 static void coda_setup_iram(struct coda_ctx
*ctx
)
621 struct coda_iram_info
*iram_info
= &ctx
->iram_info
;
622 struct coda_dev
*dev
= ctx
->dev
;
630 memset(iram_info
, 0, sizeof(*iram_info
));
631 iram_info
->next_paddr
= dev
->iram
.paddr
;
632 iram_info
->remaining
= dev
->iram
.size
;
634 if (!dev
->iram
.vaddr
)
637 switch (dev
->devtype
->product
) {
639 dbk_bits
= CODA7_USE_HOST_DBK_ENABLE
;
640 bit_bits
= CODA7_USE_HOST_BIT_ENABLE
;
641 ip_bits
= CODA7_USE_HOST_IP_ENABLE
;
642 me_bits
= CODA7_USE_HOST_ME_ENABLE
;
645 dbk_bits
= CODA7_USE_HOST_DBK_ENABLE
| CODA7_USE_DBK_ENABLE
;
646 bit_bits
= CODA7_USE_HOST_BIT_ENABLE
| CODA7_USE_BIT_ENABLE
;
647 ip_bits
= CODA7_USE_HOST_IP_ENABLE
| CODA7_USE_IP_ENABLE
;
648 me_bits
= CODA7_USE_HOST_ME_ENABLE
| CODA7_USE_ME_ENABLE
;
651 dbk_bits
= CODA9_USE_HOST_DBK_ENABLE
| CODA9_USE_DBK_ENABLE
;
652 bit_bits
= CODA9_USE_HOST_BIT_ENABLE
| CODA7_USE_BIT_ENABLE
;
653 ip_bits
= CODA9_USE_HOST_IP_ENABLE
| CODA7_USE_IP_ENABLE
;
656 default: /* CODA_DX6 */
660 if (ctx
->inst_type
== CODA_INST_ENCODER
) {
661 struct coda_q_data
*q_data_src
;
663 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
664 mb_width
= DIV_ROUND_UP(q_data_src
->rect
.width
, 16);
665 w128
= mb_width
* 128;
668 /* Prioritize in case IRAM is too small for everything */
669 if (dev
->devtype
->product
== CODA_HX4
||
670 dev
->devtype
->product
== CODA_7541
) {
671 iram_info
->search_ram_size
= round_up(mb_width
* 16 *
673 iram_info
->search_ram_paddr
= coda_iram_alloc(iram_info
,
674 iram_info
->search_ram_size
);
675 if (!iram_info
->search_ram_paddr
) {
676 pr_err("IRAM is smaller than the search ram size\n");
679 iram_info
->axi_sram_use
|= me_bits
;
682 /* Only H.264BP and H.263P3 are considered */
683 iram_info
->buf_dbk_y_use
= coda_iram_alloc(iram_info
, w64
);
684 iram_info
->buf_dbk_c_use
= coda_iram_alloc(iram_info
, w64
);
685 if (!iram_info
->buf_dbk_c_use
)
687 iram_info
->axi_sram_use
|= dbk_bits
;
689 iram_info
->buf_bit_use
= coda_iram_alloc(iram_info
, w128
);
690 if (!iram_info
->buf_bit_use
)
692 iram_info
->axi_sram_use
|= bit_bits
;
694 iram_info
->buf_ip_ac_dc_use
= coda_iram_alloc(iram_info
, w128
);
695 if (!iram_info
->buf_ip_ac_dc_use
)
697 iram_info
->axi_sram_use
|= ip_bits
;
699 /* OVL and BTP disabled for encoder */
700 } else if (ctx
->inst_type
== CODA_INST_DECODER
) {
701 struct coda_q_data
*q_data_dst
;
703 q_data_dst
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_CAPTURE
);
704 mb_width
= DIV_ROUND_UP(q_data_dst
->width
, 16);
705 w128
= mb_width
* 128;
707 iram_info
->buf_dbk_y_use
= coda_iram_alloc(iram_info
, w128
);
708 iram_info
->buf_dbk_c_use
= coda_iram_alloc(iram_info
, w128
);
709 if (!iram_info
->buf_dbk_c_use
)
711 iram_info
->axi_sram_use
|= dbk_bits
;
713 iram_info
->buf_bit_use
= coda_iram_alloc(iram_info
, w128
);
714 if (!iram_info
->buf_bit_use
)
716 iram_info
->axi_sram_use
|= bit_bits
;
718 iram_info
->buf_ip_ac_dc_use
= coda_iram_alloc(iram_info
, w128
);
719 if (!iram_info
->buf_ip_ac_dc_use
)
721 iram_info
->axi_sram_use
|= ip_bits
;
723 /* OVL and BTP unused as there is no VC1 support yet */
727 if (!(iram_info
->axi_sram_use
& CODA7_USE_HOST_IP_ENABLE
))
728 coda_dbg(1, ctx
, "IRAM smaller than needed\n");
730 if (dev
->devtype
->product
== CODA_HX4
||
731 dev
->devtype
->product
== CODA_7541
) {
732 /* TODO - Enabling these causes picture errors on CODA7541 */
733 if (ctx
->inst_type
== CODA_INST_DECODER
) {
735 iram_info
->axi_sram_use
&= ~(CODA7_USE_HOST_IP_ENABLE
|
736 CODA7_USE_IP_ENABLE
);
739 iram_info
->axi_sram_use
&= ~(CODA7_USE_HOST_IP_ENABLE
|
740 CODA7_USE_HOST_DBK_ENABLE
|
741 CODA7_USE_IP_ENABLE
|
742 CODA7_USE_DBK_ENABLE
);
747 static u32 coda_supported_firmwares
[] = {
748 CODA_FIRMWARE_VERNUM(CODA_DX6
, 2, 2, 5),
749 CODA_FIRMWARE_VERNUM(CODA_HX4
, 1, 4, 50),
750 CODA_FIRMWARE_VERNUM(CODA_7541
, 1, 4, 50),
751 CODA_FIRMWARE_VERNUM(CODA_960
, 2, 1, 5),
752 CODA_FIRMWARE_VERNUM(CODA_960
, 2, 1, 9),
753 CODA_FIRMWARE_VERNUM(CODA_960
, 2, 3, 10),
754 CODA_FIRMWARE_VERNUM(CODA_960
, 3, 1, 1),
757 static bool coda_firmware_supported(u32 vernum
)
761 for (i
= 0; i
< ARRAY_SIZE(coda_supported_firmwares
); i
++)
762 if (vernum
== coda_supported_firmwares
[i
])
767 int coda_check_firmware(struct coda_dev
*dev
)
769 u16 product
, major
, minor
, release
;
773 ret
= clk_prepare_enable(dev
->clk_per
);
777 ret
= clk_prepare_enable(dev
->clk_ahb
);
781 coda_write(dev
, 0, CODA_CMD_FIRMWARE_VERNUM
);
782 coda_write(dev
, CODA_REG_BIT_BUSY_FLAG
, CODA_REG_BIT_BUSY
);
783 coda_write(dev
, 0, CODA_REG_BIT_RUN_INDEX
);
784 coda_write(dev
, 0, CODA_REG_BIT_RUN_COD_STD
);
785 coda_write(dev
, CODA_COMMAND_FIRMWARE_GET
, CODA_REG_BIT_RUN_COMMAND
);
786 if (coda_wait_timeout(dev
)) {
787 v4l2_err(&dev
->v4l2_dev
, "firmware get command error\n");
792 if (dev
->devtype
->product
== CODA_960
) {
793 data
= coda_read(dev
, CODA9_CMD_FIRMWARE_CODE_REV
);
794 v4l2_info(&dev
->v4l2_dev
, "Firmware code revision: %d\n",
798 /* Check we are compatible with the loaded firmware */
799 data
= coda_read(dev
, CODA_CMD_FIRMWARE_VERNUM
);
800 product
= CODA_FIRMWARE_PRODUCT(data
);
801 major
= CODA_FIRMWARE_MAJOR(data
);
802 minor
= CODA_FIRMWARE_MINOR(data
);
803 release
= CODA_FIRMWARE_RELEASE(data
);
805 clk_disable_unprepare(dev
->clk_per
);
806 clk_disable_unprepare(dev
->clk_ahb
);
808 if (product
!= dev
->devtype
->product
) {
809 v4l2_err(&dev
->v4l2_dev
,
810 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
811 coda_product_name(dev
->devtype
->product
),
812 coda_product_name(product
), major
, minor
, release
);
816 v4l2_info(&dev
->v4l2_dev
, "Initialized %s.\n",
817 coda_product_name(product
));
819 if (coda_firmware_supported(data
)) {
820 v4l2_info(&dev
->v4l2_dev
, "Firmware version: %u.%u.%u\n",
821 major
, minor
, release
);
823 v4l2_warn(&dev
->v4l2_dev
,
824 "Unsupported firmware version: %u.%u.%u\n",
825 major
, minor
, release
);
831 clk_disable_unprepare(dev
->clk_ahb
);
833 clk_disable_unprepare(dev
->clk_per
);
838 static void coda9_set_frame_cache(struct coda_ctx
*ctx
, u32 fourcc
)
840 u32 cache_size
, cache_config
;
842 if (ctx
->tiled_map_type
== GDI_LINEAR_FRAME_MAP
) {
843 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
844 cache_size
= 0x20262024;
845 cache_config
= 2 << CODA9_CACHE_PAGEMERGE_OFFSET
;
847 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
848 cache_size
= 0x02440243;
849 cache_config
= 1 << CODA9_CACHE_PAGEMERGE_OFFSET
;
851 coda_write(ctx
->dev
, cache_size
, CODA9_CMD_SET_FRAME_CACHE_SIZE
);
852 if (fourcc
== V4L2_PIX_FMT_NV12
|| fourcc
== V4L2_PIX_FMT_YUYV
) {
853 cache_config
|= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET
|
854 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET
|
855 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET
;
857 cache_config
|= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET
|
858 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET
|
859 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET
;
861 coda_write(ctx
->dev
, cache_config
, CODA9_CMD_SET_FRAME_CACHE_CONFIG
);
865 * Encoder context operations
868 static int coda_encoder_reqbufs(struct coda_ctx
*ctx
,
869 struct v4l2_requestbuffers
*rb
)
871 struct coda_q_data
*q_data_src
;
874 if (rb
->type
!= V4L2_BUF_TYPE_VIDEO_OUTPUT
)
878 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
879 ret
= coda_alloc_context_buffers(ctx
, q_data_src
);
883 coda_free_context_buffers(ctx
);
889 static int coda_start_encoding(struct coda_ctx
*ctx
)
891 struct coda_dev
*dev
= ctx
->dev
;
892 struct v4l2_device
*v4l2_dev
= &dev
->v4l2_dev
;
893 struct coda_q_data
*q_data_src
, *q_data_dst
;
894 u32 bitstream_buf
, bitstream_size
;
895 struct vb2_v4l2_buffer
*buf
;
896 int gamma
, ret
, value
;
901 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
902 q_data_dst
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_CAPTURE
);
903 dst_fourcc
= q_data_dst
->fourcc
;
905 buf
= v4l2_m2m_next_dst_buf(ctx
->fh
.m2m_ctx
);
906 bitstream_buf
= vb2_dma_contig_plane_dma_addr(&buf
->vb2_buf
, 0);
907 bitstream_size
= q_data_dst
->sizeimage
;
909 if (!coda_is_initialized(dev
)) {
910 v4l2_err(v4l2_dev
, "coda is not initialized.\n");
914 if (dst_fourcc
== V4L2_PIX_FMT_JPEG
) {
915 if (!ctx
->params
.jpeg_qmat_tab
[0])
916 ctx
->params
.jpeg_qmat_tab
[0] = kmalloc(64, GFP_KERNEL
);
917 if (!ctx
->params
.jpeg_qmat_tab
[1])
918 ctx
->params
.jpeg_qmat_tab
[1] = kmalloc(64, GFP_KERNEL
);
919 coda_set_jpeg_compression_quality(ctx
, ctx
->params
.jpeg_quality
);
922 mutex_lock(&dev
->coda_mutex
);
924 coda_write(dev
, ctx
->parabuf
.paddr
, CODA_REG_BIT_PARA_BUF_ADDR
);
925 coda_write(dev
, bitstream_buf
, CODA_REG_BIT_RD_PTR(ctx
->reg_idx
));
926 coda_write(dev
, bitstream_buf
, CODA_REG_BIT_WR_PTR(ctx
->reg_idx
));
927 switch (dev
->devtype
->product
) {
929 coda_write(dev
, CODADX6_STREAM_BUF_DYNALLOC_EN
|
930 CODADX6_STREAM_BUF_PIC_RESET
, CODA_REG_BIT_STREAM_CTRL
);
933 coda_write(dev
, 0, CODA9_GDI_WPROT_RGN_EN
);
937 coda_write(dev
, CODA7_STREAM_BUF_DYNALLOC_EN
|
938 CODA7_STREAM_BUF_PIC_RESET
, CODA_REG_BIT_STREAM_CTRL
);
942 ctx
->frame_mem_ctrl
&= ~(CODA_FRAME_CHROMA_INTERLEAVE
| (0x3 << 9) |
943 CODA9_FRAME_TILED2LINEAR
);
944 if (q_data_src
->fourcc
== V4L2_PIX_FMT_NV12
)
945 ctx
->frame_mem_ctrl
|= CODA_FRAME_CHROMA_INTERLEAVE
;
946 if (ctx
->tiled_map_type
== GDI_TILED_FRAME_MB_RASTER_MAP
)
947 ctx
->frame_mem_ctrl
|= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR
;
948 coda_write(dev
, ctx
->frame_mem_ctrl
, CODA_REG_BIT_FRAME_MEM_CTRL
);
950 if (dev
->devtype
->product
== CODA_DX6
) {
951 /* Configure the coda */
952 coda_write(dev
, dev
->iram
.paddr
,
953 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR
);
956 /* Could set rotation here if needed */
958 switch (dev
->devtype
->product
) {
960 value
= (q_data_src
->rect
.width
& CODADX6_PICWIDTH_MASK
)
961 << CODADX6_PICWIDTH_OFFSET
;
962 value
|= (q_data_src
->rect
.height
& CODADX6_PICHEIGHT_MASK
)
963 << CODA_PICHEIGHT_OFFSET
;
967 if (dst_fourcc
== V4L2_PIX_FMT_H264
) {
968 value
= (round_up(q_data_src
->rect
.width
, 16) &
969 CODA7_PICWIDTH_MASK
) << CODA7_PICWIDTH_OFFSET
;
970 value
|= (round_up(q_data_src
->rect
.height
, 16) &
971 CODA7_PICHEIGHT_MASK
) << CODA_PICHEIGHT_OFFSET
;
976 value
= (q_data_src
->rect
.width
& CODA7_PICWIDTH_MASK
)
977 << CODA7_PICWIDTH_OFFSET
;
978 value
|= (q_data_src
->rect
.height
& CODA7_PICHEIGHT_MASK
)
979 << CODA_PICHEIGHT_OFFSET
;
981 coda_write(dev
, value
, CODA_CMD_ENC_SEQ_SRC_SIZE
);
982 if (dst_fourcc
== V4L2_PIX_FMT_JPEG
)
983 ctx
->params
.framerate
= 0;
984 coda_write(dev
, ctx
->params
.framerate
,
985 CODA_CMD_ENC_SEQ_SRC_F_RATE
);
987 ctx
->params
.codec_mode
= ctx
->codec
->mode
;
988 switch (dst_fourcc
) {
989 case V4L2_PIX_FMT_MPEG4
:
990 if (dev
->devtype
->product
== CODA_960
)
991 coda_write(dev
, CODA9_STD_MPEG4
,
992 CODA_CMD_ENC_SEQ_COD_STD
);
994 coda_write(dev
, CODA_STD_MPEG4
,
995 CODA_CMD_ENC_SEQ_COD_STD
);
996 coda_write(dev
, 0, CODA_CMD_ENC_SEQ_MP4_PARA
);
998 case V4L2_PIX_FMT_H264
:
999 if (dev
->devtype
->product
== CODA_960
)
1000 coda_write(dev
, CODA9_STD_H264
,
1001 CODA_CMD_ENC_SEQ_COD_STD
);
1003 coda_write(dev
, CODA_STD_H264
,
1004 CODA_CMD_ENC_SEQ_COD_STD
);
1005 value
= ((ctx
->params
.h264_disable_deblocking_filter_idc
&
1006 CODA_264PARAM_DISABLEDEBLK_MASK
) <<
1007 CODA_264PARAM_DISABLEDEBLK_OFFSET
) |
1008 ((ctx
->params
.h264_slice_alpha_c0_offset_div2
&
1009 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK
) <<
1010 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET
) |
1011 ((ctx
->params
.h264_slice_beta_offset_div2
&
1012 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK
) <<
1013 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET
) |
1014 (ctx
->params
.h264_constrained_intra_pred_flag
<<
1015 CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_OFFSET
) |
1016 (ctx
->params
.h264_chroma_qp_index_offset
&
1017 CODA_264PARAM_CHROMAQPOFFSET_MASK
);
1018 coda_write(dev
, value
, CODA_CMD_ENC_SEQ_264_PARA
);
1020 case V4L2_PIX_FMT_JPEG
:
1021 coda_write(dev
, 0, CODA_CMD_ENC_SEQ_JPG_PARA
);
1022 coda_write(dev
, ctx
->params
.jpeg_restart_interval
,
1023 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL
);
1024 coda_write(dev
, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN
);
1025 coda_write(dev
, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE
);
1026 coda_write(dev
, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET
);
1028 coda_jpeg_write_tables(ctx
);
1032 "dst format (0x%08x) invalid.\n", dst_fourcc
);
1038 * slice mode and GOP size registers are used for thumb size/offset
1041 if (dst_fourcc
!= V4L2_PIX_FMT_JPEG
) {
1042 switch (ctx
->params
.slice_mode
) {
1043 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE
:
1046 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB
:
1047 value
= (ctx
->params
.slice_max_mb
&
1048 CODA_SLICING_SIZE_MASK
)
1049 << CODA_SLICING_SIZE_OFFSET
;
1050 value
|= (1 & CODA_SLICING_UNIT_MASK
)
1051 << CODA_SLICING_UNIT_OFFSET
;
1052 value
|= 1 & CODA_SLICING_MODE_MASK
;
1054 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES
:
1055 value
= (ctx
->params
.slice_max_bits
&
1056 CODA_SLICING_SIZE_MASK
)
1057 << CODA_SLICING_SIZE_OFFSET
;
1058 value
|= (0 & CODA_SLICING_UNIT_MASK
)
1059 << CODA_SLICING_UNIT_OFFSET
;
1060 value
|= 1 & CODA_SLICING_MODE_MASK
;
1063 coda_write(dev
, value
, CODA_CMD_ENC_SEQ_SLICE_MODE
);
1064 value
= ctx
->params
.gop_size
;
1065 coda_write(dev
, value
, CODA_CMD_ENC_SEQ_GOP_SIZE
);
1068 if (ctx
->params
.bitrate
) {
1069 /* Rate control enabled */
1070 value
= (ctx
->params
.bitrate
& CODA_RATECONTROL_BITRATE_MASK
)
1071 << CODA_RATECONTROL_BITRATE_OFFSET
;
1072 value
|= 1 & CODA_RATECONTROL_ENABLE_MASK
;
1073 value
|= (ctx
->params
.vbv_delay
&
1074 CODA_RATECONTROL_INITIALDELAY_MASK
)
1075 << CODA_RATECONTROL_INITIALDELAY_OFFSET
;
1076 if (dev
->devtype
->product
== CODA_960
)
1077 value
|= BIT(31); /* disable autoskip */
1081 coda_write(dev
, value
, CODA_CMD_ENC_SEQ_RC_PARA
);
1083 coda_write(dev
, ctx
->params
.vbv_size
, CODA_CMD_ENC_SEQ_RC_BUF_SIZE
);
1084 coda_write(dev
, ctx
->params
.intra_refresh
,
1085 CODA_CMD_ENC_SEQ_INTRA_REFRESH
);
1087 coda_write(dev
, bitstream_buf
, CODA_CMD_ENC_SEQ_BB_START
);
1088 coda_write(dev
, bitstream_size
/ 1024, CODA_CMD_ENC_SEQ_BB_SIZE
);
1092 if (dev
->devtype
->product
== CODA_960
)
1093 gamma
= CODA9_DEFAULT_GAMMA
;
1095 gamma
= CODA_DEFAULT_GAMMA
;
1097 coda_write(dev
, (gamma
& CODA_GAMMA_MASK
) << CODA_GAMMA_OFFSET
,
1098 CODA_CMD_ENC_SEQ_RC_GAMMA
);
1101 if (ctx
->params
.h264_min_qp
|| ctx
->params
.h264_max_qp
) {
1103 ctx
->params
.h264_min_qp
<< CODA_QPMIN_OFFSET
|
1104 ctx
->params
.h264_max_qp
<< CODA_QPMAX_OFFSET
,
1105 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX
);
1107 if (dev
->devtype
->product
== CODA_960
) {
1108 if (ctx
->params
.h264_max_qp
)
1109 value
|= 1 << CODA9_OPTION_RCQPMAX_OFFSET
;
1110 if (CODA_DEFAULT_GAMMA
> 0)
1111 value
|= 1 << CODA9_OPTION_GAMMA_OFFSET
;
1113 if (CODA_DEFAULT_GAMMA
> 0) {
1114 if (dev
->devtype
->product
== CODA_DX6
)
1115 value
|= 1 << CODADX6_OPTION_GAMMA_OFFSET
;
1117 value
|= 1 << CODA7_OPTION_GAMMA_OFFSET
;
1119 if (ctx
->params
.h264_min_qp
)
1120 value
|= 1 << CODA7_OPTION_RCQPMIN_OFFSET
;
1121 if (ctx
->params
.h264_max_qp
)
1122 value
|= 1 << CODA7_OPTION_RCQPMAX_OFFSET
;
1124 coda_write(dev
, value
, CODA_CMD_ENC_SEQ_OPTION
);
1126 coda_write(dev
, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE
);
1128 coda_setup_iram(ctx
);
1130 if (dst_fourcc
== V4L2_PIX_FMT_H264
) {
1131 switch (dev
->devtype
->product
) {
1133 value
= FMO_SLICE_SAVE_BUF_SIZE
<< 7;
1134 coda_write(dev
, value
, CODADX6_CMD_ENC_SEQ_FMO
);
1138 coda_write(dev
, ctx
->iram_info
.search_ram_paddr
,
1139 CODA7_CMD_ENC_SEQ_SEARCH_BASE
);
1140 coda_write(dev
, ctx
->iram_info
.search_ram_size
,
1141 CODA7_CMD_ENC_SEQ_SEARCH_SIZE
);
1144 coda_write(dev
, 0, CODA9_CMD_ENC_SEQ_ME_OPTION
);
1145 coda_write(dev
, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT
);
1149 ret
= coda_command_sync(ctx
, CODA_COMMAND_SEQ_INIT
);
1151 v4l2_err(v4l2_dev
, "CODA_COMMAND_SEQ_INIT timeout\n");
1155 if (coda_read(dev
, CODA_RET_ENC_SEQ_SUCCESS
) == 0) {
1156 v4l2_err(v4l2_dev
, "CODA_COMMAND_SEQ_INIT failed\n");
1160 ctx
->initialized
= 1;
1162 if (dst_fourcc
!= V4L2_PIX_FMT_JPEG
) {
1163 if (dev
->devtype
->product
== CODA_960
)
1164 ctx
->num_internal_frames
= 4;
1166 ctx
->num_internal_frames
= 2;
1167 ret
= coda_alloc_framebuffers(ctx
, q_data_src
, dst_fourcc
);
1169 v4l2_err(v4l2_dev
, "failed to allocate framebuffers\n");
1173 stride
= q_data_src
->bytesperline
;
1175 ctx
->num_internal_frames
= 0;
1179 coda_write(dev
, num_fb
, CODA_CMD_SET_FRAME_BUF_NUM
);
1180 coda_write(dev
, stride
, CODA_CMD_SET_FRAME_BUF_STRIDE
);
1182 if (dev
->devtype
->product
== CODA_HX4
||
1183 dev
->devtype
->product
== CODA_7541
) {
1184 coda_write(dev
, q_data_src
->bytesperline
,
1185 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE
);
1187 if (dev
->devtype
->product
!= CODA_DX6
) {
1188 coda_write(dev
, ctx
->iram_info
.buf_bit_use
,
1189 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR
);
1190 coda_write(dev
, ctx
->iram_info
.buf_ip_ac_dc_use
,
1191 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR
);
1192 coda_write(dev
, ctx
->iram_info
.buf_dbk_y_use
,
1193 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR
);
1194 coda_write(dev
, ctx
->iram_info
.buf_dbk_c_use
,
1195 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR
);
1196 coda_write(dev
, ctx
->iram_info
.buf_ovl_use
,
1197 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR
);
1198 if (dev
->devtype
->product
== CODA_960
) {
1199 coda_write(dev
, ctx
->iram_info
.buf_btp_use
,
1200 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR
);
1202 coda9_set_frame_cache(ctx
, q_data_src
->fourcc
);
1205 coda_write(dev
, ctx
->internal_frames
[2].paddr
,
1206 CODA9_CMD_SET_FRAME_SUBSAMP_A
);
1207 coda_write(dev
, ctx
->internal_frames
[3].paddr
,
1208 CODA9_CMD_SET_FRAME_SUBSAMP_B
);
1212 ret
= coda_command_sync(ctx
, CODA_COMMAND_SET_FRAME_BUF
);
1214 v4l2_err(v4l2_dev
, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1218 coda_dbg(1, ctx
, "start encoding %dx%d %4.4s->%4.4s @ %d/%d Hz\n",
1219 q_data_src
->rect
.width
, q_data_src
->rect
.height
,
1220 (char *)&ctx
->codec
->src_fourcc
, (char *)&dst_fourcc
,
1221 ctx
->params
.framerate
& 0xffff,
1222 (ctx
->params
.framerate
>> 16) + 1);
1224 /* Save stream headers */
1225 buf
= v4l2_m2m_next_dst_buf(ctx
->fh
.m2m_ctx
);
1226 switch (dst_fourcc
) {
1227 case V4L2_PIX_FMT_H264
:
1229 * Get SPS in the first frame and copy it to an
1230 * intermediate buffer.
1232 ret
= coda_encode_header(ctx
, buf
, CODA_HEADER_H264_SPS
,
1233 &ctx
->vpu_header
[0][0],
1234 &ctx
->vpu_header_size
[0]);
1239 * If visible width or height are not aligned to macroblock
1240 * size, the crop_right and crop_bottom SPS fields must be set
1241 * to the difference between visible and coded size. This is
1242 * only supported by CODA960 firmware. All others do not allow
1243 * writing frame cropping parameters, so we have to manually
1244 * fix up the SPS RBSP (Sequence Parameter Set Raw Byte
1245 * Sequence Payload) ourselves.
1247 if (ctx
->dev
->devtype
->product
!= CODA_960
&&
1248 ((q_data_src
->rect
.width
% 16) ||
1249 (q_data_src
->rect
.height
% 16))) {
1250 ret
= coda_h264_sps_fixup(ctx
, q_data_src
->rect
.width
,
1251 q_data_src
->rect
.height
,
1252 &ctx
->vpu_header
[0][0],
1253 &ctx
->vpu_header_size
[0],
1254 sizeof(ctx
->vpu_header
[0]));
1260 * Get PPS in the first frame and copy it to an
1261 * intermediate buffer.
1263 ret
= coda_encode_header(ctx
, buf
, CODA_HEADER_H264_PPS
,
1264 &ctx
->vpu_header
[1][0],
1265 &ctx
->vpu_header_size
[1]);
1270 * Length of H.264 headers is variable and thus it might not be
1271 * aligned for the coda to append the encoded frame. In that is
1272 * the case a filler NAL must be added to header 2.
1274 ctx
->vpu_header_size
[2] = coda_h264_padding(
1275 (ctx
->vpu_header_size
[0] +
1276 ctx
->vpu_header_size
[1]),
1277 ctx
->vpu_header
[2]);
1279 case V4L2_PIX_FMT_MPEG4
:
1281 * Get VOS in the first frame and copy it to an
1282 * intermediate buffer
1284 ret
= coda_encode_header(ctx
, buf
, CODA_HEADER_MP4V_VOS
,
1285 &ctx
->vpu_header
[0][0],
1286 &ctx
->vpu_header_size
[0]);
1290 ret
= coda_encode_header(ctx
, buf
, CODA_HEADER_MP4V_VIS
,
1291 &ctx
->vpu_header
[1][0],
1292 &ctx
->vpu_header_size
[1]);
1296 ret
= coda_encode_header(ctx
, buf
, CODA_HEADER_MP4V_VOL
,
1297 &ctx
->vpu_header
[2][0],
1298 &ctx
->vpu_header_size
[2]);
1303 /* No more formats need to save headers at the moment */
1308 mutex_unlock(&dev
->coda_mutex
);
1312 static int coda_prepare_encode(struct coda_ctx
*ctx
)
1314 struct coda_q_data
*q_data_src
, *q_data_dst
;
1315 struct vb2_v4l2_buffer
*src_buf
, *dst_buf
;
1316 struct coda_dev
*dev
= ctx
->dev
;
1318 int quant_param
= 0;
1319 u32 pic_stream_buffer_addr
, pic_stream_buffer_size
;
1324 src_buf
= v4l2_m2m_next_src_buf(ctx
->fh
.m2m_ctx
);
1325 dst_buf
= v4l2_m2m_next_dst_buf(ctx
->fh
.m2m_ctx
);
1326 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
1327 q_data_dst
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_CAPTURE
);
1328 dst_fourcc
= q_data_dst
->fourcc
;
1330 src_buf
->sequence
= ctx
->osequence
;
1331 dst_buf
->sequence
= ctx
->osequence
;
1334 force_ipicture
= ctx
->params
.force_ipicture
;
1336 ctx
->params
.force_ipicture
= false;
1337 else if (ctx
->params
.gop_size
!= 0 &&
1338 (src_buf
->sequence
% ctx
->params
.gop_size
) == 0)
1342 * Workaround coda firmware BUG that only marks the first
1343 * frame as IDR. This is a problem for some decoders that can't
1344 * recover when a frame is lost.
1346 if (!force_ipicture
) {
1347 src_buf
->flags
|= V4L2_BUF_FLAG_PFRAME
;
1348 src_buf
->flags
&= ~V4L2_BUF_FLAG_KEYFRAME
;
1350 src_buf
->flags
|= V4L2_BUF_FLAG_KEYFRAME
;
1351 src_buf
->flags
&= ~V4L2_BUF_FLAG_PFRAME
;
1354 if (dev
->devtype
->product
== CODA_960
)
1355 coda_set_gdi_regs(ctx
);
1358 * Copy headers in front of the first frame and forced I frames for
1359 * H.264 only. In MPEG4 they are already copied by the CODA.
1361 if (src_buf
->sequence
== 0 || force_ipicture
) {
1362 pic_stream_buffer_addr
=
1363 vb2_dma_contig_plane_dma_addr(&dst_buf
->vb2_buf
, 0) +
1364 ctx
->vpu_header_size
[0] +
1365 ctx
->vpu_header_size
[1] +
1366 ctx
->vpu_header_size
[2];
1367 pic_stream_buffer_size
= q_data_dst
->sizeimage
-
1368 ctx
->vpu_header_size
[0] -
1369 ctx
->vpu_header_size
[1] -
1370 ctx
->vpu_header_size
[2];
1371 memcpy(vb2_plane_vaddr(&dst_buf
->vb2_buf
, 0),
1372 &ctx
->vpu_header
[0][0], ctx
->vpu_header_size
[0]);
1373 memcpy(vb2_plane_vaddr(&dst_buf
->vb2_buf
, 0)
1374 + ctx
->vpu_header_size
[0], &ctx
->vpu_header
[1][0],
1375 ctx
->vpu_header_size
[1]);
1376 memcpy(vb2_plane_vaddr(&dst_buf
->vb2_buf
, 0)
1377 + ctx
->vpu_header_size
[0] + ctx
->vpu_header_size
[1],
1378 &ctx
->vpu_header
[2][0], ctx
->vpu_header_size
[2]);
1380 pic_stream_buffer_addr
=
1381 vb2_dma_contig_plane_dma_addr(&dst_buf
->vb2_buf
, 0);
1382 pic_stream_buffer_size
= q_data_dst
->sizeimage
;
1385 if (force_ipicture
) {
1386 switch (dst_fourcc
) {
1387 case V4L2_PIX_FMT_H264
:
1388 quant_param
= ctx
->params
.h264_intra_qp
;
1390 case V4L2_PIX_FMT_MPEG4
:
1391 quant_param
= ctx
->params
.mpeg4_intra_qp
;
1393 case V4L2_PIX_FMT_JPEG
:
1397 v4l2_warn(&ctx
->dev
->v4l2_dev
,
1398 "cannot set intra qp, fmt not supported\n");
1402 switch (dst_fourcc
) {
1403 case V4L2_PIX_FMT_H264
:
1404 quant_param
= ctx
->params
.h264_inter_qp
;
1406 case V4L2_PIX_FMT_MPEG4
:
1407 quant_param
= ctx
->params
.mpeg4_inter_qp
;
1410 v4l2_warn(&ctx
->dev
->v4l2_dev
,
1411 "cannot set inter qp, fmt not supported\n");
1417 if (ctx
->params
.rot_mode
)
1418 rot_mode
= CODA_ROT_MIR_ENABLE
| ctx
->params
.rot_mode
;
1419 coda_write(dev
, rot_mode
, CODA_CMD_ENC_PIC_ROT_MODE
);
1420 coda_write(dev
, quant_param
, CODA_CMD_ENC_PIC_QS
);
1422 if (dev
->devtype
->product
== CODA_960
) {
1423 coda_write(dev
, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX
);
1424 coda_write(dev
, q_data_src
->bytesperline
,
1425 CODA9_CMD_ENC_PIC_SRC_STRIDE
);
1426 coda_write(dev
, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC
);
1428 reg
= CODA9_CMD_ENC_PIC_SRC_ADDR_Y
;
1430 reg
= CODA_CMD_ENC_PIC_SRC_ADDR_Y
;
1432 coda_write_base(ctx
, q_data_src
, src_buf
, reg
);
1434 coda_write(dev
, force_ipicture
<< 1 & 0x2,
1435 CODA_CMD_ENC_PIC_OPTION
);
1437 coda_write(dev
, pic_stream_buffer_addr
, CODA_CMD_ENC_PIC_BB_START
);
1438 coda_write(dev
, pic_stream_buffer_size
/ 1024,
1439 CODA_CMD_ENC_PIC_BB_SIZE
);
1441 if (!ctx
->streamon_out
) {
1442 /* After streamoff on the output side, set stream end flag */
1443 ctx
->bit_stream_param
|= CODA_BIT_STREAM_END_FLAG
;
1444 coda_write(dev
, ctx
->bit_stream_param
,
1445 CODA_REG_BIT_BIT_STREAM_PARAM
);
1448 if (dev
->devtype
->product
!= CODA_DX6
)
1449 coda_write(dev
, ctx
->iram_info
.axi_sram_use
,
1450 CODA7_REG_BIT_AXI_SRAM_USE
);
1452 trace_coda_enc_pic_run(ctx
, src_buf
);
1454 coda_command_async(ctx
, CODA_COMMAND_PIC_RUN
);
1459 static void coda_finish_encode(struct coda_ctx
*ctx
)
1461 struct vb2_v4l2_buffer
*src_buf
, *dst_buf
;
1462 struct coda_dev
*dev
= ctx
->dev
;
1463 u32 wr_ptr
, start_ptr
;
1465 src_buf
= v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
1466 dst_buf
= v4l2_m2m_next_dst_buf(ctx
->fh
.m2m_ctx
);
1468 trace_coda_enc_pic_done(ctx
, dst_buf
);
1470 /* Get results from the coda */
1471 start_ptr
= coda_read(dev
, CODA_CMD_ENC_PIC_BB_START
);
1472 wr_ptr
= coda_read(dev
, CODA_REG_BIT_WR_PTR(ctx
->reg_idx
));
1474 /* Calculate bytesused field */
1475 if (dst_buf
->sequence
== 0 ||
1476 src_buf
->flags
& V4L2_BUF_FLAG_KEYFRAME
) {
1477 vb2_set_plane_payload(&dst_buf
->vb2_buf
, 0, wr_ptr
- start_ptr
+
1478 ctx
->vpu_header_size
[0] +
1479 ctx
->vpu_header_size
[1] +
1480 ctx
->vpu_header_size
[2]);
1482 vb2_set_plane_payload(&dst_buf
->vb2_buf
, 0, wr_ptr
- start_ptr
);
1485 coda_dbg(1, ctx
, "frame size = %u\n", wr_ptr
- start_ptr
);
1487 coda_read(dev
, CODA_RET_ENC_PIC_SLICE_NUM
);
1488 coda_read(dev
, CODA_RET_ENC_PIC_FLAG
);
1490 if (coda_read(dev
, CODA_RET_ENC_PIC_TYPE
) == 0) {
1491 dst_buf
->flags
|= V4L2_BUF_FLAG_KEYFRAME
;
1492 dst_buf
->flags
&= ~V4L2_BUF_FLAG_PFRAME
;
1494 dst_buf
->flags
|= V4L2_BUF_FLAG_PFRAME
;
1495 dst_buf
->flags
&= ~V4L2_BUF_FLAG_KEYFRAME
;
1498 dst_buf
->vb2_buf
.timestamp
= src_buf
->vb2_buf
.timestamp
;
1499 dst_buf
->field
= src_buf
->field
;
1500 dst_buf
->flags
&= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK
;
1502 src_buf
->flags
& V4L2_BUF_FLAG_TSTAMP_SRC_MASK
;
1503 dst_buf
->timecode
= src_buf
->timecode
;
1505 v4l2_m2m_buf_done(src_buf
, VB2_BUF_STATE_DONE
);
1507 dst_buf
= v4l2_m2m_dst_buf_remove(ctx
->fh
.m2m_ctx
);
1508 coda_m2m_buf_done(ctx
, dst_buf
, VB2_BUF_STATE_DONE
);
1511 if (ctx
->gopcounter
< 0)
1512 ctx
->gopcounter
= ctx
->params
.gop_size
- 1;
1514 coda_dbg(1, ctx
, "job finished: encoded %c frame (%d)\n",
1515 (dst_buf
->flags
& V4L2_BUF_FLAG_KEYFRAME
) ? 'I' : 'P',
1519 static void coda_seq_end_work(struct work_struct
*work
)
1521 struct coda_ctx
*ctx
= container_of(work
, struct coda_ctx
, seq_end_work
);
1522 struct coda_dev
*dev
= ctx
->dev
;
1524 mutex_lock(&ctx
->buffer_mutex
);
1525 mutex_lock(&dev
->coda_mutex
);
1527 if (ctx
->initialized
== 0)
1530 coda_dbg(1, ctx
, "%s: sent command 'SEQ_END' to coda\n", __func__
);
1531 if (coda_command_sync(ctx
, CODA_COMMAND_SEQ_END
)) {
1532 v4l2_err(&dev
->v4l2_dev
,
1533 "CODA_COMMAND_SEQ_END failed\n");
1537 * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1538 * from the output stream after the h.264 decoder has run. Resetting the
1539 * hardware after the decoder has finished seems to help.
1541 if (dev
->devtype
->product
== CODA_960
)
1544 kfifo_init(&ctx
->bitstream_fifo
,
1545 ctx
->bitstream
.vaddr
, ctx
->bitstream
.size
);
1547 coda_free_framebuffers(ctx
);
1549 ctx
->initialized
= 0;
1552 mutex_unlock(&dev
->coda_mutex
);
1553 mutex_unlock(&ctx
->buffer_mutex
);
1556 static void coda_bit_release(struct coda_ctx
*ctx
)
1558 mutex_lock(&ctx
->buffer_mutex
);
1559 coda_free_framebuffers(ctx
);
1560 coda_free_context_buffers(ctx
);
1561 coda_free_bitstream_buffer(ctx
);
1562 mutex_unlock(&ctx
->buffer_mutex
);
1565 const struct coda_context_ops coda_bit_encode_ops
= {
1566 .queue_init
= coda_encoder_queue_init
,
1567 .reqbufs
= coda_encoder_reqbufs
,
1568 .start_streaming
= coda_start_encoding
,
1569 .prepare_run
= coda_prepare_encode
,
1570 .finish_run
= coda_finish_encode
,
1571 .seq_end_work
= coda_seq_end_work
,
1572 .release
= coda_bit_release
,
1576 * Decoder context operations
1579 static int coda_alloc_bitstream_buffer(struct coda_ctx
*ctx
,
1580 struct coda_q_data
*q_data
)
1582 if (ctx
->bitstream
.vaddr
)
1585 ctx
->bitstream
.size
= roundup_pow_of_two(q_data
->sizeimage
* 2);
1586 ctx
->bitstream
.vaddr
= dma_alloc_wc(&ctx
->dev
->plat_dev
->dev
,
1587 ctx
->bitstream
.size
,
1588 &ctx
->bitstream
.paddr
, GFP_KERNEL
);
1589 if (!ctx
->bitstream
.vaddr
) {
1590 v4l2_err(&ctx
->dev
->v4l2_dev
,
1591 "failed to allocate bitstream ringbuffer");
1594 kfifo_init(&ctx
->bitstream_fifo
,
1595 ctx
->bitstream
.vaddr
, ctx
->bitstream
.size
);
1600 static void coda_free_bitstream_buffer(struct coda_ctx
*ctx
)
1602 if (ctx
->bitstream
.vaddr
== NULL
)
1605 dma_free_wc(&ctx
->dev
->plat_dev
->dev
, ctx
->bitstream
.size
,
1606 ctx
->bitstream
.vaddr
, ctx
->bitstream
.paddr
);
1607 ctx
->bitstream
.vaddr
= NULL
;
1608 kfifo_init(&ctx
->bitstream_fifo
, NULL
, 0);
1611 static int coda_decoder_reqbufs(struct coda_ctx
*ctx
,
1612 struct v4l2_requestbuffers
*rb
)
1614 struct coda_q_data
*q_data_src
;
1617 if (rb
->type
!= V4L2_BUF_TYPE_VIDEO_OUTPUT
)
1621 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
1622 ret
= coda_alloc_context_buffers(ctx
, q_data_src
);
1625 ret
= coda_alloc_bitstream_buffer(ctx
, q_data_src
);
1627 coda_free_context_buffers(ctx
);
1631 coda_free_bitstream_buffer(ctx
);
1632 coda_free_context_buffers(ctx
);
1638 static bool coda_reorder_enable(struct coda_ctx
*ctx
)
1640 struct coda_dev
*dev
= ctx
->dev
;
1643 if (dev
->devtype
->product
!= CODA_HX4
&&
1644 dev
->devtype
->product
!= CODA_7541
&&
1645 dev
->devtype
->product
!= CODA_960
)
1648 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_JPEG
)
1651 if (ctx
->codec
->src_fourcc
!= V4L2_PIX_FMT_H264
)
1654 profile
= coda_h264_profile(ctx
->params
.h264_profile_idc
);
1656 v4l2_warn(&dev
->v4l2_dev
, "Unknown H264 Profile: %u\n",
1657 ctx
->params
.h264_profile_idc
);
1659 /* Baseline profile does not support reordering */
1660 return profile
> V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE
;
1663 static int __coda_start_decoding(struct coda_ctx
*ctx
)
1665 struct coda_q_data
*q_data_src
, *q_data_dst
;
1666 u32 bitstream_buf
, bitstream_size
;
1667 struct coda_dev
*dev
= ctx
->dev
;
1669 u32 src_fourcc
, dst_fourcc
;
1673 coda_dbg(1, ctx
, "Video Data Order Adapter: %s\n",
1674 ctx
->use_vdoa
? "Enabled" : "Disabled");
1676 /* Start decoding */
1677 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
1678 q_data_dst
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_CAPTURE
);
1679 bitstream_buf
= ctx
->bitstream
.paddr
;
1680 bitstream_size
= ctx
->bitstream
.size
;
1681 src_fourcc
= q_data_src
->fourcc
;
1682 dst_fourcc
= q_data_dst
->fourcc
;
1684 coda_write(dev
, ctx
->parabuf
.paddr
, CODA_REG_BIT_PARA_BUF_ADDR
);
1686 /* Update coda bitstream read and write pointers from kfifo */
1687 coda_kfifo_sync_to_device_full(ctx
);
1689 ctx
->frame_mem_ctrl
&= ~(CODA_FRAME_CHROMA_INTERLEAVE
| (0x3 << 9) |
1690 CODA9_FRAME_TILED2LINEAR
);
1691 if (dst_fourcc
== V4L2_PIX_FMT_NV12
|| dst_fourcc
== V4L2_PIX_FMT_YUYV
)
1692 ctx
->frame_mem_ctrl
|= CODA_FRAME_CHROMA_INTERLEAVE
;
1693 if (ctx
->tiled_map_type
== GDI_TILED_FRAME_MB_RASTER_MAP
)
1694 ctx
->frame_mem_ctrl
|= (0x3 << 9) |
1695 ((ctx
->use_vdoa
) ? 0 : CODA9_FRAME_TILED2LINEAR
);
1696 coda_write(dev
, ctx
->frame_mem_ctrl
, CODA_REG_BIT_FRAME_MEM_CTRL
);
1698 ctx
->display_idx
= -1;
1699 ctx
->frm_dis_flg
= 0;
1700 coda_write(dev
, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx
->reg_idx
));
1702 coda_write(dev
, bitstream_buf
, CODA_CMD_DEC_SEQ_BB_START
);
1703 coda_write(dev
, bitstream_size
/ 1024, CODA_CMD_DEC_SEQ_BB_SIZE
);
1705 if (coda_reorder_enable(ctx
))
1706 val
|= CODA_REORDER_ENABLE
;
1707 if (ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_JPEG
)
1708 val
|= CODA_NO_INT_ENABLE
;
1709 coda_write(dev
, val
, CODA_CMD_DEC_SEQ_OPTION
);
1711 ctx
->params
.codec_mode
= ctx
->codec
->mode
;
1712 if (dev
->devtype
->product
== CODA_960
&&
1713 src_fourcc
== V4L2_PIX_FMT_MPEG4
)
1714 ctx
->params
.codec_mode_aux
= CODA_MP4_AUX_MPEG4
;
1716 ctx
->params
.codec_mode_aux
= 0;
1717 if (src_fourcc
== V4L2_PIX_FMT_MPEG4
) {
1718 coda_write(dev
, CODA_MP4_CLASS_MPEG4
,
1719 CODA_CMD_DEC_SEQ_MP4_ASP_CLASS
);
1721 if (src_fourcc
== V4L2_PIX_FMT_H264
) {
1722 if (dev
->devtype
->product
== CODA_HX4
||
1723 dev
->devtype
->product
== CODA_7541
) {
1724 coda_write(dev
, ctx
->psbuf
.paddr
,
1725 CODA_CMD_DEC_SEQ_PS_BB_START
);
1726 coda_write(dev
, (CODA7_PS_BUF_SIZE
/ 1024),
1727 CODA_CMD_DEC_SEQ_PS_BB_SIZE
);
1729 if (dev
->devtype
->product
== CODA_960
) {
1730 coda_write(dev
, 0, CODA_CMD_DEC_SEQ_X264_MV_EN
);
1731 coda_write(dev
, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE
);
1734 if (src_fourcc
== V4L2_PIX_FMT_JPEG
)
1735 coda_write(dev
, 0, CODA_CMD_DEC_SEQ_JPG_THUMB_EN
);
1736 if (dev
->devtype
->product
!= CODA_960
)
1737 coda_write(dev
, 0, CODA_CMD_DEC_SEQ_SRC_SIZE
);
1739 ctx
->bit_stream_param
= CODA_BIT_DEC_SEQ_INIT_ESCAPE
;
1740 ret
= coda_command_sync(ctx
, CODA_COMMAND_SEQ_INIT
);
1741 ctx
->bit_stream_param
= 0;
1743 v4l2_err(&dev
->v4l2_dev
, "CODA_COMMAND_SEQ_INIT timeout\n");
1746 ctx
->initialized
= 1;
1748 /* Update kfifo out pointer from coda bitstream read pointer */
1749 coda_kfifo_sync_from_device(ctx
);
1751 if (coda_read(dev
, CODA_RET_DEC_SEQ_SUCCESS
) == 0) {
1752 v4l2_err(&dev
->v4l2_dev
,
1753 "CODA_COMMAND_SEQ_INIT failed, error code = 0x%x\n",
1754 coda_read(dev
, CODA_RET_DEC_SEQ_ERR_REASON
));
1758 val
= coda_read(dev
, CODA_RET_DEC_SEQ_SRC_SIZE
);
1759 if (dev
->devtype
->product
== CODA_DX6
) {
1760 width
= (val
>> CODADX6_PICWIDTH_OFFSET
) & CODADX6_PICWIDTH_MASK
;
1761 height
= val
& CODADX6_PICHEIGHT_MASK
;
1763 width
= (val
>> CODA7_PICWIDTH_OFFSET
) & CODA7_PICWIDTH_MASK
;
1764 height
= val
& CODA7_PICHEIGHT_MASK
;
1767 if (width
> q_data_dst
->bytesperline
|| height
> q_data_dst
->height
) {
1768 v4l2_err(&dev
->v4l2_dev
, "stream is %dx%d, not %dx%d\n",
1769 width
, height
, q_data_dst
->bytesperline
,
1770 q_data_dst
->height
);
1774 width
= round_up(width
, 16);
1775 height
= round_up(height
, 16);
1777 coda_dbg(1, ctx
, "start decoding: %dx%d\n", width
, height
);
1779 ctx
->num_internal_frames
= coda_read(dev
, CODA_RET_DEC_SEQ_FRAME_NEED
);
1781 * If the VDOA is used, the decoder needs one additional frame,
1782 * because the frames are freed when the next frame is decoded.
1783 * Otherwise there are visible errors in the decoded frames (green
1784 * regions in displayed frames) and a broken order of frames (earlier
1785 * frames are sporadically displayed after later frames).
1788 ctx
->num_internal_frames
+= 1;
1789 if (ctx
->num_internal_frames
> CODA_MAX_FRAMEBUFFERS
) {
1790 v4l2_err(&dev
->v4l2_dev
,
1791 "not enough framebuffers to decode (%d < %d)\n",
1792 CODA_MAX_FRAMEBUFFERS
, ctx
->num_internal_frames
);
1796 if (src_fourcc
== V4L2_PIX_FMT_H264
) {
1800 left_right
= coda_read(dev
, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT
);
1801 top_bottom
= coda_read(dev
, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM
);
1803 q_data_dst
->rect
.left
= (left_right
>> 10) & 0x3ff;
1804 q_data_dst
->rect
.top
= (top_bottom
>> 10) & 0x3ff;
1805 q_data_dst
->rect
.width
= width
- q_data_dst
->rect
.left
-
1806 (left_right
& 0x3ff);
1807 q_data_dst
->rect
.height
= height
- q_data_dst
->rect
.top
-
1808 (top_bottom
& 0x3ff);
1811 ret
= coda_alloc_framebuffers(ctx
, q_data_dst
, src_fourcc
);
1813 v4l2_err(&dev
->v4l2_dev
, "failed to allocate framebuffers\n");
1817 /* Tell the decoder how many frame buffers we allocated. */
1818 coda_write(dev
, ctx
->num_internal_frames
, CODA_CMD_SET_FRAME_BUF_NUM
);
1819 coda_write(dev
, width
, CODA_CMD_SET_FRAME_BUF_STRIDE
);
1821 if (dev
->devtype
->product
!= CODA_DX6
) {
1822 /* Set secondary AXI IRAM */
1823 coda_setup_iram(ctx
);
1825 coda_write(dev
, ctx
->iram_info
.buf_bit_use
,
1826 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR
);
1827 coda_write(dev
, ctx
->iram_info
.buf_ip_ac_dc_use
,
1828 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR
);
1829 coda_write(dev
, ctx
->iram_info
.buf_dbk_y_use
,
1830 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR
);
1831 coda_write(dev
, ctx
->iram_info
.buf_dbk_c_use
,
1832 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR
);
1833 coda_write(dev
, ctx
->iram_info
.buf_ovl_use
,
1834 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR
);
1835 if (dev
->devtype
->product
== CODA_960
) {
1836 coda_write(dev
, ctx
->iram_info
.buf_btp_use
,
1837 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR
);
1839 coda_write(dev
, -1, CODA9_CMD_SET_FRAME_DELAY
);
1840 coda9_set_frame_cache(ctx
, dst_fourcc
);
1844 if (src_fourcc
== V4L2_PIX_FMT_H264
) {
1845 coda_write(dev
, ctx
->slicebuf
.paddr
,
1846 CODA_CMD_SET_FRAME_SLICE_BB_START
);
1847 coda_write(dev
, ctx
->slicebuf
.size
/ 1024,
1848 CODA_CMD_SET_FRAME_SLICE_BB_SIZE
);
1851 if (dev
->devtype
->product
== CODA_HX4
||
1852 dev
->devtype
->product
== CODA_7541
) {
1853 int max_mb_x
= 1920 / 16;
1854 int max_mb_y
= 1088 / 16;
1855 int max_mb_num
= max_mb_x
* max_mb_y
;
1857 coda_write(dev
, max_mb_num
<< 16 | max_mb_x
<< 8 | max_mb_y
,
1858 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE
);
1859 } else if (dev
->devtype
->product
== CODA_960
) {
1860 int max_mb_x
= 1920 / 16;
1861 int max_mb_y
= 1088 / 16;
1862 int max_mb_num
= max_mb_x
* max_mb_y
;
1864 coda_write(dev
, max_mb_num
<< 16 | max_mb_x
<< 8 | max_mb_y
,
1865 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE
);
1868 if (coda_command_sync(ctx
, CODA_COMMAND_SET_FRAME_BUF
)) {
1869 v4l2_err(&ctx
->dev
->v4l2_dev
,
1870 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1877 static int coda_start_decoding(struct coda_ctx
*ctx
)
1879 struct coda_dev
*dev
= ctx
->dev
;
1882 mutex_lock(&dev
->coda_mutex
);
1883 ret
= __coda_start_decoding(ctx
);
1884 mutex_unlock(&dev
->coda_mutex
);
1889 static int coda_prepare_decode(struct coda_ctx
*ctx
)
1891 struct vb2_v4l2_buffer
*dst_buf
;
1892 struct coda_dev
*dev
= ctx
->dev
;
1893 struct coda_q_data
*q_data_dst
;
1894 struct coda_buffer_meta
*meta
;
1896 u32 reg_addr
, reg_stride
;
1898 dst_buf
= v4l2_m2m_next_dst_buf(ctx
->fh
.m2m_ctx
);
1899 q_data_dst
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_CAPTURE
);
1901 /* Try to copy source buffer contents into the bitstream ringbuffer */
1902 mutex_lock(&ctx
->bitstream_mutex
);
1903 coda_fill_bitstream(ctx
, NULL
);
1904 mutex_unlock(&ctx
->bitstream_mutex
);
1906 if (coda_get_bitstream_payload(ctx
) < 512 &&
1907 (!(ctx
->bit_stream_param
& CODA_BIT_STREAM_END_FLAG
))) {
1908 coda_dbg(1, ctx
, "bitstream payload: %d, skipping\n",
1909 coda_get_bitstream_payload(ctx
));
1910 v4l2_m2m_job_finish(ctx
->dev
->m2m_dev
, ctx
->fh
.m2m_ctx
);
1914 /* Run coda_start_decoding (again) if not yet initialized */
1915 if (!ctx
->initialized
) {
1916 int ret
= __coda_start_decoding(ctx
);
1919 v4l2_err(&dev
->v4l2_dev
, "failed to start decoding\n");
1920 v4l2_m2m_job_finish(ctx
->dev
->m2m_dev
, ctx
->fh
.m2m_ctx
);
1923 ctx
->initialized
= 1;
1927 if (dev
->devtype
->product
== CODA_960
)
1928 coda_set_gdi_regs(ctx
);
1930 if (ctx
->use_vdoa
&&
1931 ctx
->display_idx
>= 0 &&
1932 ctx
->display_idx
< ctx
->num_internal_frames
) {
1933 vdoa_device_run(ctx
->vdoa
,
1934 vb2_dma_contig_plane_dma_addr(&dst_buf
->vb2_buf
, 0),
1935 ctx
->internal_frames
[ctx
->display_idx
].paddr
);
1937 if (dev
->devtype
->product
== CODA_960
) {
1939 * The CODA960 seems to have an internal list of
1940 * buffers with 64 entries that includes the
1941 * registered frame buffers as well as the rotator
1944 * ROT_INDEX needs to be < 0x40, but >
1945 * ctx->num_internal_frames.
1948 CODA_MAX_FRAMEBUFFERS
+ dst_buf
->vb2_buf
.index
,
1949 CODA9_CMD_DEC_PIC_ROT_INDEX
);
1951 reg_addr
= CODA9_CMD_DEC_PIC_ROT_ADDR_Y
;
1952 reg_stride
= CODA9_CMD_DEC_PIC_ROT_STRIDE
;
1954 reg_addr
= CODA_CMD_DEC_PIC_ROT_ADDR_Y
;
1955 reg_stride
= CODA_CMD_DEC_PIC_ROT_STRIDE
;
1957 coda_write_base(ctx
, q_data_dst
, dst_buf
, reg_addr
);
1958 coda_write(dev
, q_data_dst
->bytesperline
, reg_stride
);
1960 rot_mode
= CODA_ROT_MIR_ENABLE
| ctx
->params
.rot_mode
;
1963 coda_write(dev
, rot_mode
, CODA_CMD_DEC_PIC_ROT_MODE
);
1965 switch (dev
->devtype
->product
) {
1970 coda_write(dev
, CODA_PRE_SCAN_EN
, CODA_CMD_DEC_PIC_OPTION
);
1973 /* 'hardcode to use interrupt disable mode'? */
1974 coda_write(dev
, (1 << 10), CODA_CMD_DEC_PIC_OPTION
);
1978 coda_write(dev
, 0, CODA_CMD_DEC_PIC_SKIP_NUM
);
1980 coda_write(dev
, 0, CODA_CMD_DEC_PIC_BB_START
);
1981 coda_write(dev
, 0, CODA_CMD_DEC_PIC_START_BYTE
);
1983 if (dev
->devtype
->product
!= CODA_DX6
)
1984 coda_write(dev
, ctx
->iram_info
.axi_sram_use
,
1985 CODA7_REG_BIT_AXI_SRAM_USE
);
1987 spin_lock(&ctx
->buffer_meta_lock
);
1988 meta
= list_first_entry_or_null(&ctx
->buffer_meta_list
,
1989 struct coda_buffer_meta
, list
);
1991 if (meta
&& ctx
->codec
->src_fourcc
== V4L2_PIX_FMT_JPEG
) {
1993 /* If this is the last buffer in the bitstream, add padding */
1994 if (meta
->end
== ctx
->bitstream_fifo
.kfifo
.in
) {
1995 static unsigned char buf
[512];
1998 /* Pad to multiple of 256 and then add 256 more */
1999 pad
= ((0 - meta
->end
) & 0xff) + 256;
2001 memset(buf
, 0xff, sizeof(buf
));
2003 kfifo_in(&ctx
->bitstream_fifo
, buf
, pad
);
2006 spin_unlock(&ctx
->buffer_meta_lock
);
2008 coda_kfifo_sync_to_device_full(ctx
);
2010 /* Clear decode success flag */
2011 coda_write(dev
, 0, CODA_RET_DEC_PIC_SUCCESS
);
2013 /* Clear error return value */
2014 coda_write(dev
, 0, CODA_RET_DEC_PIC_ERR_MB
);
2016 trace_coda_dec_pic_run(ctx
, meta
);
2018 coda_command_async(ctx
, CODA_COMMAND_PIC_RUN
);
2023 static void coda_finish_decode(struct coda_ctx
*ctx
)
2025 struct coda_dev
*dev
= ctx
->dev
;
2026 struct coda_q_data
*q_data_src
;
2027 struct coda_q_data
*q_data_dst
;
2028 struct vb2_v4l2_buffer
*dst_buf
;
2029 struct coda_buffer_meta
*meta
;
2039 /* Update kfifo out pointer from coda bitstream read pointer */
2040 coda_kfifo_sync_from_device(ctx
);
2043 * in stream-end mode, the read pointer can overshoot the write pointer
2044 * by up to 512 bytes
2046 if (ctx
->bit_stream_param
& CODA_BIT_STREAM_END_FLAG
) {
2047 if (coda_get_bitstream_payload(ctx
) >= ctx
->bitstream
.size
- 512)
2048 kfifo_init(&ctx
->bitstream_fifo
,
2049 ctx
->bitstream
.vaddr
, ctx
->bitstream
.size
);
2052 q_data_src
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT
);
2053 src_fourcc
= q_data_src
->fourcc
;
2055 val
= coda_read(dev
, CODA_RET_DEC_PIC_SUCCESS
);
2057 pr_err("DEC_PIC_SUCCESS = %d\n", val
);
2059 success
= val
& 0x1;
2061 v4l2_err(&dev
->v4l2_dev
, "decode failed\n");
2063 if (src_fourcc
== V4L2_PIX_FMT_H264
) {
2065 v4l2_err(&dev
->v4l2_dev
,
2066 "insufficient PS buffer space (%d bytes)\n",
2069 v4l2_err(&dev
->v4l2_dev
,
2070 "insufficient slice buffer space (%d bytes)\n",
2071 ctx
->slicebuf
.size
);
2074 val
= coda_read(dev
, CODA_RET_DEC_PIC_SIZE
);
2075 width
= (val
>> 16) & 0xffff;
2076 height
= val
& 0xffff;
2078 q_data_dst
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_CAPTURE
);
2080 /* frame crop information */
2081 if (src_fourcc
== V4L2_PIX_FMT_H264
) {
2085 left_right
= coda_read(dev
, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT
);
2086 top_bottom
= coda_read(dev
, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM
);
2088 if (left_right
== 0xffffffff && top_bottom
== 0xffffffff) {
2089 /* Keep current crop information */
2091 struct v4l2_rect
*rect
= &q_data_dst
->rect
;
2093 rect
->left
= left_right
>> 16 & 0xffff;
2094 rect
->top
= top_bottom
>> 16 & 0xffff;
2095 rect
->width
= width
- rect
->left
-
2096 (left_right
& 0xffff);
2097 rect
->height
= height
- rect
->top
-
2098 (top_bottom
& 0xffff);
2104 err_mb
= coda_read(dev
, CODA_RET_DEC_PIC_ERR_MB
);
2106 v4l2_err(&dev
->v4l2_dev
,
2107 "errors in %d macroblocks\n", err_mb
);
2109 if (dev
->devtype
->product
== CODA_HX4
||
2110 dev
->devtype
->product
== CODA_7541
) {
2111 val
= coda_read(dev
, CODA_RET_DEC_PIC_OPTION
);
2113 /* not enough bitstream data */
2114 coda_dbg(1, ctx
, "prescan failed: %d\n", val
);
2120 /* Wait until the VDOA finished writing the previous display frame */
2121 if (ctx
->use_vdoa
&&
2122 ctx
->display_idx
>= 0 &&
2123 ctx
->display_idx
< ctx
->num_internal_frames
) {
2124 err_vdoa
= vdoa_wait_for_completion(ctx
->vdoa
);
2127 ctx
->frm_dis_flg
= coda_read(dev
,
2128 CODA_REG_BIT_FRM_DIS_FLG(ctx
->reg_idx
));
2130 /* The previous display frame was copied out and can be overwritten */
2131 if (ctx
->display_idx
>= 0 &&
2132 ctx
->display_idx
< ctx
->num_internal_frames
) {
2133 ctx
->frm_dis_flg
&= ~(1 << ctx
->display_idx
);
2134 coda_write(dev
, ctx
->frm_dis_flg
,
2135 CODA_REG_BIT_FRM_DIS_FLG(ctx
->reg_idx
));
2139 * The index of the last decoded frame, not necessarily in
2140 * display order, and the index of the next display frame.
2141 * The latter could have been decoded in a previous run.
2143 decoded_idx
= coda_read(dev
, CODA_RET_DEC_PIC_CUR_IDX
);
2144 display_idx
= coda_read(dev
, CODA_RET_DEC_PIC_FRAME_IDX
);
2146 if (decoded_idx
== -1) {
2147 /* no frame was decoded, but we might have a display frame */
2148 if (display_idx
>= 0 && display_idx
< ctx
->num_internal_frames
)
2149 ctx
->sequence_offset
++;
2150 else if (ctx
->display_idx
< 0)
2152 } else if (decoded_idx
== -2) {
2153 /* no frame was decoded, we still return remaining buffers */
2154 } else if (decoded_idx
< 0 || decoded_idx
>= ctx
->num_internal_frames
) {
2155 v4l2_err(&dev
->v4l2_dev
,
2156 "decoded frame index out of range: %d\n", decoded_idx
);
2158 val
= coda_read(dev
, CODA_RET_DEC_PIC_FRAME_NUM
) - 1;
2159 val
-= ctx
->sequence_offset
;
2160 spin_lock(&ctx
->buffer_meta_lock
);
2161 if (!list_empty(&ctx
->buffer_meta_list
)) {
2162 meta
= list_first_entry(&ctx
->buffer_meta_list
,
2163 struct coda_buffer_meta
, list
);
2164 list_del(&meta
->list
);
2166 spin_unlock(&ctx
->buffer_meta_lock
);
2168 * Clamp counters to 16 bits for comparison, as the HW
2169 * counter rolls over at this point for h.264. This
2170 * may be different for other formats, but using 16 bits
2171 * should be enough to detect most errors and saves us
2172 * from doing different things based on the format.
2174 if ((val
& 0xffff) != (meta
->sequence
& 0xffff)) {
2175 v4l2_err(&dev
->v4l2_dev
,
2176 "sequence number mismatch (%d(%d) != %d)\n",
2177 val
, ctx
->sequence_offset
,
2180 ctx
->frame_metas
[decoded_idx
] = *meta
;
2183 spin_unlock(&ctx
->buffer_meta_lock
);
2184 v4l2_err(&dev
->v4l2_dev
, "empty timestamp list!\n");
2185 memset(&ctx
->frame_metas
[decoded_idx
], 0,
2186 sizeof(struct coda_buffer_meta
));
2187 ctx
->frame_metas
[decoded_idx
].sequence
= val
;
2188 ctx
->sequence_offset
++;
2191 trace_coda_dec_pic_done(ctx
, &ctx
->frame_metas
[decoded_idx
]);
2193 val
= coda_read(dev
, CODA_RET_DEC_PIC_TYPE
) & 0x7;
2195 ctx
->frame_types
[decoded_idx
] = V4L2_BUF_FLAG_KEYFRAME
;
2197 ctx
->frame_types
[decoded_idx
] = V4L2_BUF_FLAG_PFRAME
;
2199 ctx
->frame_types
[decoded_idx
] = V4L2_BUF_FLAG_BFRAME
;
2201 ctx
->frame_errors
[decoded_idx
] = err_mb
;
2204 if (display_idx
== -1) {
2206 * no more frames to be decoded, but there could still
2207 * be rotator output to dequeue
2210 } else if (display_idx
== -3) {
2211 /* possibly prescan failure */
2212 } else if (display_idx
< 0 || display_idx
>= ctx
->num_internal_frames
) {
2213 v4l2_err(&dev
->v4l2_dev
,
2214 "presentation frame index out of range: %d\n",
2218 /* If a frame was copied out, return it */
2219 if (ctx
->display_idx
>= 0 &&
2220 ctx
->display_idx
< ctx
->num_internal_frames
) {
2221 dst_buf
= v4l2_m2m_dst_buf_remove(ctx
->fh
.m2m_ctx
);
2222 dst_buf
->sequence
= ctx
->osequence
++;
2224 dst_buf
->field
= V4L2_FIELD_NONE
;
2225 dst_buf
->flags
&= ~(V4L2_BUF_FLAG_KEYFRAME
|
2226 V4L2_BUF_FLAG_PFRAME
|
2227 V4L2_BUF_FLAG_BFRAME
);
2228 dst_buf
->flags
|= ctx
->frame_types
[ctx
->display_idx
];
2229 meta
= &ctx
->frame_metas
[ctx
->display_idx
];
2230 dst_buf
->timecode
= meta
->timecode
;
2231 dst_buf
->vb2_buf
.timestamp
= meta
->timestamp
;
2233 trace_coda_dec_rot_done(ctx
, dst_buf
, meta
);
2235 vb2_set_plane_payload(&dst_buf
->vb2_buf
, 0,
2236 q_data_dst
->sizeimage
);
2238 if (ctx
->frame_errors
[ctx
->display_idx
] || err_vdoa
)
2239 coda_m2m_buf_done(ctx
, dst_buf
, VB2_BUF_STATE_ERROR
);
2241 coda_m2m_buf_done(ctx
, dst_buf
, VB2_BUF_STATE_DONE
);
2243 coda_dbg(1, ctx
, "job finished: decoded %c frame (%u/%u)\n",
2244 (dst_buf
->flags
& V4L2_BUF_FLAG_KEYFRAME
) ? 'I' :
2245 ((dst_buf
->flags
& V4L2_BUF_FLAG_PFRAME
) ? 'P' : 'B'),
2246 dst_buf
->sequence
, ctx
->qsequence
);
2248 coda_dbg(1, ctx
, "job finished: no frame decoded (%u/%u)\n",
2249 ctx
->osequence
, ctx
->qsequence
);
2252 /* The rotator will copy the current display frame next time */
2253 ctx
->display_idx
= display_idx
;
2256 * The current decode run might have brought the bitstream fill level
2257 * below the size where we can start the next decode run. As userspace
2258 * might have filled the output queue completely and might thus be
2259 * blocked, we can't rely on the next qbuf to trigger the bitstream
2260 * refill. Check if we have data to refill the bitstream now.
2262 mutex_lock(&ctx
->bitstream_mutex
);
2263 coda_fill_bitstream(ctx
, NULL
);
2264 mutex_unlock(&ctx
->bitstream_mutex
);
2267 static void coda_decode_timeout(struct coda_ctx
*ctx
)
2269 struct vb2_v4l2_buffer
*dst_buf
;
2272 * For now this only handles the case where we would deadlock with
2273 * userspace, i.e. userspace issued DEC_CMD_STOP and waits for EOS,
2274 * but after a failed decode run we would hold the context and wait for
2275 * userspace to queue more buffers.
2277 if (!(ctx
->bit_stream_param
& CODA_BIT_STREAM_END_FLAG
))
2280 dst_buf
= v4l2_m2m_dst_buf_remove(ctx
->fh
.m2m_ctx
);
2281 dst_buf
->sequence
= ctx
->qsequence
- 1;
2283 coda_m2m_buf_done(ctx
, dst_buf
, VB2_BUF_STATE_ERROR
);
2286 const struct coda_context_ops coda_bit_decode_ops
= {
2287 .queue_init
= coda_decoder_queue_init
,
2288 .reqbufs
= coda_decoder_reqbufs
,
2289 .start_streaming
= coda_start_decoding
,
2290 .prepare_run
= coda_prepare_decode
,
2291 .finish_run
= coda_finish_decode
,
2292 .run_timeout
= coda_decode_timeout
,
2293 .seq_end_work
= coda_seq_end_work
,
2294 .release
= coda_bit_release
,
2297 irqreturn_t
coda_irq_handler(int irq
, void *data
)
2299 struct coda_dev
*dev
= data
;
2300 struct coda_ctx
*ctx
;
2302 /* read status register to attend the IRQ */
2303 coda_read(dev
, CODA_REG_BIT_INT_STATUS
);
2304 coda_write(dev
, CODA_REG_BIT_INT_CLEAR_SET
,
2305 CODA_REG_BIT_INT_CLEAR
);
2307 ctx
= v4l2_m2m_get_curr_priv(dev
->m2m_dev
);
2309 v4l2_err(&dev
->v4l2_dev
,
2310 "Instance released before the end of transaction\n");
2311 mutex_unlock(&dev
->coda_mutex
);
2315 trace_coda_bit_done(ctx
);
2317 if (ctx
->aborting
) {
2318 coda_dbg(1, ctx
, "task has been aborted\n");
2321 if (coda_isbusy(ctx
->dev
)) {
2322 coda_dbg(1, ctx
, "coda is still busy!!!!\n");
2326 complete(&ctx
->completion
);