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[mirror_ubuntu-hirsute-kernel.git] / drivers / media / platform / davinci / dm644x_ccdc.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2006-2009 Texas Instruments Inc
4 *
5 * CCDC hardware module for DM6446
6 * ------------------------------
7 *
8 * This module is for configuring CCD controller of DM6446 VPFE to capture
9 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
10 * such as Defect Pixel Correction, Color Space Conversion etc to
11 * pre-process the Raw Bayer RGB data, before writing it to SDRAM.
12 * This file is named DM644x so that other variants such DM6443
13 * may be supported using the same module.
14 *
15 * TODO: Test Raw bayer parameter settings and bayer capture
16 * Split module parameter structure to module specific ioctl structs
17 * investigate if enum used for user space type definition
18 * to be replaced by #defines or integer
19 */
20 #include <linux/platform_device.h>
21 #include <linux/uaccess.h>
22 #include <linux/videodev2.h>
23 #include <linux/gfp.h>
24 #include <linux/err.h>
25 #include <linux/module.h>
26
27 #include <media/davinci/dm644x_ccdc.h>
28 #include <media/davinci/vpss.h>
29
30 #include "dm644x_ccdc_regs.h"
31 #include "ccdc_hw_device.h"
32
33 MODULE_LICENSE("GPL");
34 MODULE_DESCRIPTION("CCDC Driver for DM6446");
35 MODULE_AUTHOR("Texas Instruments");
36
37 static struct ccdc_oper_config {
38 struct device *dev;
39 /* CCDC interface type */
40 enum vpfe_hw_if_type if_type;
41 /* Raw Bayer configuration */
42 struct ccdc_params_raw bayer;
43 /* YCbCr configuration */
44 struct ccdc_params_ycbcr ycbcr;
45 /* ccdc base address */
46 void __iomem *base_addr;
47 } ccdc_cfg = {
48 /* Raw configurations */
49 .bayer = {
50 .pix_fmt = CCDC_PIXFMT_RAW,
51 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
52 .win = CCDC_WIN_VGA,
53 .fid_pol = VPFE_PINPOL_POSITIVE,
54 .vd_pol = VPFE_PINPOL_POSITIVE,
55 .hd_pol = VPFE_PINPOL_POSITIVE,
56 .config_params = {
57 .data_sz = CCDC_DATA_10BITS,
58 },
59 },
60 .ycbcr = {
61 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
62 .frm_fmt = CCDC_FRMFMT_INTERLACED,
63 .win = CCDC_WIN_PAL,
64 .fid_pol = VPFE_PINPOL_POSITIVE,
65 .vd_pol = VPFE_PINPOL_POSITIVE,
66 .hd_pol = VPFE_PINPOL_POSITIVE,
67 .bt656_enable = 1,
68 .pix_order = CCDC_PIXORDER_CBYCRY,
69 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
70 },
71 };
72
73 #define CCDC_MAX_RAW_YUV_FORMATS 2
74
75 /* Raw Bayer formats */
76 static u32 ccdc_raw_bayer_pix_formats[] =
77 {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
78
79 /* Raw YUV formats */
80 static u32 ccdc_raw_yuv_pix_formats[] =
81 {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
82
83 /* CCDC Save/Restore context */
84 static u32 ccdc_ctx[CCDC_REG_END / sizeof(u32)];
85
86 /* register access routines */
87 static inline u32 regr(u32 offset)
88 {
89 return __raw_readl(ccdc_cfg.base_addr + offset);
90 }
91
92 static inline void regw(u32 val, u32 offset)
93 {
94 __raw_writel(val, ccdc_cfg.base_addr + offset);
95 }
96
97 static void ccdc_enable(int flag)
98 {
99 regw(flag, CCDC_PCR);
100 }
101
102 static void ccdc_enable_vport(int flag)
103 {
104 if (flag)
105 /* enable video port */
106 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
107 else
108 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
109 }
110
111 /*
112 * ccdc_setwin()
113 * This function will configure the window size
114 * to be capture in CCDC reg
115 */
116 static void ccdc_setwin(struct v4l2_rect *image_win,
117 enum ccdc_frmfmt frm_fmt,
118 int ppc)
119 {
120 int horz_start, horz_nr_pixels;
121 int vert_start, vert_nr_lines;
122 int val = 0, mid_img = 0;
123
124 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
125 /*
126 * ppc - per pixel count. indicates how many pixels per cell
127 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
128 * raw capture this is 1
129 */
130 horz_start = image_win->left << (ppc - 1);
131 horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
132 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
133 CCDC_HORZ_INFO);
134
135 vert_start = image_win->top;
136
137 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
138 vert_nr_lines = (image_win->height >> 1) - 1;
139 vert_start >>= 1;
140 /* Since first line doesn't have any data */
141 vert_start += 1;
142 /* configure VDINT0 */
143 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
144 regw(val, CCDC_VDINT);
145
146 } else {
147 /* Since first line doesn't have any data */
148 vert_start += 1;
149 vert_nr_lines = image_win->height - 1;
150 /*
151 * configure VDINT0 and VDINT1. VDINT1 will be at half
152 * of image height
153 */
154 mid_img = vert_start + (image_win->height / 2);
155 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
156 (mid_img & CCDC_VDINT_VDINT1_MASK);
157 regw(val, CCDC_VDINT);
158
159 }
160 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
161 CCDC_VERT_START);
162 regw(vert_nr_lines, CCDC_VERT_LINES);
163 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
164 }
165
166 static void ccdc_readregs(void)
167 {
168 unsigned int val = 0;
169
170 val = regr(CCDC_ALAW);
171 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val);
172 val = regr(CCDC_CLAMP);
173 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val);
174 val = regr(CCDC_DCSUB);
175 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val);
176 val = regr(CCDC_BLKCMP);
177 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val);
178 val = regr(CCDC_FPC_ADDR);
179 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val);
180 val = regr(CCDC_FPC);
181 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val);
182 val = regr(CCDC_FMTCFG);
183 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val);
184 val = regr(CCDC_COLPTN);
185 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val);
186 val = regr(CCDC_FMT_HORZ);
187 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val);
188 val = regr(CCDC_FMT_VERT);
189 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val);
190 val = regr(CCDC_HSIZE_OFF);
191 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
192 val = regr(CCDC_SDOFST);
193 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val);
194 val = regr(CCDC_VP_OUT);
195 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val);
196 val = regr(CCDC_SYN_MODE);
197 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val);
198 val = regr(CCDC_HORZ_INFO);
199 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val);
200 val = regr(CCDC_VERT_START);
201 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val);
202 val = regr(CCDC_VERT_LINES);
203 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val);
204 }
205
206 static int ccdc_close(struct device *dev)
207 {
208 return 0;
209 }
210
211 /*
212 * ccdc_restore_defaults()
213 * This function will write defaults to all CCDC registers
214 */
215 static void ccdc_restore_defaults(void)
216 {
217 int i;
218
219 /* disable CCDC */
220 ccdc_enable(0);
221 /* set all registers to default value */
222 for (i = 4; i <= 0x94; i += 4)
223 regw(0, i);
224 regw(CCDC_NO_CULLING, CCDC_CULLING);
225 regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
226 }
227
228 static int ccdc_open(struct device *device)
229 {
230 ccdc_restore_defaults();
231 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
232 ccdc_enable_vport(1);
233 return 0;
234 }
235
236 static void ccdc_sbl_reset(void)
237 {
238 vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
239 }
240
241 /*
242 * ccdc_config_ycbcr()
243 * This function will configure CCDC for YCbCr video capture
244 */
245 static void ccdc_config_ycbcr(void)
246 {
247 struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
248 u32 syn_mode;
249
250 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
251 /*
252 * first restore the CCDC registers to default values
253 * This is important since we assume default values to be set in
254 * a lot of registers that we didn't touch
255 */
256 ccdc_restore_defaults();
257
258 /*
259 * configure pixel format, frame format, configure video frame
260 * format, enable output to SDRAM, enable internal timing generator
261 * and 8bit pack mode
262 */
263 syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
264 CCDC_SYN_MODE_INPMOD_SHIFT) |
265 ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
266 CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
267 CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
268
269 /* setup BT.656 sync mode */
270 if (params->bt656_enable) {
271 regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
272
273 /*
274 * configure the FID, VD, HD pin polarity,
275 * fld,hd pol positive, vd negative, 8-bit data
276 */
277 syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
278 if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
279 syn_mode |= CCDC_SYN_MODE_10BITS;
280 else
281 syn_mode |= CCDC_SYN_MODE_8BITS;
282 } else {
283 /* y/c external sync mode */
284 syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
285 CCDC_FID_POL_SHIFT) |
286 ((params->hd_pol & CCDC_HD_POL_MASK) <<
287 CCDC_HD_POL_SHIFT) |
288 ((params->vd_pol & CCDC_VD_POL_MASK) <<
289 CCDC_VD_POL_SHIFT));
290 }
291 regw(syn_mode, CCDC_SYN_MODE);
292
293 /* configure video window */
294 ccdc_setwin(&params->win, params->frm_fmt, 2);
295
296 /*
297 * configure the order of y cb cr in SDRAM, and disable latch
298 * internal register on vsync
299 */
300 if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
301 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
302 CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
303 CCDC_CCDCFG);
304 else
305 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
306 CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
307
308 /*
309 * configure the horizontal line offset. This should be a
310 * on 32 byte boundary. So clear LSB 5 bits
311 */
312 regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
313
314 /* configure the memory line offset */
315 if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
316 /* two fields are interleaved in memory */
317 regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
318
319 ccdc_sbl_reset();
320 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
321 }
322
323 static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
324 {
325 u32 val;
326
327 if (!bclamp->enable) {
328 /* configure DCSub */
329 val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
330 regw(val, CCDC_DCSUB);
331 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val);
332 regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
333 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to CLAMP...\n");
334 return;
335 }
336 /*
337 * Configure gain, Start pixel, No of line to be avg,
338 * No of pixel/line to be avg, & Enable the Black clamping
339 */
340 val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
341 ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
342 CCDC_BLK_ST_PXL_SHIFT) |
343 ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
344 CCDC_BLK_SAMPLE_LINE_SHIFT) |
345 ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
346 CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
347 regw(val, CCDC_CLAMP);
348 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val);
349 /* If Black clamping is enable then make dcsub 0 */
350 regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
351 dev_dbg(ccdc_cfg.dev, "\nWriting 0x00000000 to DCSUB...\n");
352 }
353
354 static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
355 {
356 u32 val;
357
358 val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
359 ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
360 CCDC_BLK_COMP_GB_COMP_SHIFT) |
361 ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
362 CCDC_BLK_COMP_GR_COMP_SHIFT) |
363 ((bcomp->r & CCDC_BLK_COMP_MASK) <<
364 CCDC_BLK_COMP_R_COMP_SHIFT));
365 regw(val, CCDC_BLKCMP);
366 }
367
368 /*
369 * ccdc_config_raw()
370 * This function will configure CCDC for Raw capture mode
371 */
372 static void ccdc_config_raw(void)
373 {
374 struct ccdc_params_raw *params = &ccdc_cfg.bayer;
375 struct ccdc_config_params_raw *config_params =
376 &ccdc_cfg.bayer.config_params;
377 unsigned int syn_mode = 0;
378 unsigned int val;
379
380 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
381
382 /* Reset CCDC */
383 ccdc_restore_defaults();
384
385 /* Disable latching function registers on VSYNC */
386 regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
387
388 /*
389 * Configure the vertical sync polarity(SYN_MODE.VDPOL),
390 * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
391 * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
392 * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
393 * SDRAM, enable internal timing generator
394 */
395 syn_mode =
396 (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
397 ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
398 ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
399 ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
400 ((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
401 CCDC_DATA_SZ_SHIFT) |
402 ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
403 CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
404
405 /* Enable and configure aLaw register if needed */
406 if (config_params->alaw.enable) {
407 val = ((config_params->alaw.gamma_wd &
408 CCDC_ALAW_GAMMA_WD_MASK) | CCDC_ALAW_ENABLE);
409 regw(val, CCDC_ALAW);
410 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val);
411 }
412
413 /* Configure video window */
414 ccdc_setwin(&params->win, params->frm_fmt, CCDC_PPC_RAW);
415
416 /* Configure Black Clamp */
417 ccdc_config_black_clamp(&config_params->blk_clamp);
418
419 /* Configure Black level compensation */
420 ccdc_config_black_compense(&config_params->blk_comp);
421
422 /* If data size is 8 bit then pack the data */
423 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
424 config_params->alaw.enable)
425 syn_mode |= CCDC_DATA_PACK_ENABLE;
426
427 /* disable video port */
428 val = CCDC_DISABLE_VIDEO_PORT;
429
430 if (config_params->data_sz == CCDC_DATA_8BITS)
431 val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
432 << CCDC_FMTCFG_VPIN_SHIFT;
433 else
434 val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
435 << CCDC_FMTCFG_VPIN_SHIFT;
436 /* Write value in FMTCFG */
437 regw(val, CCDC_FMTCFG);
438
439 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val);
440 /* Configure the color pattern according to mt9t001 sensor */
441 regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
442
443 dev_dbg(ccdc_cfg.dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
444 /*
445 * Configure Data formatter(Video port) pixel selection
446 * (FMT_HORZ, FMT_VERT)
447 */
448 val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
449 CCDC_FMT_HORZ_FMTSPH_SHIFT) |
450 (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
451 regw(val, CCDC_FMT_HORZ);
452
453 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
454 val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
455 << CCDC_FMT_VERT_FMTSLV_SHIFT;
456 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
457 val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
458 else
459 val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
460
461 dev_dbg(ccdc_cfg.dev, "\nparams->win.height 0x%x ...\n",
462 params->win.height);
463 regw(val, CCDC_FMT_VERT);
464
465 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val);
466
467 dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)...");
468
469 /*
470 * Configure Horizontal offset register. If pack 8 is enabled then
471 * 1 pixel will take 1 byte
472 */
473 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
474 config_params->alaw.enable)
475 regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
476 CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
477 else
478 /* else one pixel will take 2 byte */
479 regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
480 CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
481 CCDC_HSIZE_OFF);
482
483 /* Set value for SDOFST */
484 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
485 if (params->image_invert_enable) {
486 /* For intelace inverse mode */
487 regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
488 dev_dbg(ccdc_cfg.dev, "\nWriting 0x4B6D to SDOFST..\n");
489 }
490
491 else {
492 /* For intelace non inverse mode */
493 regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
494 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0249 to SDOFST..\n");
495 }
496 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
497 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
498 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to SDOFST...\n");
499 }
500
501 /*
502 * Configure video port pixel selection (VPOUT)
503 * Here -1 is to make the height value less than FMT_VERT.FMTLNV
504 */
505 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
506 val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
507 << CCDC_VP_OUT_VERT_NUM_SHIFT;
508 else
509 val =
510 ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
511 1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
512 CCDC_VP_OUT_VERT_NUM_SHIFT;
513
514 val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
515 << CCDC_VP_OUT_HORZ_NUM_SHIFT;
516 val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
517 regw(val, CCDC_VP_OUT);
518
519 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val);
520 regw(syn_mode, CCDC_SYN_MODE);
521 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
522
523 ccdc_sbl_reset();
524 dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
525 ccdc_readregs();
526 }
527
528 static int ccdc_configure(void)
529 {
530 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
531 ccdc_config_raw();
532 else
533 ccdc_config_ycbcr();
534 return 0;
535 }
536
537 static int ccdc_set_buftype(enum ccdc_buftype buf_type)
538 {
539 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
540 ccdc_cfg.bayer.buf_type = buf_type;
541 else
542 ccdc_cfg.ycbcr.buf_type = buf_type;
543 return 0;
544 }
545
546 static enum ccdc_buftype ccdc_get_buftype(void)
547 {
548 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
549 return ccdc_cfg.bayer.buf_type;
550 return ccdc_cfg.ycbcr.buf_type;
551 }
552
553 static int ccdc_enum_pix(u32 *pix, int i)
554 {
555 int ret = -EINVAL;
556 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
557 if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
558 *pix = ccdc_raw_bayer_pix_formats[i];
559 ret = 0;
560 }
561 } else {
562 if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
563 *pix = ccdc_raw_yuv_pix_formats[i];
564 ret = 0;
565 }
566 }
567 return ret;
568 }
569
570 static int ccdc_set_pixel_format(u32 pixfmt)
571 {
572 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
573 ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
574 if (pixfmt == V4L2_PIX_FMT_SBGGR8)
575 ccdc_cfg.bayer.config_params.alaw.enable = 1;
576 else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
577 return -EINVAL;
578 } else {
579 if (pixfmt == V4L2_PIX_FMT_YUYV)
580 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
581 else if (pixfmt == V4L2_PIX_FMT_UYVY)
582 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
583 else
584 return -EINVAL;
585 }
586 return 0;
587 }
588
589 static u32 ccdc_get_pixel_format(void)
590 {
591 struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
592 u32 pixfmt;
593
594 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
595 if (alaw->enable)
596 pixfmt = V4L2_PIX_FMT_SBGGR8;
597 else
598 pixfmt = V4L2_PIX_FMT_SBGGR16;
599 else {
600 if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
601 pixfmt = V4L2_PIX_FMT_YUYV;
602 else
603 pixfmt = V4L2_PIX_FMT_UYVY;
604 }
605 return pixfmt;
606 }
607
608 static int ccdc_set_image_window(struct v4l2_rect *win)
609 {
610 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
611 ccdc_cfg.bayer.win = *win;
612 else
613 ccdc_cfg.ycbcr.win = *win;
614 return 0;
615 }
616
617 static void ccdc_get_image_window(struct v4l2_rect *win)
618 {
619 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
620 *win = ccdc_cfg.bayer.win;
621 else
622 *win = ccdc_cfg.ycbcr.win;
623 }
624
625 static unsigned int ccdc_get_line_length(void)
626 {
627 struct ccdc_config_params_raw *config_params =
628 &ccdc_cfg.bayer.config_params;
629 unsigned int len;
630
631 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
632 if ((config_params->alaw.enable) ||
633 (config_params->data_sz == CCDC_DATA_8BITS))
634 len = ccdc_cfg.bayer.win.width;
635 else
636 len = ccdc_cfg.bayer.win.width * 2;
637 } else
638 len = ccdc_cfg.ycbcr.win.width * 2;
639 return ALIGN(len, 32);
640 }
641
642 static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
643 {
644 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
645 ccdc_cfg.bayer.frm_fmt = frm_fmt;
646 else
647 ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
648 return 0;
649 }
650
651 static enum ccdc_frmfmt ccdc_get_frame_format(void)
652 {
653 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
654 return ccdc_cfg.bayer.frm_fmt;
655 else
656 return ccdc_cfg.ycbcr.frm_fmt;
657 }
658
659 static int ccdc_getfid(void)
660 {
661 return (regr(CCDC_SYN_MODE) >> 15) & 1;
662 }
663
664 /* misc operations */
665 static inline void ccdc_setfbaddr(unsigned long addr)
666 {
667 regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
668 }
669
670 static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
671 {
672 ccdc_cfg.if_type = params->if_type;
673
674 switch (params->if_type) {
675 case VPFE_BT656:
676 case VPFE_YCBCR_SYNC_16:
677 case VPFE_YCBCR_SYNC_8:
678 case VPFE_BT656_10BIT:
679 ccdc_cfg.ycbcr.vd_pol = params->vdpol;
680 ccdc_cfg.ycbcr.hd_pol = params->hdpol;
681 break;
682 default:
683 /* TODO add support for raw bayer here */
684 return -EINVAL;
685 }
686 return 0;
687 }
688
689 static void ccdc_save_context(void)
690 {
691 ccdc_ctx[CCDC_PCR >> 2] = regr(CCDC_PCR);
692 ccdc_ctx[CCDC_SYN_MODE >> 2] = regr(CCDC_SYN_MODE);
693 ccdc_ctx[CCDC_HD_VD_WID >> 2] = regr(CCDC_HD_VD_WID);
694 ccdc_ctx[CCDC_PIX_LINES >> 2] = regr(CCDC_PIX_LINES);
695 ccdc_ctx[CCDC_HORZ_INFO >> 2] = regr(CCDC_HORZ_INFO);
696 ccdc_ctx[CCDC_VERT_START >> 2] = regr(CCDC_VERT_START);
697 ccdc_ctx[CCDC_VERT_LINES >> 2] = regr(CCDC_VERT_LINES);
698 ccdc_ctx[CCDC_CULLING >> 2] = regr(CCDC_CULLING);
699 ccdc_ctx[CCDC_HSIZE_OFF >> 2] = regr(CCDC_HSIZE_OFF);
700 ccdc_ctx[CCDC_SDOFST >> 2] = regr(CCDC_SDOFST);
701 ccdc_ctx[CCDC_SDR_ADDR >> 2] = regr(CCDC_SDR_ADDR);
702 ccdc_ctx[CCDC_CLAMP >> 2] = regr(CCDC_CLAMP);
703 ccdc_ctx[CCDC_DCSUB >> 2] = regr(CCDC_DCSUB);
704 ccdc_ctx[CCDC_COLPTN >> 2] = regr(CCDC_COLPTN);
705 ccdc_ctx[CCDC_BLKCMP >> 2] = regr(CCDC_BLKCMP);
706 ccdc_ctx[CCDC_FPC >> 2] = regr(CCDC_FPC);
707 ccdc_ctx[CCDC_FPC_ADDR >> 2] = regr(CCDC_FPC_ADDR);
708 ccdc_ctx[CCDC_VDINT >> 2] = regr(CCDC_VDINT);
709 ccdc_ctx[CCDC_ALAW >> 2] = regr(CCDC_ALAW);
710 ccdc_ctx[CCDC_REC656IF >> 2] = regr(CCDC_REC656IF);
711 ccdc_ctx[CCDC_CCDCFG >> 2] = regr(CCDC_CCDCFG);
712 ccdc_ctx[CCDC_FMTCFG >> 2] = regr(CCDC_FMTCFG);
713 ccdc_ctx[CCDC_FMT_HORZ >> 2] = regr(CCDC_FMT_HORZ);
714 ccdc_ctx[CCDC_FMT_VERT >> 2] = regr(CCDC_FMT_VERT);
715 ccdc_ctx[CCDC_FMT_ADDR0 >> 2] = regr(CCDC_FMT_ADDR0);
716 ccdc_ctx[CCDC_FMT_ADDR1 >> 2] = regr(CCDC_FMT_ADDR1);
717 ccdc_ctx[CCDC_FMT_ADDR2 >> 2] = regr(CCDC_FMT_ADDR2);
718 ccdc_ctx[CCDC_FMT_ADDR3 >> 2] = regr(CCDC_FMT_ADDR3);
719 ccdc_ctx[CCDC_FMT_ADDR4 >> 2] = regr(CCDC_FMT_ADDR4);
720 ccdc_ctx[CCDC_FMT_ADDR5 >> 2] = regr(CCDC_FMT_ADDR5);
721 ccdc_ctx[CCDC_FMT_ADDR6 >> 2] = regr(CCDC_FMT_ADDR6);
722 ccdc_ctx[CCDC_FMT_ADDR7 >> 2] = regr(CCDC_FMT_ADDR7);
723 ccdc_ctx[CCDC_PRGEVEN_0 >> 2] = regr(CCDC_PRGEVEN_0);
724 ccdc_ctx[CCDC_PRGEVEN_1 >> 2] = regr(CCDC_PRGEVEN_1);
725 ccdc_ctx[CCDC_PRGODD_0 >> 2] = regr(CCDC_PRGODD_0);
726 ccdc_ctx[CCDC_PRGODD_1 >> 2] = regr(CCDC_PRGODD_1);
727 ccdc_ctx[CCDC_VP_OUT >> 2] = regr(CCDC_VP_OUT);
728 }
729
730 static void ccdc_restore_context(void)
731 {
732 regw(ccdc_ctx[CCDC_SYN_MODE >> 2], CCDC_SYN_MODE);
733 regw(ccdc_ctx[CCDC_HD_VD_WID >> 2], CCDC_HD_VD_WID);
734 regw(ccdc_ctx[CCDC_PIX_LINES >> 2], CCDC_PIX_LINES);
735 regw(ccdc_ctx[CCDC_HORZ_INFO >> 2], CCDC_HORZ_INFO);
736 regw(ccdc_ctx[CCDC_VERT_START >> 2], CCDC_VERT_START);
737 regw(ccdc_ctx[CCDC_VERT_LINES >> 2], CCDC_VERT_LINES);
738 regw(ccdc_ctx[CCDC_CULLING >> 2], CCDC_CULLING);
739 regw(ccdc_ctx[CCDC_HSIZE_OFF >> 2], CCDC_HSIZE_OFF);
740 regw(ccdc_ctx[CCDC_SDOFST >> 2], CCDC_SDOFST);
741 regw(ccdc_ctx[CCDC_SDR_ADDR >> 2], CCDC_SDR_ADDR);
742 regw(ccdc_ctx[CCDC_CLAMP >> 2], CCDC_CLAMP);
743 regw(ccdc_ctx[CCDC_DCSUB >> 2], CCDC_DCSUB);
744 regw(ccdc_ctx[CCDC_COLPTN >> 2], CCDC_COLPTN);
745 regw(ccdc_ctx[CCDC_BLKCMP >> 2], CCDC_BLKCMP);
746 regw(ccdc_ctx[CCDC_FPC >> 2], CCDC_FPC);
747 regw(ccdc_ctx[CCDC_FPC_ADDR >> 2], CCDC_FPC_ADDR);
748 regw(ccdc_ctx[CCDC_VDINT >> 2], CCDC_VDINT);
749 regw(ccdc_ctx[CCDC_ALAW >> 2], CCDC_ALAW);
750 regw(ccdc_ctx[CCDC_REC656IF >> 2], CCDC_REC656IF);
751 regw(ccdc_ctx[CCDC_CCDCFG >> 2], CCDC_CCDCFG);
752 regw(ccdc_ctx[CCDC_FMTCFG >> 2], CCDC_FMTCFG);
753 regw(ccdc_ctx[CCDC_FMT_HORZ >> 2], CCDC_FMT_HORZ);
754 regw(ccdc_ctx[CCDC_FMT_VERT >> 2], CCDC_FMT_VERT);
755 regw(ccdc_ctx[CCDC_FMT_ADDR0 >> 2], CCDC_FMT_ADDR0);
756 regw(ccdc_ctx[CCDC_FMT_ADDR1 >> 2], CCDC_FMT_ADDR1);
757 regw(ccdc_ctx[CCDC_FMT_ADDR2 >> 2], CCDC_FMT_ADDR2);
758 regw(ccdc_ctx[CCDC_FMT_ADDR3 >> 2], CCDC_FMT_ADDR3);
759 regw(ccdc_ctx[CCDC_FMT_ADDR4 >> 2], CCDC_FMT_ADDR4);
760 regw(ccdc_ctx[CCDC_FMT_ADDR5 >> 2], CCDC_FMT_ADDR5);
761 regw(ccdc_ctx[CCDC_FMT_ADDR6 >> 2], CCDC_FMT_ADDR6);
762 regw(ccdc_ctx[CCDC_FMT_ADDR7 >> 2], CCDC_FMT_ADDR7);
763 regw(ccdc_ctx[CCDC_PRGEVEN_0 >> 2], CCDC_PRGEVEN_0);
764 regw(ccdc_ctx[CCDC_PRGEVEN_1 >> 2], CCDC_PRGEVEN_1);
765 regw(ccdc_ctx[CCDC_PRGODD_0 >> 2], CCDC_PRGODD_0);
766 regw(ccdc_ctx[CCDC_PRGODD_1 >> 2], CCDC_PRGODD_1);
767 regw(ccdc_ctx[CCDC_VP_OUT >> 2], CCDC_VP_OUT);
768 regw(ccdc_ctx[CCDC_PCR >> 2], CCDC_PCR);
769 }
770 static const struct ccdc_hw_device ccdc_hw_dev = {
771 .name = "DM6446 CCDC",
772 .owner = THIS_MODULE,
773 .hw_ops = {
774 .open = ccdc_open,
775 .close = ccdc_close,
776 .reset = ccdc_sbl_reset,
777 .enable = ccdc_enable,
778 .set_hw_if_params = ccdc_set_hw_if_params,
779 .configure = ccdc_configure,
780 .set_buftype = ccdc_set_buftype,
781 .get_buftype = ccdc_get_buftype,
782 .enum_pix = ccdc_enum_pix,
783 .set_pixel_format = ccdc_set_pixel_format,
784 .get_pixel_format = ccdc_get_pixel_format,
785 .set_frame_format = ccdc_set_frame_format,
786 .get_frame_format = ccdc_get_frame_format,
787 .set_image_window = ccdc_set_image_window,
788 .get_image_window = ccdc_get_image_window,
789 .get_line_length = ccdc_get_line_length,
790 .setfbaddr = ccdc_setfbaddr,
791 .getfid = ccdc_getfid,
792 },
793 };
794
795 static int dm644x_ccdc_probe(struct platform_device *pdev)
796 {
797 struct resource *res;
798 int status = 0;
799
800 /*
801 * first try to register with vpfe. If not correct platform, then we
802 * don't have to iomap
803 */
804 status = vpfe_register_ccdc_device(&ccdc_hw_dev);
805 if (status < 0)
806 return status;
807
808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
809 if (!res) {
810 status = -ENODEV;
811 goto fail_nores;
812 }
813
814 res = request_mem_region(res->start, resource_size(res), res->name);
815 if (!res) {
816 status = -EBUSY;
817 goto fail_nores;
818 }
819
820 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
821 if (!ccdc_cfg.base_addr) {
822 status = -ENOMEM;
823 goto fail_nomem;
824 }
825
826 ccdc_cfg.dev = &pdev->dev;
827 printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
828 return 0;
829 fail_nomem:
830 release_mem_region(res->start, resource_size(res));
831 fail_nores:
832 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
833 return status;
834 }
835
836 static int dm644x_ccdc_remove(struct platform_device *pdev)
837 {
838 struct resource *res;
839
840 iounmap(ccdc_cfg.base_addr);
841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
842 if (res)
843 release_mem_region(res->start, resource_size(res));
844 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
845 return 0;
846 }
847
848 static int dm644x_ccdc_suspend(struct device *dev)
849 {
850 /* Save CCDC context */
851 ccdc_save_context();
852 /* Disable CCDC */
853 ccdc_enable(0);
854
855 return 0;
856 }
857
858 static int dm644x_ccdc_resume(struct device *dev)
859 {
860 /* Restore CCDC context */
861 ccdc_restore_context();
862
863 return 0;
864 }
865
866 static const struct dev_pm_ops dm644x_ccdc_pm_ops = {
867 .suspend = dm644x_ccdc_suspend,
868 .resume = dm644x_ccdc_resume,
869 };
870
871 static struct platform_driver dm644x_ccdc_driver = {
872 .driver = {
873 .name = "dm644x_ccdc",
874 .pm = &dm644x_ccdc_pm_ops,
875 },
876 .remove = dm644x_ccdc_remove,
877 .probe = dm644x_ccdc_probe,
878 };
879
880 module_platform_driver(dm644x_ccdc_driver);
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