2 * Copyright (C) 2006-2009 Texas Instruments Inc
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * CCDC hardware module for DM6446
15 * ------------------------------
17 * This module is for configuring CCD controller of DM6446 VPFE to capture
18 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
19 * such as Defect Pixel Correction, Color Space Conversion etc to
20 * pre-process the Raw Bayer RGB data, before writing it to SDRAM. This
21 * module also allows application to configure individual
22 * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL.
23 * To do so, application includes dm644x_ccdc.h and vpfe_capture.h header
24 * files. The setparams() API is called by vpfe_capture driver
25 * to configure module parameters. This file is named DM644x so that other
26 * variants such DM6443 may be supported using the same module.
28 * TODO: Test Raw bayer parameter settings and bayer capture
29 * Split module parameter structure to module specific ioctl structs
30 * investigate if enum used for user space type definition
31 * to be replaced by #defines or integer
33 #include <linux/platform_device.h>
34 #include <linux/uaccess.h>
35 #include <linux/videodev2.h>
36 #include <linux/gfp.h>
37 #include <linux/err.h>
38 #include <linux/module.h>
40 #include <media/davinci/dm644x_ccdc.h>
41 #include <media/davinci/vpss.h>
43 #include "dm644x_ccdc_regs.h"
44 #include "ccdc_hw_device.h"
46 MODULE_LICENSE("GPL");
47 MODULE_DESCRIPTION("CCDC Driver for DM6446");
48 MODULE_AUTHOR("Texas Instruments");
50 static struct ccdc_oper_config
{
52 /* CCDC interface type */
53 enum vpfe_hw_if_type if_type
;
54 /* Raw Bayer configuration */
55 struct ccdc_params_raw bayer
;
56 /* YCbCr configuration */
57 struct ccdc_params_ycbcr ycbcr
;
58 /* ccdc base address */
59 void __iomem
*base_addr
;
61 /* Raw configurations */
63 .pix_fmt
= CCDC_PIXFMT_RAW
,
64 .frm_fmt
= CCDC_FRMFMT_PROGRESSIVE
,
66 .fid_pol
= VPFE_PINPOL_POSITIVE
,
67 .vd_pol
= VPFE_PINPOL_POSITIVE
,
68 .hd_pol
= VPFE_PINPOL_POSITIVE
,
70 .data_sz
= CCDC_DATA_10BITS
,
74 .pix_fmt
= CCDC_PIXFMT_YCBCR_8BIT
,
75 .frm_fmt
= CCDC_FRMFMT_INTERLACED
,
77 .fid_pol
= VPFE_PINPOL_POSITIVE
,
78 .vd_pol
= VPFE_PINPOL_POSITIVE
,
79 .hd_pol
= VPFE_PINPOL_POSITIVE
,
81 .pix_order
= CCDC_PIXORDER_CBYCRY
,
82 .buf_type
= CCDC_BUFTYPE_FLD_INTERLEAVED
86 #define CCDC_MAX_RAW_YUV_FORMATS 2
88 /* Raw Bayer formats */
89 static u32 ccdc_raw_bayer_pix_formats
[] =
90 {V4L2_PIX_FMT_SBGGR8
, V4L2_PIX_FMT_SBGGR16
};
93 static u32 ccdc_raw_yuv_pix_formats
[] =
94 {V4L2_PIX_FMT_UYVY
, V4L2_PIX_FMT_YUYV
};
96 /* CCDC Save/Restore context */
97 static u32 ccdc_ctx
[CCDC_REG_END
/ sizeof(u32
)];
99 /* register access routines */
100 static inline u32
regr(u32 offset
)
102 return __raw_readl(ccdc_cfg
.base_addr
+ offset
);
105 static inline void regw(u32 val
, u32 offset
)
107 __raw_writel(val
, ccdc_cfg
.base_addr
+ offset
);
110 static void ccdc_enable(int flag
)
112 regw(flag
, CCDC_PCR
);
115 static void ccdc_enable_vport(int flag
)
118 /* enable video port */
119 regw(CCDC_ENABLE_VIDEO_PORT
, CCDC_FMTCFG
);
121 regw(CCDC_DISABLE_VIDEO_PORT
, CCDC_FMTCFG
);
126 * This function will configure the window size
127 * to be capture in CCDC reg
129 static void ccdc_setwin(struct v4l2_rect
*image_win
,
130 enum ccdc_frmfmt frm_fmt
,
133 int horz_start
, horz_nr_pixels
;
134 int vert_start
, vert_nr_lines
;
135 int val
= 0, mid_img
= 0;
137 dev_dbg(ccdc_cfg
.dev
, "\nStarting ccdc_setwin...");
139 * ppc - per pixel count. indicates how many pixels per cell
140 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
141 * raw capture this is 1
143 horz_start
= image_win
->left
<< (ppc
- 1);
144 horz_nr_pixels
= (image_win
->width
<< (ppc
- 1)) - 1;
145 regw((horz_start
<< CCDC_HORZ_INFO_SPH_SHIFT
) | horz_nr_pixels
,
148 vert_start
= image_win
->top
;
150 if (frm_fmt
== CCDC_FRMFMT_INTERLACED
) {
151 vert_nr_lines
= (image_win
->height
>> 1) - 1;
153 /* Since first line doesn't have any data */
155 /* configure VDINT0 */
156 val
= (vert_start
<< CCDC_VDINT_VDINT0_SHIFT
);
157 regw(val
, CCDC_VDINT
);
160 /* Since first line doesn't have any data */
162 vert_nr_lines
= image_win
->height
- 1;
164 * configure VDINT0 and VDINT1. VDINT1 will be at half
167 mid_img
= vert_start
+ (image_win
->height
/ 2);
168 val
= (vert_start
<< CCDC_VDINT_VDINT0_SHIFT
) |
169 (mid_img
& CCDC_VDINT_VDINT1_MASK
);
170 regw(val
, CCDC_VDINT
);
173 regw((vert_start
<< CCDC_VERT_START_SLV0_SHIFT
) | vert_start
,
175 regw(vert_nr_lines
, CCDC_VERT_LINES
);
176 dev_dbg(ccdc_cfg
.dev
, "\nEnd of ccdc_setwin...");
179 static void ccdc_readregs(void)
181 unsigned int val
= 0;
183 val
= regr(CCDC_ALAW
);
184 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to ALAW...\n", val
);
185 val
= regr(CCDC_CLAMP
);
186 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to CLAMP...\n", val
);
187 val
= regr(CCDC_DCSUB
);
188 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to DCSUB...\n", val
);
189 val
= regr(CCDC_BLKCMP
);
190 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to BLKCMP...\n", val
);
191 val
= regr(CCDC_FPC_ADDR
);
192 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to FPC_ADDR...\n", val
);
193 val
= regr(CCDC_FPC
);
194 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to FPC...\n", val
);
195 val
= regr(CCDC_FMTCFG
);
196 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to FMTCFG...\n", val
);
197 val
= regr(CCDC_COLPTN
);
198 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to COLPTN...\n", val
);
199 val
= regr(CCDC_FMT_HORZ
);
200 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to FMT_HORZ...\n", val
);
201 val
= regr(CCDC_FMT_VERT
);
202 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to FMT_VERT...\n", val
);
203 val
= regr(CCDC_HSIZE_OFF
);
204 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to HSIZE_OFF...\n", val
);
205 val
= regr(CCDC_SDOFST
);
206 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to SDOFST...\n", val
);
207 val
= regr(CCDC_VP_OUT
);
208 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to VP_OUT...\n", val
);
209 val
= regr(CCDC_SYN_MODE
);
210 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to SYN_MODE...\n", val
);
211 val
= regr(CCDC_HORZ_INFO
);
212 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to HORZ_INFO...\n", val
);
213 val
= regr(CCDC_VERT_START
);
214 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to VERT_START...\n", val
);
215 val
= regr(CCDC_VERT_LINES
);
216 dev_notice(ccdc_cfg
.dev
, "\nReading 0x%x to VERT_LINES...\n", val
);
219 static int validate_ccdc_param(struct ccdc_config_params_raw
*ccdcparam
)
221 if (ccdcparam
->alaw
.enable
) {
222 u8 max_gamma
= ccdc_gamma_width_max_bit(ccdcparam
->alaw
.gamma_wd
);
223 u8 max_data
= ccdc_data_size_max_bit(ccdcparam
->data_sz
);
225 if ((ccdcparam
->alaw
.gamma_wd
> CCDC_GAMMA_BITS_09_0
) ||
226 (ccdcparam
->alaw
.gamma_wd
< CCDC_GAMMA_BITS_15_6
) ||
227 (max_gamma
> max_data
)) {
228 dev_dbg(ccdc_cfg
.dev
, "\nInvalid data line select");
235 static int ccdc_update_raw_params(struct ccdc_config_params_raw
*raw_params
)
237 struct ccdc_config_params_raw
*config_params
=
238 &ccdc_cfg
.bayer
.config_params
;
239 unsigned int *fpc_virtaddr
= NULL
;
240 unsigned int *fpc_physaddr
= NULL
;
242 memcpy(config_params
, raw_params
, sizeof(*raw_params
));
244 * allocate memory for fault pixel table and copy the user
245 * values to the table
247 if (!config_params
->fault_pxl
.enable
)
250 fpc_physaddr
= (unsigned int *)config_params
->fault_pxl
.fpc_table_addr
;
251 fpc_virtaddr
= (unsigned int *)phys_to_virt(
252 (unsigned long)fpc_physaddr
);
254 * Allocate memory for FPC table if current
255 * FPC table buffer is not big enough to
256 * accommodate FPC Number requested
258 if (raw_params
->fault_pxl
.fp_num
!= config_params
->fault_pxl
.fp_num
) {
259 if (fpc_physaddr
!= NULL
) {
260 free_pages((unsigned long)fpc_virtaddr
,
262 (config_params
->fault_pxl
.fp_num
*
266 /* Allocate memory for FPC table */
268 (unsigned int *)__get_free_pages(GFP_KERNEL
| GFP_DMA
,
269 get_order(raw_params
->
273 if (fpc_virtaddr
== NULL
) {
274 dev_dbg(ccdc_cfg
.dev
,
275 "\nUnable to allocate memory for FPC");
279 (unsigned int *)virt_to_phys((void *)fpc_virtaddr
);
282 /* Copy number of fault pixels and FPC table */
283 config_params
->fault_pxl
.fp_num
= raw_params
->fault_pxl
.fp_num
;
284 if (copy_from_user(fpc_virtaddr
,
285 (void __user
*)raw_params
->fault_pxl
.fpc_table_addr
,
286 config_params
->fault_pxl
.fp_num
* FP_NUM_BYTES
)) {
287 dev_dbg(ccdc_cfg
.dev
, "\n copy_from_user failed");
290 config_params
->fault_pxl
.fpc_table_addr
= (unsigned long)fpc_physaddr
;
294 static int ccdc_close(struct device
*dev
)
296 struct ccdc_config_params_raw
*config_params
=
297 &ccdc_cfg
.bayer
.config_params
;
298 unsigned int *fpc_physaddr
= NULL
, *fpc_virtaddr
= NULL
;
300 fpc_physaddr
= (unsigned int *)config_params
->fault_pxl
.fpc_table_addr
;
302 if (fpc_physaddr
!= NULL
) {
303 fpc_virtaddr
= (unsigned int *)
304 phys_to_virt((unsigned long)fpc_physaddr
);
305 free_pages((unsigned long)fpc_virtaddr
,
306 get_order(config_params
->fault_pxl
.fp_num
*
313 * ccdc_restore_defaults()
314 * This function will write defaults to all CCDC registers
316 static void ccdc_restore_defaults(void)
322 /* set all registers to default value */
323 for (i
= 4; i
<= 0x94; i
+= 4)
325 regw(CCDC_NO_CULLING
, CCDC_CULLING
);
326 regw(CCDC_GAMMA_BITS_11_2
, CCDC_ALAW
);
329 static int ccdc_open(struct device
*device
)
331 ccdc_restore_defaults();
332 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
333 ccdc_enable_vport(1);
337 static void ccdc_sbl_reset(void)
339 vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O
);
342 /* Parameter operations */
343 static int ccdc_set_params(void __user
*params
)
345 struct ccdc_config_params_raw ccdc_raw_params
;
348 if (ccdc_cfg
.if_type
!= VPFE_RAW_BAYER
)
351 x
= copy_from_user(&ccdc_raw_params
, params
, sizeof(ccdc_raw_params
));
353 dev_dbg(ccdc_cfg
.dev
, "ccdc_set_params: error in copyingccdc params, %d\n",
358 if (!validate_ccdc_param(&ccdc_raw_params
)) {
359 if (!ccdc_update_raw_params(&ccdc_raw_params
))
366 * ccdc_config_ycbcr()
367 * This function will configure CCDC for YCbCr video capture
369 static void ccdc_config_ycbcr(void)
371 struct ccdc_params_ycbcr
*params
= &ccdc_cfg
.ycbcr
;
374 dev_dbg(ccdc_cfg
.dev
, "\nStarting ccdc_config_ycbcr...");
376 * first restore the CCDC registers to default values
377 * This is important since we assume default values to be set in
378 * a lot of registers that we didn't touch
380 ccdc_restore_defaults();
383 * configure pixel format, frame format, configure video frame
384 * format, enable output to SDRAM, enable internal timing generator
387 syn_mode
= (((params
->pix_fmt
& CCDC_SYN_MODE_INPMOD_MASK
) <<
388 CCDC_SYN_MODE_INPMOD_SHIFT
) |
389 ((params
->frm_fmt
& CCDC_SYN_FLDMODE_MASK
) <<
390 CCDC_SYN_FLDMODE_SHIFT
) | CCDC_VDHDEN_ENABLE
|
391 CCDC_WEN_ENABLE
| CCDC_DATA_PACK_ENABLE
);
393 /* setup BT.656 sync mode */
394 if (params
->bt656_enable
) {
395 regw(CCDC_REC656IF_BT656_EN
, CCDC_REC656IF
);
398 * configure the FID, VD, HD pin polarity,
399 * fld,hd pol positive, vd negative, 8-bit data
401 syn_mode
|= CCDC_SYN_MODE_VD_POL_NEGATIVE
;
402 if (ccdc_cfg
.if_type
== VPFE_BT656_10BIT
)
403 syn_mode
|= CCDC_SYN_MODE_10BITS
;
405 syn_mode
|= CCDC_SYN_MODE_8BITS
;
407 /* y/c external sync mode */
408 syn_mode
|= (((params
->fid_pol
& CCDC_FID_POL_MASK
) <<
409 CCDC_FID_POL_SHIFT
) |
410 ((params
->hd_pol
& CCDC_HD_POL_MASK
) <<
412 ((params
->vd_pol
& CCDC_VD_POL_MASK
) <<
415 regw(syn_mode
, CCDC_SYN_MODE
);
417 /* configure video window */
418 ccdc_setwin(¶ms
->win
, params
->frm_fmt
, 2);
421 * configure the order of y cb cr in SDRAM, and disable latch
422 * internal register on vsync
424 if (ccdc_cfg
.if_type
== VPFE_BT656_10BIT
)
425 regw((params
->pix_order
<< CCDC_CCDCFG_Y8POS_SHIFT
) |
426 CCDC_LATCH_ON_VSYNC_DISABLE
| CCDC_CCDCFG_BW656_10BIT
,
429 regw((params
->pix_order
<< CCDC_CCDCFG_Y8POS_SHIFT
) |
430 CCDC_LATCH_ON_VSYNC_DISABLE
, CCDC_CCDCFG
);
433 * configure the horizontal line offset. This should be a
434 * on 32 byte boundary. So clear LSB 5 bits
436 regw(((params
->win
.width
* 2 + 31) & ~0x1f), CCDC_HSIZE_OFF
);
438 /* configure the memory line offset */
439 if (params
->buf_type
== CCDC_BUFTYPE_FLD_INTERLEAVED
)
440 /* two fields are interleaved in memory */
441 regw(CCDC_SDOFST_FIELD_INTERLEAVED
, CCDC_SDOFST
);
444 dev_dbg(ccdc_cfg
.dev
, "\nEnd of ccdc_config_ycbcr...\n");
447 static void ccdc_config_black_clamp(struct ccdc_black_clamp
*bclamp
)
451 if (!bclamp
->enable
) {
452 /* configure DCSub */
453 val
= (bclamp
->dc_sub
) & CCDC_BLK_DC_SUB_MASK
;
454 regw(val
, CCDC_DCSUB
);
455 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to DCSUB...\n", val
);
456 regw(CCDC_CLAMP_DEFAULT_VAL
, CCDC_CLAMP
);
457 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x0000 to CLAMP...\n");
461 * Configure gain, Start pixel, No of line to be avg,
462 * No of pixel/line to be avg, & Enable the Black clamping
464 val
= ((bclamp
->sgain
& CCDC_BLK_SGAIN_MASK
) |
465 ((bclamp
->start_pixel
& CCDC_BLK_ST_PXL_MASK
) <<
466 CCDC_BLK_ST_PXL_SHIFT
) |
467 ((bclamp
->sample_ln
& CCDC_BLK_SAMPLE_LINE_MASK
) <<
468 CCDC_BLK_SAMPLE_LINE_SHIFT
) |
469 ((bclamp
->sample_pixel
& CCDC_BLK_SAMPLE_LN_MASK
) <<
470 CCDC_BLK_SAMPLE_LN_SHIFT
) | CCDC_BLK_CLAMP_ENABLE
);
471 regw(val
, CCDC_CLAMP
);
472 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to CLAMP...\n", val
);
473 /* If Black clamping is enable then make dcsub 0 */
474 regw(CCDC_DCSUB_DEFAULT_VAL
, CCDC_DCSUB
);
475 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x00000000 to DCSUB...\n");
478 static void ccdc_config_black_compense(struct ccdc_black_compensation
*bcomp
)
482 val
= ((bcomp
->b
& CCDC_BLK_COMP_MASK
) |
483 ((bcomp
->gb
& CCDC_BLK_COMP_MASK
) <<
484 CCDC_BLK_COMP_GB_COMP_SHIFT
) |
485 ((bcomp
->gr
& CCDC_BLK_COMP_MASK
) <<
486 CCDC_BLK_COMP_GR_COMP_SHIFT
) |
487 ((bcomp
->r
& CCDC_BLK_COMP_MASK
) <<
488 CCDC_BLK_COMP_R_COMP_SHIFT
));
489 regw(val
, CCDC_BLKCMP
);
492 static void ccdc_config_fpc(struct ccdc_fault_pixel
*fpc
)
496 /* Initially disable FPC */
497 val
= CCDC_FPC_DISABLE
;
503 /* Configure Fault pixel if needed */
504 regw(fpc
->fpc_table_addr
, CCDC_FPC_ADDR
);
505 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%lx to FPC_ADDR...\n",
506 (fpc
->fpc_table_addr
));
507 /* Write the FPC params with FPC disable */
508 val
= fpc
->fp_num
& CCDC_FPC_FPC_NUM_MASK
;
511 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to FPC...\n", val
);
512 /* read the FPC register */
513 val
= regr(CCDC_FPC
) | CCDC_FPC_ENABLE
;
515 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to FPC...\n", val
);
520 * This function will configure CCDC for Raw capture mode
522 static void ccdc_config_raw(void)
524 struct ccdc_params_raw
*params
= &ccdc_cfg
.bayer
;
525 struct ccdc_config_params_raw
*config_params
=
526 &ccdc_cfg
.bayer
.config_params
;
527 unsigned int syn_mode
= 0;
530 dev_dbg(ccdc_cfg
.dev
, "\nStarting ccdc_config_raw...");
533 ccdc_restore_defaults();
535 /* Disable latching function registers on VSYNC */
536 regw(CCDC_LATCH_ON_VSYNC_DISABLE
, CCDC_CCDCFG
);
539 * Configure the vertical sync polarity(SYN_MODE.VDPOL),
540 * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
541 * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
542 * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
543 * SDRAM, enable internal timing generator
546 (((params
->vd_pol
& CCDC_VD_POL_MASK
) << CCDC_VD_POL_SHIFT
) |
547 ((params
->hd_pol
& CCDC_HD_POL_MASK
) << CCDC_HD_POL_SHIFT
) |
548 ((params
->fid_pol
& CCDC_FID_POL_MASK
) << CCDC_FID_POL_SHIFT
) |
549 ((params
->frm_fmt
& CCDC_FRM_FMT_MASK
) << CCDC_FRM_FMT_SHIFT
) |
550 ((config_params
->data_sz
& CCDC_DATA_SZ_MASK
) <<
551 CCDC_DATA_SZ_SHIFT
) |
552 ((params
->pix_fmt
& CCDC_PIX_FMT_MASK
) << CCDC_PIX_FMT_SHIFT
) |
553 CCDC_WEN_ENABLE
| CCDC_VDHDEN_ENABLE
);
555 /* Enable and configure aLaw register if needed */
556 if (config_params
->alaw
.enable
) {
557 val
= ((config_params
->alaw
.gamma_wd
&
558 CCDC_ALAW_GAMMA_WD_MASK
) | CCDC_ALAW_ENABLE
);
559 regw(val
, CCDC_ALAW
);
560 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to ALAW...\n", val
);
563 /* Configure video window */
564 ccdc_setwin(¶ms
->win
, params
->frm_fmt
, CCDC_PPC_RAW
);
566 /* Configure Black Clamp */
567 ccdc_config_black_clamp(&config_params
->blk_clamp
);
569 /* Configure Black level compensation */
570 ccdc_config_black_compense(&config_params
->blk_comp
);
572 /* Configure Fault Pixel Correction */
573 ccdc_config_fpc(&config_params
->fault_pxl
);
575 /* If data size is 8 bit then pack the data */
576 if ((config_params
->data_sz
== CCDC_DATA_8BITS
) ||
577 config_params
->alaw
.enable
)
578 syn_mode
|= CCDC_DATA_PACK_ENABLE
;
580 /* disable video port */
581 val
= CCDC_DISABLE_VIDEO_PORT
;
583 if (config_params
->data_sz
== CCDC_DATA_8BITS
)
584 val
|= (CCDC_DATA_10BITS
& CCDC_FMTCFG_VPIN_MASK
)
585 << CCDC_FMTCFG_VPIN_SHIFT
;
587 val
|= (config_params
->data_sz
& CCDC_FMTCFG_VPIN_MASK
)
588 << CCDC_FMTCFG_VPIN_SHIFT
;
589 /* Write value in FMTCFG */
590 regw(val
, CCDC_FMTCFG
);
592 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to FMTCFG...\n", val
);
593 /* Configure the color pattern according to mt9t001 sensor */
594 regw(CCDC_COLPTN_VAL
, CCDC_COLPTN
);
596 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0xBB11BB11 to COLPTN...\n");
598 * Configure Data formatter(Video port) pixel selection
599 * (FMT_HORZ, FMT_VERT)
601 val
= ((params
->win
.left
& CCDC_FMT_HORZ_FMTSPH_MASK
) <<
602 CCDC_FMT_HORZ_FMTSPH_SHIFT
) |
603 (params
->win
.width
& CCDC_FMT_HORZ_FMTLNH_MASK
);
604 regw(val
, CCDC_FMT_HORZ
);
606 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to FMT_HORZ...\n", val
);
607 val
= (params
->win
.top
& CCDC_FMT_VERT_FMTSLV_MASK
)
608 << CCDC_FMT_VERT_FMTSLV_SHIFT
;
609 if (params
->frm_fmt
== CCDC_FRMFMT_PROGRESSIVE
)
610 val
|= (params
->win
.height
) & CCDC_FMT_VERT_FMTLNV_MASK
;
612 val
|= (params
->win
.height
>> 1) & CCDC_FMT_VERT_FMTLNV_MASK
;
614 dev_dbg(ccdc_cfg
.dev
, "\nparams->win.height 0x%x ...\n",
616 regw(val
, CCDC_FMT_VERT
);
618 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to FMT_VERT...\n", val
);
620 dev_dbg(ccdc_cfg
.dev
, "\nbelow regw(val, FMT_VERT)...");
623 * Configure Horizontal offset register. If pack 8 is enabled then
624 * 1 pixel will take 1 byte
626 if ((config_params
->data_sz
== CCDC_DATA_8BITS
) ||
627 config_params
->alaw
.enable
)
628 regw((params
->win
.width
+ CCDC_32BYTE_ALIGN_VAL
) &
629 CCDC_HSIZE_OFF_MASK
, CCDC_HSIZE_OFF
);
631 /* else one pixel will take 2 byte */
632 regw(((params
->win
.width
* CCDC_TWO_BYTES_PER_PIXEL
) +
633 CCDC_32BYTE_ALIGN_VAL
) & CCDC_HSIZE_OFF_MASK
,
636 /* Set value for SDOFST */
637 if (params
->frm_fmt
== CCDC_FRMFMT_INTERLACED
) {
638 if (params
->image_invert_enable
) {
639 /* For intelace inverse mode */
640 regw(CCDC_INTERLACED_IMAGE_INVERT
, CCDC_SDOFST
);
641 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x4B6D to SDOFST..\n");
645 /* For intelace non inverse mode */
646 regw(CCDC_INTERLACED_NO_IMAGE_INVERT
, CCDC_SDOFST
);
647 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x0249 to SDOFST..\n");
649 } else if (params
->frm_fmt
== CCDC_FRMFMT_PROGRESSIVE
) {
650 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT
, CCDC_SDOFST
);
651 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x0000 to SDOFST...\n");
655 * Configure video port pixel selection (VPOUT)
656 * Here -1 is to make the height value less than FMT_VERT.FMTLNV
658 if (params
->frm_fmt
== CCDC_FRMFMT_PROGRESSIVE
)
659 val
= (((params
->win
.height
- 1) & CCDC_VP_OUT_VERT_NUM_MASK
))
660 << CCDC_VP_OUT_VERT_NUM_SHIFT
;
663 ((((params
->win
.height
>> CCDC_INTERLACED_HEIGHT_SHIFT
) -
664 1) & CCDC_VP_OUT_VERT_NUM_MASK
)) <<
665 CCDC_VP_OUT_VERT_NUM_SHIFT
;
667 val
|= ((((params
->win
.width
))) & CCDC_VP_OUT_HORZ_NUM_MASK
)
668 << CCDC_VP_OUT_HORZ_NUM_SHIFT
;
669 val
|= (params
->win
.left
) & CCDC_VP_OUT_HORZ_ST_MASK
;
670 regw(val
, CCDC_VP_OUT
);
672 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to VP_OUT...\n", val
);
673 regw(syn_mode
, CCDC_SYN_MODE
);
674 dev_dbg(ccdc_cfg
.dev
, "\nWriting 0x%x to SYN_MODE...\n", syn_mode
);
677 dev_dbg(ccdc_cfg
.dev
, "\nend of ccdc_config_raw...");
681 static int ccdc_configure(void)
683 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
690 static int ccdc_set_buftype(enum ccdc_buftype buf_type
)
692 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
693 ccdc_cfg
.bayer
.buf_type
= buf_type
;
695 ccdc_cfg
.ycbcr
.buf_type
= buf_type
;
699 static enum ccdc_buftype
ccdc_get_buftype(void)
701 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
702 return ccdc_cfg
.bayer
.buf_type
;
703 return ccdc_cfg
.ycbcr
.buf_type
;
706 static int ccdc_enum_pix(u32
*pix
, int i
)
709 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
) {
710 if (i
< ARRAY_SIZE(ccdc_raw_bayer_pix_formats
)) {
711 *pix
= ccdc_raw_bayer_pix_formats
[i
];
715 if (i
< ARRAY_SIZE(ccdc_raw_yuv_pix_formats
)) {
716 *pix
= ccdc_raw_yuv_pix_formats
[i
];
723 static int ccdc_set_pixel_format(u32 pixfmt
)
725 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
) {
726 ccdc_cfg
.bayer
.pix_fmt
= CCDC_PIXFMT_RAW
;
727 if (pixfmt
== V4L2_PIX_FMT_SBGGR8
)
728 ccdc_cfg
.bayer
.config_params
.alaw
.enable
= 1;
729 else if (pixfmt
!= V4L2_PIX_FMT_SBGGR16
)
732 if (pixfmt
== V4L2_PIX_FMT_YUYV
)
733 ccdc_cfg
.ycbcr
.pix_order
= CCDC_PIXORDER_YCBYCR
;
734 else if (pixfmt
== V4L2_PIX_FMT_UYVY
)
735 ccdc_cfg
.ycbcr
.pix_order
= CCDC_PIXORDER_CBYCRY
;
742 static u32
ccdc_get_pixel_format(void)
744 struct ccdc_a_law
*alaw
= &ccdc_cfg
.bayer
.config_params
.alaw
;
747 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
749 pixfmt
= V4L2_PIX_FMT_SBGGR8
;
751 pixfmt
= V4L2_PIX_FMT_SBGGR16
;
753 if (ccdc_cfg
.ycbcr
.pix_order
== CCDC_PIXORDER_YCBYCR
)
754 pixfmt
= V4L2_PIX_FMT_YUYV
;
756 pixfmt
= V4L2_PIX_FMT_UYVY
;
761 static int ccdc_set_image_window(struct v4l2_rect
*win
)
763 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
764 ccdc_cfg
.bayer
.win
= *win
;
766 ccdc_cfg
.ycbcr
.win
= *win
;
770 static void ccdc_get_image_window(struct v4l2_rect
*win
)
772 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
773 *win
= ccdc_cfg
.bayer
.win
;
775 *win
= ccdc_cfg
.ycbcr
.win
;
778 static unsigned int ccdc_get_line_length(void)
780 struct ccdc_config_params_raw
*config_params
=
781 &ccdc_cfg
.bayer
.config_params
;
784 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
) {
785 if ((config_params
->alaw
.enable
) ||
786 (config_params
->data_sz
== CCDC_DATA_8BITS
))
787 len
= ccdc_cfg
.bayer
.win
.width
;
789 len
= ccdc_cfg
.bayer
.win
.width
* 2;
791 len
= ccdc_cfg
.ycbcr
.win
.width
* 2;
792 return ALIGN(len
, 32);
795 static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt
)
797 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
798 ccdc_cfg
.bayer
.frm_fmt
= frm_fmt
;
800 ccdc_cfg
.ycbcr
.frm_fmt
= frm_fmt
;
804 static enum ccdc_frmfmt
ccdc_get_frame_format(void)
806 if (ccdc_cfg
.if_type
== VPFE_RAW_BAYER
)
807 return ccdc_cfg
.bayer
.frm_fmt
;
809 return ccdc_cfg
.ycbcr
.frm_fmt
;
812 static int ccdc_getfid(void)
814 return (regr(CCDC_SYN_MODE
) >> 15) & 1;
817 /* misc operations */
818 static inline void ccdc_setfbaddr(unsigned long addr
)
820 regw(addr
& 0xffffffe0, CCDC_SDR_ADDR
);
823 static int ccdc_set_hw_if_params(struct vpfe_hw_if_param
*params
)
825 ccdc_cfg
.if_type
= params
->if_type
;
827 switch (params
->if_type
) {
829 case VPFE_YCBCR_SYNC_16
:
830 case VPFE_YCBCR_SYNC_8
:
831 case VPFE_BT656_10BIT
:
832 ccdc_cfg
.ycbcr
.vd_pol
= params
->vdpol
;
833 ccdc_cfg
.ycbcr
.hd_pol
= params
->hdpol
;
836 /* TODO add support for raw bayer here */
842 static void ccdc_save_context(void)
844 ccdc_ctx
[CCDC_PCR
>> 2] = regr(CCDC_PCR
);
845 ccdc_ctx
[CCDC_SYN_MODE
>> 2] = regr(CCDC_SYN_MODE
);
846 ccdc_ctx
[CCDC_HD_VD_WID
>> 2] = regr(CCDC_HD_VD_WID
);
847 ccdc_ctx
[CCDC_PIX_LINES
>> 2] = regr(CCDC_PIX_LINES
);
848 ccdc_ctx
[CCDC_HORZ_INFO
>> 2] = regr(CCDC_HORZ_INFO
);
849 ccdc_ctx
[CCDC_VERT_START
>> 2] = regr(CCDC_VERT_START
);
850 ccdc_ctx
[CCDC_VERT_LINES
>> 2] = regr(CCDC_VERT_LINES
);
851 ccdc_ctx
[CCDC_CULLING
>> 2] = regr(CCDC_CULLING
);
852 ccdc_ctx
[CCDC_HSIZE_OFF
>> 2] = regr(CCDC_HSIZE_OFF
);
853 ccdc_ctx
[CCDC_SDOFST
>> 2] = regr(CCDC_SDOFST
);
854 ccdc_ctx
[CCDC_SDR_ADDR
>> 2] = regr(CCDC_SDR_ADDR
);
855 ccdc_ctx
[CCDC_CLAMP
>> 2] = regr(CCDC_CLAMP
);
856 ccdc_ctx
[CCDC_DCSUB
>> 2] = regr(CCDC_DCSUB
);
857 ccdc_ctx
[CCDC_COLPTN
>> 2] = regr(CCDC_COLPTN
);
858 ccdc_ctx
[CCDC_BLKCMP
>> 2] = regr(CCDC_BLKCMP
);
859 ccdc_ctx
[CCDC_FPC
>> 2] = regr(CCDC_FPC
);
860 ccdc_ctx
[CCDC_FPC_ADDR
>> 2] = regr(CCDC_FPC_ADDR
);
861 ccdc_ctx
[CCDC_VDINT
>> 2] = regr(CCDC_VDINT
);
862 ccdc_ctx
[CCDC_ALAW
>> 2] = regr(CCDC_ALAW
);
863 ccdc_ctx
[CCDC_REC656IF
>> 2] = regr(CCDC_REC656IF
);
864 ccdc_ctx
[CCDC_CCDCFG
>> 2] = regr(CCDC_CCDCFG
);
865 ccdc_ctx
[CCDC_FMTCFG
>> 2] = regr(CCDC_FMTCFG
);
866 ccdc_ctx
[CCDC_FMT_HORZ
>> 2] = regr(CCDC_FMT_HORZ
);
867 ccdc_ctx
[CCDC_FMT_VERT
>> 2] = regr(CCDC_FMT_VERT
);
868 ccdc_ctx
[CCDC_FMT_ADDR0
>> 2] = regr(CCDC_FMT_ADDR0
);
869 ccdc_ctx
[CCDC_FMT_ADDR1
>> 2] = regr(CCDC_FMT_ADDR1
);
870 ccdc_ctx
[CCDC_FMT_ADDR2
>> 2] = regr(CCDC_FMT_ADDR2
);
871 ccdc_ctx
[CCDC_FMT_ADDR3
>> 2] = regr(CCDC_FMT_ADDR3
);
872 ccdc_ctx
[CCDC_FMT_ADDR4
>> 2] = regr(CCDC_FMT_ADDR4
);
873 ccdc_ctx
[CCDC_FMT_ADDR5
>> 2] = regr(CCDC_FMT_ADDR5
);
874 ccdc_ctx
[CCDC_FMT_ADDR6
>> 2] = regr(CCDC_FMT_ADDR6
);
875 ccdc_ctx
[CCDC_FMT_ADDR7
>> 2] = regr(CCDC_FMT_ADDR7
);
876 ccdc_ctx
[CCDC_PRGEVEN_0
>> 2] = regr(CCDC_PRGEVEN_0
);
877 ccdc_ctx
[CCDC_PRGEVEN_1
>> 2] = regr(CCDC_PRGEVEN_1
);
878 ccdc_ctx
[CCDC_PRGODD_0
>> 2] = regr(CCDC_PRGODD_0
);
879 ccdc_ctx
[CCDC_PRGODD_1
>> 2] = regr(CCDC_PRGODD_1
);
880 ccdc_ctx
[CCDC_VP_OUT
>> 2] = regr(CCDC_VP_OUT
);
883 static void ccdc_restore_context(void)
885 regw(ccdc_ctx
[CCDC_SYN_MODE
>> 2], CCDC_SYN_MODE
);
886 regw(ccdc_ctx
[CCDC_HD_VD_WID
>> 2], CCDC_HD_VD_WID
);
887 regw(ccdc_ctx
[CCDC_PIX_LINES
>> 2], CCDC_PIX_LINES
);
888 regw(ccdc_ctx
[CCDC_HORZ_INFO
>> 2], CCDC_HORZ_INFO
);
889 regw(ccdc_ctx
[CCDC_VERT_START
>> 2], CCDC_VERT_START
);
890 regw(ccdc_ctx
[CCDC_VERT_LINES
>> 2], CCDC_VERT_LINES
);
891 regw(ccdc_ctx
[CCDC_CULLING
>> 2], CCDC_CULLING
);
892 regw(ccdc_ctx
[CCDC_HSIZE_OFF
>> 2], CCDC_HSIZE_OFF
);
893 regw(ccdc_ctx
[CCDC_SDOFST
>> 2], CCDC_SDOFST
);
894 regw(ccdc_ctx
[CCDC_SDR_ADDR
>> 2], CCDC_SDR_ADDR
);
895 regw(ccdc_ctx
[CCDC_CLAMP
>> 2], CCDC_CLAMP
);
896 regw(ccdc_ctx
[CCDC_DCSUB
>> 2], CCDC_DCSUB
);
897 regw(ccdc_ctx
[CCDC_COLPTN
>> 2], CCDC_COLPTN
);
898 regw(ccdc_ctx
[CCDC_BLKCMP
>> 2], CCDC_BLKCMP
);
899 regw(ccdc_ctx
[CCDC_FPC
>> 2], CCDC_FPC
);
900 regw(ccdc_ctx
[CCDC_FPC_ADDR
>> 2], CCDC_FPC_ADDR
);
901 regw(ccdc_ctx
[CCDC_VDINT
>> 2], CCDC_VDINT
);
902 regw(ccdc_ctx
[CCDC_ALAW
>> 2], CCDC_ALAW
);
903 regw(ccdc_ctx
[CCDC_REC656IF
>> 2], CCDC_REC656IF
);
904 regw(ccdc_ctx
[CCDC_CCDCFG
>> 2], CCDC_CCDCFG
);
905 regw(ccdc_ctx
[CCDC_FMTCFG
>> 2], CCDC_FMTCFG
);
906 regw(ccdc_ctx
[CCDC_FMT_HORZ
>> 2], CCDC_FMT_HORZ
);
907 regw(ccdc_ctx
[CCDC_FMT_VERT
>> 2], CCDC_FMT_VERT
);
908 regw(ccdc_ctx
[CCDC_FMT_ADDR0
>> 2], CCDC_FMT_ADDR0
);
909 regw(ccdc_ctx
[CCDC_FMT_ADDR1
>> 2], CCDC_FMT_ADDR1
);
910 regw(ccdc_ctx
[CCDC_FMT_ADDR2
>> 2], CCDC_FMT_ADDR2
);
911 regw(ccdc_ctx
[CCDC_FMT_ADDR3
>> 2], CCDC_FMT_ADDR3
);
912 regw(ccdc_ctx
[CCDC_FMT_ADDR4
>> 2], CCDC_FMT_ADDR4
);
913 regw(ccdc_ctx
[CCDC_FMT_ADDR5
>> 2], CCDC_FMT_ADDR5
);
914 regw(ccdc_ctx
[CCDC_FMT_ADDR6
>> 2], CCDC_FMT_ADDR6
);
915 regw(ccdc_ctx
[CCDC_FMT_ADDR7
>> 2], CCDC_FMT_ADDR7
);
916 regw(ccdc_ctx
[CCDC_PRGEVEN_0
>> 2], CCDC_PRGEVEN_0
);
917 regw(ccdc_ctx
[CCDC_PRGEVEN_1
>> 2], CCDC_PRGEVEN_1
);
918 regw(ccdc_ctx
[CCDC_PRGODD_0
>> 2], CCDC_PRGODD_0
);
919 regw(ccdc_ctx
[CCDC_PRGODD_1
>> 2], CCDC_PRGODD_1
);
920 regw(ccdc_ctx
[CCDC_VP_OUT
>> 2], CCDC_VP_OUT
);
921 regw(ccdc_ctx
[CCDC_PCR
>> 2], CCDC_PCR
);
923 static struct ccdc_hw_device ccdc_hw_dev
= {
924 .name
= "DM6446 CCDC",
925 .owner
= THIS_MODULE
,
929 .reset
= ccdc_sbl_reset
,
930 .enable
= ccdc_enable
,
931 .set_hw_if_params
= ccdc_set_hw_if_params
,
932 .set_params
= ccdc_set_params
,
933 .configure
= ccdc_configure
,
934 .set_buftype
= ccdc_set_buftype
,
935 .get_buftype
= ccdc_get_buftype
,
936 .enum_pix
= ccdc_enum_pix
,
937 .set_pixel_format
= ccdc_set_pixel_format
,
938 .get_pixel_format
= ccdc_get_pixel_format
,
939 .set_frame_format
= ccdc_set_frame_format
,
940 .get_frame_format
= ccdc_get_frame_format
,
941 .set_image_window
= ccdc_set_image_window
,
942 .get_image_window
= ccdc_get_image_window
,
943 .get_line_length
= ccdc_get_line_length
,
944 .setfbaddr
= ccdc_setfbaddr
,
945 .getfid
= ccdc_getfid
,
949 static int dm644x_ccdc_probe(struct platform_device
*pdev
)
951 struct resource
*res
;
955 * first try to register with vpfe. If not correct platform, then we
956 * don't have to iomap
958 status
= vpfe_register_ccdc_device(&ccdc_hw_dev
);
962 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
968 res
= request_mem_region(res
->start
, resource_size(res
), res
->name
);
974 ccdc_cfg
.base_addr
= ioremap_nocache(res
->start
, resource_size(res
));
975 if (!ccdc_cfg
.base_addr
) {
980 ccdc_cfg
.dev
= &pdev
->dev
;
981 printk(KERN_NOTICE
"%s is registered with vpfe.\n", ccdc_hw_dev
.name
);
984 release_mem_region(res
->start
, resource_size(res
));
986 vpfe_unregister_ccdc_device(&ccdc_hw_dev
);
990 static int dm644x_ccdc_remove(struct platform_device
*pdev
)
992 struct resource
*res
;
994 iounmap(ccdc_cfg
.base_addr
);
995 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
997 release_mem_region(res
->start
, resource_size(res
));
998 vpfe_unregister_ccdc_device(&ccdc_hw_dev
);
1002 static int dm644x_ccdc_suspend(struct device
*dev
)
1004 /* Save CCDC context */
1005 ccdc_save_context();
1012 static int dm644x_ccdc_resume(struct device
*dev
)
1014 /* Restore CCDC context */
1015 ccdc_restore_context();
1020 static const struct dev_pm_ops dm644x_ccdc_pm_ops
= {
1021 .suspend
= dm644x_ccdc_suspend
,
1022 .resume
= dm644x_ccdc_resume
,
1025 static struct platform_driver dm644x_ccdc_driver
= {
1027 .name
= "dm644x_ccdc",
1028 .pm
= &dm644x_ccdc_pm_ops
,
1030 .remove
= dm644x_ccdc_remove
,
1031 .probe
= dm644x_ccdc_probe
,
1034 module_platform_driver(dm644x_ccdc_driver
);