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[mirror_ubuntu-bionic-kernel.git] / drivers / media / platform / exynos-gsc / gsc-core.c
1 /*
2 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Samsung EXYNOS5 SoC series G-Scaler driver
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/workqueue.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/list.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <linux/of.h>
27 #include <media/v4l2-ioctl.h>
28
29 #include "gsc-core.h"
30
31 #define GSC_CLOCK_GATE_NAME "gscl"
32
33 static const struct gsc_fmt gsc_formats[] = {
34 {
35 .name = "RGB565",
36 .pixelformat = V4L2_PIX_FMT_RGB565X,
37 .depth = { 16 },
38 .color = GSC_RGB,
39 .num_planes = 1,
40 .num_comp = 1,
41 }, {
42 .name = "BGRX-8-8-8-8, 32 bpp",
43 .pixelformat = V4L2_PIX_FMT_BGR32,
44 .depth = { 32 },
45 .color = GSC_RGB,
46 .num_planes = 1,
47 .num_comp = 1,
48 }, {
49 .name = "YUV 4:2:2 packed, YCbYCr",
50 .pixelformat = V4L2_PIX_FMT_YUYV,
51 .depth = { 16 },
52 .color = GSC_YUV422,
53 .yorder = GSC_LSB_Y,
54 .corder = GSC_CBCR,
55 .num_planes = 1,
56 .num_comp = 1,
57 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
58 }, {
59 .name = "YUV 4:2:2 packed, CbYCrY",
60 .pixelformat = V4L2_PIX_FMT_UYVY,
61 .depth = { 16 },
62 .color = GSC_YUV422,
63 .yorder = GSC_LSB_C,
64 .corder = GSC_CBCR,
65 .num_planes = 1,
66 .num_comp = 1,
67 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
68 }, {
69 .name = "YUV 4:2:2 packed, CrYCbY",
70 .pixelformat = V4L2_PIX_FMT_VYUY,
71 .depth = { 16 },
72 .color = GSC_YUV422,
73 .yorder = GSC_LSB_C,
74 .corder = GSC_CRCB,
75 .num_planes = 1,
76 .num_comp = 1,
77 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
78 }, {
79 .name = "YUV 4:2:2 packed, YCrYCb",
80 .pixelformat = V4L2_PIX_FMT_YVYU,
81 .depth = { 16 },
82 .color = GSC_YUV422,
83 .yorder = GSC_LSB_Y,
84 .corder = GSC_CRCB,
85 .num_planes = 1,
86 .num_comp = 1,
87 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
88 }, {
89 .name = "YUV 4:4:4 planar, YCbYCr",
90 .pixelformat = V4L2_PIX_FMT_YUV32,
91 .depth = { 32 },
92 .color = GSC_YUV444,
93 .yorder = GSC_LSB_Y,
94 .corder = GSC_CBCR,
95 .num_planes = 1,
96 .num_comp = 1,
97 }, {
98 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
99 .pixelformat = V4L2_PIX_FMT_YUV422P,
100 .depth = { 16 },
101 .color = GSC_YUV422,
102 .yorder = GSC_LSB_Y,
103 .corder = GSC_CBCR,
104 .num_planes = 1,
105 .num_comp = 3,
106 }, {
107 .name = "YUV 4:2:2 planar, Y/CbCr",
108 .pixelformat = V4L2_PIX_FMT_NV16,
109 .depth = { 16 },
110 .color = GSC_YUV422,
111 .yorder = GSC_LSB_Y,
112 .corder = GSC_CBCR,
113 .num_planes = 1,
114 .num_comp = 2,
115 }, {
116 .name = "YUV 4:2:2 planar, Y/CrCb",
117 .pixelformat = V4L2_PIX_FMT_NV61,
118 .depth = { 16 },
119 .color = GSC_YUV422,
120 .yorder = GSC_LSB_Y,
121 .corder = GSC_CRCB,
122 .num_planes = 1,
123 .num_comp = 2,
124 }, {
125 .name = "YUV 4:2:0 planar, YCbCr",
126 .pixelformat = V4L2_PIX_FMT_YUV420,
127 .depth = { 12 },
128 .color = GSC_YUV420,
129 .yorder = GSC_LSB_Y,
130 .corder = GSC_CBCR,
131 .num_planes = 1,
132 .num_comp = 3,
133 }, {
134 .name = "YUV 4:2:0 planar, YCrCb",
135 .pixelformat = V4L2_PIX_FMT_YVU420,
136 .depth = { 12 },
137 .color = GSC_YUV420,
138 .yorder = GSC_LSB_Y,
139 .corder = GSC_CRCB,
140 .num_planes = 1,
141 .num_comp = 3,
142
143 }, {
144 .name = "YUV 4:2:0 planar, Y/CbCr",
145 .pixelformat = V4L2_PIX_FMT_NV12,
146 .depth = { 12 },
147 .color = GSC_YUV420,
148 .yorder = GSC_LSB_Y,
149 .corder = GSC_CBCR,
150 .num_planes = 1,
151 .num_comp = 2,
152 }, {
153 .name = "YUV 4:2:0 planar, Y/CrCb",
154 .pixelformat = V4L2_PIX_FMT_NV21,
155 .depth = { 12 },
156 .color = GSC_YUV420,
157 .yorder = GSC_LSB_Y,
158 .corder = GSC_CRCB,
159 .num_planes = 1,
160 .num_comp = 2,
161 }, {
162 .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr",
163 .pixelformat = V4L2_PIX_FMT_NV12M,
164 .depth = { 8, 4 },
165 .color = GSC_YUV420,
166 .yorder = GSC_LSB_Y,
167 .corder = GSC_CBCR,
168 .num_planes = 2,
169 .num_comp = 2,
170 }, {
171 .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
172 .pixelformat = V4L2_PIX_FMT_YUV420M,
173 .depth = { 8, 2, 2 },
174 .color = GSC_YUV420,
175 .yorder = GSC_LSB_Y,
176 .corder = GSC_CBCR,
177 .num_planes = 3,
178 .num_comp = 3,
179 }, {
180 .name = "YUV 4:2:0 non-contig. 3p, Y/Cr/Cb",
181 .pixelformat = V4L2_PIX_FMT_YVU420M,
182 .depth = { 8, 2, 2 },
183 .color = GSC_YUV420,
184 .yorder = GSC_LSB_Y,
185 .corder = GSC_CRCB,
186 .num_planes = 3,
187 .num_comp = 3,
188 }, {
189 .name = "YUV 4:2:0 n.c. 2p, Y/CbCr tiled",
190 .pixelformat = V4L2_PIX_FMT_NV12MT_16X16,
191 .depth = { 8, 4 },
192 .color = GSC_YUV420,
193 .yorder = GSC_LSB_Y,
194 .corder = GSC_CBCR,
195 .num_planes = 2,
196 .num_comp = 2,
197 }
198 };
199
200 const struct gsc_fmt *get_format(int index)
201 {
202 if (index >= ARRAY_SIZE(gsc_formats))
203 return NULL;
204
205 return (struct gsc_fmt *)&gsc_formats[index];
206 }
207
208 const struct gsc_fmt *find_fmt(u32 *pixelformat, u32 *mbus_code, u32 index)
209 {
210 const struct gsc_fmt *fmt, *def_fmt = NULL;
211 unsigned int i;
212
213 if (index >= ARRAY_SIZE(gsc_formats))
214 return NULL;
215
216 for (i = 0; i < ARRAY_SIZE(gsc_formats); ++i) {
217 fmt = get_format(i);
218 if (pixelformat && fmt->pixelformat == *pixelformat)
219 return fmt;
220 if (mbus_code && fmt->mbus_code == *mbus_code)
221 return fmt;
222 if (index == i)
223 def_fmt = fmt;
224 }
225 return def_fmt;
226
227 }
228
229 void gsc_set_frame_size(struct gsc_frame *frame, int width, int height)
230 {
231 frame->f_width = width;
232 frame->f_height = height;
233 frame->crop.width = width;
234 frame->crop.height = height;
235 frame->crop.left = 0;
236 frame->crop.top = 0;
237 }
238
239 int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst,
240 u32 *ratio)
241 {
242 if ((dst > src) || (dst >= src / var->poly_sc_down_max)) {
243 *ratio = 1;
244 return 0;
245 }
246
247 if ((src / var->poly_sc_down_max / var->pre_sc_down_max) > dst) {
248 pr_err("Exceeded maximum downscaling ratio (1/16))");
249 return -EINVAL;
250 }
251
252 *ratio = (dst > (src / 8)) ? 2 : 4;
253
254 return 0;
255 }
256
257 void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh)
258 {
259 if (hratio == 4 && vratio == 4)
260 *sh = 4;
261 else if ((hratio == 4 && vratio == 2) ||
262 (hratio == 2 && vratio == 4))
263 *sh = 3;
264 else if ((hratio == 4 && vratio == 1) ||
265 (hratio == 1 && vratio == 4) ||
266 (hratio == 2 && vratio == 2))
267 *sh = 2;
268 else if (hratio == 1 && vratio == 1)
269 *sh = 0;
270 else
271 *sh = 1;
272 }
273
274 void gsc_check_src_scale_info(struct gsc_variant *var,
275 struct gsc_frame *s_frame, u32 *wratio,
276 u32 tx, u32 ty, u32 *hratio)
277 {
278 int remainder = 0, walign, halign;
279
280 if (is_yuv420(s_frame->fmt->color)) {
281 walign = GSC_SC_ALIGN_4;
282 halign = GSC_SC_ALIGN_4;
283 } else if (is_yuv422(s_frame->fmt->color)) {
284 walign = GSC_SC_ALIGN_4;
285 halign = GSC_SC_ALIGN_2;
286 } else {
287 walign = GSC_SC_ALIGN_2;
288 halign = GSC_SC_ALIGN_2;
289 }
290
291 remainder = s_frame->crop.width % (*wratio * walign);
292 if (remainder) {
293 s_frame->crop.width -= remainder;
294 gsc_cal_prescaler_ratio(var, s_frame->crop.width, tx, wratio);
295 pr_info("cropped src width size is recalculated from %d to %d",
296 s_frame->crop.width + remainder, s_frame->crop.width);
297 }
298
299 remainder = s_frame->crop.height % (*hratio * halign);
300 if (remainder) {
301 s_frame->crop.height -= remainder;
302 gsc_cal_prescaler_ratio(var, s_frame->crop.height, ty, hratio);
303 pr_info("cropped src height size is recalculated from %d to %d",
304 s_frame->crop.height + remainder, s_frame->crop.height);
305 }
306 }
307
308 int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f)
309 {
310 const struct gsc_fmt *fmt;
311
312 fmt = find_fmt(NULL, NULL, f->index);
313 if (!fmt)
314 return -EINVAL;
315
316 strlcpy(f->description, fmt->name, sizeof(f->description));
317 f->pixelformat = fmt->pixelformat;
318
319 return 0;
320 }
321
322 static int get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index, u32 *ret_addr)
323 {
324 if (frm->addr.y == addr) {
325 *index = 0;
326 *ret_addr = frm->addr.y;
327 } else if (frm->addr.cb == addr) {
328 *index = 1;
329 *ret_addr = frm->addr.cb;
330 } else if (frm->addr.cr == addr) {
331 *index = 2;
332 *ret_addr = frm->addr.cr;
333 } else {
334 pr_err("Plane address is wrong");
335 return -EINVAL;
336 }
337 return 0;
338 }
339
340 void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
341 {
342 u32 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len;
343 f_chk_addr = f_chk_len = s_chk_addr = s_chk_len = 0;
344
345 f_chk_addr = frm->addr.y;
346 f_chk_len = frm->payload[0];
347 if (frm->fmt->num_planes == 2) {
348 s_chk_addr = frm->addr.cb;
349 s_chk_len = frm->payload[1];
350 } else if (frm->fmt->num_planes == 3) {
351 u32 low_addr, low_plane, mid_addr, mid_plane;
352 u32 high_addr, high_plane;
353 u32 t_min, t_max;
354
355 t_min = min3(frm->addr.y, frm->addr.cb, frm->addr.cr);
356 if (get_plane_info(frm, t_min, &low_plane, &low_addr))
357 return;
358 t_max = max3(frm->addr.y, frm->addr.cb, frm->addr.cr);
359 if (get_plane_info(frm, t_max, &high_plane, &high_addr))
360 return;
361
362 mid_plane = 3 - (low_plane + high_plane);
363 if (mid_plane == 0)
364 mid_addr = frm->addr.y;
365 else if (mid_plane == 1)
366 mid_addr = frm->addr.cb;
367 else if (mid_plane == 2)
368 mid_addr = frm->addr.cr;
369 else
370 return;
371
372 f_chk_addr = low_addr;
373 if (mid_addr + frm->payload[mid_plane] - low_addr >
374 high_addr + frm->payload[high_plane] - mid_addr) {
375 f_chk_len = frm->payload[low_plane];
376 s_chk_addr = mid_addr;
377 s_chk_len = high_addr +
378 frm->payload[high_plane] - mid_addr;
379 } else {
380 f_chk_len = mid_addr +
381 frm->payload[mid_plane] - low_addr;
382 s_chk_addr = high_addr;
383 s_chk_len = frm->payload[high_plane];
384 }
385 }
386 pr_debug("f_addr = 0x%08x, f_len = %d, s_addr = 0x%08x, s_len = %d\n",
387 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len);
388 }
389
390 int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
391 {
392 struct gsc_dev *gsc = ctx->gsc_dev;
393 struct gsc_variant *variant = gsc->variant;
394 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
395 const struct gsc_fmt *fmt;
396 u32 max_w, max_h, mod_x, mod_y;
397 u32 min_w, min_h, tmp_w, tmp_h;
398 int i;
399
400 pr_debug("user put w: %d, h: %d", pix_mp->width, pix_mp->height);
401
402 fmt = find_fmt(&pix_mp->pixelformat, NULL, 0);
403 if (!fmt) {
404 pr_err("pixelformat format (0x%X) invalid\n",
405 pix_mp->pixelformat);
406 return -EINVAL;
407 }
408
409 if (pix_mp->field == V4L2_FIELD_ANY)
410 pix_mp->field = V4L2_FIELD_NONE;
411 else if (pix_mp->field != V4L2_FIELD_NONE) {
412 pr_err("Not supported field order(%d)\n", pix_mp->field);
413 return -EINVAL;
414 }
415
416 max_w = variant->pix_max->target_rot_dis_w;
417 max_h = variant->pix_max->target_rot_dis_h;
418
419 mod_x = ffs(variant->pix_align->org_w) - 1;
420 if (is_yuv420(fmt->color))
421 mod_y = ffs(variant->pix_align->org_h) - 1;
422 else
423 mod_y = ffs(variant->pix_align->org_h) - 2;
424
425 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
426 min_w = variant->pix_min->org_w;
427 min_h = variant->pix_min->org_h;
428 } else {
429 min_w = variant->pix_min->target_rot_dis_w;
430 min_h = variant->pix_min->target_rot_dis_h;
431 }
432
433 pr_debug("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d",
434 mod_x, mod_y, max_w, max_h);
435
436 /* To check if image size is modified to adjust parameter against
437 hardware abilities */
438 tmp_w = pix_mp->width;
439 tmp_h = pix_mp->height;
440
441 v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x,
442 &pix_mp->height, min_h, max_h, mod_y, 0);
443 if (tmp_w != pix_mp->width || tmp_h != pix_mp->height)
444 pr_debug("Image size has been modified from %dx%d to %dx%d\n",
445 tmp_w, tmp_h, pix_mp->width, pix_mp->height);
446
447 pix_mp->num_planes = fmt->num_planes;
448
449 if (pix_mp->width >= 1280) /* HD */
450 pix_mp->colorspace = V4L2_COLORSPACE_REC709;
451 else /* SD */
452 pix_mp->colorspace = V4L2_COLORSPACE_SMPTE170M;
453
454 for (i = 0; i < pix_mp->num_planes; ++i) {
455 struct v4l2_plane_pix_format *plane_fmt = &pix_mp->plane_fmt[i];
456 u32 bpl = plane_fmt->bytesperline;
457
458 if (fmt->num_comp == 1 && /* Packed */
459 (bpl == 0 || (bpl * 8 / fmt->depth[i]) < pix_mp->width))
460 bpl = pix_mp->width * fmt->depth[i] / 8;
461
462 if (fmt->num_comp > 1 && /* Planar */
463 (bpl == 0 || bpl < pix_mp->width))
464 bpl = pix_mp->width;
465
466 if (i != 0 && fmt->num_comp == 3)
467 bpl /= 2;
468
469 plane_fmt->bytesperline = bpl;
470 plane_fmt->sizeimage = max(pix_mp->width * pix_mp->height *
471 fmt->depth[i] / 8,
472 plane_fmt->sizeimage);
473 pr_debug("[%d]: bpl: %d, sizeimage: %d",
474 i, bpl, pix_mp->plane_fmt[i].sizeimage);
475 }
476
477 return 0;
478 }
479
480 int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
481 {
482 struct gsc_frame *frame;
483 struct v4l2_pix_format_mplane *pix_mp;
484 int i;
485
486 frame = ctx_get_frame(ctx, f->type);
487 if (IS_ERR(frame))
488 return PTR_ERR(frame);
489
490 pix_mp = &f->fmt.pix_mp;
491
492 pix_mp->width = frame->f_width;
493 pix_mp->height = frame->f_height;
494 pix_mp->field = V4L2_FIELD_NONE;
495 pix_mp->pixelformat = frame->fmt->pixelformat;
496 pix_mp->colorspace = V4L2_COLORSPACE_REC709;
497 pix_mp->num_planes = frame->fmt->num_planes;
498
499 for (i = 0; i < pix_mp->num_planes; ++i) {
500 pix_mp->plane_fmt[i].bytesperline = (frame->f_width *
501 frame->fmt->depth[i]) / 8;
502 pix_mp->plane_fmt[i].sizeimage =
503 pix_mp->plane_fmt[i].bytesperline * frame->f_height;
504 }
505
506 return 0;
507 }
508
509 void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h)
510 {
511 if (tmp_w != *w || tmp_h != *h) {
512 pr_info("Cropped size has been modified from %dx%d to %dx%d",
513 *w, *h, tmp_w, tmp_h);
514 *w = tmp_w;
515 *h = tmp_h;
516 }
517 }
518
519 int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
520 {
521 struct gsc_frame *frame;
522
523 frame = ctx_get_frame(ctx, cr->type);
524 if (IS_ERR(frame))
525 return PTR_ERR(frame);
526
527 cr->c = frame->crop;
528
529 return 0;
530 }
531
532 int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
533 {
534 struct gsc_frame *f;
535 struct gsc_dev *gsc = ctx->gsc_dev;
536 struct gsc_variant *variant = gsc->variant;
537 u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h;
538 u32 min_w, min_h, max_w, max_h;
539
540 if (cr->c.top < 0 || cr->c.left < 0) {
541 pr_err("doesn't support negative values for top & left\n");
542 return -EINVAL;
543 }
544 pr_debug("user put w: %d, h: %d", cr->c.width, cr->c.height);
545
546 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
547 f = &ctx->d_frame;
548 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
549 f = &ctx->s_frame;
550 else
551 return -EINVAL;
552
553 max_w = f->f_width;
554 max_h = f->f_height;
555 tmp_w = cr->c.width;
556 tmp_h = cr->c.height;
557
558 if (V4L2_TYPE_IS_OUTPUT(cr->type)) {
559 if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 1) ||
560 is_rgb(f->fmt->color))
561 min_w = 32;
562 else
563 min_w = 64;
564 if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 3) ||
565 is_yuv420(f->fmt->color))
566 min_h = 32;
567 else
568 min_h = 16;
569 } else {
570 if (is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color))
571 mod_x = ffs(variant->pix_align->target_w) - 1;
572 if (is_yuv420(f->fmt->color))
573 mod_y = ffs(variant->pix_align->target_h) - 1;
574 if (ctx->gsc_ctrls.rotate->val == 90 ||
575 ctx->gsc_ctrls.rotate->val == 270) {
576 max_w = f->f_height;
577 max_h = f->f_width;
578 min_w = variant->pix_min->target_rot_en_w;
579 min_h = variant->pix_min->target_rot_en_h;
580 tmp_w = cr->c.height;
581 tmp_h = cr->c.width;
582 } else {
583 min_w = variant->pix_min->target_rot_dis_w;
584 min_h = variant->pix_min->target_rot_dis_h;
585 }
586 }
587 pr_debug("mod_x: %d, mod_y: %d, min_w: %d, min_h = %d",
588 mod_x, mod_y, min_w, min_h);
589 pr_debug("tmp_w : %d, tmp_h : %d", tmp_w, tmp_h);
590
591 v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x,
592 &tmp_h, min_h, max_h, mod_y, 0);
593
594 if (!V4L2_TYPE_IS_OUTPUT(cr->type) &&
595 (ctx->gsc_ctrls.rotate->val == 90 ||
596 ctx->gsc_ctrls.rotate->val == 270))
597 gsc_check_crop_change(tmp_h, tmp_w,
598 &cr->c.width, &cr->c.height);
599 else
600 gsc_check_crop_change(tmp_w, tmp_h,
601 &cr->c.width, &cr->c.height);
602
603
604 /* adjust left/top if cropping rectangle is out of bounds */
605 /* Need to add code to algin left value with 2's multiple */
606 if (cr->c.left + tmp_w > max_w)
607 cr->c.left = max_w - tmp_w;
608 if (cr->c.top + tmp_h > max_h)
609 cr->c.top = max_h - tmp_h;
610
611 if ((is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) &&
612 cr->c.left & 1)
613 cr->c.left -= 1;
614
615 pr_debug("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
616 cr->c.left, cr->c.top, cr->c.width, cr->c.height, max_w, max_h);
617
618 return 0;
619 }
620
621 int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
622 int dh, int rot, int out_path)
623 {
624 int tmp_w, tmp_h, sc_down_max;
625
626 if (out_path == GSC_DMA)
627 sc_down_max = var->sc_down_max;
628 else
629 sc_down_max = var->local_sc_down;
630
631 if (rot == 90 || rot == 270) {
632 tmp_w = dh;
633 tmp_h = dw;
634 } else {
635 tmp_w = dw;
636 tmp_h = dh;
637 }
638
639 if ((sw / tmp_w) > sc_down_max ||
640 (sh / tmp_h) > sc_down_max ||
641 (tmp_w / sw) > var->sc_up_max ||
642 (tmp_h / sh) > var->sc_up_max)
643 return -EINVAL;
644
645 return 0;
646 }
647
648 int gsc_set_scaler_info(struct gsc_ctx *ctx)
649 {
650 struct gsc_scaler *sc = &ctx->scaler;
651 struct gsc_frame *s_frame = &ctx->s_frame;
652 struct gsc_frame *d_frame = &ctx->d_frame;
653 struct gsc_variant *variant = ctx->gsc_dev->variant;
654 struct device *dev = &ctx->gsc_dev->pdev->dev;
655 int tx, ty;
656 int ret;
657
658 ret = gsc_check_scaler_ratio(variant, s_frame->crop.width,
659 s_frame->crop.height, d_frame->crop.width, d_frame->crop.height,
660 ctx->gsc_ctrls.rotate->val, ctx->out_path);
661 if (ret) {
662 pr_err("out of scaler range");
663 return ret;
664 }
665
666 if (ctx->gsc_ctrls.rotate->val == 90 ||
667 ctx->gsc_ctrls.rotate->val == 270) {
668 ty = d_frame->crop.width;
669 tx = d_frame->crop.height;
670 } else {
671 tx = d_frame->crop.width;
672 ty = d_frame->crop.height;
673 }
674
675 if (tx <= 0 || ty <= 0) {
676 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
677 return -EINVAL;
678 }
679
680 ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.width,
681 tx, &sc->pre_hratio);
682 if (ret) {
683 pr_err("Horizontal scale ratio is out of range");
684 return ret;
685 }
686
687 ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.height,
688 ty, &sc->pre_vratio);
689 if (ret) {
690 pr_err("Vertical scale ratio is out of range");
691 return ret;
692 }
693
694 gsc_check_src_scale_info(variant, s_frame, &sc->pre_hratio,
695 tx, ty, &sc->pre_vratio);
696
697 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
698 &sc->pre_shfactor);
699
700 sc->main_hratio = (s_frame->crop.width << 16) / tx;
701 sc->main_vratio = (s_frame->crop.height << 16) / ty;
702
703 pr_debug("scaler input/output size : sx = %d, sy = %d, tx = %d, ty = %d",
704 s_frame->crop.width, s_frame->crop.height, tx, ty);
705 pr_debug("scaler ratio info : pre_shfactor : %d, pre_h : %d",
706 sc->pre_shfactor, sc->pre_hratio);
707 pr_debug("pre_v :%d, main_h : %d, main_v : %d",
708 sc->pre_vratio, sc->main_hratio, sc->main_vratio);
709
710 return 0;
711 }
712
713 static int __gsc_s_ctrl(struct gsc_ctx *ctx, struct v4l2_ctrl *ctrl)
714 {
715 struct gsc_dev *gsc = ctx->gsc_dev;
716 struct gsc_variant *variant = gsc->variant;
717 unsigned int flags = GSC_DST_FMT | GSC_SRC_FMT;
718 int ret = 0;
719
720 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
721 return 0;
722
723 switch (ctrl->id) {
724 case V4L2_CID_HFLIP:
725 ctx->hflip = ctrl->val;
726 break;
727
728 case V4L2_CID_VFLIP:
729 ctx->vflip = ctrl->val;
730 break;
731
732 case V4L2_CID_ROTATE:
733 if ((ctx->state & flags) == flags) {
734 ret = gsc_check_scaler_ratio(variant,
735 ctx->s_frame.crop.width,
736 ctx->s_frame.crop.height,
737 ctx->d_frame.crop.width,
738 ctx->d_frame.crop.height,
739 ctx->gsc_ctrls.rotate->val,
740 ctx->out_path);
741
742 if (ret)
743 return -EINVAL;
744 }
745
746 ctx->rotation = ctrl->val;
747 break;
748
749 case V4L2_CID_ALPHA_COMPONENT:
750 ctx->d_frame.alpha = ctrl->val;
751 break;
752 }
753
754 ctx->state |= GSC_PARAMS;
755 return 0;
756 }
757
758 static int gsc_s_ctrl(struct v4l2_ctrl *ctrl)
759 {
760 struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
761 unsigned long flags;
762 int ret;
763
764 spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
765 ret = __gsc_s_ctrl(ctx, ctrl);
766 spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
767
768 return ret;
769 }
770
771 static const struct v4l2_ctrl_ops gsc_ctrl_ops = {
772 .s_ctrl = gsc_s_ctrl,
773 };
774
775 int gsc_ctrls_create(struct gsc_ctx *ctx)
776 {
777 if (ctx->ctrls_rdy) {
778 pr_err("Control handler of this context was created already");
779 return 0;
780 }
781
782 v4l2_ctrl_handler_init(&ctx->ctrl_handler, GSC_MAX_CTRL_NUM);
783
784 ctx->gsc_ctrls.rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler,
785 &gsc_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0);
786 ctx->gsc_ctrls.hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
787 &gsc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
788 ctx->gsc_ctrls.vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
789 &gsc_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
790 ctx->gsc_ctrls.global_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
791 &gsc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0);
792
793 ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
794
795 if (ctx->ctrl_handler.error) {
796 int err = ctx->ctrl_handler.error;
797 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
798 pr_err("Failed to create G-Scaler control handlers");
799 return err;
800 }
801
802 return 0;
803 }
804
805 void gsc_ctrls_delete(struct gsc_ctx *ctx)
806 {
807 if (ctx->ctrls_rdy) {
808 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
809 ctx->ctrls_rdy = false;
810 }
811 }
812
813 /* The color format (num_comp, num_planes) must be already configured. */
814 int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
815 struct gsc_frame *frame, struct gsc_addr *addr)
816 {
817 int ret = 0;
818 u32 pix_size;
819
820 if ((vb == NULL) || (frame == NULL))
821 return -EINVAL;
822
823 pix_size = frame->f_width * frame->f_height;
824
825 pr_debug("num_planes= %d, num_comp= %d, pix_size= %d",
826 frame->fmt->num_planes, frame->fmt->num_comp, pix_size);
827
828 addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
829
830 if (frame->fmt->num_planes == 1) {
831 switch (frame->fmt->num_comp) {
832 case 1:
833 addr->cb = 0;
834 addr->cr = 0;
835 break;
836 case 2:
837 /* decompose Y into Y/Cb */
838 addr->cb = (dma_addr_t)(addr->y + pix_size);
839 addr->cr = 0;
840 break;
841 case 3:
842 /* decompose Y into Y/Cb/Cr */
843 addr->cb = (dma_addr_t)(addr->y + pix_size);
844 if (GSC_YUV420 == frame->fmt->color)
845 addr->cr = (dma_addr_t)(addr->cb
846 + (pix_size >> 2));
847 else /* 422 */
848 addr->cr = (dma_addr_t)(addr->cb
849 + (pix_size >> 1));
850 break;
851 default:
852 pr_err("Invalid the number of color planes");
853 return -EINVAL;
854 }
855 } else {
856 if (frame->fmt->num_planes >= 2)
857 addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
858
859 if (frame->fmt->num_planes == 3)
860 addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
861 }
862
863 if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) ||
864 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) ||
865 (frame->fmt->pixelformat == V4L2_PIX_FMT_NV61) ||
866 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) ||
867 (frame->fmt->pixelformat == V4L2_PIX_FMT_NV21) ||
868 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M))
869 swap(addr->cb, addr->cr);
870
871 pr_debug("ADDR: y= %pad cb= %pad cr= %pad ret= %d",
872 &addr->y, &addr->cb, &addr->cr, ret);
873
874 return ret;
875 }
876
877 static irqreturn_t gsc_irq_handler(int irq, void *priv)
878 {
879 struct gsc_dev *gsc = priv;
880 struct gsc_ctx *ctx;
881 int gsc_irq;
882
883 gsc_irq = gsc_hw_get_irq_status(gsc);
884 gsc_hw_clear_irq(gsc, gsc_irq);
885
886 if (gsc_irq == GSC_IRQ_OVERRUN) {
887 pr_err("Local path input over-run interrupt has occurred!\n");
888 return IRQ_HANDLED;
889 }
890
891 spin_lock(&gsc->slock);
892
893 if (test_and_clear_bit(ST_M2M_PEND, &gsc->state)) {
894
895 gsc_hw_enable_control(gsc, false);
896
897 if (test_and_clear_bit(ST_M2M_SUSPENDING, &gsc->state)) {
898 set_bit(ST_M2M_SUSPENDED, &gsc->state);
899 wake_up(&gsc->irq_queue);
900 goto isr_unlock;
901 }
902 ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
903
904 if (!ctx || !ctx->m2m_ctx)
905 goto isr_unlock;
906
907 spin_unlock(&gsc->slock);
908 gsc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
909
910 /* wake_up job_abort, stop_streaming */
911 if (ctx->state & GSC_CTX_STOP_REQ) {
912 ctx->state &= ~GSC_CTX_STOP_REQ;
913 wake_up(&gsc->irq_queue);
914 }
915 return IRQ_HANDLED;
916 }
917
918 isr_unlock:
919 spin_unlock(&gsc->slock);
920 return IRQ_HANDLED;
921 }
922
923 static struct gsc_pix_max gsc_v_100_max = {
924 .org_scaler_bypass_w = 8192,
925 .org_scaler_bypass_h = 8192,
926 .org_scaler_input_w = 4800,
927 .org_scaler_input_h = 3344,
928 .real_rot_dis_w = 4800,
929 .real_rot_dis_h = 3344,
930 .real_rot_en_w = 2047,
931 .real_rot_en_h = 2047,
932 .target_rot_dis_w = 4800,
933 .target_rot_dis_h = 3344,
934 .target_rot_en_w = 2016,
935 .target_rot_en_h = 2016,
936 };
937
938 static struct gsc_pix_min gsc_v_100_min = {
939 .org_w = 64,
940 .org_h = 32,
941 .real_w = 64,
942 .real_h = 32,
943 .target_rot_dis_w = 64,
944 .target_rot_dis_h = 32,
945 .target_rot_en_w = 32,
946 .target_rot_en_h = 16,
947 };
948
949 static struct gsc_pix_align gsc_v_100_align = {
950 .org_h = 16,
951 .org_w = 16, /* yuv420 : 16, others : 8 */
952 .offset_h = 2, /* yuv420/422 : 2, others : 1 */
953 .real_w = 16, /* yuv420/422 : 4~16, others : 2~8 */
954 .real_h = 16, /* yuv420 : 4~16, others : 1 */
955 .target_w = 2, /* yuv420/422 : 2, others : 1 */
956 .target_h = 2, /* yuv420 : 2, others : 1 */
957 };
958
959 static struct gsc_variant gsc_v_100_variant = {
960 .pix_max = &gsc_v_100_max,
961 .pix_min = &gsc_v_100_min,
962 .pix_align = &gsc_v_100_align,
963 .in_buf_cnt = 32,
964 .out_buf_cnt = 32,
965 .sc_up_max = 8,
966 .sc_down_max = 16,
967 .poly_sc_down_max = 4,
968 .pre_sc_down_max = 4,
969 .local_sc_down = 2,
970 };
971
972 static struct gsc_driverdata gsc_v_100_drvdata = {
973 .variant = {
974 [0] = &gsc_v_100_variant,
975 [1] = &gsc_v_100_variant,
976 [2] = &gsc_v_100_variant,
977 [3] = &gsc_v_100_variant,
978 },
979 .num_entities = 4,
980 .lclk_frequency = 266000000UL,
981 };
982
983 static const struct of_device_id exynos_gsc_match[] = {
984 {
985 .compatible = "samsung,exynos5-gsc",
986 .data = &gsc_v_100_drvdata,
987 },
988 {},
989 };
990 MODULE_DEVICE_TABLE(of, exynos_gsc_match);
991
992 static void *gsc_get_drv_data(struct platform_device *pdev)
993 {
994 struct gsc_driverdata *driver_data = NULL;
995 const struct of_device_id *match;
996
997 match = of_match_node(exynos_gsc_match, pdev->dev.of_node);
998 if (match)
999 driver_data = (struct gsc_driverdata *)match->data;
1000
1001 return driver_data;
1002 }
1003
1004 static void gsc_clk_put(struct gsc_dev *gsc)
1005 {
1006 if (!IS_ERR(gsc->clock))
1007 clk_unprepare(gsc->clock);
1008 }
1009
1010 static int gsc_clk_get(struct gsc_dev *gsc)
1011 {
1012 int ret;
1013
1014 dev_dbg(&gsc->pdev->dev, "gsc_clk_get Called\n");
1015
1016 gsc->clock = devm_clk_get(&gsc->pdev->dev, GSC_CLOCK_GATE_NAME);
1017 if (IS_ERR(gsc->clock)) {
1018 dev_err(&gsc->pdev->dev, "failed to get clock~~~: %s\n",
1019 GSC_CLOCK_GATE_NAME);
1020 return PTR_ERR(gsc->clock);
1021 }
1022
1023 ret = clk_prepare(gsc->clock);
1024 if (ret < 0) {
1025 dev_err(&gsc->pdev->dev, "clock prepare failed for clock: %s\n",
1026 GSC_CLOCK_GATE_NAME);
1027 gsc->clock = ERR_PTR(-EINVAL);
1028 return ret;
1029 }
1030
1031 return 0;
1032 }
1033
1034 static int gsc_m2m_suspend(struct gsc_dev *gsc)
1035 {
1036 unsigned long flags;
1037 int timeout;
1038
1039 spin_lock_irqsave(&gsc->slock, flags);
1040 if (!gsc_m2m_pending(gsc)) {
1041 spin_unlock_irqrestore(&gsc->slock, flags);
1042 return 0;
1043 }
1044 clear_bit(ST_M2M_SUSPENDED, &gsc->state);
1045 set_bit(ST_M2M_SUSPENDING, &gsc->state);
1046 spin_unlock_irqrestore(&gsc->slock, flags);
1047
1048 timeout = wait_event_timeout(gsc->irq_queue,
1049 test_bit(ST_M2M_SUSPENDED, &gsc->state),
1050 GSC_SHUTDOWN_TIMEOUT);
1051
1052 clear_bit(ST_M2M_SUSPENDING, &gsc->state);
1053 return timeout == 0 ? -EAGAIN : 0;
1054 }
1055
1056 static int gsc_m2m_resume(struct gsc_dev *gsc)
1057 {
1058 struct gsc_ctx *ctx;
1059 unsigned long flags;
1060
1061 spin_lock_irqsave(&gsc->slock, flags);
1062 /* Clear for full H/W setup in first run after resume */
1063 ctx = gsc->m2m.ctx;
1064 gsc->m2m.ctx = NULL;
1065 spin_unlock_irqrestore(&gsc->slock, flags);
1066
1067 if (test_and_clear_bit(ST_M2M_SUSPENDED, &gsc->state))
1068 gsc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
1069
1070 return 0;
1071 }
1072
1073 static int gsc_probe(struct platform_device *pdev)
1074 {
1075 struct gsc_dev *gsc;
1076 struct resource *res;
1077 struct gsc_driverdata *drv_data = gsc_get_drv_data(pdev);
1078 struct device *dev = &pdev->dev;
1079 int ret;
1080
1081 gsc = devm_kzalloc(dev, sizeof(struct gsc_dev), GFP_KERNEL);
1082 if (!gsc)
1083 return -ENOMEM;
1084
1085 ret = of_alias_get_id(pdev->dev.of_node, "gsc");
1086 if (ret < 0)
1087 return ret;
1088
1089 gsc->id = ret;
1090 if (gsc->id >= drv_data->num_entities) {
1091 dev_err(dev, "Invalid platform device id: %d\n", gsc->id);
1092 return -EINVAL;
1093 }
1094
1095 gsc->variant = drv_data->variant[gsc->id];
1096 gsc->pdev = pdev;
1097
1098 init_waitqueue_head(&gsc->irq_queue);
1099 spin_lock_init(&gsc->slock);
1100 mutex_init(&gsc->lock);
1101 gsc->clock = ERR_PTR(-EINVAL);
1102
1103 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1104 gsc->regs = devm_ioremap_resource(dev, res);
1105 if (IS_ERR(gsc->regs))
1106 return PTR_ERR(gsc->regs);
1107
1108 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1109 if (!res) {
1110 dev_err(dev, "failed to get IRQ resource\n");
1111 return -ENXIO;
1112 }
1113
1114 ret = gsc_clk_get(gsc);
1115 if (ret)
1116 return ret;
1117
1118 ret = devm_request_irq(dev, res->start, gsc_irq_handler,
1119 0, pdev->name, gsc);
1120 if (ret) {
1121 dev_err(dev, "failed to install irq (%d)\n", ret);
1122 goto err_clk;
1123 }
1124
1125 ret = v4l2_device_register(dev, &gsc->v4l2_dev);
1126 if (ret)
1127 goto err_clk;
1128
1129 ret = gsc_register_m2m_device(gsc);
1130 if (ret)
1131 goto err_v4l2;
1132
1133 platform_set_drvdata(pdev, gsc);
1134 pm_runtime_enable(dev);
1135 ret = pm_runtime_get_sync(&pdev->dev);
1136 if (ret < 0)
1137 goto err_m2m;
1138
1139 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1140
1141 dev_dbg(dev, "gsc-%d registered successfully\n", gsc->id);
1142
1143 pm_runtime_put(dev);
1144 return 0;
1145
1146 err_m2m:
1147 gsc_unregister_m2m_device(gsc);
1148 err_v4l2:
1149 v4l2_device_unregister(&gsc->v4l2_dev);
1150 err_clk:
1151 gsc_clk_put(gsc);
1152 return ret;
1153 }
1154
1155 static int gsc_remove(struct platform_device *pdev)
1156 {
1157 struct gsc_dev *gsc = platform_get_drvdata(pdev);
1158
1159 gsc_unregister_m2m_device(gsc);
1160 v4l2_device_unregister(&gsc->v4l2_dev);
1161
1162 vb2_dma_contig_clear_max_seg_size(&pdev->dev);
1163 pm_runtime_disable(&pdev->dev);
1164 gsc_clk_put(gsc);
1165
1166 dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name);
1167 return 0;
1168 }
1169
1170 static int gsc_runtime_resume(struct device *dev)
1171 {
1172 struct gsc_dev *gsc = dev_get_drvdata(dev);
1173 int ret = 0;
1174
1175 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
1176
1177 ret = clk_enable(gsc->clock);
1178 if (ret)
1179 return ret;
1180
1181 gsc_hw_set_sw_reset(gsc);
1182 gsc_wait_reset(gsc);
1183
1184 return gsc_m2m_resume(gsc);
1185 }
1186
1187 static int gsc_runtime_suspend(struct device *dev)
1188 {
1189 struct gsc_dev *gsc = dev_get_drvdata(dev);
1190 int ret = 0;
1191
1192 ret = gsc_m2m_suspend(gsc);
1193 if (!ret)
1194 clk_disable(gsc->clock);
1195
1196 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
1197 return ret;
1198 }
1199
1200 static int gsc_resume(struct device *dev)
1201 {
1202 struct gsc_dev *gsc = dev_get_drvdata(dev);
1203 unsigned long flags;
1204
1205 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
1206
1207 /* Do not resume if the device was idle before system suspend */
1208 spin_lock_irqsave(&gsc->slock, flags);
1209 if (!test_and_clear_bit(ST_SUSPEND, &gsc->state) ||
1210 !gsc_m2m_opened(gsc)) {
1211 spin_unlock_irqrestore(&gsc->slock, flags);
1212 return 0;
1213 }
1214 spin_unlock_irqrestore(&gsc->slock, flags);
1215
1216 if (!pm_runtime_suspended(dev))
1217 return gsc_runtime_resume(dev);
1218
1219 return 0;
1220 }
1221
1222 static int gsc_suspend(struct device *dev)
1223 {
1224 struct gsc_dev *gsc = dev_get_drvdata(dev);
1225
1226 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
1227
1228 if (test_and_set_bit(ST_SUSPEND, &gsc->state))
1229 return 0;
1230
1231 if (!pm_runtime_suspended(dev))
1232 return gsc_runtime_suspend(dev);
1233
1234 return 0;
1235 }
1236
1237 static const struct dev_pm_ops gsc_pm_ops = {
1238 .suspend = gsc_suspend,
1239 .resume = gsc_resume,
1240 .runtime_suspend = gsc_runtime_suspend,
1241 .runtime_resume = gsc_runtime_resume,
1242 };
1243
1244 static struct platform_driver gsc_driver = {
1245 .probe = gsc_probe,
1246 .remove = gsc_remove,
1247 .driver = {
1248 .name = GSC_MODULE_NAME,
1249 .pm = &gsc_pm_ops,
1250 .of_match_table = exynos_gsc_match,
1251 }
1252 };
1253
1254 module_platform_driver(gsc_driver);
1255
1256 MODULE_AUTHOR("Hyunwong Kim <khw0178.kim@samsung.com>");
1257 MODULE_DESCRIPTION("Samsung EXYNOS5 Soc series G-Scaler driver");
1258 MODULE_LICENSE("GPL");
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