2 * Marvell camera core structures.
4 * Copyright 2011 Jonathan Corbet corbet@lwn.net
9 #include <linux/list.h>
10 #include <media/v4l2-common.h>
11 #include <media/v4l2-dev.h>
12 #include <media/videobuf2-core.h>
15 * Create our own symbols for the supported buffer modes, but, for now,
16 * base them entirely on which videobuf2 options have been selected.
18 #if defined(CONFIG_VIDEOBUF2_VMALLOC) || defined(CONFIG_VIDEOBUF2_VMALLOC_MODULE)
19 #define MCAM_MODE_VMALLOC 1
22 #if defined(CONFIG_VIDEOBUF2_DMA_CONTIG) || defined(CONFIG_VIDEOBUF2_DMA_CONTIG_MODULE)
23 #define MCAM_MODE_DMA_CONTIG 1
26 #if defined(CONFIG_VIDEOBUF2_DMA_SG) || defined(CONFIG_VIDEOBUF2_DMA_SG_MODULE)
27 #define MCAM_MODE_DMA_SG 1
30 #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
31 !defined(MCAM_MODE_DMA_SG)
32 #error One of the videobuf buffer modes must be selected in the config
37 S_NOTREADY
, /* Not yet initialized */
38 S_IDLE
, /* Just hanging around */
39 S_FLAKED
, /* Some sort of problem */
40 S_STREAMING
, /* Streaming data */
41 S_BUFWAIT
/* streaming requested but no buffers yet */
43 #define MAX_DMA_BUFS 3
46 * Different platforms work best with different buffer modes, so we
47 * let the platform pick.
49 enum mcam_buffer_mode
{
56 * Is a given buffer mode supported by the current kernel configuration?
58 static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode
)
61 #ifdef MCAM_MODE_VMALLOC
64 #ifdef MCAM_MODE_DMA_CONTIG
67 #ifdef MCAM_MODE_DMA_SG
79 struct mcam_frame_state
{
82 unsigned int delivered
;
86 * A description of one of our devices.
87 * Locking: controlled by s_mutex. Certain fields, however, require
88 * the dev_lock spinlock; they are marked as such by comments.
89 * dev_lock is also required for access to device registers.
93 * These fields should be set by the platform code prior to
94 * calling mcam_register().
96 struct i2c_adapter
*i2c_adapter
;
97 unsigned char __iomem
*regs
;
99 struct device
*dev
; /* For messages, dma alloc */
100 unsigned int chip_id
;
101 short int clock_speed
; /* Sensor clock speed, default 30 */
102 short int use_smbus
; /* SMBUS or straight I2c? */
103 enum mcam_buffer_mode buffer_mode
;
105 * Callbacks from the core to the platform code.
107 void (*plat_power_up
) (struct mcam_camera
*cam
);
108 void (*plat_power_down
) (struct mcam_camera
*cam
);
111 * Everything below here is private to the mcam core and
112 * should not be touched by the platform code.
114 struct v4l2_device v4l2_dev
;
115 enum mcam_state state
;
116 unsigned long flags
; /* Buffer status, mainly (dev_lock) */
117 int users
; /* How many open FDs */
119 struct mcam_frame_state frame_state
; /* Frame state counter */
121 * Subsystem structures.
123 struct video_device vdev
;
124 struct v4l2_subdev
*sensor
;
125 unsigned short sensor_addr
;
127 /* Videobuf2 stuff */
128 struct vb2_queue vb_queue
;
129 struct list_head buffers
; /* Available frames */
131 unsigned int nbufs
; /* How many are alloc'd */
132 int next_buf
; /* Next to consume (dev_lock) */
134 /* DMA buffers - vmalloc mode */
135 #ifdef MCAM_MODE_VMALLOC
136 unsigned int dma_buf_size
; /* allocated size */
137 void *dma_bufs
[MAX_DMA_BUFS
]; /* Internal buffer addresses */
138 dma_addr_t dma_handles
[MAX_DMA_BUFS
]; /* Buffer bus addresses */
139 struct tasklet_struct s_tasklet
;
141 unsigned int sequence
; /* Frame sequence number */
142 unsigned int buf_seq
[MAX_DMA_BUFS
]; /* Sequence for individual bufs */
144 /* DMA buffers - DMA modes */
145 struct mcam_vb_buffer
*vb_bufs
[MAX_DMA_BUFS
];
146 struct vb2_alloc_ctx
*vb_alloc_ctx
;
148 /* Mode-specific ops, set at open time */
149 void (*dma_setup
)(struct mcam_camera
*cam
);
150 void (*frame_complete
)(struct mcam_camera
*cam
, int frame
);
152 /* Current operating parameters */
153 u32 sensor_type
; /* Currently ov7670 only */
154 struct v4l2_pix_format pix_format
;
155 enum v4l2_mbus_pixelcode mbus_code
;
158 struct mutex s_mutex
; /* Access to this structure */
163 * Register I/O functions. These are here because the platform code
164 * may legitimately need to mess with the register space.
167 * Device register I/O
169 static inline void mcam_reg_write(struct mcam_camera
*cam
, unsigned int reg
,
172 iowrite32(val
, cam
->regs
+ reg
);
175 static inline unsigned int mcam_reg_read(struct mcam_camera
*cam
,
178 return ioread32(cam
->regs
+ reg
);
182 static inline void mcam_reg_write_mask(struct mcam_camera
*cam
, unsigned int reg
,
183 unsigned int val
, unsigned int mask
)
185 unsigned int v
= mcam_reg_read(cam
, reg
);
187 v
= (v
& ~mask
) | (val
& mask
);
188 mcam_reg_write(cam
, reg
, v
);
191 static inline void mcam_reg_clear_bit(struct mcam_camera
*cam
,
192 unsigned int reg
, unsigned int val
)
194 mcam_reg_write_mask(cam
, reg
, 0, val
);
197 static inline void mcam_reg_set_bit(struct mcam_camera
*cam
,
198 unsigned int reg
, unsigned int val
)
200 mcam_reg_write_mask(cam
, reg
, val
, val
);
204 * Functions for use by platform code.
206 int mccic_register(struct mcam_camera
*cam
);
207 int mccic_irq(struct mcam_camera
*cam
, unsigned int irqs
);
208 void mccic_shutdown(struct mcam_camera
*cam
);
210 void mccic_suspend(struct mcam_camera
*cam
);
211 int mccic_resume(struct mcam_camera
*cam
);
215 * Register definitions for the m88alp01 camera interface. Offsets in bytes
216 * as given in the spec.
218 #define REG_Y0BAR 0x00
219 #define REG_Y1BAR 0x04
220 #define REG_Y2BAR 0x08
223 #define REG_IMGPITCH 0x24 /* Image pitch register */
224 #define IMGP_YP_SHFT 2 /* Y pitch params */
225 #define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
226 #define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
227 #define IMGP_UVP_MASK 0x3ffc0000
228 #define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
229 #define IRQ_EOF0 0x00000001 /* End of frame 0 */
230 #define IRQ_EOF1 0x00000002 /* End of frame 1 */
231 #define IRQ_EOF2 0x00000004 /* End of frame 2 */
232 #define IRQ_SOF0 0x00000008 /* Start of frame 0 */
233 #define IRQ_SOF1 0x00000010 /* Start of frame 1 */
234 #define IRQ_SOF2 0x00000020 /* Start of frame 2 */
235 #define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
236 #define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
237 #define IRQ_TWSIR 0x00020000 /* TWSI read */
238 #define IRQ_TWSIE 0x00040000 /* TWSI error */
239 #define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
240 #define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
241 #define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
242 #define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
243 #define REG_IRQSTAT 0x30 /* IRQ status / clear */
245 #define REG_IMGSIZE 0x34 /* Image size */
246 #define IMGSZ_V_MASK 0x1fff0000
247 #define IMGSZ_V_SHIFT 16
248 #define IMGSZ_H_MASK 0x00003fff
249 #define REG_IMGOFFSET 0x38 /* IMage offset */
251 #define REG_CTRL0 0x3c /* Control 0 */
252 #define C0_ENABLE 0x00000001 /* Makes the whole thing go */
254 /* Mask for all the format bits */
255 #define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
258 #define C0_RGB4_RGBX 0x00000000
259 #define C0_RGB4_XRGB 0x00000004
260 #define C0_RGB4_BGRX 0x00000008
261 #define C0_RGB4_XBGR 0x0000000c
262 #define C0_RGB5_RGGB 0x00000000
263 #define C0_RGB5_GRBG 0x00000004
264 #define C0_RGB5_GBRG 0x00000008
265 #define C0_RGB5_BGGR 0x0000000c
267 /* Spec has two fields for DIN and DOUT, but they must match, so
268 combine them here. */
269 #define C0_DF_YUV 0x00000000 /* Data is YUV */
270 #define C0_DF_RGB 0x000000a0 /* ... RGB */
271 #define C0_DF_BAYER 0x00000140 /* ... Bayer */
272 /* 8-8-8 must be missing from the below - ask */
273 #define C0_RGBF_565 0x00000000
274 #define C0_RGBF_444 0x00000800
275 #define C0_RGB_BGR 0x00001000 /* Blue comes first */
276 #define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
277 #define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
278 #define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
279 /* Think that 420 packed must be 111 - ask */
280 #define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
281 #define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
282 #define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
283 #define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
284 #define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
285 #define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
286 #define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
287 #define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
288 /* Bayer bits 18,19 if needed */
289 #define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
290 #define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
291 #define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
292 #define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
293 #define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
294 #define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
295 #define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
297 /* Bits below C1_444ALPHA are not present in Cafe */
298 #define REG_CTRL1 0x40 /* Control 1 */
299 #define C1_CLKGATE 0x00000001 /* Sensor clock gate */
300 #define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */
301 #define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */
302 #define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
303 #define C1_ALPHA_SHFT 20
304 #define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
305 #define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
306 #define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
307 #define C1_DMAB_MASK 0x06000000
308 #define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
309 #define C1_PWRDWN 0x10000000 /* Power down */
311 #define REG_CLKCTRL 0x88 /* Clock control */
312 #define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
314 /* This appears to be a Cafe-only register */
315 #define REG_UBAR 0xc4 /* Upper base address register */
317 /* Armada 610 DMA descriptor registers */
318 #define REG_DMA_DESC_Y 0x200
319 #define REG_DMA_DESC_U 0x204
320 #define REG_DMA_DESC_V 0x208
321 #define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */
322 #define REG_DESC_LEN_U 0x210
323 #define REG_DESC_LEN_V 0x214
326 * Useful stuff that probably belongs somewhere global.
328 #define VGA_WIDTH 640
329 #define VGA_HEIGHT 480
331 #endif /* _MCAM_CORE_H */