drivers/media/platform/omap3isp/ispcsi2.c

   1 /*
   2  * ispcsi2.c
   3  *
   4  * TI OMAP3 ISP - CSI2 module
   5  *
   6  * Copyright (C) 2010 Nokia Corporation
   7  * Copyright (C) 2009 Texas Instruments, Inc.
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #include <linux/delay.h>
  17 #include <media/v4l2-common.h>
  18 #include <linux/v4l2-mediabus.h>
  19 #include <linux/mm.h>
  20
  21 #include "isp.h"
  22 #include "ispreg.h"
  23 #include "ispcsi2.h"
  24
  25 /*
  26  * csi2_if_enable - Enable CSI2 Receiver interface.
  27  * @enable: enable flag
  28  *
  29  */
  30 static void csi2_if_enable(struct isp_device *isp,
  31                            struct isp_csi2_device *csi2, u8 enable)
  32 {
  33         struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
  34
  35         isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN,
  36                         enable ? ISPCSI2_CTRL_IF_EN : 0);
  37
  38         currctrl->if_enable = enable;
  39 }
  40
  41 /*
  42  * csi2_recv_config - CSI2 receiver module configuration.
  43  * @currctrl: isp_csi2_ctrl_cfg structure
  44  *
  45  */
  46 static void csi2_recv_config(struct isp_device *isp,
  47                              struct isp_csi2_device *csi2,
  48                              struct isp_csi2_ctrl_cfg *currctrl)
  49 {
  50         u32 reg;
  51
  52         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
  53
  54         if (currctrl->frame_mode)
  55                 reg |= ISPCSI2_CTRL_FRAME;
  56         else
  57                 reg &= ~ISPCSI2_CTRL_FRAME;
  58
  59         if (currctrl->vp_clk_enable)
  60                 reg |= ISPCSI2_CTRL_VP_CLK_EN;
  61         else
  62                 reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
  63
  64         if (currctrl->vp_only_enable)
  65                 reg |= ISPCSI2_CTRL_VP_ONLY_EN;
  66         else
  67                 reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
  68
  69         reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
  70         reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
  71
  72         if (currctrl->ecc_enable)
  73                 reg |= ISPCSI2_CTRL_ECC_EN;
  74         else
  75                 reg &= ~ISPCSI2_CTRL_ECC_EN;
  76
  77         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
  78 }
  79
  80 static const unsigned int csi2_input_fmts[] = {
  81         MEDIA_BUS_FMT_SGRBG10_1X10,
  82         MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  83         MEDIA_BUS_FMT_SRGGB10_1X10,
  84         MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
  85         MEDIA_BUS_FMT_SBGGR10_1X10,
  86         MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
  87         MEDIA_BUS_FMT_SGBRG10_1X10,
  88         MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
  89         MEDIA_BUS_FMT_YUYV8_2X8,
  90 };
  91
  92 /* To set the format on the CSI2 requires a mapping function that takes
  93  * the following inputs:
  94  * - 3 different formats (at this time)
  95  * - 2 destinations (mem, vp+mem) (vp only handled separately)
  96  * - 2 decompression options (on, off)
  97  * - 2 isp revisions (certain format must be handled differently on OMAP3630)
  98  * Output should be CSI2 frame format code
  99  * Array indices as follows: [format][dest][decompr][is_3630]
 100  * Not all combinations are valid. 0 means invalid.
 101  */
 102 static const u16 __csi2_fmt_map[3][2][2][2] = {
 103         /* RAW10 formats */
 104         {
 105                 /* Output to memory */
 106                 {
 107                         /* No DPCM decompression */
 108                         { CSI2_PIX_FMT_RAW10_EXP16, CSI2_PIX_FMT_RAW10_EXP16 },
 109                         /* DPCM decompression */
 110                         { 0, 0 },
 111                 },
 112                 /* Output to both */
 113                 {
 114                         /* No DPCM decompression */
 115                         { CSI2_PIX_FMT_RAW10_EXP16_VP,
 116                           CSI2_PIX_FMT_RAW10_EXP16_VP },
 117                         /* DPCM decompression */
 118                         { 0, 0 },
 119                 },
 120         },
 121         /* RAW10 DPCM8 formats */
 122         {
 123                 /* Output to memory */
 124                 {
 125                         /* No DPCM decompression */
 126                         { CSI2_PIX_FMT_RAW8, CSI2_USERDEF_8BIT_DATA1 },
 127                         /* DPCM decompression */
 128                         { CSI2_PIX_FMT_RAW8_DPCM10_EXP16,
 129                           CSI2_USERDEF_8BIT_DATA1_DPCM10 },
 130                 },
 131                 /* Output to both */
 132                 {
 133                         /* No DPCM decompression */
 134                         { CSI2_PIX_FMT_RAW8_VP,
 135                           CSI2_PIX_FMT_RAW8_VP },
 136                         /* DPCM decompression */
 137                         { CSI2_PIX_FMT_RAW8_DPCM10_VP,
 138                           CSI2_USERDEF_8BIT_DATA1_DPCM10_VP },
 139                 },
 140         },
 141         /* YUYV8 2X8 formats */
 142         {
 143                 /* Output to memory */
 144                 {
 145                         /* No DPCM decompression */
 146                         { CSI2_PIX_FMT_YUV422_8BIT,
 147                           CSI2_PIX_FMT_YUV422_8BIT },
 148                         /* DPCM decompression */
 149                         { 0, 0 },
 150                 },
 151                 /* Output to both */
 152                 {
 153                         /* No DPCM decompression */
 154                         { CSI2_PIX_FMT_YUV422_8BIT_VP,
 155                           CSI2_PIX_FMT_YUV422_8BIT_VP },
 156                         /* DPCM decompression */
 157                         { 0, 0 },
 158                 },
 159         },
 160 };
 161
 162 /*
 163  * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
 164  * @csi2: ISP CSI2 device
 165  *
 166  * Returns CSI2 physical format id
 167  */
 168 static u16 csi2_ctx_map_format(struct isp_csi2_device *csi2)
 169 {
 170         const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
 171         int fmtidx, destidx, is_3630;
 172
 173         switch (fmt->code) {
 174         case MEDIA_BUS_FMT_SGRBG10_1X10:
 175         case MEDIA_BUS_FMT_SRGGB10_1X10:
 176         case MEDIA_BUS_FMT_SBGGR10_1X10:
 177         case MEDIA_BUS_FMT_SGBRG10_1X10:
 178                 fmtidx = 0;
 179                 break;
 180         case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
 181         case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
 182         case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
 183         case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
 184                 fmtidx = 1;
 185                 break;
 186         case MEDIA_BUS_FMT_YUYV8_2X8:
 187                 fmtidx = 2;
 188                 break;
 189         default:
 190                 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
 191                      fmt->code);
 192                 return 0;
 193         }
 194
 195         if (!(csi2->output & CSI2_OUTPUT_CCDC) &&
 196             !(csi2->output & CSI2_OUTPUT_MEMORY)) {
 197                 /* Neither output enabled is a valid combination */
 198                 return CSI2_PIX_FMT_OTHERS;
 199         }
 200
 201         /* If we need to skip frames at the beginning of the stream disable the
 202          * video port to avoid sending the skipped frames to the CCDC.
 203          */
 204         destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_CCDC);
 205         is_3630 = csi2->isp->revision == ISP_REVISION_15_0;
 206
 207         return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress][is_3630];
 208 }
 209
 210 /*
 211  * csi2_set_outaddr - Set memory address to save output image
 212  * @csi2: Pointer to ISP CSI2a device.
 213  * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
 214  *
 215  * Sets the memory address where the output will be saved.
 216  *
 217  * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
 218  * boundary.
 219  */
 220 static void csi2_set_outaddr(struct isp_csi2_device *csi2, u32 addr)
 221 {
 222         struct isp_device *isp = csi2->isp;
 223         struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0];
 224
 225         ctx->ping_addr = addr;
 226         ctx->pong_addr = addr;
 227         isp_reg_writel(isp, ctx->ping_addr,
 228                        csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
 229         isp_reg_writel(isp, ctx->pong_addr,
 230                        csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
 231 }
 232
 233 /*
 234  * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
 235  *                      be enabled by CSI2.
 236  * @format_id: mapped format id
 237  *
 238  */
 239 static inline int is_usr_def_mapping(u32 format_id)
 240 {
 241         return (format_id & 0x40) ? 1 : 0;
 242 }
 243
 244 /*
 245  * csi2_ctx_enable - Enable specified CSI2 context
 246  * @ctxnum: Context number, valid between 0 and 7 values.
 247  * @enable: enable
 248  *
 249  */
 250 static void csi2_ctx_enable(struct isp_device *isp,
 251                             struct isp_csi2_device *csi2, u8 ctxnum, u8 enable)
 252 {
 253         struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
 254         unsigned int skip = 0;
 255         u32 reg;
 256
 257         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
 258
 259         if (enable) {
 260                 if (csi2->frame_skip)
 261                         skip = csi2->frame_skip;
 262                 else if (csi2->output & CSI2_OUTPUT_MEMORY)
 263                         skip = 1;
 264
 265                 reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
 266                 reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
 267                     |  (skip << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
 268                     |  ISPCSI2_CTX_CTRL1_CTX_EN;
 269         } else {
 270                 reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
 271         }
 272
 273         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
 274         ctx->enabled = enable;
 275 }
 276
 277 /*
 278  * csi2_ctx_config - CSI2 context configuration.
 279  * @ctx: context configuration
 280  *
 281  */
 282 static void csi2_ctx_config(struct isp_device *isp,
 283                             struct isp_csi2_device *csi2,
 284                             struct isp_csi2_ctx_cfg *ctx)
 285 {
 286         u32 reg;
 287
 288         /* Set up CSI2_CTx_CTRL1 */
 289         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
 290
 291         if (ctx->eof_enabled)
 292                 reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
 293         else
 294                 reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
 295
 296         if (ctx->eol_enabled)
 297                 reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
 298         else
 299                 reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
 300
 301         if (ctx->checksum_enabled)
 302                 reg |= ISPCSI2_CTX_CTRL1_CS_EN;
 303         else
 304                 reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
 305
 306         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
 307
 308         /* Set up CSI2_CTx_CTRL2 */
 309         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
 310
 311         reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
 312         reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
 313
 314         reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
 315         reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
 316
 317         if (ctx->dpcm_decompress) {
 318                 if (ctx->dpcm_predictor)
 319                         reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
 320                 else
 321                         reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
 322         }
 323
 324         if (is_usr_def_mapping(ctx->format_id)) {
 325                 reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
 326                 reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
 327         }
 328
 329         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
 330
 331         /* Set up CSI2_CTx_CTRL3 */
 332         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
 333         reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
 334         reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
 335
 336         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
 337
 338         /* Set up CSI2_CTx_DAT_OFST */
 339         reg = isp_reg_readl(isp, csi2->regs1,
 340                             ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
 341         reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
 342         reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
 343         isp_reg_writel(isp, reg, csi2->regs1,
 344                        ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
 345
 346         isp_reg_writel(isp, ctx->ping_addr,
 347                        csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
 348
 349         isp_reg_writel(isp, ctx->pong_addr,
 350                        csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
 351 }
 352
 353 /*
 354  * csi2_timing_config - CSI2 timing configuration.
 355  * @timing: csi2_timing_cfg structure
 356  */
 357 static void csi2_timing_config(struct isp_device *isp,
 358                                struct isp_csi2_device *csi2,
 359                                struct isp_csi2_timing_cfg *timing)
 360 {
 361         u32 reg;
 362
 363         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
 364
 365         if (timing->force_rx_mode)
 366                 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
 367         else
 368                 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
 369
 370         if (timing->stop_state_16x)
 371                 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
 372         else
 373                 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
 374
 375         if (timing->stop_state_4x)
 376                 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
 377         else
 378                 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
 379
 380         reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
 381         reg |= timing->stop_state_counter <<
 382                ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
 383
 384         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
 385 }
 386
 387 /*
 388  * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
 389  * @enable: Enable/disable CSI2 Context interrupts
 390  */
 391 static void csi2_irq_ctx_set(struct isp_device *isp,
 392                              struct isp_csi2_device *csi2, int enable)
 393 {
 394         int i;
 395
 396         for (i = 0; i < 8; i++) {
 397                 isp_reg_writel(isp, ISPCSI2_CTX_IRQSTATUS_FE_IRQ, csi2->regs1,
 398                                ISPCSI2_CTX_IRQSTATUS(i));
 399                 if (enable)
 400                         isp_reg_set(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
 401                                     ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
 402                 else
 403                         isp_reg_clr(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
 404                                     ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
 405         }
 406 }
 407
 408 /*
 409  * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
 410  * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
 411  */
 412 static void csi2_irq_complexio1_set(struct isp_device *isp,
 413                                     struct isp_csi2_device *csi2, int enable)
 414 {
 415         u32 reg;
 416         reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
 417                 ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER |
 418                 ISPCSI2_PHY_IRQENABLE_STATEULPM5 |
 419                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 |
 420                 ISPCSI2_PHY_IRQENABLE_ERRESC5 |
 421                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 |
 422                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 |
 423                 ISPCSI2_PHY_IRQENABLE_STATEULPM4 |
 424                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 |
 425                 ISPCSI2_PHY_IRQENABLE_ERRESC4 |
 426                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 |
 427                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 |
 428                 ISPCSI2_PHY_IRQENABLE_STATEULPM3 |
 429                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 |
 430                 ISPCSI2_PHY_IRQENABLE_ERRESC3 |
 431                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 |
 432                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 |
 433                 ISPCSI2_PHY_IRQENABLE_STATEULPM2 |
 434                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 |
 435                 ISPCSI2_PHY_IRQENABLE_ERRESC2 |
 436                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 |
 437                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 |
 438                 ISPCSI2_PHY_IRQENABLE_STATEULPM1 |
 439                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 |
 440                 ISPCSI2_PHY_IRQENABLE_ERRESC1 |
 441                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 |
 442                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS1;
 443         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
 444         if (enable)
 445                 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
 446         else
 447                 reg = 0;
 448         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
 449 }
 450
 451 /*
 452  * csi2_irq_status_set - Enables CSI2 Status IRQs.
 453  * @enable: Enable/disable CSI2 Status interrupts
 454  */
 455 static void csi2_irq_status_set(struct isp_device *isp,
 456                                 struct isp_csi2_device *csi2, int enable)
 457 {
 458         u32 reg;
 459         reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
 460                 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
 461                 ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
 462                 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
 463                 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
 464                 ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
 465                 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
 466                 ISPCSI2_IRQSTATUS_CONTEXT(0);
 467         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
 468         if (enable)
 469                 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
 470         else
 471                 reg = 0;
 472
 473         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
 474 }
 475
 476 /*
 477  * omap3isp_csi2_reset - Resets the CSI2 module.
 478  *
 479  * Must be called with the phy lock held.
 480  *
 481  * Returns 0 if successful, or -EBUSY if power command didn't respond.
 482  */
 483 int omap3isp_csi2_reset(struct isp_csi2_device *csi2)
 484 {
 485         struct isp_device *isp = csi2->isp;
 486         u8 soft_reset_retries = 0;
 487         u32 reg;
 488         int i;
 489
 490         if (!csi2->available)
 491                 return -ENODEV;
 492
 493         if (csi2->phy->entity)
 494                 return -EBUSY;
 495
 496         isp_reg_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
 497                     ISPCSI2_SYSCONFIG_SOFT_RESET);
 498
 499         do {
 500                 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
 501                                     ISPCSI2_SYSSTATUS_RESET_DONE;
 502                 if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
 503                         break;
 504                 soft_reset_retries++;
 505                 if (soft_reset_retries < 5)
 506                         udelay(100);
 507         } while (soft_reset_retries < 5);
 508
 509         if (soft_reset_retries == 5) {
 510                 dev_err(isp->dev, "CSI2: Soft reset try count exceeded!\n");
 511                 return -EBUSY;
 512         }
 513
 514         if (isp->revision == ISP_REVISION_15_0)
 515                 isp_reg_set(isp, csi2->regs1, ISPCSI2_PHY_CFG,
 516                             ISPCSI2_PHY_CFG_RESET_CTRL);
 517
 518         i = 100;
 519         do {
 520                 reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
 521                     & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK;
 522                 if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)
 523                         break;
 524                 udelay(100);
 525         } while (--i > 0);
 526
 527         if (i == 0) {
 528                 dev_err(isp->dev,
 529                         "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
 530                 return -EBUSY;
 531         }
 532
 533         if (isp->autoidle)
 534                 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
 535                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 536                                 ISPCSI2_SYSCONFIG_AUTO_IDLE,
 537                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART |
 538                                 ((isp->revision == ISP_REVISION_15_0) ?
 539                                  ISPCSI2_SYSCONFIG_AUTO_IDLE : 0));
 540         else
 541                 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
 542                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 543                                 ISPCSI2_SYSCONFIG_AUTO_IDLE,
 544                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO);
 545
 546         return 0;
 547 }
 548
 549 static int csi2_configure(struct isp_csi2_device *csi2)
 550 {
 551         struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
 552         const struct isp_bus_cfg *buscfg;
 553         struct isp_device *isp = csi2->isp;
 554         struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
 555         struct v4l2_subdev *sensor;
 556         struct media_pad *pad;
 557
 558         /*
 559          * CSI2 fields that can be updated while the context has
 560          * been enabled or the interface has been enabled are not
 561          * updated dynamically currently. So we do not allow to
 562          * reconfigure if either has been enabled
 563          */
 564         if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
 565                 return -EBUSY;
 566
 567         pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
 568         sensor = media_entity_to_v4l2_subdev(pad->entity);
 569         buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
 570
 571         csi2->frame_skip = 0;
 572         v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
 573
 574         csi2->ctrl.vp_out_ctrl =
 575                 clamp_t(unsigned int, pipe->l3_ick / pipe->external_rate - 1,
 576                         1, 3);
 577         dev_dbg(isp->dev, "%s: l3_ick %lu, external_rate %u, vp_out_ctrl %u\n",
 578                 __func__, pipe->l3_ick,  pipe->external_rate,
 579                 csi2->ctrl.vp_out_ctrl);
 580         csi2->ctrl.frame_mode = ISP_CSI2_FRAME_IMMEDIATE;
 581         csi2->ctrl.ecc_enable = buscfg->bus.csi2.crc;
 582
 583         timing->ionum = 1;
 584         timing->force_rx_mode = 1;
 585         timing->stop_state_16x = 1;
 586         timing->stop_state_4x = 1;
 587         timing->stop_state_counter = 0x1FF;
 588
 589         /*
 590          * The CSI2 receiver can't do any format conversion except DPCM
 591          * decompression, so every set_format call configures both pads
 592          * and enables DPCM decompression as a special case:
 593          */
 594         if (csi2->formats[CSI2_PAD_SINK].code !=
 595             csi2->formats[CSI2_PAD_SOURCE].code)
 596                 csi2->dpcm_decompress = true;
 597         else
 598                 csi2->dpcm_decompress = false;
 599
 600         csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
 601
 602         if (csi2->video_out.bpl_padding == 0)
 603                 csi2->contexts[0].data_offset = 0;
 604         else
 605                 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
 606
 607         /*
 608          * Enable end of frame and end of line signals generation for
 609          * context 0. These signals are generated from CSI2 receiver to
 610          * qualify the last pixel of a frame and the last pixel of a line.
 611          * Without enabling the signals CSI2 receiver writes data to memory
 612          * beyond buffer size and/or data line offset is not handled correctly.
 613          */
 614         csi2->contexts[0].eof_enabled = 1;
 615         csi2->contexts[0].eol_enabled = 1;
 616
 617         csi2_irq_complexio1_set(isp, csi2, 1);
 618         csi2_irq_ctx_set(isp, csi2, 1);
 619         csi2_irq_status_set(isp, csi2, 1);
 620
 621         /* Set configuration (timings, format and links) */
 622         csi2_timing_config(isp, csi2, timing);
 623         csi2_recv_config(isp, csi2, &csi2->ctrl);
 624         csi2_ctx_config(isp, csi2, &csi2->contexts[0]);
 625
 626         return 0;
 627 }
 628
 629 /*
 630  * csi2_print_status - Prints CSI2 debug information.
 631  */
 632 #define CSI2_PRINT_REGISTER(isp, regs, name)\
 633         dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
 634                 isp_reg_readl(isp, regs, ISPCSI2_##name))
 635
 636 static void csi2_print_status(struct isp_csi2_device *csi2)
 637 {
 638         struct isp_device *isp = csi2->isp;
 639
 640         if (!csi2->available)
 641                 return;
 642
 643         dev_dbg(isp->dev, "-------------CSI2 Register dump-------------\n");
 644
 645         CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSCONFIG);
 646         CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSSTATUS);
 647         CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQENABLE);
 648         CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQSTATUS);
 649         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTRL);
 650         CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_H);
 651         CSI2_PRINT_REGISTER(isp, csi2->regs1, GNQ);
 652         CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_CFG);
 653         CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQSTATUS);
 654         CSI2_PRINT_REGISTER(isp, csi2->regs1, SHORT_PACKET);
 655         CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQENABLE);
 656         CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_P);
 657         CSI2_PRINT_REGISTER(isp, csi2->regs1, TIMING);
 658         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL1(0));
 659         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL2(0));
 660         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_OFST(0));
 661         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PING_ADDR(0));
 662         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PONG_ADDR(0));
 663         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQENABLE(0));
 664         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQSTATUS(0));
 665         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL3(0));
 666
 667         dev_dbg(isp->dev, "--------------------------------------------\n");
 668 }
 669
 670 /* -----------------------------------------------------------------------------
 671  * Interrupt handling
 672  */
 673
 674 /*
 675  * csi2_isr_buffer - Does buffer handling at end-of-frame
 676  * when writing to memory.
 677  */
 678 static void csi2_isr_buffer(struct isp_csi2_device *csi2)
 679 {
 680         struct isp_device *isp = csi2->isp;
 681         struct isp_buffer *buffer;
 682
 683         csi2_ctx_enable(isp, csi2, 0, 0);
 684
 685         buffer = omap3isp_video_buffer_next(&csi2->video_out);
 686
 687         /*
 688          * Let video queue operation restart engine if there is an underrun
 689          * condition.
 690          */
 691         if (buffer == NULL)
 692                 return;
 693
 694         csi2_set_outaddr(csi2, buffer->dma);
 695         csi2_ctx_enable(isp, csi2, 0, 1);
 696 }
 697
 698 static void csi2_isr_ctx(struct isp_csi2_device *csi2,
 699                          struct isp_csi2_ctx_cfg *ctx)
 700 {
 701         struct isp_device *isp = csi2->isp;
 702         unsigned int n = ctx->ctxnum;
 703         u32 status;
 704
 705         status = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
 706         isp_reg_writel(isp, status, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
 707
 708         if (!(status & ISPCSI2_CTX_IRQSTATUS_FE_IRQ))
 709                 return;
 710
 711         /* Skip interrupts until we reach the frame skip count. The CSI2 will be
 712          * automatically disabled, as the frame skip count has been programmed
 713          * in the CSI2_CTx_CTRL1::COUNT field, so re-enable it.
 714          *
 715          * It would have been nice to rely on the FRAME_NUMBER interrupt instead
 716          * but it turned out that the interrupt is only generated when the CSI2
 717          * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
 718          * correctly and reaches 0 when data is forwarded to the video port only
 719          * but no interrupt arrives). Maybe a CSI2 hardware bug.
 720          */
 721         if (csi2->frame_skip) {
 722                 csi2->frame_skip--;
 723                 if (csi2->frame_skip == 0) {
 724                         ctx->format_id = csi2_ctx_map_format(csi2);
 725                         csi2_ctx_config(isp, csi2, ctx);
 726                         csi2_ctx_enable(isp, csi2, n, 1);
 727                 }
 728                 return;
 729         }
 730
 731         if (csi2->output & CSI2_OUTPUT_MEMORY)
 732                 csi2_isr_buffer(csi2);
 733 }
 734
 735 /*
 736  * omap3isp_csi2_isr - CSI2 interrupt handling.
 737  */
 738 void omap3isp_csi2_isr(struct isp_csi2_device *csi2)
 739 {
 740         struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
 741         u32 csi2_irqstatus, cpxio1_irqstatus;
 742         struct isp_device *isp = csi2->isp;
 743
 744         if (!csi2->available)
 745                 return;
 746
 747         csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS);
 748         isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS);
 749
 750         /* Failure Cases */
 751         if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
 752                 cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1,
 753                                                  ISPCSI2_PHY_IRQSTATUS);
 754                 isp_reg_writel(isp, cpxio1_irqstatus,
 755                                csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
 756                 dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ %x\n",
 757                         cpxio1_irqstatus);
 758                 pipe->error = true;
 759         }
 760
 761         if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
 762                               ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
 763                               ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
 764                               ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
 765                               ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) {
 766                 dev_dbg(isp->dev,
 767                         "CSI2 Err: OCP:%d, Short_pack:%d, ECC:%d, CPXIO2:%d, FIFO_OVF:%d,\n",
 768                         (csi2_irqstatus &
 769                          ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0,
 770                         (csi2_irqstatus &
 771                          ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0,
 772                         (csi2_irqstatus &
 773                          ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0,
 774                         (csi2_irqstatus &
 775                          ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0,
 776                         (csi2_irqstatus &
 777                          ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0);
 778                 pipe->error = true;
 779         }
 780
 781         if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
 782                 return;
 783
 784         /* Successful cases */
 785         if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0))
 786                 csi2_isr_ctx(csi2, &csi2->contexts[0]);
 787
 788         if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
 789                 dev_dbg(isp->dev, "CSI2: ECC correction done\n");
 790 }
 791
 792 /* -----------------------------------------------------------------------------
 793  * ISP video operations
 794  */
 795
 796 /*
 797  * csi2_queue - Queues the first buffer when using memory output
 798  * @video: The video node
 799  * @buffer: buffer to queue
 800  */
 801 static int csi2_queue(struct isp_video *video, struct isp_buffer *buffer)
 802 {
 803         struct isp_device *isp = video->isp;
 804         struct isp_csi2_device *csi2 = &isp->isp_csi2a;
 805
 806         csi2_set_outaddr(csi2, buffer->dma);
 807
 808         /*
 809          * If streaming was enabled before there was a buffer queued
 810          * or underrun happened in the ISR, the hardware was not enabled
 811          * and DMA queue flag ISP_VIDEO_DMAQUEUE_UNDERRUN is still set.
 812          * Enable it now.
 813          */
 814         if (csi2->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
 815                 /* Enable / disable context 0 and IRQs */
 816                 csi2_if_enable(isp, csi2, 1);
 817                 csi2_ctx_enable(isp, csi2, 0, 1);
 818                 isp_video_dmaqueue_flags_clr(&csi2->video_out);
 819         }
 820
 821         return 0;
 822 }
 823
 824 static const struct isp_video_operations csi2_ispvideo_ops = {
 825         .queue = csi2_queue,
 826 };
 827
 828 /* -----------------------------------------------------------------------------
 829  * V4L2 subdev operations
 830  */
 831
 832 static struct v4l2_mbus_framefmt *
 833 __csi2_get_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
 834                   unsigned int pad, enum v4l2_subdev_format_whence which)
 835 {
 836         if (which == V4L2_SUBDEV_FORMAT_TRY)
 837                 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
 838         else
 839                 return &csi2->formats[pad];
 840 }
 841
 842 static void
 843 csi2_try_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
 844                 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
 845                 enum v4l2_subdev_format_whence which)
 846 {
 847         u32 pixelcode;
 848         struct v4l2_mbus_framefmt *format;
 849         const struct isp_format_info *info;
 850         unsigned int i;
 851
 852         switch (pad) {
 853         case CSI2_PAD_SINK:
 854                 /* Clamp the width and height to valid range (1-8191). */
 855                 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
 856                         if (fmt->code == csi2_input_fmts[i])
 857                                 break;
 858                 }
 859
 860                 /* If not found, use SGRBG10 as default */
 861                 if (i >= ARRAY_SIZE(csi2_input_fmts))
 862                         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 863
 864                 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
 865                 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
 866                 break;
 867
 868         case CSI2_PAD_SOURCE:
 869                 /* Source format same as sink format, except for DPCM
 870                  * compression.
 871                  */
 872                 pixelcode = fmt->code;
 873                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
 874                 memcpy(fmt, format, sizeof(*fmt));
 875
 876                 /*
 877                  * Only Allow DPCM decompression, and check that the
 878                  * pattern is preserved
 879                  */
 880                 info = omap3isp_video_format_info(fmt->code);
 881                 if (info->uncompressed == pixelcode)
 882                         fmt->code = pixelcode;
 883                 break;
 884         }
 885
 886         /* RGB, non-interlaced */
 887         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 888         fmt->field = V4L2_FIELD_NONE;
 889 }
 890
 891 /*
 892  * csi2_enum_mbus_code - Handle pixel format enumeration
 893  * @sd     : pointer to v4l2 subdev structure
 894  * @cfg: V4L2 subdev pad configuration
 895  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 896  * return -EINVAL or zero on success
 897  */
 898 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
 899                                struct v4l2_subdev_pad_config *cfg,
 900                                struct v4l2_subdev_mbus_code_enum *code)
 901 {
 902         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 903         struct v4l2_mbus_framefmt *format;
 904         const struct isp_format_info *info;
 905
 906         if (code->pad == CSI2_PAD_SINK) {
 907                 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
 908                         return -EINVAL;
 909
 910                 code->code = csi2_input_fmts[code->index];
 911         } else {
 912                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
 913                                            code->which);
 914                 switch (code->index) {
 915                 case 0:
 916                         /* Passthrough sink pad code */
 917                         code->code = format->code;
 918                         break;
 919                 case 1:
 920                         /* Uncompressed code */
 921                         info = omap3isp_video_format_info(format->code);
 922                         if (info->uncompressed == format->code)
 923                                 return -EINVAL;
 924
 925                         code->code = info->uncompressed;
 926                         break;
 927                 default:
 928                         return -EINVAL;
 929                 }
 930         }
 931
 932         return 0;
 933 }
 934
 935 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
 936                                 struct v4l2_subdev_pad_config *cfg,
 937                                 struct v4l2_subdev_frame_size_enum *fse)
 938 {
 939         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 940         struct v4l2_mbus_framefmt format;
 941
 942         if (fse->index != 0)
 943                 return -EINVAL;
 944
 945         format.code = fse->code;
 946         format.width = 1;
 947         format.height = 1;
 948         csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
 949         fse->min_width = format.width;
 950         fse->min_height = format.height;
 951
 952         if (format.code != fse->code)
 953                 return -EINVAL;
 954
 955         format.code = fse->code;
 956         format.width = -1;
 957         format.height = -1;
 958         csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
 959         fse->max_width = format.width;
 960         fse->max_height = format.height;
 961
 962         return 0;
 963 }
 964
 965 /*
 966  * csi2_get_format - Handle get format by pads subdev method
 967  * @sd : pointer to v4l2 subdev structure
 968  * @cfg: V4L2 subdev pad configuration
 969  * @fmt: pointer to v4l2 subdev format structure
 970  * return -EINVAL or zero on success
 971  */
 972 static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
 973                            struct v4l2_subdev_format *fmt)
 974 {
 975         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 976         struct v4l2_mbus_framefmt *format;
 977
 978         format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
 979         if (format == NULL)
 980                 return -EINVAL;
 981
 982         fmt->format = *format;
 983         return 0;
 984 }
 985
 986 /*
 987  * csi2_set_format - Handle set format by pads subdev method
 988  * @sd : pointer to v4l2 subdev structure
 989  * @cfg: V4L2 subdev pad configuration
 990  * @fmt: pointer to v4l2 subdev format structure
 991  * return -EINVAL or zero on success
 992  */
 993 static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
 994                            struct v4l2_subdev_format *fmt)
 995 {
 996         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 997         struct v4l2_mbus_framefmt *format;
 998
 999         format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
1000         if (format == NULL)
1001                 return -EINVAL;
1002
1003         csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
1004         *format = fmt->format;
1005
1006         /* Propagate the format from sink to source */
1007         if (fmt->pad == CSI2_PAD_SINK) {
1008                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
1009                                            fmt->which);
1010                 *format = fmt->format;
1011                 csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
1012         }
1013
1014         return 0;
1015 }
1016
1017 /*
1018  * csi2_init_formats - Initialize formats on all pads
1019  * @sd: ISP CSI2 V4L2 subdevice
1020  * @fh: V4L2 subdev file handle
1021  *
1022  * Initialize all pad formats with default values. If fh is not NULL, try
1023  * formats are initialized on the file handle. Otherwise active formats are
1024  * initialized on the device.
1025  */
1026 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1027 {
1028         struct v4l2_subdev_format format;
1029
1030         memset(&format, 0, sizeof(format));
1031         format.pad = CSI2_PAD_SINK;
1032         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1033         format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1034         format.format.width = 4096;
1035         format.format.height = 4096;
1036         csi2_set_format(sd, fh ? fh->pad : NULL, &format);
1037
1038         return 0;
1039 }
1040
1041 /*
1042  * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1043  * @sd: ISP CSI2 V4L2 subdevice
1044  * @enable: ISP pipeline stream state
1045  *
1046  * Return 0 on success or a negative error code otherwise.
1047  */
1048 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1049 {
1050         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1051         struct isp_device *isp = csi2->isp;
1052         struct isp_video *video_out = &csi2->video_out;
1053
1054         switch (enable) {
1055         case ISP_PIPELINE_STREAM_CONTINUOUS:
1056                 if (omap3isp_csiphy_acquire(csi2->phy, &sd->entity) < 0)
1057                         return -ENODEV;
1058                 if (csi2->output & CSI2_OUTPUT_MEMORY)
1059                         omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1060                 csi2_configure(csi2);
1061                 csi2_print_status(csi2);
1062
1063                 /*
1064                  * When outputting to memory with no buffer available, let the
1065                  * buffer queue handler start the hardware. A DMA queue flag
1066                  * ISP_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1067                  * a buffer available.
1068                  */
1069                 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1070                     !(video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED))
1071                         break;
1072                 /* Enable context 0 and IRQs */
1073                 atomic_set(&csi2->stopping, 0);
1074                 csi2_ctx_enable(isp, csi2, 0, 1);
1075                 csi2_if_enable(isp, csi2, 1);
1076                 isp_video_dmaqueue_flags_clr(video_out);
1077                 break;
1078
1079         case ISP_PIPELINE_STREAM_STOPPED:
1080                 if (csi2->state == ISP_PIPELINE_STREAM_STOPPED)
1081                         return 0;
1082                 if (omap3isp_module_sync_idle(&sd->entity, &csi2->wait,
1083                                               &csi2->stopping))
1084                         dev_dbg(isp->dev, "%s: module stop timeout.\n",
1085                                 sd->name);
1086                 csi2_ctx_enable(isp, csi2, 0, 0);
1087                 csi2_if_enable(isp, csi2, 0);
1088                 csi2_irq_ctx_set(isp, csi2, 0);
1089                 omap3isp_csiphy_release(csi2->phy);
1090                 isp_video_dmaqueue_flags_clr(video_out);
1091                 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1092                 break;
1093         }
1094
1095         csi2->state = enable;
1096         return 0;
1097 }
1098
1099 /* subdev video operations */
1100 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1101         .s_stream = csi2_set_stream,
1102 };
1103
1104 /* subdev pad operations */
1105 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1106         .enum_mbus_code = csi2_enum_mbus_code,
1107         .enum_frame_size = csi2_enum_frame_size,
1108         .get_fmt = csi2_get_format,
1109         .set_fmt = csi2_set_format,
1110 };
1111
1112 /* subdev operations */
1113 static const struct v4l2_subdev_ops csi2_ops = {
1114         .video = &csi2_video_ops,
1115         .pad = &csi2_pad_ops,
1116 };
1117
1118 /* subdev internal operations */
1119 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1120         .open = csi2_init_formats,
1121 };
1122
1123 /* -----------------------------------------------------------------------------
1124  * Media entity operations
1125  */
1126
1127 /*
1128  * csi2_link_setup - Setup CSI2 connections.
1129  * @entity : Pointer to media entity structure
1130  * @local  : Pointer to local pad array
1131  * @remote : Pointer to remote pad array
1132  * @flags  : Link flags
1133  * return -EINVAL or zero on success
1134  */
1135 static int csi2_link_setup(struct media_entity *entity,
1136                            const struct media_pad *local,
1137                            const struct media_pad *remote, u32 flags)
1138 {
1139         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1140         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1141         struct isp_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1142         unsigned int index = local->index;
1143
1144         /*
1145          * The ISP core doesn't support pipelines with multiple video outputs.
1146          * Revisit this when it will be implemented, and return -EBUSY for now.
1147          */
1148
1149         /* FIXME: this is actually a hack! */
1150         if (is_media_entity_v4l2_subdev(remote->entity))
1151                 index |= 2 << 16;
1152
1153         switch (index) {
1154         case CSI2_PAD_SOURCE:
1155                 if (flags & MEDIA_LNK_FL_ENABLED) {
1156                         if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1157                                 return -EBUSY;
1158                         csi2->output |= CSI2_OUTPUT_MEMORY;
1159                 } else {
1160                         csi2->output &= ~CSI2_OUTPUT_MEMORY;
1161                 }
1162                 break;
1163
1164         case CSI2_PAD_SOURCE | 2 << 16:
1165                 if (flags & MEDIA_LNK_FL_ENABLED) {
1166                         if (csi2->output & ~CSI2_OUTPUT_CCDC)
1167                                 return -EBUSY;
1168                         csi2->output |= CSI2_OUTPUT_CCDC;
1169                 } else {
1170                         csi2->output &= ~CSI2_OUTPUT_CCDC;
1171                 }
1172                 break;
1173
1174         default:
1175                 /* Link from camera to CSI2 is fixed... */
1176                 return -EINVAL;
1177         }
1178
1179         ctrl->vp_only_enable =
1180                 (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
1181         ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_CCDC);
1182
1183         return 0;
1184 }
1185
1186 /* media operations */
1187 static const struct media_entity_operations csi2_media_ops = {
1188         .link_setup = csi2_link_setup,
1189         .link_validate = v4l2_subdev_link_validate,
1190 };
1191
1192 void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2)
1193 {
1194         v4l2_device_unregister_subdev(&csi2->subdev);
1195         omap3isp_video_unregister(&csi2->video_out);
1196 }
1197
1198 int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
1199                                     struct v4l2_device *vdev)
1200 {
1201         int ret;
1202
1203         /* Register the subdev and video nodes. */
1204         ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1205         if (ret < 0)
1206                 goto error;
1207
1208         ret = omap3isp_video_register(&csi2->video_out, vdev);
1209         if (ret < 0)
1210                 goto error;
1211
1212         return 0;
1213
1214 error:
1215         omap3isp_csi2_unregister_entities(csi2);
1216         return ret;
1217 }
1218
1219 /* -----------------------------------------------------------------------------
1220  * ISP CSI2 initialisation and cleanup
1221  */
1222
1223 /*
1224  * csi2_init_entities - Initialize subdev and media entity.
1225  * @csi2: Pointer to csi2 structure.
1226  * return -ENOMEM or zero on success
1227  */
1228 static int csi2_init_entities(struct isp_csi2_device *csi2)
1229 {
1230         struct v4l2_subdev *sd = &csi2->subdev;
1231         struct media_pad *pads = csi2->pads;
1232         struct media_entity *me = &sd->entity;
1233         int ret;
1234
1235         v4l2_subdev_init(sd, &csi2_ops);
1236         sd->internal_ops = &csi2_internal_ops;
1237         strscpy(sd->name, "OMAP3 ISP CSI2a", sizeof(sd->name));
1238
1239         sd->grp_id = 1 << 16;   /* group ID for isp subdevs */
1240         v4l2_set_subdevdata(sd, csi2);
1241         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1242
1243         pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1244         pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1245                                     | MEDIA_PAD_FL_MUST_CONNECT;
1246
1247         me->ops = &csi2_media_ops;
1248         ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
1249         if (ret < 0)
1250                 return ret;
1251
1252         csi2_init_formats(sd, NULL);
1253
1254         /* Video device node */
1255         csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1256         csi2->video_out.ops = &csi2_ispvideo_ops;
1257         csi2->video_out.bpl_alignment = 32;
1258         csi2->video_out.bpl_zero_padding = 1;
1259         csi2->video_out.bpl_max = 0x1ffe0;
1260         csi2->video_out.isp = csi2->isp;
1261         csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1262
1263         ret = omap3isp_video_init(&csi2->video_out, "CSI2a");
1264         if (ret < 0)
1265                 goto error_video;
1266
1267         return 0;
1268
1269 error_video:
1270         media_entity_cleanup(&csi2->subdev.entity);
1271         return ret;
1272 }
1273
1274 /*
1275  * omap3isp_csi2_init - Routine for module driver init
1276  */
1277 int omap3isp_csi2_init(struct isp_device *isp)
1278 {
1279         struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1280         struct isp_csi2_device *csi2c = &isp->isp_csi2c;
1281         int ret;
1282
1283         csi2a->isp = isp;
1284         csi2a->available = 1;
1285         csi2a->regs1 = OMAP3_ISP_IOMEM_CSI2A_REGS1;
1286         csi2a->regs2 = OMAP3_ISP_IOMEM_CSI2A_REGS2;
1287         csi2a->phy = &isp->isp_csiphy2;
1288         csi2a->state = ISP_PIPELINE_STREAM_STOPPED;
1289         init_waitqueue_head(&csi2a->wait);
1290
1291         ret = csi2_init_entities(csi2a);
1292         if (ret < 0)
1293                 return ret;
1294
1295         if (isp->revision == ISP_REVISION_15_0) {
1296                 csi2c->isp = isp;
1297                 csi2c->available = 1;
1298                 csi2c->regs1 = OMAP3_ISP_IOMEM_CSI2C_REGS1;
1299                 csi2c->regs2 = OMAP3_ISP_IOMEM_CSI2C_REGS2;
1300                 csi2c->phy = &isp->isp_csiphy1;
1301                 csi2c->state = ISP_PIPELINE_STREAM_STOPPED;
1302                 init_waitqueue_head(&csi2c->wait);
1303         }
1304
1305         return 0;
1306 }
1307
1308 /*
1309  * omap3isp_csi2_cleanup - Routine for module driver cleanup
1310  */
1311 void omap3isp_csi2_cleanup(struct isp_device *isp)
1312 {
1313         struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1314
1315         omap3isp_video_cleanup(&csi2a->video_out);
1316         media_entity_cleanup(&csi2a->subdev.entity);
1317 }