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Merge tag 'sound-4.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[mirror_ubuntu-bionic-kernel.git] / drivers / media / platform / pxa_camera.c
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/of_graph.h>
29 #include <linux/time.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dma/pxa-dma.h>
37
38 #include <media/v4l2-async.h>
39 #include <media/v4l2-clk.h>
40 #include <media/v4l2-common.h>
41 #include <media/v4l2-ctrls.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-event.h>
44 #include <media/v4l2-ioctl.h>
45 #include <media/v4l2-fwnode.h>
46
47 #include <media/videobuf2-dma-sg.h>
48
49 #include <linux/videodev2.h>
50
51 #include <linux/platform_data/media/camera-pxa.h>
52
53 #define PXA_CAM_VERSION "0.0.6"
54 #define PXA_CAM_DRV_NAME "pxa27x-camera"
55
56 #define DEFAULT_WIDTH 640
57 #define DEFAULT_HEIGHT 480
58
59 /* Camera Interface */
60 #define CICR0 0x0000
61 #define CICR1 0x0004
62 #define CICR2 0x0008
63 #define CICR3 0x000C
64 #define CICR4 0x0010
65 #define CISR 0x0014
66 #define CIFR 0x0018
67 #define CITOR 0x001C
68 #define CIBR0 0x0028
69 #define CIBR1 0x0030
70 #define CIBR2 0x0038
71
72 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
73 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
74 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
75 #define CICR0_ENB (1 << 28) /* Camera interface enable */
76 #define CICR0_DIS (1 << 27) /* Camera interface disable */
77 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
78 #define CICR0_TOM (1 << 9) /* Time-out mask */
79 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
80 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
81 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
82 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
83 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
84 #define CICR0_CDM (1 << 3) /* Disable-done mask */
85 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
86 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
87 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
88
89 #define CICR1_TBIT (1 << 31) /* Transparency bit */
90 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
91 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
92 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
93 #define CICR1_RGB_F (1 << 11) /* RGB format */
94 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
95 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
96 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
97 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
98 #define CICR1_DW (0x7 << 0) /* Data width mask */
99
100 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
101 wait count mask */
102 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
103 wait count mask */
104 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
105 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
106 wait count mask */
107 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
108 wait count mask */
109
110 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
111 wait count mask */
112 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
113 wait count mask */
114 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
115 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
116 wait count mask */
117 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
118
119 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
120 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
121 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
122 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
123 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
124 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
125 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
126 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
127
128 #define CISR_FTO (1 << 15) /* FIFO time-out */
129 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
130 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
131 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
132 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
133 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
134 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
135 #define CISR_EOL (1 << 8) /* End of line */
136 #define CISR_PAR_ERR (1 << 7) /* Parity error */
137 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
138 #define CISR_CDD (1 << 5) /* Camera interface disable done */
139 #define CISR_SOF (1 << 4) /* Start of frame */
140 #define CISR_EOF (1 << 3) /* End of frame */
141 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
142 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
143 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
144
145 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
146 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
147 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
148 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
149 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
150 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
151 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
152 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
153
154 #define CICR0_SIM_MP (0 << 24)
155 #define CICR0_SIM_SP (1 << 24)
156 #define CICR0_SIM_MS (2 << 24)
157 #define CICR0_SIM_EP (3 << 24)
158 #define CICR0_SIM_ES (4 << 24)
159
160 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
161 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
162 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
163 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
164 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
165
166 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
167 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
168 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
169 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
170 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
171
172 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
173 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
174 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
175 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
176
177 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
178 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
179 CICR0_EOFM | CICR0_FOM)
180
181 #define sensor_call(cam, o, f, args...) \
182 v4l2_subdev_call(cam->sensor, o, f, ##args)
183
184 /*
185 * Format handling
186 */
187
188 /**
189 * enum pxa_mbus_packing - data packing types on the media-bus
190 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
191 * sample represents one pixel
192 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
193 * possibly incomplete byte high bits are padding
194 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
195 * to 16 bits
196 */
197 enum pxa_mbus_packing {
198 PXA_MBUS_PACKING_NONE,
199 PXA_MBUS_PACKING_2X8_PADHI,
200 PXA_MBUS_PACKING_EXTEND16,
201 };
202
203 /**
204 * enum pxa_mbus_order - sample order on the media bus
205 * @PXA_MBUS_ORDER_LE: least significant sample first
206 * @PXA_MBUS_ORDER_BE: most significant sample first
207 */
208 enum pxa_mbus_order {
209 PXA_MBUS_ORDER_LE,
210 PXA_MBUS_ORDER_BE,
211 };
212
213 /**
214 * enum pxa_mbus_layout - planes layout in memory
215 * @PXA_MBUS_LAYOUT_PACKED: color components packed
216 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
217 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
218 * chroma plane (C plane is half the size
219 * of Y plane)
220 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
221 * chroma plane (C plane is the same size
222 * as Y plane)
223 */
224 enum pxa_mbus_layout {
225 PXA_MBUS_LAYOUT_PACKED = 0,
226 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
227 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
228 PXA_MBUS_LAYOUT_PLANAR_Y_C,
229 };
230
231 /**
232 * struct pxa_mbus_pixelfmt - Data format on the media bus
233 * @name: Name of the format
234 * @fourcc: Fourcc code, that will be obtained if the data is
235 * stored in memory in the following way:
236 * @packing: Type of sample-packing, that has to be used
237 * @order: Sample order when storing in memory
238 * @layout: Planes layout in memory
239 * @bits_per_sample: How many bits the bridge has to sample
240 */
241 struct pxa_mbus_pixelfmt {
242 const char *name;
243 u32 fourcc;
244 enum pxa_mbus_packing packing;
245 enum pxa_mbus_order order;
246 enum pxa_mbus_layout layout;
247 u8 bits_per_sample;
248 };
249
250 /**
251 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
252 * @code: mediabus pixel-code
253 * @fmt: pixel format description
254 */
255 struct pxa_mbus_lookup {
256 u32 code;
257 struct pxa_mbus_pixelfmt fmt;
258 };
259
260 static const struct pxa_mbus_lookup mbus_fmt[] = {
261 {
262 .code = MEDIA_BUS_FMT_YUYV8_2X8,
263 .fmt = {
264 .fourcc = V4L2_PIX_FMT_YUYV,
265 .name = "YUYV",
266 .bits_per_sample = 8,
267 .packing = PXA_MBUS_PACKING_2X8_PADHI,
268 .order = PXA_MBUS_ORDER_LE,
269 .layout = PXA_MBUS_LAYOUT_PACKED,
270 },
271 }, {
272 .code = MEDIA_BUS_FMT_YVYU8_2X8,
273 .fmt = {
274 .fourcc = V4L2_PIX_FMT_YVYU,
275 .name = "YVYU",
276 .bits_per_sample = 8,
277 .packing = PXA_MBUS_PACKING_2X8_PADHI,
278 .order = PXA_MBUS_ORDER_LE,
279 .layout = PXA_MBUS_LAYOUT_PACKED,
280 },
281 }, {
282 .code = MEDIA_BUS_FMT_UYVY8_2X8,
283 .fmt = {
284 .fourcc = V4L2_PIX_FMT_UYVY,
285 .name = "UYVY",
286 .bits_per_sample = 8,
287 .packing = PXA_MBUS_PACKING_2X8_PADHI,
288 .order = PXA_MBUS_ORDER_LE,
289 .layout = PXA_MBUS_LAYOUT_PACKED,
290 },
291 }, {
292 .code = MEDIA_BUS_FMT_VYUY8_2X8,
293 .fmt = {
294 .fourcc = V4L2_PIX_FMT_VYUY,
295 .name = "VYUY",
296 .bits_per_sample = 8,
297 .packing = PXA_MBUS_PACKING_2X8_PADHI,
298 .order = PXA_MBUS_ORDER_LE,
299 .layout = PXA_MBUS_LAYOUT_PACKED,
300 },
301 }, {
302 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
303 .fmt = {
304 .fourcc = V4L2_PIX_FMT_RGB555,
305 .name = "RGB555",
306 .bits_per_sample = 8,
307 .packing = PXA_MBUS_PACKING_2X8_PADHI,
308 .order = PXA_MBUS_ORDER_LE,
309 .layout = PXA_MBUS_LAYOUT_PACKED,
310 },
311 }, {
312 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
313 .fmt = {
314 .fourcc = V4L2_PIX_FMT_RGB555X,
315 .name = "RGB555X",
316 .bits_per_sample = 8,
317 .packing = PXA_MBUS_PACKING_2X8_PADHI,
318 .order = PXA_MBUS_ORDER_BE,
319 .layout = PXA_MBUS_LAYOUT_PACKED,
320 },
321 }, {
322 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
323 .fmt = {
324 .fourcc = V4L2_PIX_FMT_RGB565,
325 .name = "RGB565",
326 .bits_per_sample = 8,
327 .packing = PXA_MBUS_PACKING_2X8_PADHI,
328 .order = PXA_MBUS_ORDER_LE,
329 .layout = PXA_MBUS_LAYOUT_PACKED,
330 },
331 }, {
332 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
333 .fmt = {
334 .fourcc = V4L2_PIX_FMT_RGB565X,
335 .name = "RGB565X",
336 .bits_per_sample = 8,
337 .packing = PXA_MBUS_PACKING_2X8_PADHI,
338 .order = PXA_MBUS_ORDER_BE,
339 .layout = PXA_MBUS_LAYOUT_PACKED,
340 },
341 }, {
342 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
343 .fmt = {
344 .fourcc = V4L2_PIX_FMT_SBGGR8,
345 .name = "Bayer 8 BGGR",
346 .bits_per_sample = 8,
347 .packing = PXA_MBUS_PACKING_NONE,
348 .order = PXA_MBUS_ORDER_LE,
349 .layout = PXA_MBUS_LAYOUT_PACKED,
350 },
351 }, {
352 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
353 .fmt = {
354 .fourcc = V4L2_PIX_FMT_SGBRG8,
355 .name = "Bayer 8 GBRG",
356 .bits_per_sample = 8,
357 .packing = PXA_MBUS_PACKING_NONE,
358 .order = PXA_MBUS_ORDER_LE,
359 .layout = PXA_MBUS_LAYOUT_PACKED,
360 },
361 }, {
362 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
363 .fmt = {
364 .fourcc = V4L2_PIX_FMT_SGRBG8,
365 .name = "Bayer 8 GRBG",
366 .bits_per_sample = 8,
367 .packing = PXA_MBUS_PACKING_NONE,
368 .order = PXA_MBUS_ORDER_LE,
369 .layout = PXA_MBUS_LAYOUT_PACKED,
370 },
371 }, {
372 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
373 .fmt = {
374 .fourcc = V4L2_PIX_FMT_SRGGB8,
375 .name = "Bayer 8 RGGB",
376 .bits_per_sample = 8,
377 .packing = PXA_MBUS_PACKING_NONE,
378 .order = PXA_MBUS_ORDER_LE,
379 .layout = PXA_MBUS_LAYOUT_PACKED,
380 },
381 }, {
382 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
383 .fmt = {
384 .fourcc = V4L2_PIX_FMT_SBGGR10,
385 .name = "Bayer 10 BGGR",
386 .bits_per_sample = 10,
387 .packing = PXA_MBUS_PACKING_EXTEND16,
388 .order = PXA_MBUS_ORDER_LE,
389 .layout = PXA_MBUS_LAYOUT_PACKED,
390 },
391 }, {
392 .code = MEDIA_BUS_FMT_Y8_1X8,
393 .fmt = {
394 .fourcc = V4L2_PIX_FMT_GREY,
395 .name = "Grey",
396 .bits_per_sample = 8,
397 .packing = PXA_MBUS_PACKING_NONE,
398 .order = PXA_MBUS_ORDER_LE,
399 .layout = PXA_MBUS_LAYOUT_PACKED,
400 },
401 }, {
402 .code = MEDIA_BUS_FMT_Y10_1X10,
403 .fmt = {
404 .fourcc = V4L2_PIX_FMT_Y10,
405 .name = "Grey 10bit",
406 .bits_per_sample = 10,
407 .packing = PXA_MBUS_PACKING_EXTEND16,
408 .order = PXA_MBUS_ORDER_LE,
409 .layout = PXA_MBUS_LAYOUT_PACKED,
410 },
411 }, {
412 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
413 .fmt = {
414 .fourcc = V4L2_PIX_FMT_SBGGR10,
415 .name = "Bayer 10 BGGR",
416 .bits_per_sample = 8,
417 .packing = PXA_MBUS_PACKING_2X8_PADHI,
418 .order = PXA_MBUS_ORDER_LE,
419 .layout = PXA_MBUS_LAYOUT_PACKED,
420 },
421 }, {
422 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
423 .fmt = {
424 .fourcc = V4L2_PIX_FMT_SBGGR10,
425 .name = "Bayer 10 BGGR",
426 .bits_per_sample = 8,
427 .packing = PXA_MBUS_PACKING_2X8_PADHI,
428 .order = PXA_MBUS_ORDER_BE,
429 .layout = PXA_MBUS_LAYOUT_PACKED,
430 },
431 }, {
432 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
433 .fmt = {
434 .fourcc = V4L2_PIX_FMT_RGB444,
435 .name = "RGB444",
436 .bits_per_sample = 8,
437 .packing = PXA_MBUS_PACKING_2X8_PADHI,
438 .order = PXA_MBUS_ORDER_BE,
439 .layout = PXA_MBUS_LAYOUT_PACKED,
440 },
441 }, {
442 .code = MEDIA_BUS_FMT_UYVY8_1X16,
443 .fmt = {
444 .fourcc = V4L2_PIX_FMT_UYVY,
445 .name = "UYVY 16bit",
446 .bits_per_sample = 16,
447 .packing = PXA_MBUS_PACKING_EXTEND16,
448 .order = PXA_MBUS_ORDER_LE,
449 .layout = PXA_MBUS_LAYOUT_PACKED,
450 },
451 }, {
452 .code = MEDIA_BUS_FMT_VYUY8_1X16,
453 .fmt = {
454 .fourcc = V4L2_PIX_FMT_VYUY,
455 .name = "VYUY 16bit",
456 .bits_per_sample = 16,
457 .packing = PXA_MBUS_PACKING_EXTEND16,
458 .order = PXA_MBUS_ORDER_LE,
459 .layout = PXA_MBUS_LAYOUT_PACKED,
460 },
461 }, {
462 .code = MEDIA_BUS_FMT_YUYV8_1X16,
463 .fmt = {
464 .fourcc = V4L2_PIX_FMT_YUYV,
465 .name = "YUYV 16bit",
466 .bits_per_sample = 16,
467 .packing = PXA_MBUS_PACKING_EXTEND16,
468 .order = PXA_MBUS_ORDER_LE,
469 .layout = PXA_MBUS_LAYOUT_PACKED,
470 },
471 }, {
472 .code = MEDIA_BUS_FMT_YVYU8_1X16,
473 .fmt = {
474 .fourcc = V4L2_PIX_FMT_YVYU,
475 .name = "YVYU 16bit",
476 .bits_per_sample = 16,
477 .packing = PXA_MBUS_PACKING_EXTEND16,
478 .order = PXA_MBUS_ORDER_LE,
479 .layout = PXA_MBUS_LAYOUT_PACKED,
480 },
481 }, {
482 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
483 .fmt = {
484 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
485 .name = "Bayer 10 BGGR DPCM 8",
486 .bits_per_sample = 8,
487 .packing = PXA_MBUS_PACKING_NONE,
488 .order = PXA_MBUS_ORDER_LE,
489 .layout = PXA_MBUS_LAYOUT_PACKED,
490 },
491 }, {
492 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
493 .fmt = {
494 .fourcc = V4L2_PIX_FMT_SGBRG10,
495 .name = "Bayer 10 GBRG",
496 .bits_per_sample = 10,
497 .packing = PXA_MBUS_PACKING_EXTEND16,
498 .order = PXA_MBUS_ORDER_LE,
499 .layout = PXA_MBUS_LAYOUT_PACKED,
500 },
501 }, {
502 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
503 .fmt = {
504 .fourcc = V4L2_PIX_FMT_SGRBG10,
505 .name = "Bayer 10 GRBG",
506 .bits_per_sample = 10,
507 .packing = PXA_MBUS_PACKING_EXTEND16,
508 .order = PXA_MBUS_ORDER_LE,
509 .layout = PXA_MBUS_LAYOUT_PACKED,
510 },
511 }, {
512 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
513 .fmt = {
514 .fourcc = V4L2_PIX_FMT_SRGGB10,
515 .name = "Bayer 10 RGGB",
516 .bits_per_sample = 10,
517 .packing = PXA_MBUS_PACKING_EXTEND16,
518 .order = PXA_MBUS_ORDER_LE,
519 .layout = PXA_MBUS_LAYOUT_PACKED,
520 },
521 }, {
522 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
523 .fmt = {
524 .fourcc = V4L2_PIX_FMT_SBGGR12,
525 .name = "Bayer 12 BGGR",
526 .bits_per_sample = 12,
527 .packing = PXA_MBUS_PACKING_EXTEND16,
528 .order = PXA_MBUS_ORDER_LE,
529 .layout = PXA_MBUS_LAYOUT_PACKED,
530 },
531 }, {
532 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
533 .fmt = {
534 .fourcc = V4L2_PIX_FMT_SGBRG12,
535 .name = "Bayer 12 GBRG",
536 .bits_per_sample = 12,
537 .packing = PXA_MBUS_PACKING_EXTEND16,
538 .order = PXA_MBUS_ORDER_LE,
539 .layout = PXA_MBUS_LAYOUT_PACKED,
540 },
541 }, {
542 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
543 .fmt = {
544 .fourcc = V4L2_PIX_FMT_SGRBG12,
545 .name = "Bayer 12 GRBG",
546 .bits_per_sample = 12,
547 .packing = PXA_MBUS_PACKING_EXTEND16,
548 .order = PXA_MBUS_ORDER_LE,
549 .layout = PXA_MBUS_LAYOUT_PACKED,
550 },
551 }, {
552 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
553 .fmt = {
554 .fourcc = V4L2_PIX_FMT_SRGGB12,
555 .name = "Bayer 12 RGGB",
556 .bits_per_sample = 12,
557 .packing = PXA_MBUS_PACKING_EXTEND16,
558 .order = PXA_MBUS_ORDER_LE,
559 .layout = PXA_MBUS_LAYOUT_PACKED,
560 },
561 },
562 };
563
564 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
565 {
566 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
567 return width * mf->bits_per_sample / 8;
568
569 switch (mf->packing) {
570 case PXA_MBUS_PACKING_NONE:
571 return width * mf->bits_per_sample / 8;
572 case PXA_MBUS_PACKING_2X8_PADHI:
573 case PXA_MBUS_PACKING_EXTEND16:
574 return width * 2;
575 }
576 return -EINVAL;
577 }
578
579 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
580 u32 bytes_per_line, u32 height)
581 {
582 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
583 return bytes_per_line * height;
584
585 switch (mf->packing) {
586 case PXA_MBUS_PACKING_2X8_PADHI:
587 return bytes_per_line * height * 2;
588 default:
589 return -EINVAL;
590 }
591 }
592
593 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
594 u32 code,
595 const struct pxa_mbus_lookup *lookup,
596 int n)
597 {
598 int i;
599
600 for (i = 0; i < n; i++)
601 if (lookup[i].code == code)
602 return &lookup[i].fmt;
603
604 return NULL;
605 }
606
607 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
608 u32 code)
609 {
610 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
611 }
612
613 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
614 unsigned int flags)
615 {
616 unsigned long common_flags;
617 bool hsync = true, vsync = true, pclk, data, mode;
618 bool mipi_lanes, mipi_clock;
619
620 common_flags = cfg->flags & flags;
621
622 switch (cfg->type) {
623 case V4L2_MBUS_PARALLEL:
624 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
625 V4L2_MBUS_HSYNC_ACTIVE_LOW);
626 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
627 V4L2_MBUS_VSYNC_ACTIVE_LOW);
628 /* fall through */
629 case V4L2_MBUS_BT656:
630 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
631 V4L2_MBUS_PCLK_SAMPLE_FALLING);
632 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
633 V4L2_MBUS_DATA_ACTIVE_LOW);
634 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
635 return (!hsync || !vsync || !pclk || !data || !mode) ?
636 0 : common_flags;
637 case V4L2_MBUS_CSI2:
638 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
639 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
640 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
641 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
642 default:
643 WARN_ON(1);
644 return -EINVAL;
645 }
646 return 0;
647 }
648
649 /**
650 * struct soc_camera_format_xlate - match between host and sensor formats
651 * @code: code of a sensor provided format
652 * @host_fmt: host format after host translation from code
653 *
654 * Host and sensor translation structure. Used in table of host and sensor
655 * formats matchings in soc_camera_device. A host can override the generic list
656 * generation by implementing get_formats(), and use it for format checks and
657 * format setup.
658 */
659 struct soc_camera_format_xlate {
660 u32 code;
661 const struct pxa_mbus_pixelfmt *host_fmt;
662 };
663
664 /*
665 * Structures
666 */
667 enum pxa_camera_active_dma {
668 DMA_Y = 0x1,
669 DMA_U = 0x2,
670 DMA_V = 0x4,
671 };
672
673 /* buffer for one video frame */
674 struct pxa_buffer {
675 /* common v4l buffer stuff -- must be first */
676 struct vb2_v4l2_buffer vbuf;
677 struct list_head queue;
678 u32 code;
679 int nb_planes;
680 /* our descriptor lists for Y, U and V channels */
681 struct dma_async_tx_descriptor *descs[3];
682 dma_cookie_t cookie[3];
683 struct scatterlist *sg[3];
684 int sg_len[3];
685 size_t plane_sizes[3];
686 int inwork;
687 enum pxa_camera_active_dma active_dma;
688 };
689
690 struct pxa_camera_dev {
691 struct v4l2_device v4l2_dev;
692 struct video_device vdev;
693 struct v4l2_async_notifier notifier;
694 struct vb2_queue vb2_vq;
695 struct v4l2_subdev *sensor;
696 struct soc_camera_format_xlate *user_formats;
697 const struct soc_camera_format_xlate *current_fmt;
698 struct v4l2_pix_format current_pix;
699
700 struct v4l2_async_subdev asd;
701 struct v4l2_async_subdev *asds[1];
702
703 /*
704 * PXA27x is only supposed to handle one camera on its Quick Capture
705 * interface. If anyone ever builds hardware to enable more than
706 * one camera, they will have to modify this driver too
707 */
708 struct clk *clk;
709
710 unsigned int irq;
711 void __iomem *base;
712
713 int channels;
714 struct dma_chan *dma_chans[3];
715
716 struct pxacamera_platform_data *pdata;
717 struct resource *res;
718 unsigned long platform_flags;
719 unsigned long ciclk;
720 unsigned long mclk;
721 u32 mclk_divisor;
722 struct v4l2_clk *mclk_clk;
723 u16 width_flags; /* max 10 bits */
724
725 struct list_head capture;
726
727 spinlock_t lock;
728 struct mutex mlock;
729 unsigned int buf_sequence;
730
731 struct pxa_buffer *active;
732 struct tasklet_struct task_eof;
733
734 u32 save_cicr[5];
735 };
736
737 struct pxa_cam {
738 unsigned long flags;
739 };
740
741 static const char *pxa_cam_driver_description = "PXA_Camera";
742
743 /*
744 * Format translation functions
745 */
746 static const struct soc_camera_format_xlate
747 *pxa_mbus_xlate_by_fourcc(struct soc_camera_format_xlate *user_formats,
748 unsigned int fourcc)
749 {
750 unsigned int i;
751
752 for (i = 0; user_formats[i].code; i++)
753 if (user_formats[i].host_fmt->fourcc == fourcc)
754 return user_formats + i;
755 return NULL;
756 }
757
758 static struct soc_camera_format_xlate *pxa_mbus_build_fmts_xlate(
759 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
760 int (*get_formats)(struct v4l2_device *, unsigned int,
761 struct soc_camera_format_xlate *xlate))
762 {
763 unsigned int i, fmts = 0, raw_fmts = 0;
764 int ret;
765 struct v4l2_subdev_mbus_code_enum code = {
766 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
767 };
768 struct soc_camera_format_xlate *user_formats;
769
770 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
771 raw_fmts++;
772 code.index++;
773 }
774
775 /*
776 * First pass - only count formats this host-sensor
777 * configuration can provide
778 */
779 for (i = 0; i < raw_fmts; i++) {
780 ret = get_formats(v4l2_dev, i, NULL);
781 if (ret < 0)
782 return ERR_PTR(ret);
783 fmts += ret;
784 }
785
786 if (!fmts)
787 return ERR_PTR(-ENXIO);
788
789 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
790 if (!user_formats)
791 return ERR_PTR(-ENOMEM);
792
793 /* Second pass - actually fill data formats */
794 fmts = 0;
795 for (i = 0; i < raw_fmts; i++) {
796 ret = get_formats(v4l2_dev, i, user_formats + fmts);
797 if (ret < 0)
798 goto egfmt;
799 fmts += ret;
800 }
801 user_formats[fmts].code = 0;
802
803 return user_formats;
804 egfmt:
805 kfree(user_formats);
806 return ERR_PTR(ret);
807 }
808
809 /*
810 * Videobuf operations
811 */
812 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
813 {
814 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
815
816 return container_of(vbuf, struct pxa_buffer, vbuf);
817 }
818
819 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
820 {
821 return pcdev->v4l2_dev.dev;
822 }
823
824 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
825 {
826 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
827 }
828
829 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
830 enum pxa_camera_active_dma act_dma);
831
832 static void pxa_camera_dma_irq_y(void *data)
833 {
834 struct pxa_camera_dev *pcdev = data;
835
836 pxa_camera_dma_irq(pcdev, DMA_Y);
837 }
838
839 static void pxa_camera_dma_irq_u(void *data)
840 {
841 struct pxa_camera_dev *pcdev = data;
842
843 pxa_camera_dma_irq(pcdev, DMA_U);
844 }
845
846 static void pxa_camera_dma_irq_v(void *data)
847 {
848 struct pxa_camera_dev *pcdev = data;
849
850 pxa_camera_dma_irq(pcdev, DMA_V);
851 }
852
853 /**
854 * pxa_init_dma_channel - init dma descriptors
855 * @pcdev: pxa camera device
856 * @buf: pxa camera buffer
857 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
858 * @sg: dma scatter list
859 * @sglen: dma scatter list length
860 *
861 * Prepares the pxa dma descriptors to transfer one camera channel.
862 *
863 * Returns 0 if success or -ENOMEM if no memory is available
864 */
865 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
866 struct pxa_buffer *buf, int channel,
867 struct scatterlist *sg, int sglen)
868 {
869 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
870 struct dma_async_tx_descriptor *tx;
871
872 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
873 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
874 if (!tx) {
875 dev_err(pcdev_to_dev(pcdev),
876 "dmaengine_prep_slave_sg failed\n");
877 goto fail;
878 }
879
880 tx->callback_param = pcdev;
881 switch (channel) {
882 case 0:
883 tx->callback = pxa_camera_dma_irq_y;
884 break;
885 case 1:
886 tx->callback = pxa_camera_dma_irq_u;
887 break;
888 case 2:
889 tx->callback = pxa_camera_dma_irq_v;
890 break;
891 }
892
893 buf->descs[channel] = tx;
894 return 0;
895 fail:
896 dev_dbg(pcdev_to_dev(pcdev),
897 "%s (vb=%p) dma_tx=%p\n",
898 __func__, buf, tx);
899
900 return -ENOMEM;
901 }
902
903 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
904 struct pxa_buffer *buf)
905 {
906 buf->active_dma = DMA_Y;
907 if (buf->nb_planes == 3)
908 buf->active_dma |= DMA_U | DMA_V;
909 }
910
911 /**
912 * pxa_dma_start_channels - start DMA channel for active buffer
913 * @pcdev: pxa camera device
914 *
915 * Initialize DMA channels to the beginning of the active video buffer, and
916 * start these channels.
917 */
918 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
919 {
920 int i;
921
922 for (i = 0; i < pcdev->channels; i++) {
923 dev_dbg(pcdev_to_dev(pcdev),
924 "%s (channel=%d)\n", __func__, i);
925 dma_async_issue_pending(pcdev->dma_chans[i]);
926 }
927 }
928
929 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
930 {
931 int i;
932
933 for (i = 0; i < pcdev->channels; i++) {
934 dev_dbg(pcdev_to_dev(pcdev),
935 "%s (channel=%d)\n", __func__, i);
936 dmaengine_terminate_all(pcdev->dma_chans[i]);
937 }
938 }
939
940 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
941 struct pxa_buffer *buf)
942 {
943 int i;
944
945 for (i = 0; i < pcdev->channels; i++) {
946 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
947 dev_dbg(pcdev_to_dev(pcdev),
948 "%s (channel=%d) : submit vb=%p cookie=%d\n",
949 __func__, i, buf, buf->descs[i]->cookie);
950 }
951 }
952
953 /**
954 * pxa_camera_start_capture - start video capturing
955 * @pcdev: camera device
956 *
957 * Launch capturing. DMA channels should not be active yet. They should get
958 * activated at the end of frame interrupt, to capture only whole frames, and
959 * never begin the capture of a partial frame.
960 */
961 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
962 {
963 unsigned long cicr0;
964
965 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
966 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
967 /* Enable End-Of-Frame Interrupt */
968 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
969 cicr0 &= ~CICR0_EOFM;
970 __raw_writel(cicr0, pcdev->base + CICR0);
971 }
972
973 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
974 {
975 unsigned long cicr0;
976
977 pxa_dma_stop_channels(pcdev);
978
979 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
980 __raw_writel(cicr0, pcdev->base + CICR0);
981
982 pcdev->active = NULL;
983 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
984 }
985
986 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
987 struct pxa_buffer *buf,
988 enum vb2_buffer_state state)
989 {
990 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
991 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
992
993 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
994 list_del_init(&buf->queue);
995 vb->timestamp = ktime_get_ns();
996 vbuf->sequence = pcdev->buf_sequence++;
997 vbuf->field = V4L2_FIELD_NONE;
998 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
999 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
1000 __func__, buf);
1001
1002 if (list_empty(&pcdev->capture)) {
1003 pxa_camera_stop_capture(pcdev);
1004 return;
1005 }
1006
1007 pcdev->active = list_entry(pcdev->capture.next,
1008 struct pxa_buffer, queue);
1009 }
1010
1011 /**
1012 * pxa_camera_check_link_miss - check missed DMA linking
1013 * @pcdev: camera device
1014 * @last_submitted: an opaque DMA cookie for last submitted
1015 * @last_issued: an opaque DMA cookie for last issued
1016 *
1017 * The DMA chaining is done with DMA running. This means a tiny temporal window
1018 * remains, where a buffer is queued on the chain, while the chain is already
1019 * stopped. This means the tailed buffer would never be transferred by DMA.
1020 * This function restarts the capture for this corner case, where :
1021 * - DADR() == DADDR_STOP
1022 * - a videobuffer is queued on the pcdev->capture list
1023 *
1024 * Please check the "DMA hot chaining timeslice issue" in
1025 * Documentation/video4linux/pxa_camera.txt
1026 *
1027 * Context: should only be called within the dma irq handler
1028 */
1029 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
1030 dma_cookie_t last_submitted,
1031 dma_cookie_t last_issued)
1032 {
1033 bool is_dma_stopped = last_submitted != last_issued;
1034
1035 dev_dbg(pcdev_to_dev(pcdev),
1036 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1037 __func__, pcdev->active, is_dma_stopped);
1038
1039 if (pcdev->active && is_dma_stopped)
1040 pxa_camera_start_capture(pcdev);
1041 }
1042
1043 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1044 enum pxa_camera_active_dma act_dma)
1045 {
1046 struct pxa_buffer *buf, *last_buf;
1047 unsigned long flags;
1048 u32 camera_status, overrun;
1049 int chan;
1050 enum dma_status last_status;
1051 dma_cookie_t last_issued;
1052
1053 spin_lock_irqsave(&pcdev->lock, flags);
1054
1055 camera_status = __raw_readl(pcdev->base + CISR);
1056 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1057 camera_status, act_dma);
1058 overrun = CISR_IFO_0;
1059 if (pcdev->channels == 3)
1060 overrun |= CISR_IFO_1 | CISR_IFO_2;
1061
1062 /*
1063 * pcdev->active should not be NULL in DMA irq handler.
1064 *
1065 * But there is one corner case : if capture was stopped due to an
1066 * overrun of channel 1, and at that same channel 2 was completed.
1067 *
1068 * When handling the overrun in DMA irq for channel 1, we'll stop the
1069 * capture and restart it (and thus set pcdev->active to NULL). But the
1070 * DMA irq handler will already be pending for channel 2. So on entering
1071 * the DMA irq handler for channel 2 there will be no active buffer, yet
1072 * that is normal.
1073 */
1074 if (!pcdev->active)
1075 goto out;
1076
1077 buf = pcdev->active;
1078 WARN_ON(buf->inwork || list_empty(&buf->queue));
1079
1080 /*
1081 * It's normal if the last frame creates an overrun, as there
1082 * are no more DMA descriptors to fetch from QCI fifos
1083 */
1084 switch (act_dma) {
1085 case DMA_U:
1086 chan = 1;
1087 break;
1088 case DMA_V:
1089 chan = 2;
1090 break;
1091 default:
1092 chan = 0;
1093 break;
1094 }
1095 last_buf = list_entry(pcdev->capture.prev,
1096 struct pxa_buffer, queue);
1097 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1098 last_buf->cookie[chan],
1099 NULL, &last_issued);
1100 if (camera_status & overrun &&
1101 last_status != DMA_COMPLETE) {
1102 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1103 camera_status);
1104 pxa_camera_stop_capture(pcdev);
1105 list_for_each_entry(buf, &pcdev->capture, queue)
1106 pxa_dma_add_tail_buf(pcdev, buf);
1107 pxa_camera_start_capture(pcdev);
1108 goto out;
1109 }
1110 buf->active_dma &= ~act_dma;
1111 if (!buf->active_dma) {
1112 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1113 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1114 last_issued);
1115 }
1116
1117 out:
1118 spin_unlock_irqrestore(&pcdev->lock, flags);
1119 }
1120
1121 static u32 mclk_get_divisor(struct platform_device *pdev,
1122 struct pxa_camera_dev *pcdev)
1123 {
1124 unsigned long mclk = pcdev->mclk;
1125 u32 div;
1126 unsigned long lcdclk;
1127
1128 lcdclk = clk_get_rate(pcdev->clk);
1129 pcdev->ciclk = lcdclk;
1130
1131 /* mclk <= ciclk / 4 (27.4.2) */
1132 if (mclk > lcdclk / 4) {
1133 mclk = lcdclk / 4;
1134 dev_warn(&pdev->dev,
1135 "Limiting master clock to %lu\n", mclk);
1136 }
1137
1138 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1139 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1140
1141 /* If we're not supplying MCLK, leave it at 0 */
1142 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1143 pcdev->mclk = lcdclk / (2 * (div + 1));
1144
1145 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1146 lcdclk, mclk, div);
1147
1148 return div;
1149 }
1150
1151 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1152 unsigned long pclk)
1153 {
1154 /* We want a timeout > 1 pixel time, not ">=" */
1155 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1156
1157 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1158 }
1159
1160 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1161 {
1162 u32 cicr4 = 0;
1163
1164 /* disable all interrupts */
1165 __raw_writel(0x3ff, pcdev->base + CICR0);
1166
1167 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1168 cicr4 |= CICR4_PCLK_EN;
1169 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1170 cicr4 |= CICR4_MCLK_EN;
1171 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1172 cicr4 |= CICR4_PCP;
1173 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1174 cicr4 |= CICR4_HSP;
1175 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1176 cicr4 |= CICR4_VSP;
1177
1178 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1179
1180 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1181 /* Initialise the timeout under the assumption pclk = mclk */
1182 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1183 else
1184 /* "Safe default" - 13MHz */
1185 recalculate_fifo_timeout(pcdev, 13000000);
1186
1187 clk_prepare_enable(pcdev->clk);
1188 }
1189
1190 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1191 {
1192 clk_disable_unprepare(pcdev->clk);
1193 }
1194
1195 static void pxa_camera_eof(unsigned long arg)
1196 {
1197 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1198 unsigned long cifr;
1199 struct pxa_buffer *buf;
1200
1201 dev_dbg(pcdev_to_dev(pcdev),
1202 "Camera interrupt status 0x%x\n",
1203 __raw_readl(pcdev->base + CISR));
1204
1205 /* Reset the FIFOs */
1206 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1207 __raw_writel(cifr, pcdev->base + CIFR);
1208
1209 pcdev->active = list_first_entry(&pcdev->capture,
1210 struct pxa_buffer, queue);
1211 buf = pcdev->active;
1212 pxa_videobuf_set_actdma(pcdev, buf);
1213
1214 pxa_dma_start_channels(pcdev);
1215 }
1216
1217 static irqreturn_t pxa_camera_irq(int irq, void *data)
1218 {
1219 struct pxa_camera_dev *pcdev = data;
1220 unsigned long status, cicr0;
1221
1222 status = __raw_readl(pcdev->base + CISR);
1223 dev_dbg(pcdev_to_dev(pcdev),
1224 "Camera interrupt status 0x%lx\n", status);
1225
1226 if (!status)
1227 return IRQ_NONE;
1228
1229 __raw_writel(status, pcdev->base + CISR);
1230
1231 if (status & CISR_EOF) {
1232 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1233 __raw_writel(cicr0, pcdev->base + CICR0);
1234 tasklet_schedule(&pcdev->task_eof);
1235 }
1236
1237 return IRQ_HANDLED;
1238 }
1239
1240 static int test_platform_param(struct pxa_camera_dev *pcdev,
1241 unsigned char buswidth, unsigned long *flags)
1242 {
1243 /*
1244 * Platform specified synchronization and pixel clock polarities are
1245 * only a recommendation and are only used during probing. The PXA270
1246 * quick capture interface supports both.
1247 */
1248 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1249 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1250 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1251 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1252 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1253 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1254 V4L2_MBUS_DATA_ACTIVE_HIGH |
1255 V4L2_MBUS_PCLK_SAMPLE_RISING |
1256 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1257
1258 /* If requested data width is supported by the platform, use it */
1259 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1260 return 0;
1261
1262 return -EINVAL;
1263 }
1264
1265 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1266 unsigned long flags, __u32 pixfmt)
1267 {
1268 unsigned long dw, bpp;
1269 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1270 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1271
1272 if (ret < 0)
1273 y_skip_top = 0;
1274
1275 /*
1276 * Datawidth is now guaranteed to be equal to one of the three values.
1277 * We fix bit-per-pixel equal to data-width...
1278 */
1279 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1280 case 10:
1281 dw = 4;
1282 bpp = 0x40;
1283 break;
1284 case 9:
1285 dw = 3;
1286 bpp = 0x20;
1287 break;
1288 default:
1289 /*
1290 * Actually it can only be 8 now,
1291 * default is just to silence compiler warnings
1292 */
1293 case 8:
1294 dw = 2;
1295 bpp = 0;
1296 }
1297
1298 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1299 cicr4 |= CICR4_PCLK_EN;
1300 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1301 cicr4 |= CICR4_MCLK_EN;
1302 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1303 cicr4 |= CICR4_PCP;
1304 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1305 cicr4 |= CICR4_HSP;
1306 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1307 cicr4 |= CICR4_VSP;
1308
1309 cicr0 = __raw_readl(pcdev->base + CICR0);
1310 if (cicr0 & CICR0_ENB)
1311 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1312
1313 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1314
1315 switch (pixfmt) {
1316 case V4L2_PIX_FMT_YUV422P:
1317 pcdev->channels = 3;
1318 cicr1 |= CICR1_YCBCR_F;
1319 /*
1320 * Normally, pxa bus wants as input UYVY format. We allow all
1321 * reorderings of the YUV422 format, as no processing is done,
1322 * and the YUV stream is just passed through without any
1323 * transformation. Note that UYVY is the only format that
1324 * should be used if pxa framebuffer Overlay2 is used.
1325 */
1326 /* fall through */
1327 case V4L2_PIX_FMT_UYVY:
1328 case V4L2_PIX_FMT_VYUY:
1329 case V4L2_PIX_FMT_YUYV:
1330 case V4L2_PIX_FMT_YVYU:
1331 cicr1 |= CICR1_COLOR_SP_VAL(2);
1332 break;
1333 case V4L2_PIX_FMT_RGB555:
1334 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1335 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1336 break;
1337 case V4L2_PIX_FMT_RGB565:
1338 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1339 break;
1340 }
1341
1342 cicr2 = 0;
1343 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1344 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1345 cicr4 |= pcdev->mclk_divisor;
1346
1347 __raw_writel(cicr1, pcdev->base + CICR1);
1348 __raw_writel(cicr2, pcdev->base + CICR2);
1349 __raw_writel(cicr3, pcdev->base + CICR3);
1350 __raw_writel(cicr4, pcdev->base + CICR4);
1351
1352 /* CIF interrupts are not used, only DMA */
1353 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1354 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1355 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1356 __raw_writel(cicr0, pcdev->base + CICR0);
1357 }
1358
1359 /*
1360 * Videobuf2 section
1361 */
1362 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1363 {
1364 int i;
1365
1366 for (i = 0; i < 3 && buf->descs[i]; i++) {
1367 dmaengine_desc_free(buf->descs[i]);
1368 kfree(buf->sg[i]);
1369 buf->descs[i] = NULL;
1370 buf->sg[i] = NULL;
1371 buf->sg_len[i] = 0;
1372 buf->plane_sizes[i] = 0;
1373 }
1374 buf->nb_planes = 0;
1375 }
1376
1377 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1378 struct pxa_buffer *buf)
1379 {
1380 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1381 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1382 int nb_channels = pcdev->channels;
1383 int i, ret = 0;
1384 unsigned long size = vb2_plane_size(vb, 0);
1385
1386 switch (nb_channels) {
1387 case 1:
1388 buf->plane_sizes[0] = size;
1389 break;
1390 case 3:
1391 buf->plane_sizes[0] = size / 2;
1392 buf->plane_sizes[1] = size / 4;
1393 buf->plane_sizes[2] = size / 4;
1394 break;
1395 default:
1396 return -EINVAL;
1397 };
1398 buf->nb_planes = nb_channels;
1399
1400 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1401 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1402 if (ret < 0) {
1403 dev_err(pcdev_to_dev(pcdev),
1404 "sg_split failed: %d\n", ret);
1405 return ret;
1406 }
1407 for (i = 0; i < nb_channels; i++) {
1408 ret = pxa_init_dma_channel(pcdev, buf, i,
1409 buf->sg[i], buf->sg_len[i]);
1410 if (ret) {
1411 pxa_buffer_cleanup(buf);
1412 return ret;
1413 }
1414 }
1415 INIT_LIST_HEAD(&buf->queue);
1416
1417 return ret;
1418 }
1419
1420 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1421 {
1422 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1423 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1424
1425 dev_dbg(pcdev_to_dev(pcdev),
1426 "%s(vb=%p)\n", __func__, vb);
1427 pxa_buffer_cleanup(buf);
1428 }
1429
1430 static void pxac_vb2_queue(struct vb2_buffer *vb)
1431 {
1432 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1433 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1434
1435 dev_dbg(pcdev_to_dev(pcdev),
1436 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1437 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1438 pcdev->active);
1439
1440 list_add_tail(&buf->queue, &pcdev->capture);
1441
1442 pxa_dma_add_tail_buf(pcdev, buf);
1443 }
1444
1445 /*
1446 * Please check the DMA prepared buffer structure in :
1447 * Documentation/video4linux/pxa_camera.txt
1448 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1449 * modification while DMA chain is running will work anyway.
1450 */
1451 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1452 {
1453 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1454 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1455 int ret = 0;
1456
1457 switch (pcdev->channels) {
1458 case 1:
1459 case 3:
1460 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1461 break;
1462 default:
1463 return -EINVAL;
1464 }
1465
1466 dev_dbg(pcdev_to_dev(pcdev),
1467 "%s (vb=%p) nb_channels=%d size=%lu\n",
1468 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1469
1470 WARN_ON(!pcdev->current_fmt);
1471
1472 #ifdef DEBUG
1473 /*
1474 * This can be useful if you want to see if we actually fill
1475 * the buffer with something
1476 */
1477 for (i = 0; i < vb->num_planes; i++)
1478 memset((void *)vb2_plane_vaddr(vb, i),
1479 0xaa, vb2_get_plane_payload(vb, i));
1480 #endif
1481
1482 /*
1483 * I think, in buf_prepare you only have to protect global data,
1484 * the actual buffer is yours
1485 */
1486 buf->inwork = 0;
1487 pxa_videobuf_set_actdma(pcdev, buf);
1488
1489 return ret;
1490 }
1491
1492 static int pxac_vb2_init(struct vb2_buffer *vb)
1493 {
1494 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1495 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1496
1497 dev_dbg(pcdev_to_dev(pcdev),
1498 "%s(nb_channels=%d)\n",
1499 __func__, pcdev->channels);
1500
1501 return pxa_buffer_init(pcdev, buf);
1502 }
1503
1504 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1505 unsigned int *nbufs,
1506 unsigned int *num_planes, unsigned int sizes[],
1507 struct device *alloc_devs[])
1508 {
1509 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1510 int size = pcdev->current_pix.sizeimage;
1511
1512 dev_dbg(pcdev_to_dev(pcdev),
1513 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1514 __func__, vq, *nbufs, *num_planes, size);
1515 /*
1516 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1517 * format, even if there are 3 planes Y, U and V, we reply there is only
1518 * one plane, containing Y, U and V data, one after the other.
1519 */
1520 if (*num_planes)
1521 return sizes[0] < size ? -EINVAL : 0;
1522
1523 *num_planes = 1;
1524 switch (pcdev->channels) {
1525 case 1:
1526 case 3:
1527 sizes[0] = size;
1528 break;
1529 default:
1530 return -EINVAL;
1531 }
1532
1533 if (!*nbufs)
1534 *nbufs = 1;
1535
1536 return 0;
1537 }
1538
1539 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1540 {
1541 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1542
1543 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1544 __func__, count, pcdev->active);
1545
1546 pcdev->buf_sequence = 0;
1547 if (!pcdev->active)
1548 pxa_camera_start_capture(pcdev);
1549
1550 return 0;
1551 }
1552
1553 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1554 {
1555 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1556 struct pxa_buffer *buf, *tmp;
1557
1558 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1559 __func__, pcdev->active);
1560 pxa_camera_stop_capture(pcdev);
1561
1562 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1563 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1564 }
1565
1566 static const struct vb2_ops pxac_vb2_ops = {
1567 .queue_setup = pxac_vb2_queue_setup,
1568 .buf_init = pxac_vb2_init,
1569 .buf_prepare = pxac_vb2_prepare,
1570 .buf_queue = pxac_vb2_queue,
1571 .buf_cleanup = pxac_vb2_cleanup,
1572 .start_streaming = pxac_vb2_start_streaming,
1573 .stop_streaming = pxac_vb2_stop_streaming,
1574 .wait_prepare = vb2_ops_wait_prepare,
1575 .wait_finish = vb2_ops_wait_finish,
1576 };
1577
1578 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1579 {
1580 int ret;
1581 struct vb2_queue *vq = &pcdev->vb2_vq;
1582
1583 memset(vq, 0, sizeof(*vq));
1584 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1585 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1586 vq->drv_priv = pcdev;
1587 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1588 vq->buf_struct_size = sizeof(struct pxa_buffer);
1589 vq->dev = pcdev->v4l2_dev.dev;
1590
1591 vq->ops = &pxac_vb2_ops;
1592 vq->mem_ops = &vb2_dma_sg_memops;
1593 vq->lock = &pcdev->mlock;
1594
1595 ret = vb2_queue_init(vq);
1596 dev_dbg(pcdev_to_dev(pcdev),
1597 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1598
1599 return ret;
1600 }
1601
1602 /*
1603 * Video ioctls section
1604 */
1605 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1606 {
1607 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1608 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1609 unsigned long bus_flags, common_flags;
1610 int ret;
1611
1612 ret = test_platform_param(pcdev,
1613 pcdev->current_fmt->host_fmt->bits_per_sample,
1614 &bus_flags);
1615 if (ret < 0)
1616 return ret;
1617
1618 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1619 if (!ret) {
1620 common_flags = pxa_mbus_config_compatible(&cfg,
1621 bus_flags);
1622 if (!common_flags) {
1623 dev_warn(pcdev_to_dev(pcdev),
1624 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1625 cfg.flags, bus_flags);
1626 return -EINVAL;
1627 }
1628 } else if (ret != -ENOIOCTLCMD) {
1629 return ret;
1630 } else {
1631 common_flags = bus_flags;
1632 }
1633
1634 pcdev->channels = 1;
1635
1636 /* Make choises, based on platform preferences */
1637 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1638 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1639 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1640 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1641 else
1642 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1643 }
1644
1645 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1646 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1647 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1648 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1649 else
1650 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1651 }
1652
1653 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1654 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1655 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1656 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1657 else
1658 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1659 }
1660
1661 cfg.flags = common_flags;
1662 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1663 if (ret < 0 && ret != -ENOIOCTLCMD) {
1664 dev_dbg(pcdev_to_dev(pcdev),
1665 "camera s_mbus_config(0x%lx) returned %d\n",
1666 common_flags, ret);
1667 return ret;
1668 }
1669
1670 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1671
1672 return 0;
1673 }
1674
1675 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1676 unsigned char buswidth)
1677 {
1678 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1679 unsigned long bus_flags, common_flags;
1680 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1681
1682 if (ret < 0)
1683 return ret;
1684
1685 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1686 if (!ret) {
1687 common_flags = pxa_mbus_config_compatible(&cfg,
1688 bus_flags);
1689 if (!common_flags) {
1690 dev_warn(pcdev_to_dev(pcdev),
1691 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1692 cfg.flags, bus_flags);
1693 return -EINVAL;
1694 }
1695 } else if (ret == -ENOIOCTLCMD) {
1696 ret = 0;
1697 }
1698
1699 return ret;
1700 }
1701
1702 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1703 {
1704 .fourcc = V4L2_PIX_FMT_YUV422P,
1705 .name = "Planar YUV422 16 bit",
1706 .bits_per_sample = 8,
1707 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1708 .order = PXA_MBUS_ORDER_LE,
1709 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1710 },
1711 };
1712
1713 /* This will be corrected as we get more formats */
1714 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1715 {
1716 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1717 (fmt->bits_per_sample == 8 &&
1718 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1719 (fmt->bits_per_sample > 8 &&
1720 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1721 }
1722
1723 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1724 unsigned int idx,
1725 struct soc_camera_format_xlate *xlate)
1726 {
1727 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1728 int formats = 0, ret;
1729 struct v4l2_subdev_mbus_code_enum code = {
1730 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1731 .index = idx,
1732 };
1733 const struct pxa_mbus_pixelfmt *fmt;
1734
1735 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1736 if (ret < 0)
1737 /* No more formats */
1738 return 0;
1739
1740 fmt = pxa_mbus_get_fmtdesc(code.code);
1741 if (!fmt) {
1742 dev_err(pcdev_to_dev(pcdev),
1743 "Invalid format code #%u: %d\n", idx, code.code);
1744 return 0;
1745 }
1746
1747 /* This also checks support for the requested bits-per-sample */
1748 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1749 if (ret < 0)
1750 return 0;
1751
1752 switch (code.code) {
1753 case MEDIA_BUS_FMT_UYVY8_2X8:
1754 formats++;
1755 if (xlate) {
1756 xlate->host_fmt = &pxa_camera_formats[0];
1757 xlate->code = code.code;
1758 xlate++;
1759 dev_dbg(pcdev_to_dev(pcdev),
1760 "Providing format %s using code %d\n",
1761 pxa_camera_formats[0].name, code.code);
1762 }
1763 /* fall through */
1764 case MEDIA_BUS_FMT_VYUY8_2X8:
1765 case MEDIA_BUS_FMT_YUYV8_2X8:
1766 case MEDIA_BUS_FMT_YVYU8_2X8:
1767 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1768 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1769 if (xlate)
1770 dev_dbg(pcdev_to_dev(pcdev),
1771 "Providing format %s packed\n",
1772 fmt->name);
1773 break;
1774 default:
1775 if (!pxa_camera_packing_supported(fmt))
1776 return 0;
1777 if (xlate)
1778 dev_dbg(pcdev_to_dev(pcdev),
1779 "Providing format %s in pass-through mode\n",
1780 fmt->name);
1781 break;
1782 }
1783
1784 /* Generic pass-through */
1785 formats++;
1786 if (xlate) {
1787 xlate->host_fmt = fmt;
1788 xlate->code = code.code;
1789 xlate++;
1790 }
1791
1792 return formats;
1793 }
1794
1795 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1796 {
1797 struct soc_camera_format_xlate *xlate;
1798
1799 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1800 pxa_camera_get_formats);
1801 if (IS_ERR(xlate))
1802 return PTR_ERR(xlate);
1803
1804 pcdev->user_formats = xlate;
1805 return 0;
1806 }
1807
1808 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1809 {
1810 kfree(pcdev->user_formats);
1811 }
1812
1813 static int pxa_camera_check_frame(u32 width, u32 height)
1814 {
1815 /* limit to pxa hardware capabilities */
1816 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1817 (width & 0x01);
1818 }
1819
1820 #ifdef CONFIG_VIDEO_ADV_DEBUG
1821 static int pxac_vidioc_g_register(struct file *file, void *priv,
1822 struct v4l2_dbg_register *reg)
1823 {
1824 struct pxa_camera_dev *pcdev = video_drvdata(file);
1825
1826 if (reg->reg > CIBR2)
1827 return -ERANGE;
1828
1829 reg->val = __raw_readl(pcdev->base + reg->reg);
1830 reg->size = sizeof(__u32);
1831 return 0;
1832 }
1833
1834 static int pxac_vidioc_s_register(struct file *file, void *priv,
1835 const struct v4l2_dbg_register *reg)
1836 {
1837 struct pxa_camera_dev *pcdev = video_drvdata(file);
1838
1839 if (reg->reg > CIBR2)
1840 return -ERANGE;
1841 if (reg->size != sizeof(__u32))
1842 return -EINVAL;
1843 __raw_writel(reg->val, pcdev->base + reg->reg);
1844 return 0;
1845 }
1846 #endif
1847
1848 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1849 struct v4l2_fmtdesc *f)
1850 {
1851 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1852 const struct pxa_mbus_pixelfmt *format;
1853 unsigned int idx;
1854
1855 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1856 if (f->index >= idx)
1857 return -EINVAL;
1858
1859 format = pcdev->user_formats[f->index].host_fmt;
1860 f->pixelformat = format->fourcc;
1861 return 0;
1862 }
1863
1864 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1865 struct v4l2_format *f)
1866 {
1867 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1868 struct v4l2_pix_format *pix = &f->fmt.pix;
1869
1870 pix->width = pcdev->current_pix.width;
1871 pix->height = pcdev->current_pix.height;
1872 pix->bytesperline = pcdev->current_pix.bytesperline;
1873 pix->sizeimage = pcdev->current_pix.sizeimage;
1874 pix->field = pcdev->current_pix.field;
1875 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1876 pix->colorspace = pcdev->current_pix.colorspace;
1877 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1878 pcdev->current_fmt->host_fmt->fourcc);
1879 return 0;
1880 }
1881
1882 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1883 struct v4l2_format *f)
1884 {
1885 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1886 const struct soc_camera_format_xlate *xlate;
1887 struct v4l2_pix_format *pix = &f->fmt.pix;
1888 struct v4l2_subdev_pad_config pad_cfg;
1889 struct v4l2_subdev_format format = {
1890 .which = V4L2_SUBDEV_FORMAT_TRY,
1891 };
1892 struct v4l2_mbus_framefmt *mf = &format.format;
1893 __u32 pixfmt = pix->pixelformat;
1894 int ret;
1895
1896 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1897 if (!xlate) {
1898 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1899 return -EINVAL;
1900 }
1901
1902 /*
1903 * Limit to pxa hardware capabilities. YUV422P planar format requires
1904 * images size to be a multiple of 16 bytes. If not, zeros will be
1905 * inserted between Y and U planes, and U and V planes, which violates
1906 * the YUV422P standard.
1907 */
1908 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1909 &pix->height, 32, 2048, 0,
1910 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1911
1912 v4l2_fill_mbus_format(mf, pix, xlate->code);
1913 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1914 if (ret < 0)
1915 return ret;
1916
1917 v4l2_fill_pix_format(pix, mf);
1918
1919 /* Only progressive video supported so far */
1920 switch (mf->field) {
1921 case V4L2_FIELD_ANY:
1922 case V4L2_FIELD_NONE:
1923 pix->field = V4L2_FIELD_NONE;
1924 break;
1925 default:
1926 /* TODO: support interlaced at least in pass-through mode */
1927 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1928 mf->field);
1929 return -EINVAL;
1930 }
1931
1932 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1933 if (ret < 0)
1934 return ret;
1935
1936 pix->bytesperline = ret;
1937 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1938 pix->height);
1939 if (ret < 0)
1940 return ret;
1941
1942 pix->sizeimage = ret;
1943 return 0;
1944 }
1945
1946 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1947 struct v4l2_format *f)
1948 {
1949 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1950 const struct soc_camera_format_xlate *xlate;
1951 struct v4l2_pix_format *pix = &f->fmt.pix;
1952 struct v4l2_subdev_format format = {
1953 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1954 };
1955 unsigned long flags;
1956 int ret, is_busy;
1957
1958 dev_dbg(pcdev_to_dev(pcdev),
1959 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1960 pix->width, pix->height, pix->pixelformat);
1961
1962 spin_lock_irqsave(&pcdev->lock, flags);
1963 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1964 spin_unlock_irqrestore(&pcdev->lock, flags);
1965
1966 if (is_busy)
1967 return -EBUSY;
1968
1969 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1970 if (ret)
1971 return ret;
1972
1973 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1974 pix->pixelformat);
1975 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1976 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1977 if (ret < 0) {
1978 dev_warn(pcdev_to_dev(pcdev),
1979 "Failed to configure for format %x\n",
1980 pix->pixelformat);
1981 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1982 dev_warn(pcdev_to_dev(pcdev),
1983 "Camera driver produced an unsupported frame %dx%d\n",
1984 pix->width, pix->height);
1985 return -EINVAL;
1986 }
1987
1988 pcdev->current_fmt = xlate;
1989 pcdev->current_pix = *pix;
1990
1991 ret = pxa_camera_set_bus_param(pcdev);
1992 return ret;
1993 }
1994
1995 static int pxac_vidioc_querycap(struct file *file, void *priv,
1996 struct v4l2_capability *cap)
1997 {
1998 strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1999 strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
2000 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
2001 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
2002 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
2003
2004 return 0;
2005 }
2006
2007 static int pxac_vidioc_enum_input(struct file *file, void *priv,
2008 struct v4l2_input *i)
2009 {
2010 if (i->index > 0)
2011 return -EINVAL;
2012
2013 i->type = V4L2_INPUT_TYPE_CAMERA;
2014 strlcpy(i->name, "Camera", sizeof(i->name));
2015
2016 return 0;
2017 }
2018
2019 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
2020 {
2021 *i = 0;
2022
2023 return 0;
2024 }
2025
2026 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
2027 {
2028 if (i > 0)
2029 return -EINVAL;
2030
2031 return 0;
2032 }
2033
2034 static int pxac_fops_camera_open(struct file *filp)
2035 {
2036 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2037 int ret;
2038
2039 mutex_lock(&pcdev->mlock);
2040 ret = v4l2_fh_open(filp);
2041 if (ret < 0)
2042 goto out;
2043
2044 ret = sensor_call(pcdev, core, s_power, 1);
2045 if (ret)
2046 v4l2_fh_release(filp);
2047 out:
2048 mutex_unlock(&pcdev->mlock);
2049 return ret;
2050 }
2051
2052 static int pxac_fops_camera_release(struct file *filp)
2053 {
2054 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2055 int ret;
2056
2057 ret = vb2_fop_release(filp);
2058 if (ret < 0)
2059 return ret;
2060
2061 mutex_lock(&pcdev->mlock);
2062 ret = sensor_call(pcdev, core, s_power, 0);
2063 mutex_unlock(&pcdev->mlock);
2064
2065 return ret;
2066 }
2067
2068 static const struct v4l2_file_operations pxa_camera_fops = {
2069 .owner = THIS_MODULE,
2070 .open = pxac_fops_camera_open,
2071 .release = pxac_fops_camera_release,
2072 .read = vb2_fop_read,
2073 .poll = vb2_fop_poll,
2074 .mmap = vb2_fop_mmap,
2075 .unlocked_ioctl = video_ioctl2,
2076 };
2077
2078 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2079 .vidioc_querycap = pxac_vidioc_querycap,
2080
2081 .vidioc_enum_input = pxac_vidioc_enum_input,
2082 .vidioc_g_input = pxac_vidioc_g_input,
2083 .vidioc_s_input = pxac_vidioc_s_input,
2084
2085 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2086 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2087 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2088 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2089
2090 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2091 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2092 .vidioc_querybuf = vb2_ioctl_querybuf,
2093 .vidioc_qbuf = vb2_ioctl_qbuf,
2094 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2095 .vidioc_expbuf = vb2_ioctl_expbuf,
2096 .vidioc_streamon = vb2_ioctl_streamon,
2097 .vidioc_streamoff = vb2_ioctl_streamoff,
2098 #ifdef CONFIG_VIDEO_ADV_DEBUG
2099 .vidioc_g_register = pxac_vidioc_g_register,
2100 .vidioc_s_register = pxac_vidioc_s_register,
2101 #endif
2102 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2103 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2104 };
2105
2106 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2107 };
2108
2109 static const struct video_device pxa_camera_videodev_template = {
2110 .name = "pxa-camera",
2111 .minor = -1,
2112 .fops = &pxa_camera_fops,
2113 .ioctl_ops = &pxa_camera_ioctl_ops,
2114 .release = video_device_release_empty,
2115 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2116 };
2117
2118 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2119 struct v4l2_subdev *subdev,
2120 struct v4l2_async_subdev *asd)
2121 {
2122 int err;
2123 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2124 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2125 struct video_device *vdev = &pcdev->vdev;
2126 struct v4l2_pix_format *pix = &pcdev->current_pix;
2127 struct v4l2_subdev_format format = {
2128 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2129 };
2130 struct v4l2_mbus_framefmt *mf = &format.format;
2131
2132 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2133 __func__);
2134 mutex_lock(&pcdev->mlock);
2135 *vdev = pxa_camera_videodev_template;
2136 vdev->v4l2_dev = v4l2_dev;
2137 vdev->lock = &pcdev->mlock;
2138 pcdev->sensor = subdev;
2139 pcdev->vdev.queue = &pcdev->vb2_vq;
2140 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2141 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2142 video_set_drvdata(&pcdev->vdev, pcdev);
2143
2144 err = pxa_camera_build_formats(pcdev);
2145 if (err) {
2146 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2147 err);
2148 goto out;
2149 }
2150
2151 pcdev->current_fmt = pcdev->user_formats;
2152 pix->field = V4L2_FIELD_NONE;
2153 pix->width = DEFAULT_WIDTH;
2154 pix->height = DEFAULT_HEIGHT;
2155 pix->bytesperline =
2156 pxa_mbus_bytes_per_line(pix->width,
2157 pcdev->current_fmt->host_fmt);
2158 pix->sizeimage =
2159 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2160 pix->bytesperline, pix->height);
2161 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2162 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2163
2164 err = sensor_call(pcdev, core, s_power, 1);
2165 if (err)
2166 goto out;
2167
2168 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2169 if (err)
2170 goto out_sensor_poweroff;
2171
2172 v4l2_fill_pix_format(pix, mf);
2173 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2174 __func__, pix->colorspace, pix->pixelformat);
2175
2176 err = pxa_camera_init_videobuf2(pcdev);
2177 if (err)
2178 goto out_sensor_poweroff;
2179
2180 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2181 if (err) {
2182 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2183 pcdev->sensor = NULL;
2184 } else {
2185 dev_info(pcdev_to_dev(pcdev),
2186 "PXA Camera driver attached to camera %s\n",
2187 subdev->name);
2188 }
2189
2190 out_sensor_poweroff:
2191 err = sensor_call(pcdev, core, s_power, 0);
2192 out:
2193 mutex_unlock(&pcdev->mlock);
2194 return err;
2195 }
2196
2197 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2198 struct v4l2_subdev *subdev,
2199 struct v4l2_async_subdev *asd)
2200 {
2201 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2202
2203 mutex_lock(&pcdev->mlock);
2204 dev_info(pcdev_to_dev(pcdev),
2205 "PXA Camera driver detached from camera %s\n",
2206 subdev->name);
2207
2208 /* disable capture, disable interrupts */
2209 __raw_writel(0x3ff, pcdev->base + CICR0);
2210
2211 /* Stop DMA engine */
2212 pxa_dma_stop_channels(pcdev);
2213
2214 pxa_camera_destroy_formats(pcdev);
2215
2216 if (pcdev->mclk_clk) {
2217 v4l2_clk_unregister(pcdev->mclk_clk);
2218 pcdev->mclk_clk = NULL;
2219 }
2220
2221 video_unregister_device(&pcdev->vdev);
2222 pcdev->sensor = NULL;
2223
2224 mutex_unlock(&pcdev->mlock);
2225 }
2226
2227 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2228 .bound = pxa_camera_sensor_bound,
2229 .unbind = pxa_camera_sensor_unbind,
2230 };
2231
2232 /*
2233 * Driver probe, remove, suspend and resume operations
2234 */
2235 static int pxa_camera_suspend(struct device *dev)
2236 {
2237 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2238 int i = 0, ret = 0;
2239
2240 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2241 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2242 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2243 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2244 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2245
2246 if (pcdev->sensor) {
2247 ret = sensor_call(pcdev, core, s_power, 0);
2248 if (ret == -ENOIOCTLCMD)
2249 ret = 0;
2250 }
2251
2252 return ret;
2253 }
2254
2255 static int pxa_camera_resume(struct device *dev)
2256 {
2257 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2258 int i = 0, ret = 0;
2259
2260 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2261 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2262 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2263 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2264 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2265
2266 if (pcdev->sensor) {
2267 ret = sensor_call(pcdev, core, s_power, 1);
2268 if (ret == -ENOIOCTLCMD)
2269 ret = 0;
2270 }
2271
2272 /* Restart frame capture if active buffer exists */
2273 if (!ret && pcdev->active)
2274 pxa_camera_start_capture(pcdev);
2275
2276 return ret;
2277 }
2278
2279 static int pxa_camera_pdata_from_dt(struct device *dev,
2280 struct pxa_camera_dev *pcdev,
2281 struct v4l2_async_subdev *asd)
2282 {
2283 u32 mclk_rate;
2284 struct device_node *remote, *np = dev->of_node;
2285 struct v4l2_fwnode_endpoint ep;
2286 int err = of_property_read_u32(np, "clock-frequency",
2287 &mclk_rate);
2288 if (!err) {
2289 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2290 pcdev->mclk = mclk_rate;
2291 }
2292
2293 np = of_graph_get_next_endpoint(np, NULL);
2294 if (!np) {
2295 dev_err(dev, "could not find endpoint\n");
2296 return -EINVAL;
2297 }
2298
2299 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2300 if (err) {
2301 dev_err(dev, "could not parse endpoint\n");
2302 goto out;
2303 }
2304
2305 switch (ep.bus.parallel.bus_width) {
2306 case 4:
2307 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2308 break;
2309 case 5:
2310 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2311 break;
2312 case 8:
2313 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2314 break;
2315 case 9:
2316 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2317 break;
2318 case 10:
2319 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2320 break;
2321 default:
2322 break;
2323 }
2324
2325 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2326 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2327 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2328 pcdev->platform_flags |= PXA_CAMERA_HSP;
2329 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2330 pcdev->platform_flags |= PXA_CAMERA_VSP;
2331 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2332 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2333 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2334 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2335
2336 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2337 remote = of_graph_get_remote_port(np);
2338 if (remote) {
2339 asd->match.fwnode.fwnode = of_fwnode_handle(remote);
2340 of_node_put(remote);
2341 } else {
2342 dev_notice(dev, "no remote for %pOF\n", np);
2343 }
2344
2345 out:
2346 of_node_put(np);
2347
2348 return err;
2349 }
2350
2351 static int pxa_camera_probe(struct platform_device *pdev)
2352 {
2353 struct pxa_camera_dev *pcdev;
2354 struct resource *res;
2355 void __iomem *base;
2356 struct dma_slave_config config = {
2357 .src_addr_width = 0,
2358 .src_maxburst = 8,
2359 .direction = DMA_DEV_TO_MEM,
2360 };
2361 dma_cap_mask_t mask;
2362 struct pxad_param params;
2363 char clk_name[V4L2_CLK_NAME_SIZE];
2364 int irq;
2365 int err = 0, i;
2366
2367 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2368 irq = platform_get_irq(pdev, 0);
2369 if (!res || irq < 0)
2370 return -ENODEV;
2371
2372 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2373 if (!pcdev) {
2374 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2375 return -ENOMEM;
2376 }
2377
2378 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2379 if (IS_ERR(pcdev->clk))
2380 return PTR_ERR(pcdev->clk);
2381
2382 pcdev->res = res;
2383
2384 pcdev->pdata = pdev->dev.platform_data;
2385 if (&pdev->dev.of_node && !pcdev->pdata) {
2386 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2387 } else {
2388 pcdev->platform_flags = pcdev->pdata->flags;
2389 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2390 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2391 pcdev->asd.match.i2c.adapter_id =
2392 pcdev->pdata->sensor_i2c_adapter_id;
2393 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2394 }
2395 if (err < 0)
2396 return err;
2397
2398 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2399 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2400 /*
2401 * Platform hasn't set available data widths. This is bad.
2402 * Warn and use a default.
2403 */
2404 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2405 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2406 }
2407 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2408 pcdev->width_flags = 1 << 7;
2409 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2410 pcdev->width_flags |= 1 << 8;
2411 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2412 pcdev->width_flags |= 1 << 9;
2413 if (!pcdev->mclk) {
2414 dev_warn(&pdev->dev,
2415 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2416 pcdev->mclk = 20000000;
2417 }
2418
2419 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2420
2421 INIT_LIST_HEAD(&pcdev->capture);
2422 spin_lock_init(&pcdev->lock);
2423 mutex_init(&pcdev->mlock);
2424
2425 /*
2426 * Request the regions.
2427 */
2428 base = devm_ioremap_resource(&pdev->dev, res);
2429 if (IS_ERR(base))
2430 return PTR_ERR(base);
2431
2432 pcdev->irq = irq;
2433 pcdev->base = base;
2434
2435 /* request dma */
2436 dma_cap_zero(mask);
2437 dma_cap_set(DMA_SLAVE, mask);
2438 dma_cap_set(DMA_PRIVATE, mask);
2439
2440 params.prio = 0;
2441 params.drcmr = 68;
2442 pcdev->dma_chans[0] =
2443 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2444 &params, &pdev->dev, "CI_Y");
2445 if (!pcdev->dma_chans[0]) {
2446 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2447 return -ENODEV;
2448 }
2449
2450 params.drcmr = 69;
2451 pcdev->dma_chans[1] =
2452 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2453 &params, &pdev->dev, "CI_U");
2454 if (!pcdev->dma_chans[1]) {
2455 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2456 err = -ENODEV;
2457 goto exit_free_dma_y;
2458 }
2459
2460 params.drcmr = 70;
2461 pcdev->dma_chans[2] =
2462 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2463 &params, &pdev->dev, "CI_V");
2464 if (!pcdev->dma_chans[2]) {
2465 dev_err(&pdev->dev, "Can't request DMA for V\n");
2466 err = -ENODEV;
2467 goto exit_free_dma_u;
2468 }
2469
2470 for (i = 0; i < 3; i++) {
2471 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2472 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2473 if (err < 0) {
2474 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2475 err);
2476 goto exit_free_dma;
2477 }
2478 }
2479
2480 /* request irq */
2481 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2482 PXA_CAM_DRV_NAME, pcdev);
2483 if (err) {
2484 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2485 goto exit_free_dma;
2486 }
2487
2488 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2489
2490 pxa_camera_activate(pcdev);
2491
2492 dev_set_drvdata(&pdev->dev, pcdev);
2493 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2494 if (err)
2495 goto exit_free_dma;
2496
2497 pcdev->asds[0] = &pcdev->asd;
2498 pcdev->notifier.subdevs = pcdev->asds;
2499 pcdev->notifier.num_subdevs = 1;
2500 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2501
2502 if (!of_have_populated_dt())
2503 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2504
2505 err = pxa_camera_init_videobuf2(pcdev);
2506 if (err)
2507 goto exit_free_v4l2dev;
2508
2509 if (pcdev->mclk) {
2510 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2511 pcdev->asd.match.i2c.adapter_id,
2512 pcdev->asd.match.i2c.address);
2513
2514 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2515 clk_name, NULL);
2516 if (IS_ERR(pcdev->mclk_clk)) {
2517 err = PTR_ERR(pcdev->mclk_clk);
2518 goto exit_free_v4l2dev;
2519 }
2520 }
2521
2522 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2523 if (err)
2524 goto exit_free_clk;
2525
2526 return 0;
2527 exit_free_clk:
2528 v4l2_clk_unregister(pcdev->mclk_clk);
2529 exit_free_v4l2dev:
2530 v4l2_device_unregister(&pcdev->v4l2_dev);
2531 exit_free_dma:
2532 dma_release_channel(pcdev->dma_chans[2]);
2533 exit_free_dma_u:
2534 dma_release_channel(pcdev->dma_chans[1]);
2535 exit_free_dma_y:
2536 dma_release_channel(pcdev->dma_chans[0]);
2537 return err;
2538 }
2539
2540 static int pxa_camera_remove(struct platform_device *pdev)
2541 {
2542 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2543
2544 pxa_camera_deactivate(pcdev);
2545 dma_release_channel(pcdev->dma_chans[0]);
2546 dma_release_channel(pcdev->dma_chans[1]);
2547 dma_release_channel(pcdev->dma_chans[2]);
2548
2549 v4l2_async_notifier_unregister(&pcdev->notifier);
2550
2551 if (pcdev->mclk_clk) {
2552 v4l2_clk_unregister(pcdev->mclk_clk);
2553 pcdev->mclk_clk = NULL;
2554 }
2555
2556 v4l2_device_unregister(&pcdev->v4l2_dev);
2557
2558 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2559
2560 return 0;
2561 }
2562
2563 static const struct dev_pm_ops pxa_camera_pm = {
2564 .suspend = pxa_camera_suspend,
2565 .resume = pxa_camera_resume,
2566 };
2567
2568 static const struct of_device_id pxa_camera_of_match[] = {
2569 { .compatible = "marvell,pxa270-qci", },
2570 {},
2571 };
2572 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2573
2574 static struct platform_driver pxa_camera_driver = {
2575 .driver = {
2576 .name = PXA_CAM_DRV_NAME,
2577 .pm = &pxa_camera_pm,
2578 .of_match_table = of_match_ptr(pxa_camera_of_match),
2579 },
2580 .probe = pxa_camera_probe,
2581 .remove = pxa_camera_remove,
2582 };
2583
2584 module_platform_driver(pxa_camera_driver);
2585
2586 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2587 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2588 MODULE_LICENSE("GPL");
2589 MODULE_VERSION(PXA_CAM_VERSION);
2590 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
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