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ASoC: tlv320aic31xx: Reset registers during power up
[mirror_ubuntu-focal-kernel.git] / drivers / media / platform / pxa_camera.c
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/of_graph.h>
29 #include <linux/time.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dma/pxa-dma.h>
37
38 #include <media/v4l2-async.h>
39 #include <media/v4l2-clk.h>
40 #include <media/v4l2-common.h>
41 #include <media/v4l2-ctrls.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-event.h>
44 #include <media/v4l2-ioctl.h>
45 #include <media/v4l2-fwnode.h>
46
47 #include <media/videobuf2-dma-sg.h>
48
49 #include <linux/videodev2.h>
50
51 #include <linux/platform_data/media/camera-pxa.h>
52
53 #define PXA_CAM_VERSION "0.0.6"
54 #define PXA_CAM_DRV_NAME "pxa27x-camera"
55
56 #define DEFAULT_WIDTH 640
57 #define DEFAULT_HEIGHT 480
58
59 /* Camera Interface */
60 #define CICR0 0x0000
61 #define CICR1 0x0004
62 #define CICR2 0x0008
63 #define CICR3 0x000C
64 #define CICR4 0x0010
65 #define CISR 0x0014
66 #define CIFR 0x0018
67 #define CITOR 0x001C
68 #define CIBR0 0x0028
69 #define CIBR1 0x0030
70 #define CIBR2 0x0038
71
72 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
73 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
74 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
75 #define CICR0_ENB (1 << 28) /* Camera interface enable */
76 #define CICR0_DIS (1 << 27) /* Camera interface disable */
77 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
78 #define CICR0_TOM (1 << 9) /* Time-out mask */
79 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
80 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
81 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
82 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
83 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
84 #define CICR0_CDM (1 << 3) /* Disable-done mask */
85 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
86 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
87 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
88
89 #define CICR1_TBIT (1 << 31) /* Transparency bit */
90 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
91 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
92 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
93 #define CICR1_RGB_F (1 << 11) /* RGB format */
94 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
95 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
96 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
97 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
98 #define CICR1_DW (0x7 << 0) /* Data width mask */
99
100 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
101 wait count mask */
102 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
103 wait count mask */
104 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
105 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
106 wait count mask */
107 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
108 wait count mask */
109
110 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
111 wait count mask */
112 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
113 wait count mask */
114 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
115 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
116 wait count mask */
117 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
118
119 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
120 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
121 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
122 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
123 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
124 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
125 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
126 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
127
128 #define CISR_FTO (1 << 15) /* FIFO time-out */
129 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
130 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
131 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
132 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
133 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
134 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
135 #define CISR_EOL (1 << 8) /* End of line */
136 #define CISR_PAR_ERR (1 << 7) /* Parity error */
137 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
138 #define CISR_CDD (1 << 5) /* Camera interface disable done */
139 #define CISR_SOF (1 << 4) /* Start of frame */
140 #define CISR_EOF (1 << 3) /* End of frame */
141 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
142 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
143 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
144
145 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
146 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
147 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
148 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
149 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
150 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
151 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
152 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
153
154 #define CICR0_SIM_MP (0 << 24)
155 #define CICR0_SIM_SP (1 << 24)
156 #define CICR0_SIM_MS (2 << 24)
157 #define CICR0_SIM_EP (3 << 24)
158 #define CICR0_SIM_ES (4 << 24)
159
160 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
161 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
162 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
163 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
164 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
165
166 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
167 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
168 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
169 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
170 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
171
172 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
173 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
174 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
175 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
176
177 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
178 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
179 CICR0_EOFM | CICR0_FOM)
180
181 #define sensor_call(cam, o, f, args...) \
182 v4l2_subdev_call(cam->sensor, o, f, ##args)
183
184 /*
185 * Format handling
186 */
187
188 /**
189 * enum pxa_mbus_packing - data packing types on the media-bus
190 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
191 * sample represents one pixel
192 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
193 * possibly incomplete byte high bits are padding
194 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
195 * to 16 bits
196 */
197 enum pxa_mbus_packing {
198 PXA_MBUS_PACKING_NONE,
199 PXA_MBUS_PACKING_2X8_PADHI,
200 PXA_MBUS_PACKING_EXTEND16,
201 };
202
203 /**
204 * enum pxa_mbus_order - sample order on the media bus
205 * @PXA_MBUS_ORDER_LE: least significant sample first
206 * @PXA_MBUS_ORDER_BE: most significant sample first
207 */
208 enum pxa_mbus_order {
209 PXA_MBUS_ORDER_LE,
210 PXA_MBUS_ORDER_BE,
211 };
212
213 /**
214 * enum pxa_mbus_layout - planes layout in memory
215 * @PXA_MBUS_LAYOUT_PACKED: color components packed
216 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
217 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
218 * chroma plane (C plane is half the size
219 * of Y plane)
220 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
221 * chroma plane (C plane is the same size
222 * as Y plane)
223 */
224 enum pxa_mbus_layout {
225 PXA_MBUS_LAYOUT_PACKED = 0,
226 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
227 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
228 PXA_MBUS_LAYOUT_PLANAR_Y_C,
229 };
230
231 /**
232 * struct pxa_mbus_pixelfmt - Data format on the media bus
233 * @name: Name of the format
234 * @fourcc: Fourcc code, that will be obtained if the data is
235 * stored in memory in the following way:
236 * @packing: Type of sample-packing, that has to be used
237 * @order: Sample order when storing in memory
238 * @bits_per_sample: How many bits the bridge has to sample
239 */
240 struct pxa_mbus_pixelfmt {
241 const char *name;
242 u32 fourcc;
243 enum pxa_mbus_packing packing;
244 enum pxa_mbus_order order;
245 enum pxa_mbus_layout layout;
246 u8 bits_per_sample;
247 };
248
249 /**
250 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
251 * @code: mediabus pixel-code
252 * @fmt: pixel format description
253 */
254 struct pxa_mbus_lookup {
255 u32 code;
256 struct pxa_mbus_pixelfmt fmt;
257 };
258
259 static const struct pxa_mbus_lookup mbus_fmt[] = {
260 {
261 .code = MEDIA_BUS_FMT_YUYV8_2X8,
262 .fmt = {
263 .fourcc = V4L2_PIX_FMT_YUYV,
264 .name = "YUYV",
265 .bits_per_sample = 8,
266 .packing = PXA_MBUS_PACKING_2X8_PADHI,
267 .order = PXA_MBUS_ORDER_LE,
268 .layout = PXA_MBUS_LAYOUT_PACKED,
269 },
270 }, {
271 .code = MEDIA_BUS_FMT_YVYU8_2X8,
272 .fmt = {
273 .fourcc = V4L2_PIX_FMT_YVYU,
274 .name = "YVYU",
275 .bits_per_sample = 8,
276 .packing = PXA_MBUS_PACKING_2X8_PADHI,
277 .order = PXA_MBUS_ORDER_LE,
278 .layout = PXA_MBUS_LAYOUT_PACKED,
279 },
280 }, {
281 .code = MEDIA_BUS_FMT_UYVY8_2X8,
282 .fmt = {
283 .fourcc = V4L2_PIX_FMT_UYVY,
284 .name = "UYVY",
285 .bits_per_sample = 8,
286 .packing = PXA_MBUS_PACKING_2X8_PADHI,
287 .order = PXA_MBUS_ORDER_LE,
288 .layout = PXA_MBUS_LAYOUT_PACKED,
289 },
290 }, {
291 .code = MEDIA_BUS_FMT_VYUY8_2X8,
292 .fmt = {
293 .fourcc = V4L2_PIX_FMT_VYUY,
294 .name = "VYUY",
295 .bits_per_sample = 8,
296 .packing = PXA_MBUS_PACKING_2X8_PADHI,
297 .order = PXA_MBUS_ORDER_LE,
298 .layout = PXA_MBUS_LAYOUT_PACKED,
299 },
300 }, {
301 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
302 .fmt = {
303 .fourcc = V4L2_PIX_FMT_RGB555,
304 .name = "RGB555",
305 .bits_per_sample = 8,
306 .packing = PXA_MBUS_PACKING_2X8_PADHI,
307 .order = PXA_MBUS_ORDER_LE,
308 .layout = PXA_MBUS_LAYOUT_PACKED,
309 },
310 }, {
311 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
312 .fmt = {
313 .fourcc = V4L2_PIX_FMT_RGB555X,
314 .name = "RGB555X",
315 .bits_per_sample = 8,
316 .packing = PXA_MBUS_PACKING_2X8_PADHI,
317 .order = PXA_MBUS_ORDER_BE,
318 .layout = PXA_MBUS_LAYOUT_PACKED,
319 },
320 }, {
321 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
322 .fmt = {
323 .fourcc = V4L2_PIX_FMT_RGB565,
324 .name = "RGB565",
325 .bits_per_sample = 8,
326 .packing = PXA_MBUS_PACKING_2X8_PADHI,
327 .order = PXA_MBUS_ORDER_LE,
328 .layout = PXA_MBUS_LAYOUT_PACKED,
329 },
330 }, {
331 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
332 .fmt = {
333 .fourcc = V4L2_PIX_FMT_RGB565X,
334 .name = "RGB565X",
335 .bits_per_sample = 8,
336 .packing = PXA_MBUS_PACKING_2X8_PADHI,
337 .order = PXA_MBUS_ORDER_BE,
338 .layout = PXA_MBUS_LAYOUT_PACKED,
339 },
340 }, {
341 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
342 .fmt = {
343 .fourcc = V4L2_PIX_FMT_SBGGR8,
344 .name = "Bayer 8 BGGR",
345 .bits_per_sample = 8,
346 .packing = PXA_MBUS_PACKING_NONE,
347 .order = PXA_MBUS_ORDER_LE,
348 .layout = PXA_MBUS_LAYOUT_PACKED,
349 },
350 }, {
351 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
352 .fmt = {
353 .fourcc = V4L2_PIX_FMT_SGBRG8,
354 .name = "Bayer 8 GBRG",
355 .bits_per_sample = 8,
356 .packing = PXA_MBUS_PACKING_NONE,
357 .order = PXA_MBUS_ORDER_LE,
358 .layout = PXA_MBUS_LAYOUT_PACKED,
359 },
360 }, {
361 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
362 .fmt = {
363 .fourcc = V4L2_PIX_FMT_SGRBG8,
364 .name = "Bayer 8 GRBG",
365 .bits_per_sample = 8,
366 .packing = PXA_MBUS_PACKING_NONE,
367 .order = PXA_MBUS_ORDER_LE,
368 .layout = PXA_MBUS_LAYOUT_PACKED,
369 },
370 }, {
371 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
372 .fmt = {
373 .fourcc = V4L2_PIX_FMT_SRGGB8,
374 .name = "Bayer 8 RGGB",
375 .bits_per_sample = 8,
376 .packing = PXA_MBUS_PACKING_NONE,
377 .order = PXA_MBUS_ORDER_LE,
378 .layout = PXA_MBUS_LAYOUT_PACKED,
379 },
380 }, {
381 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
382 .fmt = {
383 .fourcc = V4L2_PIX_FMT_SBGGR10,
384 .name = "Bayer 10 BGGR",
385 .bits_per_sample = 10,
386 .packing = PXA_MBUS_PACKING_EXTEND16,
387 .order = PXA_MBUS_ORDER_LE,
388 .layout = PXA_MBUS_LAYOUT_PACKED,
389 },
390 }, {
391 .code = MEDIA_BUS_FMT_Y8_1X8,
392 .fmt = {
393 .fourcc = V4L2_PIX_FMT_GREY,
394 .name = "Grey",
395 .bits_per_sample = 8,
396 .packing = PXA_MBUS_PACKING_NONE,
397 .order = PXA_MBUS_ORDER_LE,
398 .layout = PXA_MBUS_LAYOUT_PACKED,
399 },
400 }, {
401 .code = MEDIA_BUS_FMT_Y10_1X10,
402 .fmt = {
403 .fourcc = V4L2_PIX_FMT_Y10,
404 .name = "Grey 10bit",
405 .bits_per_sample = 10,
406 .packing = PXA_MBUS_PACKING_EXTEND16,
407 .order = PXA_MBUS_ORDER_LE,
408 .layout = PXA_MBUS_LAYOUT_PACKED,
409 },
410 }, {
411 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
412 .fmt = {
413 .fourcc = V4L2_PIX_FMT_SBGGR10,
414 .name = "Bayer 10 BGGR",
415 .bits_per_sample = 8,
416 .packing = PXA_MBUS_PACKING_2X8_PADHI,
417 .order = PXA_MBUS_ORDER_LE,
418 .layout = PXA_MBUS_LAYOUT_PACKED,
419 },
420 }, {
421 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
422 .fmt = {
423 .fourcc = V4L2_PIX_FMT_SBGGR10,
424 .name = "Bayer 10 BGGR",
425 .bits_per_sample = 8,
426 .packing = PXA_MBUS_PACKING_2X8_PADHI,
427 .order = PXA_MBUS_ORDER_BE,
428 .layout = PXA_MBUS_LAYOUT_PACKED,
429 },
430 }, {
431 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
432 .fmt = {
433 .fourcc = V4L2_PIX_FMT_RGB444,
434 .name = "RGB444",
435 .bits_per_sample = 8,
436 .packing = PXA_MBUS_PACKING_2X8_PADHI,
437 .order = PXA_MBUS_ORDER_BE,
438 .layout = PXA_MBUS_LAYOUT_PACKED,
439 },
440 }, {
441 .code = MEDIA_BUS_FMT_UYVY8_1X16,
442 .fmt = {
443 .fourcc = V4L2_PIX_FMT_UYVY,
444 .name = "UYVY 16bit",
445 .bits_per_sample = 16,
446 .packing = PXA_MBUS_PACKING_EXTEND16,
447 .order = PXA_MBUS_ORDER_LE,
448 .layout = PXA_MBUS_LAYOUT_PACKED,
449 },
450 }, {
451 .code = MEDIA_BUS_FMT_VYUY8_1X16,
452 .fmt = {
453 .fourcc = V4L2_PIX_FMT_VYUY,
454 .name = "VYUY 16bit",
455 .bits_per_sample = 16,
456 .packing = PXA_MBUS_PACKING_EXTEND16,
457 .order = PXA_MBUS_ORDER_LE,
458 .layout = PXA_MBUS_LAYOUT_PACKED,
459 },
460 }, {
461 .code = MEDIA_BUS_FMT_YUYV8_1X16,
462 .fmt = {
463 .fourcc = V4L2_PIX_FMT_YUYV,
464 .name = "YUYV 16bit",
465 .bits_per_sample = 16,
466 .packing = PXA_MBUS_PACKING_EXTEND16,
467 .order = PXA_MBUS_ORDER_LE,
468 .layout = PXA_MBUS_LAYOUT_PACKED,
469 },
470 }, {
471 .code = MEDIA_BUS_FMT_YVYU8_1X16,
472 .fmt = {
473 .fourcc = V4L2_PIX_FMT_YVYU,
474 .name = "YVYU 16bit",
475 .bits_per_sample = 16,
476 .packing = PXA_MBUS_PACKING_EXTEND16,
477 .order = PXA_MBUS_ORDER_LE,
478 .layout = PXA_MBUS_LAYOUT_PACKED,
479 },
480 }, {
481 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
482 .fmt = {
483 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
484 .name = "Bayer 10 BGGR DPCM 8",
485 .bits_per_sample = 8,
486 .packing = PXA_MBUS_PACKING_NONE,
487 .order = PXA_MBUS_ORDER_LE,
488 .layout = PXA_MBUS_LAYOUT_PACKED,
489 },
490 }, {
491 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
492 .fmt = {
493 .fourcc = V4L2_PIX_FMT_SGBRG10,
494 .name = "Bayer 10 GBRG",
495 .bits_per_sample = 10,
496 .packing = PXA_MBUS_PACKING_EXTEND16,
497 .order = PXA_MBUS_ORDER_LE,
498 .layout = PXA_MBUS_LAYOUT_PACKED,
499 },
500 }, {
501 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
502 .fmt = {
503 .fourcc = V4L2_PIX_FMT_SGRBG10,
504 .name = "Bayer 10 GRBG",
505 .bits_per_sample = 10,
506 .packing = PXA_MBUS_PACKING_EXTEND16,
507 .order = PXA_MBUS_ORDER_LE,
508 .layout = PXA_MBUS_LAYOUT_PACKED,
509 },
510 }, {
511 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
512 .fmt = {
513 .fourcc = V4L2_PIX_FMT_SRGGB10,
514 .name = "Bayer 10 RGGB",
515 .bits_per_sample = 10,
516 .packing = PXA_MBUS_PACKING_EXTEND16,
517 .order = PXA_MBUS_ORDER_LE,
518 .layout = PXA_MBUS_LAYOUT_PACKED,
519 },
520 }, {
521 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
522 .fmt = {
523 .fourcc = V4L2_PIX_FMT_SBGGR12,
524 .name = "Bayer 12 BGGR",
525 .bits_per_sample = 12,
526 .packing = PXA_MBUS_PACKING_EXTEND16,
527 .order = PXA_MBUS_ORDER_LE,
528 .layout = PXA_MBUS_LAYOUT_PACKED,
529 },
530 }, {
531 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
532 .fmt = {
533 .fourcc = V4L2_PIX_FMT_SGBRG12,
534 .name = "Bayer 12 GBRG",
535 .bits_per_sample = 12,
536 .packing = PXA_MBUS_PACKING_EXTEND16,
537 .order = PXA_MBUS_ORDER_LE,
538 .layout = PXA_MBUS_LAYOUT_PACKED,
539 },
540 }, {
541 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
542 .fmt = {
543 .fourcc = V4L2_PIX_FMT_SGRBG12,
544 .name = "Bayer 12 GRBG",
545 .bits_per_sample = 12,
546 .packing = PXA_MBUS_PACKING_EXTEND16,
547 .order = PXA_MBUS_ORDER_LE,
548 .layout = PXA_MBUS_LAYOUT_PACKED,
549 },
550 }, {
551 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
552 .fmt = {
553 .fourcc = V4L2_PIX_FMT_SRGGB12,
554 .name = "Bayer 12 RGGB",
555 .bits_per_sample = 12,
556 .packing = PXA_MBUS_PACKING_EXTEND16,
557 .order = PXA_MBUS_ORDER_LE,
558 .layout = PXA_MBUS_LAYOUT_PACKED,
559 },
560 },
561 };
562
563 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
564 {
565 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
566 return width * mf->bits_per_sample / 8;
567
568 switch (mf->packing) {
569 case PXA_MBUS_PACKING_NONE:
570 return width * mf->bits_per_sample / 8;
571 case PXA_MBUS_PACKING_2X8_PADHI:
572 case PXA_MBUS_PACKING_EXTEND16:
573 return width * 2;
574 }
575 return -EINVAL;
576 }
577
578 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
579 u32 bytes_per_line, u32 height)
580 {
581 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
582 return bytes_per_line * height;
583
584 switch (mf->packing) {
585 case PXA_MBUS_PACKING_2X8_PADHI:
586 return bytes_per_line * height * 2;
587 default:
588 return -EINVAL;
589 }
590 }
591
592 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
593 u32 code,
594 const struct pxa_mbus_lookup *lookup,
595 int n)
596 {
597 int i;
598
599 for (i = 0; i < n; i++)
600 if (lookup[i].code == code)
601 return &lookup[i].fmt;
602
603 return NULL;
604 }
605
606 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
607 u32 code)
608 {
609 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
610 }
611
612 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
613 unsigned int flags)
614 {
615 unsigned long common_flags;
616 bool hsync = true, vsync = true, pclk, data, mode;
617 bool mipi_lanes, mipi_clock;
618
619 common_flags = cfg->flags & flags;
620
621 switch (cfg->type) {
622 case V4L2_MBUS_PARALLEL:
623 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
624 V4L2_MBUS_HSYNC_ACTIVE_LOW);
625 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
626 V4L2_MBUS_VSYNC_ACTIVE_LOW);
627 /* fall through */
628 case V4L2_MBUS_BT656:
629 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
630 V4L2_MBUS_PCLK_SAMPLE_FALLING);
631 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
632 V4L2_MBUS_DATA_ACTIVE_LOW);
633 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
634 return (!hsync || !vsync || !pclk || !data || !mode) ?
635 0 : common_flags;
636 case V4L2_MBUS_CSI2:
637 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
638 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
639 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
640 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
641 default:
642 WARN_ON(1);
643 return -EINVAL;
644 }
645 return 0;
646 }
647
648 /**
649 * struct soc_camera_format_xlate - match between host and sensor formats
650 * @code: code of a sensor provided format
651 * @host_fmt: host format after host translation from code
652 *
653 * Host and sensor translation structure. Used in table of host and sensor
654 * formats matchings in soc_camera_device. A host can override the generic list
655 * generation by implementing get_formats(), and use it for format checks and
656 * format setup.
657 */
658 struct soc_camera_format_xlate {
659 u32 code;
660 const struct pxa_mbus_pixelfmt *host_fmt;
661 };
662
663 /*
664 * Structures
665 */
666 enum pxa_camera_active_dma {
667 DMA_Y = 0x1,
668 DMA_U = 0x2,
669 DMA_V = 0x4,
670 };
671
672 /* buffer for one video frame */
673 struct pxa_buffer {
674 /* common v4l buffer stuff -- must be first */
675 struct vb2_v4l2_buffer vbuf;
676 struct list_head queue;
677 u32 code;
678 int nb_planes;
679 /* our descriptor lists for Y, U and V channels */
680 struct dma_async_tx_descriptor *descs[3];
681 dma_cookie_t cookie[3];
682 struct scatterlist *sg[3];
683 int sg_len[3];
684 size_t plane_sizes[3];
685 int inwork;
686 enum pxa_camera_active_dma active_dma;
687 };
688
689 struct pxa_camera_dev {
690 struct v4l2_device v4l2_dev;
691 struct video_device vdev;
692 struct v4l2_async_notifier notifier;
693 struct vb2_queue vb2_vq;
694 struct v4l2_subdev *sensor;
695 struct soc_camera_format_xlate *user_formats;
696 const struct soc_camera_format_xlate *current_fmt;
697 struct v4l2_pix_format current_pix;
698
699 struct v4l2_async_subdev asd;
700 struct v4l2_async_subdev *asds[1];
701
702 /*
703 * PXA27x is only supposed to handle one camera on its Quick Capture
704 * interface. If anyone ever builds hardware to enable more than
705 * one camera, they will have to modify this driver too
706 */
707 struct clk *clk;
708
709 unsigned int irq;
710 void __iomem *base;
711
712 int channels;
713 struct dma_chan *dma_chans[3];
714
715 struct pxacamera_platform_data *pdata;
716 struct resource *res;
717 unsigned long platform_flags;
718 unsigned long ciclk;
719 unsigned long mclk;
720 u32 mclk_divisor;
721 struct v4l2_clk *mclk_clk;
722 u16 width_flags; /* max 10 bits */
723
724 struct list_head capture;
725
726 spinlock_t lock;
727 struct mutex mlock;
728 unsigned int buf_sequence;
729
730 struct pxa_buffer *active;
731 struct tasklet_struct task_eof;
732
733 u32 save_cicr[5];
734 };
735
736 struct pxa_cam {
737 unsigned long flags;
738 };
739
740 static const char *pxa_cam_driver_description = "PXA_Camera";
741
742 /*
743 * Format translation functions
744 */
745 static const struct soc_camera_format_xlate
746 *pxa_mbus_xlate_by_fourcc(struct soc_camera_format_xlate *user_formats,
747 unsigned int fourcc)
748 {
749 unsigned int i;
750
751 for (i = 0; user_formats[i].code; i++)
752 if (user_formats[i].host_fmt->fourcc == fourcc)
753 return user_formats + i;
754 return NULL;
755 }
756
757 static struct soc_camera_format_xlate *pxa_mbus_build_fmts_xlate(
758 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
759 int (*get_formats)(struct v4l2_device *, unsigned int,
760 struct soc_camera_format_xlate *xlate))
761 {
762 unsigned int i, fmts = 0, raw_fmts = 0;
763 int ret;
764 struct v4l2_subdev_mbus_code_enum code = {
765 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
766 };
767 struct soc_camera_format_xlate *user_formats;
768
769 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
770 raw_fmts++;
771 code.index++;
772 }
773
774 /*
775 * First pass - only count formats this host-sensor
776 * configuration can provide
777 */
778 for (i = 0; i < raw_fmts; i++) {
779 ret = get_formats(v4l2_dev, i, NULL);
780 if (ret < 0)
781 return ERR_PTR(ret);
782 fmts += ret;
783 }
784
785 if (!fmts)
786 return ERR_PTR(-ENXIO);
787
788 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
789 if (!user_formats)
790 return ERR_PTR(-ENOMEM);
791
792 /* Second pass - actually fill data formats */
793 fmts = 0;
794 for (i = 0; i < raw_fmts; i++) {
795 ret = get_formats(v4l2_dev, i, user_formats + fmts);
796 if (ret < 0)
797 goto egfmt;
798 fmts += ret;
799 }
800 user_formats[fmts].code = 0;
801
802 return user_formats;
803 egfmt:
804 kfree(user_formats);
805 return ERR_PTR(ret);
806 }
807
808 /*
809 * Videobuf operations
810 */
811 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
812 {
813 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
814
815 return container_of(vbuf, struct pxa_buffer, vbuf);
816 }
817
818 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
819 {
820 return pcdev->v4l2_dev.dev;
821 }
822
823 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
824 {
825 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
826 }
827
828 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
829 enum pxa_camera_active_dma act_dma);
830
831 static void pxa_camera_dma_irq_y(void *data)
832 {
833 struct pxa_camera_dev *pcdev = data;
834
835 pxa_camera_dma_irq(pcdev, DMA_Y);
836 }
837
838 static void pxa_camera_dma_irq_u(void *data)
839 {
840 struct pxa_camera_dev *pcdev = data;
841
842 pxa_camera_dma_irq(pcdev, DMA_U);
843 }
844
845 static void pxa_camera_dma_irq_v(void *data)
846 {
847 struct pxa_camera_dev *pcdev = data;
848
849 pxa_camera_dma_irq(pcdev, DMA_V);
850 }
851
852 /**
853 * pxa_init_dma_channel - init dma descriptors
854 * @pcdev: pxa camera device
855 * @vb: videobuffer2 buffer
856 * @dma: dma video buffer
857 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
858 * @cibr: camera Receive Buffer Register
859 *
860 * Prepares the pxa dma descriptors to transfer one camera channel.
861 *
862 * Returns 0 if success or -ENOMEM if no memory is available
863 */
864 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
865 struct pxa_buffer *buf, int channel,
866 struct scatterlist *sg, int sglen)
867 {
868 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
869 struct dma_async_tx_descriptor *tx;
870
871 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
872 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
873 if (!tx) {
874 dev_err(pcdev_to_dev(pcdev),
875 "dmaengine_prep_slave_sg failed\n");
876 goto fail;
877 }
878
879 tx->callback_param = pcdev;
880 switch (channel) {
881 case 0:
882 tx->callback = pxa_camera_dma_irq_y;
883 break;
884 case 1:
885 tx->callback = pxa_camera_dma_irq_u;
886 break;
887 case 2:
888 tx->callback = pxa_camera_dma_irq_v;
889 break;
890 }
891
892 buf->descs[channel] = tx;
893 return 0;
894 fail:
895 dev_dbg(pcdev_to_dev(pcdev),
896 "%s (vb=%p) dma_tx=%p\n",
897 __func__, buf, tx);
898
899 return -ENOMEM;
900 }
901
902 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
903 struct pxa_buffer *buf)
904 {
905 buf->active_dma = DMA_Y;
906 if (buf->nb_planes == 3)
907 buf->active_dma |= DMA_U | DMA_V;
908 }
909
910 /**
911 * pxa_dma_start_channels - start DMA channel for active buffer
912 * @pcdev: pxa camera device
913 *
914 * Initialize DMA channels to the beginning of the active video buffer, and
915 * start these channels.
916 */
917 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
918 {
919 int i;
920
921 for (i = 0; i < pcdev->channels; i++) {
922 dev_dbg(pcdev_to_dev(pcdev),
923 "%s (channel=%d)\n", __func__, i);
924 dma_async_issue_pending(pcdev->dma_chans[i]);
925 }
926 }
927
928 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
929 {
930 int i;
931
932 for (i = 0; i < pcdev->channels; i++) {
933 dev_dbg(pcdev_to_dev(pcdev),
934 "%s (channel=%d)\n", __func__, i);
935 dmaengine_terminate_all(pcdev->dma_chans[i]);
936 }
937 }
938
939 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
940 struct pxa_buffer *buf)
941 {
942 int i;
943
944 for (i = 0; i < pcdev->channels; i++) {
945 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
946 dev_dbg(pcdev_to_dev(pcdev),
947 "%s (channel=%d) : submit vb=%p cookie=%d\n",
948 __func__, i, buf, buf->descs[i]->cookie);
949 }
950 }
951
952 /**
953 * pxa_camera_start_capture - start video capturing
954 * @pcdev: camera device
955 *
956 * Launch capturing. DMA channels should not be active yet. They should get
957 * activated at the end of frame interrupt, to capture only whole frames, and
958 * never begin the capture of a partial frame.
959 */
960 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
961 {
962 unsigned long cicr0;
963
964 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
965 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
966 /* Enable End-Of-Frame Interrupt */
967 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
968 cicr0 &= ~CICR0_EOFM;
969 __raw_writel(cicr0, pcdev->base + CICR0);
970 }
971
972 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
973 {
974 unsigned long cicr0;
975
976 pxa_dma_stop_channels(pcdev);
977
978 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
979 __raw_writel(cicr0, pcdev->base + CICR0);
980
981 pcdev->active = NULL;
982 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
983 }
984
985 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
986 struct pxa_buffer *buf,
987 enum vb2_buffer_state state)
988 {
989 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
990 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
991
992 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
993 list_del_init(&buf->queue);
994 vb->timestamp = ktime_get_ns();
995 vbuf->sequence = pcdev->buf_sequence++;
996 vbuf->field = V4L2_FIELD_NONE;
997 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
998 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
999 __func__, buf);
1000
1001 if (list_empty(&pcdev->capture)) {
1002 pxa_camera_stop_capture(pcdev);
1003 return;
1004 }
1005
1006 pcdev->active = list_entry(pcdev->capture.next,
1007 struct pxa_buffer, queue);
1008 }
1009
1010 /**
1011 * pxa_camera_check_link_miss - check missed DMA linking
1012 * @pcdev: camera device
1013 *
1014 * The DMA chaining is done with DMA running. This means a tiny temporal window
1015 * remains, where a buffer is queued on the chain, while the chain is already
1016 * stopped. This means the tailed buffer would never be transferred by DMA.
1017 * This function restarts the capture for this corner case, where :
1018 * - DADR() == DADDR_STOP
1019 * - a videobuffer is queued on the pcdev->capture list
1020 *
1021 * Please check the "DMA hot chaining timeslice issue" in
1022 * Documentation/video4linux/pxa_camera.txt
1023 *
1024 * Context: should only be called within the dma irq handler
1025 */
1026 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
1027 dma_cookie_t last_submitted,
1028 dma_cookie_t last_issued)
1029 {
1030 bool is_dma_stopped = last_submitted != last_issued;
1031
1032 dev_dbg(pcdev_to_dev(pcdev),
1033 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1034 __func__, pcdev->active, is_dma_stopped);
1035
1036 if (pcdev->active && is_dma_stopped)
1037 pxa_camera_start_capture(pcdev);
1038 }
1039
1040 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1041 enum pxa_camera_active_dma act_dma)
1042 {
1043 struct pxa_buffer *buf, *last_buf;
1044 unsigned long flags;
1045 u32 camera_status, overrun;
1046 int chan;
1047 enum dma_status last_status;
1048 dma_cookie_t last_issued;
1049
1050 spin_lock_irqsave(&pcdev->lock, flags);
1051
1052 camera_status = __raw_readl(pcdev->base + CISR);
1053 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1054 camera_status, act_dma);
1055 overrun = CISR_IFO_0;
1056 if (pcdev->channels == 3)
1057 overrun |= CISR_IFO_1 | CISR_IFO_2;
1058
1059 /*
1060 * pcdev->active should not be NULL in DMA irq handler.
1061 *
1062 * But there is one corner case : if capture was stopped due to an
1063 * overrun of channel 1, and at that same channel 2 was completed.
1064 *
1065 * When handling the overrun in DMA irq for channel 1, we'll stop the
1066 * capture and restart it (and thus set pcdev->active to NULL). But the
1067 * DMA irq handler will already be pending for channel 2. So on entering
1068 * the DMA irq handler for channel 2 there will be no active buffer, yet
1069 * that is normal.
1070 */
1071 if (!pcdev->active)
1072 goto out;
1073
1074 buf = pcdev->active;
1075 WARN_ON(buf->inwork || list_empty(&buf->queue));
1076
1077 /*
1078 * It's normal if the last frame creates an overrun, as there
1079 * are no more DMA descriptors to fetch from QCI fifos
1080 */
1081 switch (act_dma) {
1082 case DMA_U:
1083 chan = 1;
1084 break;
1085 case DMA_V:
1086 chan = 2;
1087 break;
1088 default:
1089 chan = 0;
1090 break;
1091 }
1092 last_buf = list_entry(pcdev->capture.prev,
1093 struct pxa_buffer, queue);
1094 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1095 last_buf->cookie[chan],
1096 NULL, &last_issued);
1097 if (camera_status & overrun &&
1098 last_status != DMA_COMPLETE) {
1099 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1100 camera_status);
1101 pxa_camera_stop_capture(pcdev);
1102 list_for_each_entry(buf, &pcdev->capture, queue)
1103 pxa_dma_add_tail_buf(pcdev, buf);
1104 pxa_camera_start_capture(pcdev);
1105 goto out;
1106 }
1107 buf->active_dma &= ~act_dma;
1108 if (!buf->active_dma) {
1109 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1110 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1111 last_issued);
1112 }
1113
1114 out:
1115 spin_unlock_irqrestore(&pcdev->lock, flags);
1116 }
1117
1118 static u32 mclk_get_divisor(struct platform_device *pdev,
1119 struct pxa_camera_dev *pcdev)
1120 {
1121 unsigned long mclk = pcdev->mclk;
1122 u32 div;
1123 unsigned long lcdclk;
1124
1125 lcdclk = clk_get_rate(pcdev->clk);
1126 pcdev->ciclk = lcdclk;
1127
1128 /* mclk <= ciclk / 4 (27.4.2) */
1129 if (mclk > lcdclk / 4) {
1130 mclk = lcdclk / 4;
1131 dev_warn(&pdev->dev,
1132 "Limiting master clock to %lu\n", mclk);
1133 }
1134
1135 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1136 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1137
1138 /* If we're not supplying MCLK, leave it at 0 */
1139 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1140 pcdev->mclk = lcdclk / (2 * (div + 1));
1141
1142 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1143 lcdclk, mclk, div);
1144
1145 return div;
1146 }
1147
1148 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1149 unsigned long pclk)
1150 {
1151 /* We want a timeout > 1 pixel time, not ">=" */
1152 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1153
1154 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1155 }
1156
1157 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1158 {
1159 u32 cicr4 = 0;
1160
1161 /* disable all interrupts */
1162 __raw_writel(0x3ff, pcdev->base + CICR0);
1163
1164 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1165 cicr4 |= CICR4_PCLK_EN;
1166 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1167 cicr4 |= CICR4_MCLK_EN;
1168 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1169 cicr4 |= CICR4_PCP;
1170 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1171 cicr4 |= CICR4_HSP;
1172 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1173 cicr4 |= CICR4_VSP;
1174
1175 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1176
1177 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1178 /* Initialise the timeout under the assumption pclk = mclk */
1179 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1180 else
1181 /* "Safe default" - 13MHz */
1182 recalculate_fifo_timeout(pcdev, 13000000);
1183
1184 clk_prepare_enable(pcdev->clk);
1185 }
1186
1187 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1188 {
1189 clk_disable_unprepare(pcdev->clk);
1190 }
1191
1192 static void pxa_camera_eof(unsigned long arg)
1193 {
1194 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1195 unsigned long cifr;
1196 struct pxa_buffer *buf;
1197
1198 dev_dbg(pcdev_to_dev(pcdev),
1199 "Camera interrupt status 0x%x\n",
1200 __raw_readl(pcdev->base + CISR));
1201
1202 /* Reset the FIFOs */
1203 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1204 __raw_writel(cifr, pcdev->base + CIFR);
1205
1206 pcdev->active = list_first_entry(&pcdev->capture,
1207 struct pxa_buffer, queue);
1208 buf = pcdev->active;
1209 pxa_videobuf_set_actdma(pcdev, buf);
1210
1211 pxa_dma_start_channels(pcdev);
1212 }
1213
1214 static irqreturn_t pxa_camera_irq(int irq, void *data)
1215 {
1216 struct pxa_camera_dev *pcdev = data;
1217 unsigned long status, cicr0;
1218
1219 status = __raw_readl(pcdev->base + CISR);
1220 dev_dbg(pcdev_to_dev(pcdev),
1221 "Camera interrupt status 0x%lx\n", status);
1222
1223 if (!status)
1224 return IRQ_NONE;
1225
1226 __raw_writel(status, pcdev->base + CISR);
1227
1228 if (status & CISR_EOF) {
1229 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1230 __raw_writel(cicr0, pcdev->base + CICR0);
1231 tasklet_schedule(&pcdev->task_eof);
1232 }
1233
1234 return IRQ_HANDLED;
1235 }
1236
1237 static int test_platform_param(struct pxa_camera_dev *pcdev,
1238 unsigned char buswidth, unsigned long *flags)
1239 {
1240 /*
1241 * Platform specified synchronization and pixel clock polarities are
1242 * only a recommendation and are only used during probing. The PXA270
1243 * quick capture interface supports both.
1244 */
1245 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1246 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1247 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1248 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1249 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1250 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1251 V4L2_MBUS_DATA_ACTIVE_HIGH |
1252 V4L2_MBUS_PCLK_SAMPLE_RISING |
1253 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1254
1255 /* If requested data width is supported by the platform, use it */
1256 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1257 return 0;
1258
1259 return -EINVAL;
1260 }
1261
1262 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1263 unsigned long flags, __u32 pixfmt)
1264 {
1265 unsigned long dw, bpp;
1266 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1267 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1268
1269 if (ret < 0)
1270 y_skip_top = 0;
1271
1272 /*
1273 * Datawidth is now guaranteed to be equal to one of the three values.
1274 * We fix bit-per-pixel equal to data-width...
1275 */
1276 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1277 case 10:
1278 dw = 4;
1279 bpp = 0x40;
1280 break;
1281 case 9:
1282 dw = 3;
1283 bpp = 0x20;
1284 break;
1285 default:
1286 /*
1287 * Actually it can only be 8 now,
1288 * default is just to silence compiler warnings
1289 */
1290 case 8:
1291 dw = 2;
1292 bpp = 0;
1293 }
1294
1295 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1296 cicr4 |= CICR4_PCLK_EN;
1297 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1298 cicr4 |= CICR4_MCLK_EN;
1299 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1300 cicr4 |= CICR4_PCP;
1301 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1302 cicr4 |= CICR4_HSP;
1303 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1304 cicr4 |= CICR4_VSP;
1305
1306 cicr0 = __raw_readl(pcdev->base + CICR0);
1307 if (cicr0 & CICR0_ENB)
1308 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1309
1310 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1311
1312 switch (pixfmt) {
1313 case V4L2_PIX_FMT_YUV422P:
1314 pcdev->channels = 3;
1315 cicr1 |= CICR1_YCBCR_F;
1316 /*
1317 * Normally, pxa bus wants as input UYVY format. We allow all
1318 * reorderings of the YUV422 format, as no processing is done,
1319 * and the YUV stream is just passed through without any
1320 * transformation. Note that UYVY is the only format that
1321 * should be used if pxa framebuffer Overlay2 is used.
1322 */
1323 /* fall through */
1324 case V4L2_PIX_FMT_UYVY:
1325 case V4L2_PIX_FMT_VYUY:
1326 case V4L2_PIX_FMT_YUYV:
1327 case V4L2_PIX_FMT_YVYU:
1328 cicr1 |= CICR1_COLOR_SP_VAL(2);
1329 break;
1330 case V4L2_PIX_FMT_RGB555:
1331 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1332 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1333 break;
1334 case V4L2_PIX_FMT_RGB565:
1335 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1336 break;
1337 }
1338
1339 cicr2 = 0;
1340 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1341 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1342 cicr4 |= pcdev->mclk_divisor;
1343
1344 __raw_writel(cicr1, pcdev->base + CICR1);
1345 __raw_writel(cicr2, pcdev->base + CICR2);
1346 __raw_writel(cicr3, pcdev->base + CICR3);
1347 __raw_writel(cicr4, pcdev->base + CICR4);
1348
1349 /* CIF interrupts are not used, only DMA */
1350 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1351 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1352 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1353 __raw_writel(cicr0, pcdev->base + CICR0);
1354 }
1355
1356 /*
1357 * Videobuf2 section
1358 */
1359 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1360 {
1361 int i;
1362
1363 for (i = 0; i < 3 && buf->descs[i]; i++) {
1364 dmaengine_desc_free(buf->descs[i]);
1365 kfree(buf->sg[i]);
1366 buf->descs[i] = NULL;
1367 buf->sg[i] = NULL;
1368 buf->sg_len[i] = 0;
1369 buf->plane_sizes[i] = 0;
1370 }
1371 buf->nb_planes = 0;
1372 }
1373
1374 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1375 struct pxa_buffer *buf)
1376 {
1377 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1378 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1379 int nb_channels = pcdev->channels;
1380 int i, ret = 0;
1381 unsigned long size = vb2_plane_size(vb, 0);
1382
1383 switch (nb_channels) {
1384 case 1:
1385 buf->plane_sizes[0] = size;
1386 break;
1387 case 3:
1388 buf->plane_sizes[0] = size / 2;
1389 buf->plane_sizes[1] = size / 4;
1390 buf->plane_sizes[2] = size / 4;
1391 break;
1392 default:
1393 return -EINVAL;
1394 };
1395 buf->nb_planes = nb_channels;
1396
1397 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1398 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1399 if (ret < 0) {
1400 dev_err(pcdev_to_dev(pcdev),
1401 "sg_split failed: %d\n", ret);
1402 return ret;
1403 }
1404 for (i = 0; i < nb_channels; i++) {
1405 ret = pxa_init_dma_channel(pcdev, buf, i,
1406 buf->sg[i], buf->sg_len[i]);
1407 if (ret) {
1408 pxa_buffer_cleanup(buf);
1409 return ret;
1410 }
1411 }
1412 INIT_LIST_HEAD(&buf->queue);
1413
1414 return ret;
1415 }
1416
1417 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1418 {
1419 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1420 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1421
1422 dev_dbg(pcdev_to_dev(pcdev),
1423 "%s(vb=%p)\n", __func__, vb);
1424 pxa_buffer_cleanup(buf);
1425 }
1426
1427 static void pxac_vb2_queue(struct vb2_buffer *vb)
1428 {
1429 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1430 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1431
1432 dev_dbg(pcdev_to_dev(pcdev),
1433 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1434 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1435 pcdev->active);
1436
1437 list_add_tail(&buf->queue, &pcdev->capture);
1438
1439 pxa_dma_add_tail_buf(pcdev, buf);
1440 }
1441
1442 /*
1443 * Please check the DMA prepared buffer structure in :
1444 * Documentation/video4linux/pxa_camera.txt
1445 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1446 * modification while DMA chain is running will work anyway.
1447 */
1448 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1449 {
1450 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1451 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1452 int ret = 0;
1453
1454 switch (pcdev->channels) {
1455 case 1:
1456 case 3:
1457 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1458 break;
1459 default:
1460 return -EINVAL;
1461 }
1462
1463 dev_dbg(pcdev_to_dev(pcdev),
1464 "%s (vb=%p) nb_channels=%d size=%lu\n",
1465 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1466
1467 WARN_ON(!pcdev->current_fmt);
1468
1469 #ifdef DEBUG
1470 /*
1471 * This can be useful if you want to see if we actually fill
1472 * the buffer with something
1473 */
1474 for (i = 0; i < vb->num_planes; i++)
1475 memset((void *)vb2_plane_vaddr(vb, i),
1476 0xaa, vb2_get_plane_payload(vb, i));
1477 #endif
1478
1479 /*
1480 * I think, in buf_prepare you only have to protect global data,
1481 * the actual buffer is yours
1482 */
1483 buf->inwork = 0;
1484 pxa_videobuf_set_actdma(pcdev, buf);
1485
1486 return ret;
1487 }
1488
1489 static int pxac_vb2_init(struct vb2_buffer *vb)
1490 {
1491 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1492 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1493
1494 dev_dbg(pcdev_to_dev(pcdev),
1495 "%s(nb_channels=%d)\n",
1496 __func__, pcdev->channels);
1497
1498 return pxa_buffer_init(pcdev, buf);
1499 }
1500
1501 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1502 unsigned int *nbufs,
1503 unsigned int *num_planes, unsigned int sizes[],
1504 struct device *alloc_devs[])
1505 {
1506 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1507 int size = pcdev->current_pix.sizeimage;
1508
1509 dev_dbg(pcdev_to_dev(pcdev),
1510 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1511 __func__, vq, *nbufs, *num_planes, size);
1512 /*
1513 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1514 * format, even if there are 3 planes Y, U and V, we reply there is only
1515 * one plane, containing Y, U and V data, one after the other.
1516 */
1517 if (*num_planes)
1518 return sizes[0] < size ? -EINVAL : 0;
1519
1520 *num_planes = 1;
1521 switch (pcdev->channels) {
1522 case 1:
1523 case 3:
1524 sizes[0] = size;
1525 break;
1526 default:
1527 return -EINVAL;
1528 }
1529
1530 if (!*nbufs)
1531 *nbufs = 1;
1532
1533 return 0;
1534 }
1535
1536 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1537 {
1538 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1539
1540 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1541 __func__, count, pcdev->active);
1542
1543 pcdev->buf_sequence = 0;
1544 if (!pcdev->active)
1545 pxa_camera_start_capture(pcdev);
1546
1547 return 0;
1548 }
1549
1550 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1551 {
1552 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1553 struct pxa_buffer *buf, *tmp;
1554
1555 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1556 __func__, pcdev->active);
1557 pxa_camera_stop_capture(pcdev);
1558
1559 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1560 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1561 }
1562
1563 static const struct vb2_ops pxac_vb2_ops = {
1564 .queue_setup = pxac_vb2_queue_setup,
1565 .buf_init = pxac_vb2_init,
1566 .buf_prepare = pxac_vb2_prepare,
1567 .buf_queue = pxac_vb2_queue,
1568 .buf_cleanup = pxac_vb2_cleanup,
1569 .start_streaming = pxac_vb2_start_streaming,
1570 .stop_streaming = pxac_vb2_stop_streaming,
1571 .wait_prepare = vb2_ops_wait_prepare,
1572 .wait_finish = vb2_ops_wait_finish,
1573 };
1574
1575 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1576 {
1577 int ret;
1578 struct vb2_queue *vq = &pcdev->vb2_vq;
1579
1580 memset(vq, 0, sizeof(*vq));
1581 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1582 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1583 vq->drv_priv = pcdev;
1584 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1585 vq->buf_struct_size = sizeof(struct pxa_buffer);
1586 vq->dev = pcdev->v4l2_dev.dev;
1587
1588 vq->ops = &pxac_vb2_ops;
1589 vq->mem_ops = &vb2_dma_sg_memops;
1590 vq->lock = &pcdev->mlock;
1591
1592 ret = vb2_queue_init(vq);
1593 dev_dbg(pcdev_to_dev(pcdev),
1594 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1595
1596 return ret;
1597 }
1598
1599 /*
1600 * Video ioctls section
1601 */
1602 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1603 {
1604 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1605 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1606 unsigned long bus_flags, common_flags;
1607 int ret;
1608
1609 ret = test_platform_param(pcdev,
1610 pcdev->current_fmt->host_fmt->bits_per_sample,
1611 &bus_flags);
1612 if (ret < 0)
1613 return ret;
1614
1615 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1616 if (!ret) {
1617 common_flags = pxa_mbus_config_compatible(&cfg,
1618 bus_flags);
1619 if (!common_flags) {
1620 dev_warn(pcdev_to_dev(pcdev),
1621 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1622 cfg.flags, bus_flags);
1623 return -EINVAL;
1624 }
1625 } else if (ret != -ENOIOCTLCMD) {
1626 return ret;
1627 } else {
1628 common_flags = bus_flags;
1629 }
1630
1631 pcdev->channels = 1;
1632
1633 /* Make choises, based on platform preferences */
1634 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1635 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1636 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1637 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1638 else
1639 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1640 }
1641
1642 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1643 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1644 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1645 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1646 else
1647 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1648 }
1649
1650 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1651 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1652 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1653 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1654 else
1655 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1656 }
1657
1658 cfg.flags = common_flags;
1659 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1660 if (ret < 0 && ret != -ENOIOCTLCMD) {
1661 dev_dbg(pcdev_to_dev(pcdev),
1662 "camera s_mbus_config(0x%lx) returned %d\n",
1663 common_flags, ret);
1664 return ret;
1665 }
1666
1667 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1668
1669 return 0;
1670 }
1671
1672 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1673 unsigned char buswidth)
1674 {
1675 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1676 unsigned long bus_flags, common_flags;
1677 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1678
1679 if (ret < 0)
1680 return ret;
1681
1682 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1683 if (!ret) {
1684 common_flags = pxa_mbus_config_compatible(&cfg,
1685 bus_flags);
1686 if (!common_flags) {
1687 dev_warn(pcdev_to_dev(pcdev),
1688 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1689 cfg.flags, bus_flags);
1690 return -EINVAL;
1691 }
1692 } else if (ret == -ENOIOCTLCMD) {
1693 ret = 0;
1694 }
1695
1696 return ret;
1697 }
1698
1699 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1700 {
1701 .fourcc = V4L2_PIX_FMT_YUV422P,
1702 .name = "Planar YUV422 16 bit",
1703 .bits_per_sample = 8,
1704 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1705 .order = PXA_MBUS_ORDER_LE,
1706 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1707 },
1708 };
1709
1710 /* This will be corrected as we get more formats */
1711 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1712 {
1713 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1714 (fmt->bits_per_sample == 8 &&
1715 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1716 (fmt->bits_per_sample > 8 &&
1717 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1718 }
1719
1720 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1721 unsigned int idx,
1722 struct soc_camera_format_xlate *xlate)
1723 {
1724 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1725 int formats = 0, ret;
1726 struct v4l2_subdev_mbus_code_enum code = {
1727 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1728 .index = idx,
1729 };
1730 const struct pxa_mbus_pixelfmt *fmt;
1731
1732 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1733 if (ret < 0)
1734 /* No more formats */
1735 return 0;
1736
1737 fmt = pxa_mbus_get_fmtdesc(code.code);
1738 if (!fmt) {
1739 dev_err(pcdev_to_dev(pcdev),
1740 "Invalid format code #%u: %d\n", idx, code.code);
1741 return 0;
1742 }
1743
1744 /* This also checks support for the requested bits-per-sample */
1745 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1746 if (ret < 0)
1747 return 0;
1748
1749 switch (code.code) {
1750 case MEDIA_BUS_FMT_UYVY8_2X8:
1751 formats++;
1752 if (xlate) {
1753 xlate->host_fmt = &pxa_camera_formats[0];
1754 xlate->code = code.code;
1755 xlate++;
1756 dev_dbg(pcdev_to_dev(pcdev),
1757 "Providing format %s using code %d\n",
1758 pxa_camera_formats[0].name, code.code);
1759 }
1760 /* fall through */
1761 case MEDIA_BUS_FMT_VYUY8_2X8:
1762 case MEDIA_BUS_FMT_YUYV8_2X8:
1763 case MEDIA_BUS_FMT_YVYU8_2X8:
1764 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1765 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1766 if (xlate)
1767 dev_dbg(pcdev_to_dev(pcdev),
1768 "Providing format %s packed\n",
1769 fmt->name);
1770 break;
1771 default:
1772 if (!pxa_camera_packing_supported(fmt))
1773 return 0;
1774 if (xlate)
1775 dev_dbg(pcdev_to_dev(pcdev),
1776 "Providing format %s in pass-through mode\n",
1777 fmt->name);
1778 break;
1779 }
1780
1781 /* Generic pass-through */
1782 formats++;
1783 if (xlate) {
1784 xlate->host_fmt = fmt;
1785 xlate->code = code.code;
1786 xlate++;
1787 }
1788
1789 return formats;
1790 }
1791
1792 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1793 {
1794 struct soc_camera_format_xlate *xlate;
1795
1796 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1797 pxa_camera_get_formats);
1798 if (IS_ERR(xlate))
1799 return PTR_ERR(xlate);
1800
1801 pcdev->user_formats = xlate;
1802 return 0;
1803 }
1804
1805 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1806 {
1807 kfree(pcdev->user_formats);
1808 }
1809
1810 static int pxa_camera_check_frame(u32 width, u32 height)
1811 {
1812 /* limit to pxa hardware capabilities */
1813 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1814 (width & 0x01);
1815 }
1816
1817 #ifdef CONFIG_VIDEO_ADV_DEBUG
1818 static int pxac_vidioc_g_register(struct file *file, void *priv,
1819 struct v4l2_dbg_register *reg)
1820 {
1821 struct pxa_camera_dev *pcdev = video_drvdata(file);
1822
1823 if (reg->reg > CIBR2)
1824 return -ERANGE;
1825
1826 reg->val = __raw_readl(pcdev->base + reg->reg);
1827 reg->size = sizeof(__u32);
1828 return 0;
1829 }
1830
1831 static int pxac_vidioc_s_register(struct file *file, void *priv,
1832 const struct v4l2_dbg_register *reg)
1833 {
1834 struct pxa_camera_dev *pcdev = video_drvdata(file);
1835
1836 if (reg->reg > CIBR2)
1837 return -ERANGE;
1838 if (reg->size != sizeof(__u32))
1839 return -EINVAL;
1840 __raw_writel(reg->val, pcdev->base + reg->reg);
1841 return 0;
1842 }
1843 #endif
1844
1845 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1846 struct v4l2_fmtdesc *f)
1847 {
1848 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1849 const struct pxa_mbus_pixelfmt *format;
1850 unsigned int idx;
1851
1852 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1853 if (f->index >= idx)
1854 return -EINVAL;
1855
1856 format = pcdev->user_formats[f->index].host_fmt;
1857 f->pixelformat = format->fourcc;
1858 return 0;
1859 }
1860
1861 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1862 struct v4l2_format *f)
1863 {
1864 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1865 struct v4l2_pix_format *pix = &f->fmt.pix;
1866
1867 pix->width = pcdev->current_pix.width;
1868 pix->height = pcdev->current_pix.height;
1869 pix->bytesperline = pcdev->current_pix.bytesperline;
1870 pix->sizeimage = pcdev->current_pix.sizeimage;
1871 pix->field = pcdev->current_pix.field;
1872 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1873 pix->colorspace = pcdev->current_pix.colorspace;
1874 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1875 pcdev->current_fmt->host_fmt->fourcc);
1876 return 0;
1877 }
1878
1879 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1880 struct v4l2_format *f)
1881 {
1882 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1883 const struct soc_camera_format_xlate *xlate;
1884 struct v4l2_pix_format *pix = &f->fmt.pix;
1885 struct v4l2_subdev_pad_config pad_cfg;
1886 struct v4l2_subdev_format format = {
1887 .which = V4L2_SUBDEV_FORMAT_TRY,
1888 };
1889 struct v4l2_mbus_framefmt *mf = &format.format;
1890 __u32 pixfmt = pix->pixelformat;
1891 int ret;
1892
1893 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1894 if (!xlate) {
1895 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1896 return -EINVAL;
1897 }
1898
1899 /*
1900 * Limit to pxa hardware capabilities. YUV422P planar format requires
1901 * images size to be a multiple of 16 bytes. If not, zeros will be
1902 * inserted between Y and U planes, and U and V planes, which violates
1903 * the YUV422P standard.
1904 */
1905 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1906 &pix->height, 32, 2048, 0,
1907 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1908
1909 v4l2_fill_mbus_format(mf, pix, xlate->code);
1910 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1911 if (ret < 0)
1912 return ret;
1913
1914 v4l2_fill_pix_format(pix, mf);
1915
1916 /* Only progressive video supported so far */
1917 switch (mf->field) {
1918 case V4L2_FIELD_ANY:
1919 case V4L2_FIELD_NONE:
1920 pix->field = V4L2_FIELD_NONE;
1921 break;
1922 default:
1923 /* TODO: support interlaced at least in pass-through mode */
1924 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1925 mf->field);
1926 return -EINVAL;
1927 }
1928
1929 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1930 if (ret < 0)
1931 return ret;
1932
1933 pix->bytesperline = ret;
1934 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1935 pix->height);
1936 if (ret < 0)
1937 return ret;
1938
1939 pix->sizeimage = ret;
1940 return 0;
1941 }
1942
1943 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1944 struct v4l2_format *f)
1945 {
1946 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1947 const struct soc_camera_format_xlate *xlate;
1948 struct v4l2_pix_format *pix = &f->fmt.pix;
1949 struct v4l2_subdev_format format = {
1950 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1951 };
1952 unsigned long flags;
1953 int ret, is_busy;
1954
1955 dev_dbg(pcdev_to_dev(pcdev),
1956 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1957 pix->width, pix->height, pix->pixelformat);
1958
1959 spin_lock_irqsave(&pcdev->lock, flags);
1960 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1961 spin_unlock_irqrestore(&pcdev->lock, flags);
1962
1963 if (is_busy)
1964 return -EBUSY;
1965
1966 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1967 if (ret)
1968 return ret;
1969
1970 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1971 pix->pixelformat);
1972 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1973 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1974 if (ret < 0) {
1975 dev_warn(pcdev_to_dev(pcdev),
1976 "Failed to configure for format %x\n",
1977 pix->pixelformat);
1978 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1979 dev_warn(pcdev_to_dev(pcdev),
1980 "Camera driver produced an unsupported frame %dx%d\n",
1981 pix->width, pix->height);
1982 return -EINVAL;
1983 }
1984
1985 pcdev->current_fmt = xlate;
1986 pcdev->current_pix = *pix;
1987
1988 ret = pxa_camera_set_bus_param(pcdev);
1989 return ret;
1990 }
1991
1992 static int pxac_vidioc_querycap(struct file *file, void *priv,
1993 struct v4l2_capability *cap)
1994 {
1995 strlcpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1996 strlcpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1997 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1998 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1999 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
2000
2001 return 0;
2002 }
2003
2004 static int pxac_vidioc_enum_input(struct file *file, void *priv,
2005 struct v4l2_input *i)
2006 {
2007 if (i->index > 0)
2008 return -EINVAL;
2009
2010 i->type = V4L2_INPUT_TYPE_CAMERA;
2011 strlcpy(i->name, "Camera", sizeof(i->name));
2012
2013 return 0;
2014 }
2015
2016 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
2017 {
2018 *i = 0;
2019
2020 return 0;
2021 }
2022
2023 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
2024 {
2025 if (i > 0)
2026 return -EINVAL;
2027
2028 return 0;
2029 }
2030
2031 static int pxac_fops_camera_open(struct file *filp)
2032 {
2033 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2034 int ret;
2035
2036 mutex_lock(&pcdev->mlock);
2037 ret = v4l2_fh_open(filp);
2038 if (ret < 0)
2039 goto out;
2040
2041 ret = sensor_call(pcdev, core, s_power, 1);
2042 if (ret)
2043 v4l2_fh_release(filp);
2044 out:
2045 mutex_unlock(&pcdev->mlock);
2046 return ret;
2047 }
2048
2049 static int pxac_fops_camera_release(struct file *filp)
2050 {
2051 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2052 int ret;
2053
2054 ret = vb2_fop_release(filp);
2055 if (ret < 0)
2056 return ret;
2057
2058 mutex_lock(&pcdev->mlock);
2059 ret = sensor_call(pcdev, core, s_power, 0);
2060 mutex_unlock(&pcdev->mlock);
2061
2062 return ret;
2063 }
2064
2065 static const struct v4l2_file_operations pxa_camera_fops = {
2066 .owner = THIS_MODULE,
2067 .open = pxac_fops_camera_open,
2068 .release = pxac_fops_camera_release,
2069 .read = vb2_fop_read,
2070 .poll = vb2_fop_poll,
2071 .mmap = vb2_fop_mmap,
2072 .unlocked_ioctl = video_ioctl2,
2073 };
2074
2075 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2076 .vidioc_querycap = pxac_vidioc_querycap,
2077
2078 .vidioc_enum_input = pxac_vidioc_enum_input,
2079 .vidioc_g_input = pxac_vidioc_g_input,
2080 .vidioc_s_input = pxac_vidioc_s_input,
2081
2082 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2083 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2084 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2085 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2086
2087 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2088 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2089 .vidioc_querybuf = vb2_ioctl_querybuf,
2090 .vidioc_qbuf = vb2_ioctl_qbuf,
2091 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2092 .vidioc_expbuf = vb2_ioctl_expbuf,
2093 .vidioc_streamon = vb2_ioctl_streamon,
2094 .vidioc_streamoff = vb2_ioctl_streamoff,
2095 #ifdef CONFIG_VIDEO_ADV_DEBUG
2096 .vidioc_g_register = pxac_vidioc_g_register,
2097 .vidioc_s_register = pxac_vidioc_s_register,
2098 #endif
2099 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2100 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2101 };
2102
2103 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2104 };
2105
2106 static const struct video_device pxa_camera_videodev_template = {
2107 .name = "pxa-camera",
2108 .minor = -1,
2109 .fops = &pxa_camera_fops,
2110 .ioctl_ops = &pxa_camera_ioctl_ops,
2111 .release = video_device_release_empty,
2112 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2113 };
2114
2115 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2116 struct v4l2_subdev *subdev,
2117 struct v4l2_async_subdev *asd)
2118 {
2119 int err;
2120 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2121 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2122 struct video_device *vdev = &pcdev->vdev;
2123 struct v4l2_pix_format *pix = &pcdev->current_pix;
2124 struct v4l2_subdev_format format = {
2125 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2126 };
2127 struct v4l2_mbus_framefmt *mf = &format.format;
2128
2129 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2130 __func__);
2131 mutex_lock(&pcdev->mlock);
2132 *vdev = pxa_camera_videodev_template;
2133 vdev->v4l2_dev = v4l2_dev;
2134 vdev->lock = &pcdev->mlock;
2135 pcdev->sensor = subdev;
2136 pcdev->vdev.queue = &pcdev->vb2_vq;
2137 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2138 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2139 video_set_drvdata(&pcdev->vdev, pcdev);
2140
2141 err = pxa_camera_build_formats(pcdev);
2142 if (err) {
2143 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2144 err);
2145 goto out;
2146 }
2147
2148 pcdev->current_fmt = pcdev->user_formats;
2149 pix->field = V4L2_FIELD_NONE;
2150 pix->width = DEFAULT_WIDTH;
2151 pix->height = DEFAULT_HEIGHT;
2152 pix->bytesperline =
2153 pxa_mbus_bytes_per_line(pix->width,
2154 pcdev->current_fmt->host_fmt);
2155 pix->sizeimage =
2156 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2157 pix->bytesperline, pix->height);
2158 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2159 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2160
2161 err = sensor_call(pcdev, core, s_power, 1);
2162 if (err)
2163 goto out;
2164
2165 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2166 if (err)
2167 goto out_sensor_poweroff;
2168
2169 v4l2_fill_pix_format(pix, mf);
2170 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2171 __func__, pix->colorspace, pix->pixelformat);
2172
2173 err = pxa_camera_init_videobuf2(pcdev);
2174 if (err)
2175 goto out_sensor_poweroff;
2176
2177 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2178 if (err) {
2179 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2180 pcdev->sensor = NULL;
2181 } else {
2182 dev_info(pcdev_to_dev(pcdev),
2183 "PXA Camera driver attached to camera %s\n",
2184 subdev->name);
2185 }
2186
2187 out_sensor_poweroff:
2188 err = sensor_call(pcdev, core, s_power, 0);
2189 out:
2190 mutex_unlock(&pcdev->mlock);
2191 return err;
2192 }
2193
2194 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2195 struct v4l2_subdev *subdev,
2196 struct v4l2_async_subdev *asd)
2197 {
2198 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2199
2200 mutex_lock(&pcdev->mlock);
2201 dev_info(pcdev_to_dev(pcdev),
2202 "PXA Camera driver detached from camera %s\n",
2203 subdev->name);
2204
2205 /* disable capture, disable interrupts */
2206 __raw_writel(0x3ff, pcdev->base + CICR0);
2207
2208 /* Stop DMA engine */
2209 pxa_dma_stop_channels(pcdev);
2210
2211 pxa_camera_destroy_formats(pcdev);
2212
2213 if (pcdev->mclk_clk) {
2214 v4l2_clk_unregister(pcdev->mclk_clk);
2215 pcdev->mclk_clk = NULL;
2216 }
2217
2218 video_unregister_device(&pcdev->vdev);
2219 pcdev->sensor = NULL;
2220
2221 mutex_unlock(&pcdev->mlock);
2222 }
2223
2224 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2225 .bound = pxa_camera_sensor_bound,
2226 .unbind = pxa_camera_sensor_unbind,
2227 };
2228
2229 /*
2230 * Driver probe, remove, suspend and resume operations
2231 */
2232 static int pxa_camera_suspend(struct device *dev)
2233 {
2234 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2235 int i = 0, ret = 0;
2236
2237 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2238 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2239 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2240 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2241 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2242
2243 if (pcdev->sensor) {
2244 ret = sensor_call(pcdev, core, s_power, 0);
2245 if (ret == -ENOIOCTLCMD)
2246 ret = 0;
2247 }
2248
2249 return ret;
2250 }
2251
2252 static int pxa_camera_resume(struct device *dev)
2253 {
2254 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2255 int i = 0, ret = 0;
2256
2257 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2258 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2259 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2260 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2261 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2262
2263 if (pcdev->sensor) {
2264 ret = sensor_call(pcdev, core, s_power, 1);
2265 if (ret == -ENOIOCTLCMD)
2266 ret = 0;
2267 }
2268
2269 /* Restart frame capture if active buffer exists */
2270 if (!ret && pcdev->active)
2271 pxa_camera_start_capture(pcdev);
2272
2273 return ret;
2274 }
2275
2276 static int pxa_camera_pdata_from_dt(struct device *dev,
2277 struct pxa_camera_dev *pcdev,
2278 struct v4l2_async_subdev *asd)
2279 {
2280 u32 mclk_rate;
2281 struct device_node *remote, *np = dev->of_node;
2282 struct v4l2_fwnode_endpoint ep;
2283 int err = of_property_read_u32(np, "clock-frequency",
2284 &mclk_rate);
2285 if (!err) {
2286 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2287 pcdev->mclk = mclk_rate;
2288 }
2289
2290 np = of_graph_get_next_endpoint(np, NULL);
2291 if (!np) {
2292 dev_err(dev, "could not find endpoint\n");
2293 return -EINVAL;
2294 }
2295
2296 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2297 if (err) {
2298 dev_err(dev, "could not parse endpoint\n");
2299 goto out;
2300 }
2301
2302 switch (ep.bus.parallel.bus_width) {
2303 case 4:
2304 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2305 break;
2306 case 5:
2307 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2308 break;
2309 case 8:
2310 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2311 break;
2312 case 9:
2313 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2314 break;
2315 case 10:
2316 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2317 break;
2318 default:
2319 break;
2320 }
2321
2322 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2323 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2324 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2325 pcdev->platform_flags |= PXA_CAMERA_HSP;
2326 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2327 pcdev->platform_flags |= PXA_CAMERA_VSP;
2328 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2329 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2330 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2331 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2332
2333 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2334 remote = of_graph_get_remote_port(np);
2335 if (remote) {
2336 asd->match.fwnode.fwnode = of_fwnode_handle(remote);
2337 of_node_put(remote);
2338 } else {
2339 dev_notice(dev, "no remote for %pOF\n", np);
2340 }
2341
2342 out:
2343 of_node_put(np);
2344
2345 return err;
2346 }
2347
2348 static int pxa_camera_probe(struct platform_device *pdev)
2349 {
2350 struct pxa_camera_dev *pcdev;
2351 struct resource *res;
2352 void __iomem *base;
2353 struct dma_slave_config config = {
2354 .src_addr_width = 0,
2355 .src_maxburst = 8,
2356 .direction = DMA_DEV_TO_MEM,
2357 };
2358 dma_cap_mask_t mask;
2359 struct pxad_param params;
2360 char clk_name[V4L2_CLK_NAME_SIZE];
2361 int irq;
2362 int err = 0, i;
2363
2364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2365 irq = platform_get_irq(pdev, 0);
2366 if (!res || irq < 0)
2367 return -ENODEV;
2368
2369 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2370 if (!pcdev) {
2371 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2372 return -ENOMEM;
2373 }
2374
2375 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2376 if (IS_ERR(pcdev->clk))
2377 return PTR_ERR(pcdev->clk);
2378
2379 pcdev->res = res;
2380
2381 pcdev->pdata = pdev->dev.platform_data;
2382 if (&pdev->dev.of_node && !pcdev->pdata) {
2383 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2384 } else {
2385 pcdev->platform_flags = pcdev->pdata->flags;
2386 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2387 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2388 pcdev->asd.match.i2c.adapter_id =
2389 pcdev->pdata->sensor_i2c_adapter_id;
2390 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2391 }
2392 if (err < 0)
2393 return err;
2394
2395 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2396 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2397 /*
2398 * Platform hasn't set available data widths. This is bad.
2399 * Warn and use a default.
2400 */
2401 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2402 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2403 }
2404 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2405 pcdev->width_flags = 1 << 7;
2406 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2407 pcdev->width_flags |= 1 << 8;
2408 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2409 pcdev->width_flags |= 1 << 9;
2410 if (!pcdev->mclk) {
2411 dev_warn(&pdev->dev,
2412 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2413 pcdev->mclk = 20000000;
2414 }
2415
2416 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2417
2418 INIT_LIST_HEAD(&pcdev->capture);
2419 spin_lock_init(&pcdev->lock);
2420 mutex_init(&pcdev->mlock);
2421
2422 /*
2423 * Request the regions.
2424 */
2425 base = devm_ioremap_resource(&pdev->dev, res);
2426 if (IS_ERR(base))
2427 return PTR_ERR(base);
2428
2429 pcdev->irq = irq;
2430 pcdev->base = base;
2431
2432 /* request dma */
2433 dma_cap_zero(mask);
2434 dma_cap_set(DMA_SLAVE, mask);
2435 dma_cap_set(DMA_PRIVATE, mask);
2436
2437 params.prio = 0;
2438 params.drcmr = 68;
2439 pcdev->dma_chans[0] =
2440 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2441 &params, &pdev->dev, "CI_Y");
2442 if (!pcdev->dma_chans[0]) {
2443 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2444 return -ENODEV;
2445 }
2446
2447 params.drcmr = 69;
2448 pcdev->dma_chans[1] =
2449 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2450 &params, &pdev->dev, "CI_U");
2451 if (!pcdev->dma_chans[1]) {
2452 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2453 err = -ENODEV;
2454 goto exit_free_dma_y;
2455 }
2456
2457 params.drcmr = 70;
2458 pcdev->dma_chans[2] =
2459 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2460 &params, &pdev->dev, "CI_V");
2461 if (!pcdev->dma_chans[2]) {
2462 dev_err(&pdev->dev, "Can't request DMA for V\n");
2463 err = -ENODEV;
2464 goto exit_free_dma_u;
2465 }
2466
2467 for (i = 0; i < 3; i++) {
2468 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2469 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2470 if (err < 0) {
2471 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2472 err);
2473 goto exit_free_dma;
2474 }
2475 }
2476
2477 /* request irq */
2478 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2479 PXA_CAM_DRV_NAME, pcdev);
2480 if (err) {
2481 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2482 goto exit_free_dma;
2483 }
2484
2485 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2486
2487 pxa_camera_activate(pcdev);
2488
2489 dev_set_drvdata(&pdev->dev, pcdev);
2490 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2491 if (err)
2492 goto exit_free_dma;
2493
2494 pcdev->asds[0] = &pcdev->asd;
2495 pcdev->notifier.subdevs = pcdev->asds;
2496 pcdev->notifier.num_subdevs = 1;
2497 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2498
2499 if (!of_have_populated_dt())
2500 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2501
2502 err = pxa_camera_init_videobuf2(pcdev);
2503 if (err)
2504 goto exit_free_v4l2dev;
2505
2506 if (pcdev->mclk) {
2507 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2508 pcdev->asd.match.i2c.adapter_id,
2509 pcdev->asd.match.i2c.address);
2510
2511 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2512 clk_name, NULL);
2513 if (IS_ERR(pcdev->mclk_clk)) {
2514 err = PTR_ERR(pcdev->mclk_clk);
2515 goto exit_free_v4l2dev;
2516 }
2517 }
2518
2519 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2520 if (err)
2521 goto exit_free_clk;
2522
2523 return 0;
2524 exit_free_clk:
2525 v4l2_clk_unregister(pcdev->mclk_clk);
2526 exit_free_v4l2dev:
2527 v4l2_device_unregister(&pcdev->v4l2_dev);
2528 exit_free_dma:
2529 dma_release_channel(pcdev->dma_chans[2]);
2530 exit_free_dma_u:
2531 dma_release_channel(pcdev->dma_chans[1]);
2532 exit_free_dma_y:
2533 dma_release_channel(pcdev->dma_chans[0]);
2534 return err;
2535 }
2536
2537 static int pxa_camera_remove(struct platform_device *pdev)
2538 {
2539 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2540
2541 pxa_camera_deactivate(pcdev);
2542 dma_release_channel(pcdev->dma_chans[0]);
2543 dma_release_channel(pcdev->dma_chans[1]);
2544 dma_release_channel(pcdev->dma_chans[2]);
2545
2546 v4l2_async_notifier_unregister(&pcdev->notifier);
2547
2548 if (pcdev->mclk_clk) {
2549 v4l2_clk_unregister(pcdev->mclk_clk);
2550 pcdev->mclk_clk = NULL;
2551 }
2552
2553 v4l2_device_unregister(&pcdev->v4l2_dev);
2554
2555 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2556
2557 return 0;
2558 }
2559
2560 static const struct dev_pm_ops pxa_camera_pm = {
2561 .suspend = pxa_camera_suspend,
2562 .resume = pxa_camera_resume,
2563 };
2564
2565 static const struct of_device_id pxa_camera_of_match[] = {
2566 { .compatible = "marvell,pxa270-qci", },
2567 {},
2568 };
2569 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2570
2571 static struct platform_driver pxa_camera_driver = {
2572 .driver = {
2573 .name = PXA_CAM_DRV_NAME,
2574 .pm = &pxa_camera_pm,
2575 .of_match_table = of_match_ptr(pxa_camera_of_match),
2576 },
2577 .probe = pxa_camera_probe,
2578 .remove = pxa_camera_remove,
2579 };
2580
2581 module_platform_driver(pxa_camera_driver);
2582
2583 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2584 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2585 MODULE_LICENSE("GPL");
2586 MODULE_VERSION(PXA_CAM_VERSION);
2587 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
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