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timekeeping: Repair ktime_get_coarse*() granularity
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1 /*
2 * Samsung S5P G2D - 2D Graphics Accelerator Driver
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version
11 */
12
13 /* General Registers */
14 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
15 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
16 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
17 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
18 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
19 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
20 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
21
22 /* Command Registers */
23 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
24 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
25
26 /* Parameter Setting Registers (Rotate & Direction) */
27 #define ROTATE_REG 0x0200 /* Rotation reg */
28 #define SRC_MSK_DIRECT_REG 0x0204 /* Src and Mask Direction reg */
29 #define DST_PAT_DIRECT_REG 0x0208 /* Dest and Pattern Direction reg */
30
31 /* Parameter Setting Registers (Src) */
32 #define SRC_SELECT_REG 0x0300 /* Src Image Selection reg */
33 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
34 #define SRC_STRIDE_REG 0x0308 /* Src Stride reg */
35 #define SRC_COLOR_MODE_REG 0x030C /* Src Image Color Mode reg */
36 #define SRC_LEFT_TOP_REG 0x0310 /* Src Left Top Coordinate reg */
37 #define SRC_RIGHT_BOTTOM_REG 0x0314 /* Src Right Bottom Coordinate reg */
38 #define SRC_SCALE_CTRL_REG 0x0328 /* Src Scaling type select */
39 #define SRC_XSCALE_REG 0x032c /* Src X Scaling ratio */
40 #define SRC_YSCALE_REG 0x0330 /* Src Y Scaling ratio */
41
42 /* Parameter Setting Registers (Dest) */
43 #define DST_SELECT_REG 0x0400 /* Dest Image Selection reg */
44 #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */
45 #define DST_STRIDE_REG 0x0408 /* Dest Stride reg */
46 #define DST_COLOR_MODE_REG 0x040C /* Dest Image Color Mode reg */
47 #define DST_LEFT_TOP_REG 0x0410 /* Dest Left Top Coordinate reg */
48 #define DST_RIGHT_BOTTOM_REG 0x0414 /* Dest Right Bottom Coordinate reg */
49
50 /* Parameter Setting Registers (Pattern) */
51 #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */
52 #define PAT_SIZE_REG 0x0504 /* Pattern Image Size reg */
53 #define PAT_COLOR_MODE_REG 0x0508 /* Pattern Image Color Mode reg */
54 #define PAT_OFFSET_REG 0x050C /* Pattern Left Top Coordinate reg */
55 #define PAT_STRIDE_REG 0x0510 /* Pattern Stride reg */
56
57 /* Parameter Setting Registers (Mask) */
58 #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */
59 #define MASK_STRIDE_REG 0x0524 /* Mask Stride reg */
60
61 /* Parameter Setting Registers (Clipping Window) */
62 #define CW_LT_REG 0x0600 /* LeftTop coordinates of Clip Window */
63 #define CW_RB_REG 0x0604 /* RightBottom coordinates of Clip
64 Window */
65
66 /* Parameter Setting Registers (ROP & Alpha Setting) */
67 #define THIRD_OPERAND_REG 0x0610 /* Third Operand Selection reg */
68 #define ROP4_REG 0x0614 /* Raster Operation reg */
69 #define ALPHA_REG 0x0618 /* Alpha value, Fading offset value */
70
71 /* Parameter Setting Registers (Color) */
72 #define FG_COLOR_REG 0x0700 /* Foreground Color reg */
73 #define BG_COLOR_REG 0x0704 /* Background Color reg */
74 #define BS_COLOR_REG 0x0708 /* Blue Screen Color reg */
75
76 /* Parameter Setting Registers (Color Key) */
77 #define SRC_COLORKEY_CTRL_REG 0x0710 /* Src Colorkey control reg */
78 #define SRC_COLORKEY_DR_MIN_REG 0x0714 /* Src Colorkey Decision Reference
79 Min reg */
80 #define SRC_COLORKEY_DR_MAX_REG 0x0718 /* Src Colorkey Decision Reference
81 Max reg */
82 #define DST_COLORKEY_CTRL_REG 0x071C /* Dest Colorkey control reg */
83 #define DST_COLORKEY_DR_MIN_REG 0x0720 /* Dest Colorkey Decision Reference
84 Min reg */
85 #define DST_COLORKEY_DR_MAX_REG 0x0724 /* Dest Colorkey Decision Reference
86 Max reg */
87
88 /* Color mode values */
89
90 #define ORDER_XRGB 0
91 #define ORDER_RGBX 1
92 #define ORDER_XBGR 2
93 #define ORDER_BGRX 3
94
95 #define MODE_XRGB_8888 0
96 #define MODE_ARGB_8888 1
97 #define MODE_RGB_565 2
98 #define MODE_XRGB_1555 3
99 #define MODE_ARGB_1555 4
100 #define MODE_XRGB_4444 5
101 #define MODE_ARGB_4444 6
102 #define MODE_PACKED_RGB_888 7
103
104 #define COLOR_MODE(o, m) (((o) << 4) | (m))
105
106 /* ROP4 operation values */
107 #define ROP4_COPY 0xCCCC
108 #define ROP4_INVERT 0x3333
109
110 /* Hardware limits */
111 #define MAX_WIDTH 8000
112 #define MAX_HEIGHT 8000
113
114 #define G2D_TIMEOUT 500
115
116 #define DEFAULT_WIDTH 100
117 #define DEFAULT_HEIGHT 100
118
119 #define DEFAULT_SCALE_MODE (2 << 0)
120
121 /* Command mode register values */
122 #define CMD_V3_ENABLE_STRETCH (1 << 4)