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[mirror_ubuntu-artful-kernel.git] / drivers / media / platform / s5p-mfc / s5p_mfc_opr_v6.c
1 /*
2 * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
3 *
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
6 *
7 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
8 * http://www.samsung.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #undef DEBUG
16
17 #include <linux/delay.h>
18 #include <linux/mm.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/firmware.h>
22 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25
26 #include <asm/cacheflush.h>
27
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_cmd.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_pm.h"
32 #include "s5p_mfc_debug.h"
33 #include "s5p_mfc_opr.h"
34 #include "s5p_mfc_opr_v6.h"
35
36 /* #define S5P_MFC_DEBUG_REGWRITE */
37 #ifdef S5P_MFC_DEBUG_REGWRITE
38 #undef writel
39 #define writel(v, r) \
40 do { \
41 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
42 __raw_writel(v, r); \
43 } while (0)
44 #endif /* S5P_MFC_DEBUG_REGWRITE */
45
46 #define READL(offset) readl(dev->regs_base + (offset))
47 #define WRITEL(data, offset) writel((data), dev->regs_base + (offset))
48 #define OFFSETA(x) (((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET)
49 #define OFFSETB(x) (((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET)
50
51 /* Allocate temporary buffers for decoding */
52 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
53 {
54 /* NOP */
55
56 return 0;
57 }
58
59 /* Release temproary buffers for decoding */
60 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
61 {
62 /* NOP */
63 }
64
65 /* Allocate codec buffers */
66 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
67 {
68 struct s5p_mfc_dev *dev = ctx->dev;
69 unsigned int mb_width, mb_height;
70 int ret;
71
72 mb_width = MB_WIDTH(ctx->img_width);
73 mb_height = MB_HEIGHT(ctx->img_height);
74
75 if (ctx->type == MFCINST_DECODER) {
76 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
77 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
78 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
79 } else if (ctx->type == MFCINST_ENCODER) {
80 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
81 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
82 S5P_FIMV_TMV_BUFFER_ALIGN_V6);
83
84 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
85 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
86 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
87 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
88 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
89 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
90 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
91 ctx->img_width, ctx->img_height,
92 mb_width, mb_height),
93 S5P_FIMV_ME_BUFFER_ALIGN_V6);
94
95 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
96 ctx->luma_dpb_size, ctx->chroma_dpb_size);
97 } else {
98 return -EINVAL;
99 }
100
101 /* Codecs have different memory requirements */
102 switch (ctx->codec_mode) {
103 case S5P_MFC_CODEC_H264_DEC:
104 case S5P_MFC_CODEC_H264_MVC_DEC:
105 ctx->scratch_buf_size =
106 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
107 mb_width,
108 mb_height);
109 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
110 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
111 ctx->bank1.size =
112 ctx->scratch_buf_size +
113 (ctx->mv_count * ctx->mv_size);
114 break;
115 case S5P_MFC_CODEC_MPEG4_DEC:
116 if (IS_MFCV7(dev)) {
117 ctx->scratch_buf_size =
118 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
119 mb_width,
120 mb_height);
121 } else {
122 ctx->scratch_buf_size =
123 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
124 mb_width,
125 mb_height);
126 }
127
128 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
129 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
130 ctx->bank1.size = ctx->scratch_buf_size;
131 break;
132 case S5P_MFC_CODEC_VC1RCV_DEC:
133 case S5P_MFC_CODEC_VC1_DEC:
134 ctx->scratch_buf_size =
135 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
136 mb_width,
137 mb_height);
138 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
139 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
140 ctx->bank1.size = ctx->scratch_buf_size;
141 break;
142 case S5P_MFC_CODEC_MPEG2_DEC:
143 ctx->bank1.size = 0;
144 ctx->bank2.size = 0;
145 break;
146 case S5P_MFC_CODEC_H263_DEC:
147 ctx->scratch_buf_size =
148 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
149 mb_width,
150 mb_height);
151 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
152 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
153 ctx->bank1.size = ctx->scratch_buf_size;
154 break;
155 case S5P_MFC_CODEC_VP8_DEC:
156 ctx->scratch_buf_size =
157 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
158 mb_width,
159 mb_height);
160 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
161 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
162 ctx->bank1.size = ctx->scratch_buf_size;
163 break;
164 case S5P_MFC_CODEC_H264_ENC:
165 ctx->scratch_buf_size =
166 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
167 mb_width,
168 mb_height);
169 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
170 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
171 ctx->bank1.size =
172 ctx->scratch_buf_size + ctx->tmv_buffer_size +
173 (ctx->pb_count * (ctx->luma_dpb_size +
174 ctx->chroma_dpb_size + ctx->me_buffer_size));
175 ctx->bank2.size = 0;
176 break;
177 case S5P_MFC_CODEC_MPEG4_ENC:
178 case S5P_MFC_CODEC_H263_ENC:
179 ctx->scratch_buf_size =
180 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
181 mb_width,
182 mb_height);
183 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
184 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
185 ctx->bank1.size =
186 ctx->scratch_buf_size + ctx->tmv_buffer_size +
187 (ctx->pb_count * (ctx->luma_dpb_size +
188 ctx->chroma_dpb_size + ctx->me_buffer_size));
189 ctx->bank2.size = 0;
190 break;
191 case S5P_MFC_CODEC_VP8_ENC:
192 ctx->scratch_buf_size =
193 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
194 mb_width,
195 mb_height);
196 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
197 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
198 ctx->bank1.size =
199 ctx->scratch_buf_size + ctx->tmv_buffer_size +
200 (ctx->pb_count * (ctx->luma_dpb_size +
201 ctx->chroma_dpb_size + ctx->me_buffer_size));
202 ctx->bank2.size = 0;
203 break;
204 default:
205 break;
206 }
207
208 /* Allocate only if memory from bank 1 is necessary */
209 if (ctx->bank1.size > 0) {
210 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
211 if (ret) {
212 mfc_err("Failed to allocate Bank1 memory\n");
213 return ret;
214 }
215 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
216 }
217 return 0;
218 }
219
220 /* Release buffers allocated for codec */
221 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
222 {
223 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
224 }
225
226 /* Allocate memory for instance data buffer */
227 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
228 {
229 struct s5p_mfc_dev *dev = ctx->dev;
230 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
231 int ret;
232
233 mfc_debug_enter();
234
235 switch (ctx->codec_mode) {
236 case S5P_MFC_CODEC_H264_DEC:
237 case S5P_MFC_CODEC_H264_MVC_DEC:
238 ctx->ctx.size = buf_size->h264_dec_ctx;
239 break;
240 case S5P_MFC_CODEC_MPEG4_DEC:
241 case S5P_MFC_CODEC_H263_DEC:
242 case S5P_MFC_CODEC_VC1RCV_DEC:
243 case S5P_MFC_CODEC_VC1_DEC:
244 case S5P_MFC_CODEC_MPEG2_DEC:
245 case S5P_MFC_CODEC_VP8_DEC:
246 ctx->ctx.size = buf_size->other_dec_ctx;
247 break;
248 case S5P_MFC_CODEC_H264_ENC:
249 ctx->ctx.size = buf_size->h264_enc_ctx;
250 break;
251 case S5P_MFC_CODEC_MPEG4_ENC:
252 case S5P_MFC_CODEC_H263_ENC:
253 case S5P_MFC_CODEC_VP8_ENC:
254 ctx->ctx.size = buf_size->other_enc_ctx;
255 break;
256 default:
257 ctx->ctx.size = 0;
258 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
259 break;
260 }
261
262 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
263 if (ret) {
264 mfc_err("Failed to allocate instance buffer\n");
265 return ret;
266 }
267
268 memset(ctx->ctx.virt, 0, ctx->ctx.size);
269 wmb();
270
271 mfc_debug_leave();
272
273 return 0;
274 }
275
276 /* Release instance buffer */
277 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
278 {
279 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
280 }
281
282 /* Allocate context buffers for SYS_INIT */
283 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
284 {
285 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
286 int ret;
287
288 mfc_debug_enter();
289
290 dev->ctx_buf.size = buf_size->dev_ctx;
291 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
292 if (ret) {
293 mfc_err("Failed to allocate device context buffer\n");
294 return ret;
295 }
296
297 memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
298 wmb();
299
300 mfc_debug_leave();
301
302 return 0;
303 }
304
305 /* Release context buffers for SYS_INIT */
306 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
307 {
308 s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
309 }
310
311 static int calc_plane(int width, int height)
312 {
313 int mbX, mbY;
314
315 mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
316 mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
317
318 if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
319 mbY = (mbY + 1) / 2 * 2;
320
321 return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
322 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
323 }
324
325 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
326 {
327 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
328 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
329 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
330 "buffer dimensions: %dx%d\n", ctx->img_width,
331 ctx->img_height, ctx->buf_width, ctx->buf_height);
332
333 ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
334 ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
335 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
336 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
337 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
338 ctx->img_height);
339 ctx->mv_size = ALIGN(ctx->mv_size, 16);
340 } else {
341 ctx->mv_size = 0;
342 }
343 }
344
345 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
346 {
347 unsigned int mb_width, mb_height;
348
349 mb_width = MB_WIDTH(ctx->img_width);
350 mb_height = MB_HEIGHT(ctx->img_height);
351
352 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
353 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
354 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
355
356 /* MFCv7 needs pad bytes for Luma and Chroma */
357 if (IS_MFCV7(ctx->dev)) {
358 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
359 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
360 }
361 }
362
363 /* Set registers for decoding stream buffer */
364 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
365 int buf_addr, unsigned int start_num_byte,
366 unsigned int strm_size)
367 {
368 struct s5p_mfc_dev *dev = ctx->dev;
369 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
370
371 mfc_debug_enter();
372 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
373 "buf_size: 0x%08x (%d)\n",
374 ctx->inst_no, buf_addr, strm_size, strm_size);
375 WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
376 WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
377 WRITEL(buf_size->cpb, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
378 WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
379
380 mfc_debug_leave();
381 return 0;
382 }
383
384 /* Set decoding frame buffer */
385 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
386 {
387 unsigned int frame_size, i;
388 unsigned int frame_size_ch, frame_size_mv;
389 struct s5p_mfc_dev *dev = ctx->dev;
390 size_t buf_addr1;
391 int buf_size1;
392 int align_gap;
393
394 buf_addr1 = ctx->bank1.dma;
395 buf_size1 = ctx->bank1.size;
396
397 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
398 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
399 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
400
401 WRITEL(ctx->total_dpb_count, S5P_FIMV_D_NUM_DPB_V6);
402 WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
403 WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
404
405 WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
406 WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
407 buf_addr1 += ctx->scratch_buf_size;
408 buf_size1 -= ctx->scratch_buf_size;
409
410 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
411 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
412 WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
413 WRITEL(ctx->mv_count, S5P_FIMV_D_NUM_MV_V6);
414 }
415
416 frame_size = ctx->luma_size;
417 frame_size_ch = ctx->chroma_size;
418 frame_size_mv = ctx->mv_size;
419 mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
420 frame_size, frame_size_ch, frame_size_mv);
421
422 for (i = 0; i < ctx->total_dpb_count; i++) {
423 /* Bank2 */
424 mfc_debug(2, "Luma %d: %x\n", i,
425 ctx->dst_bufs[i].cookie.raw.luma);
426 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
427 S5P_FIMV_D_LUMA_DPB_V6 + i * 4);
428 mfc_debug(2, "\tChroma %d: %x\n", i,
429 ctx->dst_bufs[i].cookie.raw.chroma);
430 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
431 S5P_FIMV_D_CHROMA_DPB_V6 + i * 4);
432 }
433 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
434 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
435 for (i = 0; i < ctx->mv_count; i++) {
436 /* To test alignment */
437 align_gap = buf_addr1;
438 buf_addr1 = ALIGN(buf_addr1, 16);
439 align_gap = buf_addr1 - align_gap;
440 buf_size1 -= align_gap;
441
442 mfc_debug(2, "\tBuf1: %x, size: %d\n",
443 buf_addr1, buf_size1);
444 WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER_V6 + i * 4);
445 buf_addr1 += frame_size_mv;
446 buf_size1 -= frame_size_mv;
447 }
448 }
449
450 mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
451 buf_addr1, buf_size1, ctx->total_dpb_count);
452 if (buf_size1 < 0) {
453 mfc_debug(2, "Not enough memory has been allocated.\n");
454 return -ENOMEM;
455 }
456
457 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
458 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
459 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
460
461 mfc_debug(2, "After setting buffers.\n");
462 return 0;
463 }
464
465 /* Set registers for encoding stream buffer */
466 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
467 unsigned long addr, unsigned int size)
468 {
469 struct s5p_mfc_dev *dev = ctx->dev;
470
471 WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); /* 16B align */
472 WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
473
474 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
475 addr, size);
476
477 return 0;
478 }
479
480 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
481 unsigned long y_addr, unsigned long c_addr)
482 {
483 struct s5p_mfc_dev *dev = ctx->dev;
484
485 if (IS_MFCV7(dev)) {
486 WRITEL(y_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
487 WRITEL(c_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
488 } else {
489 WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
490 WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
491 }
492
493 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
494 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
495 }
496
497 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
498 unsigned long *y_addr, unsigned long *c_addr)
499 {
500 struct s5p_mfc_dev *dev = ctx->dev;
501 unsigned long enc_recon_y_addr, enc_recon_c_addr;
502
503 if (IS_MFCV7(dev)) {
504 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
505 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
506 } else {
507 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
508 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
509 }
510
511 enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
512 enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
513
514 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
515 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
516 }
517
518 /* Set encoding ref & codec buffer */
519 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
520 {
521 struct s5p_mfc_dev *dev = ctx->dev;
522 size_t buf_addr1;
523 int i, buf_size1;
524
525 mfc_debug_enter();
526
527 buf_addr1 = ctx->bank1.dma;
528 buf_size1 = ctx->bank1.size;
529
530 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
531
532 for (i = 0; i < ctx->pb_count; i++) {
533 WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB_V6 + (4 * i));
534 buf_addr1 += ctx->luma_dpb_size;
535 WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB_V6 + (4 * i));
536 buf_addr1 += ctx->chroma_dpb_size;
537 WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER_V6 + (4 * i));
538 buf_addr1 += ctx->me_buffer_size;
539 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
540 ctx->me_buffer_size);
541 }
542
543 WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
544 WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
545 buf_addr1 += ctx->scratch_buf_size;
546 buf_size1 -= ctx->scratch_buf_size;
547
548 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0_V6);
549 buf_addr1 += ctx->tmv_buffer_size >> 1;
550 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1_V6);
551 buf_addr1 += ctx->tmv_buffer_size >> 1;
552 buf_size1 -= ctx->tmv_buffer_size;
553
554 mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
555 buf_addr1, buf_size1, ctx->pb_count);
556 if (buf_size1 < 0) {
557 mfc_debug(2, "Not enough memory has been allocated.\n");
558 return -ENOMEM;
559 }
560
561 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
562 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
563 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
564
565 mfc_debug_leave();
566
567 return 0;
568 }
569
570 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
571 {
572 struct s5p_mfc_dev *dev = ctx->dev;
573
574 /* multi-slice control */
575 /* multi-slice MB number or bit size */
576 WRITEL(ctx->slice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
577 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
578 WRITEL(ctx->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
579 } else if (ctx->slice_mode ==
580 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
581 WRITEL(ctx->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
582 } else {
583 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
584 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
585 }
586
587 return 0;
588 }
589
590 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
591 {
592 struct s5p_mfc_dev *dev = ctx->dev;
593 struct s5p_mfc_enc_params *p = &ctx->enc_params;
594 unsigned int reg = 0;
595
596 mfc_debug_enter();
597
598 /* width */
599 WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH_V6); /* 16 align */
600 /* height */
601 WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT_V6); /* 16 align */
602
603 /* cropped width */
604 WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
605 /* cropped height */
606 WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
607 /* cropped offset */
608 WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
609
610 /* pictype : IDR period */
611 reg = 0;
612 reg |= p->gop_size & 0xFFFF;
613 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
614
615 /* multi-slice control */
616 /* multi-slice MB number or bit size */
617 ctx->slice_mode = p->slice_mode;
618 reg = 0;
619 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
620 reg |= (0x1 << 3);
621 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
622 ctx->slice_size.mb = p->slice_mb;
623 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
624 reg |= (0x1 << 3);
625 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
626 ctx->slice_size.bits = p->slice_bit;
627 } else {
628 reg &= ~(0x1 << 3);
629 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
630 }
631
632 s5p_mfc_set_slice_mode(ctx);
633
634 /* cyclic intra refresh */
635 WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE_V6);
636 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
637 if (p->intra_refresh_mb == 0)
638 reg &= ~(0x1 << 4);
639 else
640 reg |= (0x1 << 4);
641 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
642
643 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
644 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
645 reg &= ~(0x1 << 9);
646 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
647
648 /* memory structure cur. frame */
649 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
650 /* 0: Linear, 1: 2D tiled*/
651 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
652 reg &= ~(0x1 << 7);
653 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
654 /* 0: NV12(CbCr), 1: NV21(CrCb) */
655 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
656 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
657 /* 0: Linear, 1: 2D tiled*/
658 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
659 reg &= ~(0x1 << 7);
660 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
661 /* 0: NV12(CbCr), 1: NV21(CrCb) */
662 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
663 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
664 /* 0: Linear, 1: 2D tiled*/
665 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
666 reg |= (0x1 << 7);
667 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
668 /* 0: NV12(CbCr), 1: NV21(CrCb) */
669 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
670 }
671
672 /* memory structure recon. frame */
673 /* 0: Linear, 1: 2D tiled */
674 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
675 reg |= (0x1 << 8);
676 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
677
678 /* padding control & value */
679 WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL_V6);
680 if (p->pad) {
681 reg = 0;
682 /** enable */
683 reg |= (1 << 31);
684 /** cr value */
685 reg |= ((p->pad_cr & 0xFF) << 16);
686 /** cb value */
687 reg |= ((p->pad_cb & 0xFF) << 8);
688 /** y value */
689 reg |= p->pad_luma & 0xFF;
690 WRITEL(reg, S5P_FIMV_E_PADDING_CTRL_V6);
691 }
692
693 /* rate control config. */
694 reg = 0;
695 /* frame-level rate control */
696 reg |= ((p->rc_frame & 0x1) << 9);
697 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
698
699 /* bit rate */
700 if (p->rc_frame)
701 WRITEL(p->rc_bitrate,
702 S5P_FIMV_E_RC_BIT_RATE_V6);
703 else
704 WRITEL(1, S5P_FIMV_E_RC_BIT_RATE_V6);
705
706 /* reaction coefficient */
707 if (p->rc_frame) {
708 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
709 WRITEL(1, S5P_FIMV_E_RC_RPARAM_V6);
710 else /* loose CBR */
711 WRITEL(2, S5P_FIMV_E_RC_RPARAM_V6);
712 }
713
714 /* seq header ctrl */
715 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
716 reg &= ~(0x1 << 2);
717 reg |= ((p->seq_hdr_mode & 0x1) << 2);
718
719 /* frame skip mode */
720 reg &= ~(0x3);
721 reg |= (p->frame_skip_mode & 0x3);
722 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
723
724 /* 'DROP_CONTROL_ENABLE', disable */
725 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
726 reg &= ~(0x1 << 10);
727 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
728
729 /* setting for MV range [16, 256] */
730 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
731 WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6);
732
733 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
734 WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6);
735
736 WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6);
737 WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
738 WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE_V6);
739 WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL_V6);
740 WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG_V6);
741
742 WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
743 WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT_V6);
744 WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT_V6);
745
746 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
747 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
748
749 mfc_debug_leave();
750
751 return 0;
752 }
753
754 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
755 {
756 struct s5p_mfc_dev *dev = ctx->dev;
757 struct s5p_mfc_enc_params *p = &ctx->enc_params;
758 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
759 unsigned int reg = 0;
760 int i;
761
762 mfc_debug_enter();
763
764 s5p_mfc_set_enc_params(ctx);
765
766 /* pictype : number of B */
767 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
768 reg &= ~(0x3 << 16);
769 reg |= ((p->num_b_frame & 0x3) << 16);
770 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
771
772 /* profile & level */
773 reg = 0;
774 /** level */
775 reg |= ((p_h264->level & 0xFF) << 8);
776 /** profile - 0 ~ 3 */
777 reg |= p_h264->profile & 0x3F;
778 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
779
780 /* rate control config. */
781 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
782 /** macroblock level rate control */
783 reg &= ~(0x1 << 8);
784 reg |= ((p->rc_mb & 0x1) << 8);
785 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
786 /** frame QP */
787 reg &= ~(0x3F);
788 reg |= p_h264->rc_frame_qp & 0x3F;
789 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
790
791 /* max & min value of QP */
792 reg = 0;
793 /** max QP */
794 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
795 /** min QP */
796 reg |= p_h264->rc_min_qp & 0x3F;
797 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
798
799 /* other QPs */
800 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
801 if (!p->rc_frame && !p->rc_mb) {
802 reg = 0;
803 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
804 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
805 reg |= p_h264->rc_frame_qp & 0x3F;
806 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
807 }
808
809 /* frame rate */
810 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
811 reg = 0;
812 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
813 reg |= p->rc_framerate_denom & 0xFFFF;
814 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
815 }
816
817 /* vbv buffer size */
818 if (p->frame_skip_mode ==
819 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
820 WRITEL(p_h264->cpb_size & 0xFFFF,
821 S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
822
823 if (p->rc_frame)
824 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
825 }
826
827 /* interlace */
828 reg = 0;
829 reg |= ((p_h264->interlace & 0x1) << 3);
830 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
831
832 /* height */
833 if (p_h264->interlace) {
834 WRITEL(ctx->img_height >> 1,
835 S5P_FIMV_E_FRAME_HEIGHT_V6); /* 32 align */
836 /* cropped height */
837 WRITEL(ctx->img_height >> 1,
838 S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
839 }
840
841 /* loop filter ctrl */
842 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
843 reg &= ~(0x3 << 1);
844 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
845 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
846
847 /* loopfilter alpha offset */
848 if (p_h264->loop_filter_alpha < 0) {
849 reg = 0x10;
850 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
851 } else {
852 reg = 0x00;
853 reg |= (p_h264->loop_filter_alpha & 0xF);
854 }
855 WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
856
857 /* loopfilter beta offset */
858 if (p_h264->loop_filter_beta < 0) {
859 reg = 0x10;
860 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
861 } else {
862 reg = 0x00;
863 reg |= (p_h264->loop_filter_beta & 0xF);
864 }
865 WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
866
867 /* entropy coding mode */
868 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
869 reg &= ~(0x1);
870 reg |= p_h264->entropy_mode & 0x1;
871 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
872
873 /* number of ref. picture */
874 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
875 reg &= ~(0x1 << 7);
876 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
877 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
878
879 /* 8x8 transform enable */
880 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
881 reg &= ~(0x3 << 12);
882 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
883 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
884
885 /* macroblock adaptive scaling features */
886 WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG_V6);
887 if (p->rc_mb) {
888 reg = 0;
889 /** dark region */
890 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
891 /** smooth region */
892 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
893 /** static region */
894 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
895 /** high activity region */
896 reg |= p_h264->rc_mb_activity & 0x1;
897 WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG_V6);
898 }
899
900 /* aspect ratio VUI */
901 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
902 reg &= ~(0x1 << 5);
903 reg |= ((p_h264->vui_sar & 0x1) << 5);
904 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
905
906 WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO_V6);
907 WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR_V6);
908 if (p_h264->vui_sar) {
909 /* aspect ration IDC */
910 reg = 0;
911 reg |= p_h264->vui_sar_idc & 0xFF;
912 WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO_V6);
913 if (p_h264->vui_sar_idc == 0xFF) {
914 /* extended SAR */
915 reg = 0;
916 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
917 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
918 WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR_V6);
919 }
920 }
921
922 /* intra picture period for H.264 open GOP */
923 /* control */
924 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
925 reg &= ~(0x1 << 4);
926 reg |= ((p_h264->open_gop & 0x1) << 4);
927 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
928 /* value */
929 WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD_V6);
930 if (p_h264->open_gop) {
931 reg = 0;
932 reg |= p_h264->open_gop_size & 0xFFFF;
933 WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD_V6);
934 }
935
936 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
937 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
938 reg &= ~(0x3 << 9);
939 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
940
941 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
942 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
943 reg &= ~(0x1 << 14);
944 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
945
946 /* ASO */
947 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
948 reg &= ~(0x1 << 6);
949 reg |= ((p_h264->aso & 0x1) << 6);
950 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
951
952 /* hier qp enable */
953 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
954 reg &= ~(0x1 << 8);
955 reg |= ((p_h264->open_gop & 0x1) << 8);
956 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
957 reg = 0;
958 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
959 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
960 reg |= p_h264->hier_qp_layer & 0x7;
961 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
962 /* QP value for each layer */
963 for (i = 0; i < (p_h264->hier_qp_layer & 0x7); i++)
964 WRITEL(p_h264->hier_qp_layer_qp[i],
965 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 +
966 i * 4);
967 }
968 /* number of coding layer should be zero when hierarchical is disable */
969 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
970
971 /* frame packing SEI generation */
972 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
973 reg &= ~(0x1 << 25);
974 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
975 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
976 if (p_h264->sei_frame_packing) {
977 reg = 0;
978 /** current frame0 flag */
979 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
980 /** arrangement type */
981 reg |= p_h264->sei_fp_arrangement_type & 0x3;
982 WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
983 }
984
985 if (p_h264->fmo) {
986 switch (p_h264->fmo_map_type) {
987 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
988 if (p_h264->fmo_slice_grp > 4)
989 p_h264->fmo_slice_grp = 4;
990 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
991 WRITEL(p_h264->fmo_run_len[i] - 1,
992 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 +
993 i * 4);
994 break;
995 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
996 if (p_h264->fmo_slice_grp > 4)
997 p_h264->fmo_slice_grp = 4;
998 break;
999 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1000 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1001 if (p_h264->fmo_slice_grp > 2)
1002 p_h264->fmo_slice_grp = 2;
1003 WRITEL(p_h264->fmo_chg_dir & 0x1,
1004 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
1005 /* the valid range is 0 ~ number of macroblocks -1 */
1006 WRITEL(p_h264->fmo_chg_rate,
1007 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
1008 break;
1009 default:
1010 mfc_err("Unsupported map type for FMO: %d\n",
1011 p_h264->fmo_map_type);
1012 p_h264->fmo_map_type = 0;
1013 p_h264->fmo_slice_grp = 1;
1014 break;
1015 }
1016
1017 WRITEL(p_h264->fmo_map_type,
1018 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
1019 WRITEL(p_h264->fmo_slice_grp - 1,
1020 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
1021 } else {
1022 WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
1023 }
1024
1025 mfc_debug_leave();
1026
1027 return 0;
1028 }
1029
1030 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1031 {
1032 struct s5p_mfc_dev *dev = ctx->dev;
1033 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1034 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1035 unsigned int reg = 0;
1036
1037 mfc_debug_enter();
1038
1039 s5p_mfc_set_enc_params(ctx);
1040
1041 /* pictype : number of B */
1042 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
1043 reg &= ~(0x3 << 16);
1044 reg |= ((p->num_b_frame & 0x3) << 16);
1045 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
1046
1047 /* profile & level */
1048 reg = 0;
1049 /** level */
1050 reg |= ((p_mpeg4->level & 0xFF) << 8);
1051 /** profile - 0 ~ 1 */
1052 reg |= p_mpeg4->profile & 0x3F;
1053 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1054
1055 /* rate control config. */
1056 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1057 /** macroblock level rate control */
1058 reg &= ~(0x1 << 8);
1059 reg |= ((p->rc_mb & 0x1) << 8);
1060 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1061 /** frame QP */
1062 reg &= ~(0x3F);
1063 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1064 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1065
1066 /* max & min value of QP */
1067 reg = 0;
1068 /** max QP */
1069 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1070 /** min QP */
1071 reg |= p_mpeg4->rc_min_qp & 0x3F;
1072 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1073
1074 /* other QPs */
1075 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1076 if (!p->rc_frame && !p->rc_mb) {
1077 reg = 0;
1078 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1079 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1080 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1081 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1082 }
1083
1084 /* frame rate */
1085 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1086 reg = 0;
1087 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1088 reg |= p->rc_framerate_denom & 0xFFFF;
1089 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1090 }
1091
1092 /* vbv buffer size */
1093 if (p->frame_skip_mode ==
1094 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1095 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1096
1097 if (p->rc_frame)
1098 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1099 }
1100
1101 /* Disable HEC */
1102 WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS_V6);
1103 WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
1104
1105 mfc_debug_leave();
1106
1107 return 0;
1108 }
1109
1110 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1111 {
1112 struct s5p_mfc_dev *dev = ctx->dev;
1113 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1114 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1115 unsigned int reg = 0;
1116
1117 mfc_debug_enter();
1118
1119 s5p_mfc_set_enc_params(ctx);
1120
1121 /* profile & level */
1122 reg = 0;
1123 /** profile */
1124 reg |= (0x1 << 4);
1125 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1126
1127 /* rate control config. */
1128 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1129 /** macroblock level rate control */
1130 reg &= ~(0x1 << 8);
1131 reg |= ((p->rc_mb & 0x1) << 8);
1132 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1133 /** frame QP */
1134 reg &= ~(0x3F);
1135 reg |= p_h263->rc_frame_qp & 0x3F;
1136 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1137
1138 /* max & min value of QP */
1139 reg = 0;
1140 /** max QP */
1141 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1142 /** min QP */
1143 reg |= p_h263->rc_min_qp & 0x3F;
1144 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1145
1146 /* other QPs */
1147 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1148 if (!p->rc_frame && !p->rc_mb) {
1149 reg = 0;
1150 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1151 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1152 reg |= p_h263->rc_frame_qp & 0x3F;
1153 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1154 }
1155
1156 /* frame rate */
1157 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1158 reg = 0;
1159 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1160 reg |= p->rc_framerate_denom & 0xFFFF;
1161 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1162 }
1163
1164 /* vbv buffer size */
1165 if (p->frame_skip_mode ==
1166 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1167 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1168
1169 if (p->rc_frame)
1170 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1171 }
1172
1173 mfc_debug_leave();
1174
1175 return 0;
1176 }
1177
1178 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1179 {
1180 struct s5p_mfc_dev *dev = ctx->dev;
1181 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1182 struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1183 unsigned int reg = 0;
1184 unsigned int val = 0;
1185
1186 mfc_debug_enter();
1187
1188 s5p_mfc_set_enc_params(ctx);
1189
1190 /* pictype : number of B */
1191 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
1192 reg &= ~(0x3 << 16);
1193 reg |= ((p->num_b_frame & 0x3) << 16);
1194 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
1195
1196 /* profile - 0 ~ 3 */
1197 reg = p_vp8->profile & 0x3;
1198 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1199
1200 /* rate control config. */
1201 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1202 /** macroblock level rate control */
1203 reg &= ~(0x1 << 8);
1204 reg |= ((p->rc_mb & 0x1) << 8);
1205 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1206
1207 /* frame rate */
1208 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1209 reg = 0;
1210 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1211 reg |= p->rc_framerate_denom & 0xFFFF;
1212 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1213 }
1214
1215 /* frame QP */
1216 reg &= ~(0x7F);
1217 reg |= p_vp8->rc_frame_qp & 0x7F;
1218 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1219
1220 /* other QPs */
1221 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1222 if (!p->rc_frame && !p->rc_mb) {
1223 reg = 0;
1224 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1225 reg |= p_vp8->rc_frame_qp & 0x7F;
1226 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1227 }
1228
1229 /* max QP */
1230 reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1231 /* min QP */
1232 reg |= p_vp8->rc_min_qp & 0x7F;
1233 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1234
1235 /* vbv buffer size */
1236 if (p->frame_skip_mode ==
1237 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1238 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1239
1240 if (p->rc_frame)
1241 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1242 }
1243
1244 /* VP8 specific params */
1245 reg = 0;
1246 reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1247 switch (p_vp8->num_partitions) {
1248 case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1249 val = 0;
1250 break;
1251 case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1252 val = 2;
1253 break;
1254 case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1255 val = 4;
1256 break;
1257 case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1258 val = 8;
1259 break;
1260 }
1261 reg |= (val & 0xF) << 3;
1262 reg |= (p_vp8->num_ref & 0x2);
1263 WRITEL(reg, S5P_FIMV_E_VP8_OPTIONS_V7);
1264
1265 mfc_debug_leave();
1266
1267 return 0;
1268 }
1269
1270 /* Initialize decoding */
1271 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1272 {
1273 struct s5p_mfc_dev *dev = ctx->dev;
1274 unsigned int reg = 0;
1275 int fmo_aso_ctrl = 0;
1276
1277 mfc_debug_enter();
1278 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1279 S5P_FIMV_CH_SEQ_HEADER_V6);
1280 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1281 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1282 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1283 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6));
1284
1285 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1286 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1287
1288 /* When user sets desplay_delay to 0,
1289 * It works as "display_delay enable" and delay set to 0.
1290 * If user wants display_delay disable, It should be
1291 * set to negative value. */
1292 if (ctx->display_delay >= 0) {
1293 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1294 WRITEL(ctx->display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
1295 }
1296
1297 if (IS_MFCV7(dev)) {
1298 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6);
1299 reg = 0;
1300 }
1301
1302 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1303 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1304 mfc_debug(2, "Set loop filter to: %d\n",
1305 ctx->loop_filter_mpeg4);
1306 reg |= (ctx->loop_filter_mpeg4 <<
1307 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1308 }
1309 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1310 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1311
1312 if (IS_MFCV7(dev))
1313 WRITEL(reg, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V7);
1314 else
1315 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6);
1316
1317 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1318 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1319 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
1320 else
1321 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
1322
1323
1324 /* sei parse */
1325 WRITEL(ctx->sei_fp_parse & 0x1, S5P_FIMV_D_SEI_ENABLE_V6);
1326
1327 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1328 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1329 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1330
1331 mfc_debug_leave();
1332 return 0;
1333 }
1334
1335 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1336 {
1337 struct s5p_mfc_dev *dev = ctx->dev;
1338
1339 if (flush) {
1340 dev->curr_ctx = ctx->num;
1341 s5p_mfc_clean_ctx_int_flags(ctx);
1342 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1343 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1344 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1345 }
1346 }
1347
1348 /* Decode a single frame */
1349 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1350 enum s5p_mfc_decode_arg last_frame)
1351 {
1352 struct s5p_mfc_dev *dev = ctx->dev;
1353
1354 WRITEL(ctx->dec_dst_flag, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
1355 WRITEL(ctx->slice_interface & 0x1, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
1356
1357 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1358 /* Issue different commands to instance basing on whether it
1359 * is the last frame or not. */
1360 switch (last_frame) {
1361 case 0:
1362 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1363 S5P_FIMV_CH_FRAME_START_V6, NULL);
1364 break;
1365 case 1:
1366 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1367 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1368 break;
1369 default:
1370 mfc_err("Unsupported last frame arg.\n");
1371 return -EINVAL;
1372 }
1373
1374 mfc_debug(2, "Decoding a usual frame.\n");
1375 return 0;
1376 }
1377
1378 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1379 {
1380 struct s5p_mfc_dev *dev = ctx->dev;
1381
1382 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1383 s5p_mfc_set_enc_params_h264(ctx);
1384 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1385 s5p_mfc_set_enc_params_mpeg4(ctx);
1386 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1387 s5p_mfc_set_enc_params_h263(ctx);
1388 else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1389 s5p_mfc_set_enc_params_vp8(ctx);
1390 else {
1391 mfc_err("Unknown codec for encoding (%x).\n",
1392 ctx->codec_mode);
1393 return -EINVAL;
1394 }
1395
1396 /* Set stride lengths */
1397 if (IS_MFCV7(dev)) {
1398 WRITEL(ctx->img_width, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
1399 WRITEL(ctx->img_width, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
1400 }
1401
1402 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1403 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1404 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1405
1406 return 0;
1407 }
1408
1409 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1410 {
1411 struct s5p_mfc_dev *dev = ctx->dev;
1412 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1413 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1414 int i;
1415
1416 if (p_h264->aso) {
1417 for (i = 0; i < 8; i++)
1418 WRITEL(p_h264->aso_slice_order[i],
1419 S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 + i * 4);
1420 }
1421 return 0;
1422 }
1423
1424 /* Encode a single frame */
1425 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1426 {
1427 struct s5p_mfc_dev *dev = ctx->dev;
1428
1429 mfc_debug(2, "++\n");
1430
1431 /* memory structure cur. frame */
1432
1433 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1434 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1435
1436 s5p_mfc_set_slice_mode(ctx);
1437
1438 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1439 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1440 S5P_FIMV_CH_FRAME_START_V6, NULL);
1441
1442 mfc_debug(2, "--\n");
1443
1444 return 0;
1445 }
1446
1447 static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1448 {
1449 unsigned long flags;
1450 int new_ctx;
1451 int cnt;
1452
1453 spin_lock_irqsave(&dev->condlock, flags);
1454 mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx,
1455 dev->ctx_work_bits);
1456 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1457 cnt = 0;
1458 while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1459 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1460 cnt++;
1461 if (cnt > MFC_NUM_CONTEXTS) {
1462 /* No contexts to run */
1463 spin_unlock_irqrestore(&dev->condlock, flags);
1464 return -EAGAIN;
1465 }
1466 }
1467 spin_unlock_irqrestore(&dev->condlock, flags);
1468 return new_ctx;
1469 }
1470
1471 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1472 {
1473 struct s5p_mfc_dev *dev = ctx->dev;
1474 struct s5p_mfc_buf *temp_vb;
1475 unsigned long flags;
1476
1477 spin_lock_irqsave(&dev->irqlock, flags);
1478
1479 /* Frames are being decoded */
1480 if (list_empty(&ctx->src_queue)) {
1481 mfc_debug(2, "No src buffers.\n");
1482 spin_unlock_irqrestore(&dev->irqlock, flags);
1483 return;
1484 }
1485 /* Get the next source buffer */
1486 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1487 temp_vb->flags |= MFC_BUF_FLAG_USED;
1488 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1489 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0);
1490 spin_unlock_irqrestore(&dev->irqlock, flags);
1491
1492 dev->curr_ctx = ctx->num;
1493 s5p_mfc_clean_ctx_int_flags(ctx);
1494 s5p_mfc_decode_one_frame_v6(ctx, 1);
1495 }
1496
1497 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1498 {
1499 struct s5p_mfc_dev *dev = ctx->dev;
1500 struct s5p_mfc_buf *temp_vb;
1501 unsigned long flags;
1502 int last_frame = 0;
1503
1504 if (ctx->state == MFCINST_FINISHING) {
1505 last_frame = MFC_DEC_LAST_FRAME;
1506 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1507 dev->curr_ctx = ctx->num;
1508 s5p_mfc_clean_ctx_int_flags(ctx);
1509 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1510 return 0;
1511 }
1512
1513 spin_lock_irqsave(&dev->irqlock, flags);
1514 /* Frames are being decoded */
1515 if (list_empty(&ctx->src_queue)) {
1516 mfc_debug(2, "No src buffers.\n");
1517 spin_unlock_irqrestore(&dev->irqlock, flags);
1518 return -EAGAIN;
1519 }
1520 /* Get the next source buffer */
1521 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1522 temp_vb->flags |= MFC_BUF_FLAG_USED;
1523 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1524 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1525 ctx->consumed_stream,
1526 temp_vb->b->v4l2_planes[0].bytesused);
1527 spin_unlock_irqrestore(&dev->irqlock, flags);
1528
1529 dev->curr_ctx = ctx->num;
1530 s5p_mfc_clean_ctx_int_flags(ctx);
1531 if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1532 last_frame = 1;
1533 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1534 ctx->state = MFCINST_FINISHING;
1535 }
1536 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1537
1538 return 0;
1539 }
1540
1541 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1542 {
1543 struct s5p_mfc_dev *dev = ctx->dev;
1544 unsigned long flags;
1545 struct s5p_mfc_buf *dst_mb;
1546 struct s5p_mfc_buf *src_mb;
1547 unsigned long src_y_addr, src_c_addr, dst_addr;
1548 /*
1549 unsigned int src_y_size, src_c_size;
1550 */
1551 unsigned int dst_size;
1552
1553 spin_lock_irqsave(&dev->irqlock, flags);
1554
1555 if (list_empty(&ctx->src_queue)) {
1556 mfc_debug(2, "no src buffers.\n");
1557 spin_unlock_irqrestore(&dev->irqlock, flags);
1558 return -EAGAIN;
1559 }
1560
1561 if (list_empty(&ctx->dst_queue)) {
1562 mfc_debug(2, "no dst buffers.\n");
1563 spin_unlock_irqrestore(&dev->irqlock, flags);
1564 return -EAGAIN;
1565 }
1566
1567 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1568 src_mb->flags |= MFC_BUF_FLAG_USED;
1569 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
1570 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
1571
1572 mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1573 mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1574
1575 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1576
1577 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1578 dst_mb->flags |= MFC_BUF_FLAG_USED;
1579 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1580 dst_size = vb2_plane_size(dst_mb->b, 0);
1581
1582 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1583
1584 spin_unlock_irqrestore(&dev->irqlock, flags);
1585
1586 dev->curr_ctx = ctx->num;
1587 s5p_mfc_clean_ctx_int_flags(ctx);
1588 s5p_mfc_encode_one_frame_v6(ctx);
1589
1590 return 0;
1591 }
1592
1593 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1594 {
1595 struct s5p_mfc_dev *dev = ctx->dev;
1596 unsigned long flags;
1597 struct s5p_mfc_buf *temp_vb;
1598
1599 /* Initializing decoding - parsing header */
1600 spin_lock_irqsave(&dev->irqlock, flags);
1601 mfc_debug(2, "Preparing to init decoding.\n");
1602 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1603 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1604 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1605 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0,
1606 temp_vb->b->v4l2_planes[0].bytesused);
1607 spin_unlock_irqrestore(&dev->irqlock, flags);
1608 dev->curr_ctx = ctx->num;
1609 s5p_mfc_clean_ctx_int_flags(ctx);
1610 s5p_mfc_init_decode_v6(ctx);
1611 }
1612
1613 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1614 {
1615 struct s5p_mfc_dev *dev = ctx->dev;
1616 unsigned long flags;
1617 struct s5p_mfc_buf *dst_mb;
1618 unsigned long dst_addr;
1619 unsigned int dst_size;
1620
1621 spin_lock_irqsave(&dev->irqlock, flags);
1622
1623 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1624 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1625 dst_size = vb2_plane_size(dst_mb->b, 0);
1626 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1627 spin_unlock_irqrestore(&dev->irqlock, flags);
1628 dev->curr_ctx = ctx->num;
1629 s5p_mfc_clean_ctx_int_flags(ctx);
1630 s5p_mfc_init_encode_v6(ctx);
1631 }
1632
1633 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1634 {
1635 struct s5p_mfc_dev *dev = ctx->dev;
1636 int ret;
1637 /* Header was parsed now start processing
1638 * First set the output frame buffers
1639 * s5p_mfc_alloc_dec_buffers(ctx); */
1640
1641 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1642 mfc_err("It seems that not all destionation buffers were\n"
1643 "mmaped.MFC requires that all destination are mmaped\n"
1644 "before starting processing.\n");
1645 return -EAGAIN;
1646 }
1647
1648 dev->curr_ctx = ctx->num;
1649 s5p_mfc_clean_ctx_int_flags(ctx);
1650 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1651 if (ret) {
1652 mfc_err("Failed to alloc frame mem.\n");
1653 ctx->state = MFCINST_ERROR;
1654 }
1655 return ret;
1656 }
1657
1658 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1659 {
1660 struct s5p_mfc_dev *dev = ctx->dev;
1661 int ret;
1662
1663 dev->curr_ctx = ctx->num;
1664 s5p_mfc_clean_ctx_int_flags(ctx);
1665 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1666 if (ret) {
1667 mfc_err("Failed to alloc frame mem.\n");
1668 ctx->state = MFCINST_ERROR;
1669 }
1670 return ret;
1671 }
1672
1673 /* Try running an operation on hardware */
1674 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1675 {
1676 struct s5p_mfc_ctx *ctx;
1677 int new_ctx;
1678 unsigned int ret = 0;
1679
1680 mfc_debug(1, "Try run dev: %p\n", dev);
1681
1682 /* Check whether hardware is not running */
1683 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1684 /* This is perfectly ok, the scheduled ctx should wait */
1685 mfc_debug(1, "Couldn't lock HW.\n");
1686 return;
1687 }
1688
1689 /* Choose the context to run */
1690 new_ctx = s5p_mfc_get_new_ctx(dev);
1691 if (new_ctx < 0) {
1692 /* No contexts to run */
1693 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1694 mfc_err("Failed to unlock hardware.\n");
1695 return;
1696 }
1697
1698 mfc_debug(1, "No ctx is scheduled to be run.\n");
1699 return;
1700 }
1701
1702 mfc_debug(1, "New context: %d\n", new_ctx);
1703 ctx = dev->ctx[new_ctx];
1704 mfc_debug(1, "Seting new context to %p\n", ctx);
1705 /* Got context to run in ctx */
1706 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1707 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1708 mfc_debug(1, "ctx->state=%d\n", ctx->state);
1709 /* Last frame has already been sent to MFC
1710 * Now obtaining frames from MFC buffer */
1711
1712 s5p_mfc_clock_on();
1713 if (ctx->type == MFCINST_DECODER) {
1714 switch (ctx->state) {
1715 case MFCINST_FINISHING:
1716 s5p_mfc_run_dec_last_frames(ctx);
1717 break;
1718 case MFCINST_RUNNING:
1719 ret = s5p_mfc_run_dec_frame(ctx);
1720 break;
1721 case MFCINST_INIT:
1722 s5p_mfc_clean_ctx_int_flags(ctx);
1723 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1724 ctx);
1725 break;
1726 case MFCINST_RETURN_INST:
1727 s5p_mfc_clean_ctx_int_flags(ctx);
1728 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1729 ctx);
1730 break;
1731 case MFCINST_GOT_INST:
1732 s5p_mfc_run_init_dec(ctx);
1733 break;
1734 case MFCINST_HEAD_PARSED:
1735 ret = s5p_mfc_run_init_dec_buffers(ctx);
1736 break;
1737 case MFCINST_FLUSH:
1738 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1739 break;
1740 case MFCINST_RES_CHANGE_INIT:
1741 s5p_mfc_run_dec_last_frames(ctx);
1742 break;
1743 case MFCINST_RES_CHANGE_FLUSH:
1744 s5p_mfc_run_dec_last_frames(ctx);
1745 break;
1746 case MFCINST_RES_CHANGE_END:
1747 mfc_debug(2, "Finished remaining frames after resolution change.\n");
1748 ctx->capture_state = QUEUE_FREE;
1749 mfc_debug(2, "Will re-init the codec`.\n");
1750 s5p_mfc_run_init_dec(ctx);
1751 break;
1752 default:
1753 ret = -EAGAIN;
1754 }
1755 } else if (ctx->type == MFCINST_ENCODER) {
1756 switch (ctx->state) {
1757 case MFCINST_FINISHING:
1758 case MFCINST_RUNNING:
1759 ret = s5p_mfc_run_enc_frame(ctx);
1760 break;
1761 case MFCINST_INIT:
1762 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1763 ctx);
1764 break;
1765 case MFCINST_RETURN_INST:
1766 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1767 ctx);
1768 break;
1769 case MFCINST_GOT_INST:
1770 s5p_mfc_run_init_enc(ctx);
1771 break;
1772 case MFCINST_HEAD_PRODUCED:
1773 ret = s5p_mfc_run_init_enc_buffers(ctx);
1774 break;
1775 default:
1776 ret = -EAGAIN;
1777 }
1778 } else {
1779 mfc_err("invalid context type: %d\n", ctx->type);
1780 ret = -EAGAIN;
1781 }
1782
1783 if (ret) {
1784 /* Free hardware lock */
1785 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1786 mfc_err("Failed to unlock hardware.\n");
1787
1788 /* This is in deed imporant, as no operation has been
1789 * scheduled, reduce the clock count as no one will
1790 * ever do this, because no interrupt related to this try_run
1791 * will ever come from hardware. */
1792 s5p_mfc_clock_off();
1793 }
1794 }
1795
1796
1797 static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1798 {
1799 struct s5p_mfc_buf *b;
1800 int i;
1801
1802 while (!list_empty(lh)) {
1803 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1804 for (i = 0; i < b->b->num_planes; i++)
1805 vb2_set_plane_payload(b->b, i, 0);
1806 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1807 list_del(&b->list);
1808 }
1809 }
1810
1811 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1812 {
1813 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
1814 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT_V6);
1815 }
1816
1817 static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1818 unsigned int ofs)
1819 {
1820 struct s5p_mfc_dev *dev = ctx->dev;
1821
1822 s5p_mfc_clock_on();
1823 WRITEL(data, ofs);
1824 s5p_mfc_clock_off();
1825 }
1826
1827 static unsigned int
1828 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1829 {
1830 struct s5p_mfc_dev *dev = ctx->dev;
1831 int ret;
1832
1833 s5p_mfc_clock_on();
1834 ret = READL(ofs);
1835 s5p_mfc_clock_off();
1836
1837 return ret;
1838 }
1839
1840 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1841 {
1842 return mfc_read(dev, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
1843 }
1844
1845 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1846 {
1847 return mfc_read(dev, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
1848 }
1849
1850 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1851 {
1852 return mfc_read(dev, S5P_FIMV_D_DISPLAY_STATUS_V6);
1853 }
1854
1855 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1856 {
1857 return mfc_read(dev, S5P_FIMV_D_DECODED_STATUS_V6);
1858 }
1859
1860 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1861 {
1862 return mfc_read(dev, S5P_FIMV_D_DECODED_FRAME_TYPE_V6) &
1863 S5P_FIMV_DECODE_FRAME_MASK_V6;
1864 }
1865
1866 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1867 {
1868 return mfc_read(ctx->dev, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6) &
1869 S5P_FIMV_DECODE_FRAME_MASK_V6;
1870 }
1871
1872 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1873 {
1874 return mfc_read(dev, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
1875 }
1876
1877 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1878 {
1879 return mfc_read(dev, S5P_FIMV_RISC2HOST_CMD_V6) &
1880 S5P_FIMV_RISC2HOST_CMD_MASK;
1881 }
1882
1883 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1884 {
1885 return mfc_read(dev, S5P_FIMV_ERROR_CODE_V6);
1886 }
1887
1888 static int s5p_mfc_err_dec_v6(unsigned int err)
1889 {
1890 return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1891 }
1892
1893 static int s5p_mfc_err_dspl_v6(unsigned int err)
1894 {
1895 return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1896 }
1897
1898 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1899 {
1900 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
1901 }
1902
1903 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1904 {
1905 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
1906 }
1907
1908 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1909 {
1910 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_DPB_V6);
1911 }
1912
1913 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1914 {
1915 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_MV_V6);
1916 }
1917
1918 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1919 {
1920 return mfc_read(dev, S5P_FIMV_RET_INSTANCE_ID_V6);
1921 }
1922
1923 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1924 {
1925 return mfc_read(dev, S5P_FIMV_E_NUM_DPB_V6);
1926 }
1927
1928 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1929 {
1930 return mfc_read(dev, S5P_FIMV_E_STREAM_SIZE_V6);
1931 }
1932
1933 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1934 {
1935 return mfc_read(dev, S5P_FIMV_E_SLICE_TYPE_V6);
1936 }
1937
1938 static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
1939 {
1940 return mfc_read(dev, S5P_FIMV_E_PICTURE_COUNT_V6);
1941 }
1942
1943 static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
1944 {
1945 return mfc_read(ctx->dev, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
1946 }
1947
1948 static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
1949 {
1950 return mfc_read(dev, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
1951 }
1952
1953 static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
1954 {
1955 return mfc_read(dev, S5P_FIMV_D_MVC_VIEW_ID_V6);
1956 }
1957
1958 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
1959 {
1960 return s5p_mfc_read_info_v6(ctx, PIC_TIME_TOP_V6);
1961 }
1962
1963 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
1964 {
1965 return s5p_mfc_read_info_v6(ctx, PIC_TIME_BOT_V6);
1966 }
1967
1968 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
1969 {
1970 return s5p_mfc_read_info_v6(ctx, CROP_INFO_H_V6);
1971 }
1972
1973 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
1974 {
1975 return s5p_mfc_read_info_v6(ctx, CROP_INFO_V_V6);
1976 }
1977
1978 /* Initialize opr function pointers for MFC v6 */
1979 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
1980 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
1981 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
1982 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
1983 .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
1984 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
1985 .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
1986 .alloc_dev_context_buffer =
1987 s5p_mfc_alloc_dev_context_buffer_v6,
1988 .release_dev_context_buffer =
1989 s5p_mfc_release_dev_context_buffer_v6,
1990 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
1991 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
1992 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
1993 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
1994 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
1995 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
1996 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
1997 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
1998 .init_decode = s5p_mfc_init_decode_v6,
1999 .init_encode = s5p_mfc_init_encode_v6,
2000 .encode_one_frame = s5p_mfc_encode_one_frame_v6,
2001 .try_run = s5p_mfc_try_run_v6,
2002 .cleanup_queue = s5p_mfc_cleanup_queue_v6,
2003 .clear_int_flags = s5p_mfc_clear_int_flags_v6,
2004 .write_info = s5p_mfc_write_info_v6,
2005 .read_info = s5p_mfc_read_info_v6,
2006 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2007 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2008 .get_dspl_status = s5p_mfc_get_dspl_status_v6,
2009 .get_dec_status = s5p_mfc_get_dec_status_v6,
2010 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2011 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2012 .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2013 .get_int_reason = s5p_mfc_get_int_reason_v6,
2014 .get_int_err = s5p_mfc_get_int_err_v6,
2015 .err_dec = s5p_mfc_err_dec_v6,
2016 .err_dspl = s5p_mfc_err_dspl_v6,
2017 .get_img_width = s5p_mfc_get_img_width_v6,
2018 .get_img_height = s5p_mfc_get_img_height_v6,
2019 .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2020 .get_mv_count = s5p_mfc_get_mv_count_v6,
2021 .get_inst_no = s5p_mfc_get_inst_no_v6,
2022 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2023 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2024 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2025 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
2026 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
2027 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
2028 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
2029 .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2030 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2031 .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2032 .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2033 };
2034
2035 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2036 {
2037 return &s5p_mfc_ops_v6;
2038 }
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