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[mirror_ubuntu-bionic-kernel.git] / drivers / media / platform / ti-vpe / vpe.c
1 /*
2 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
3 *
4 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 *
13 * Based on the virtual v4l2-mem2mem example device
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation
18 */
19
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
23 #include <linux/fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/ioctl.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/videodev2.h>
34 #include <linux/log2.h>
35 #include <linux/sizes.h>
36
37 #include <media/v4l2-common.h>
38 #include <media/v4l2-ctrls.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-event.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-mem2mem.h>
43 #include <media/videobuf2-v4l2.h>
44 #include <media/videobuf2-dma-contig.h>
45
46 #include "vpdma.h"
47 #include "vpdma_priv.h"
48 #include "vpe_regs.h"
49 #include "sc.h"
50 #include "csc.h"
51
52 #define VPE_MODULE_NAME "vpe"
53
54 /* minimum and maximum frame sizes */
55 #define MIN_W 32
56 #define MIN_H 32
57 #define MAX_W 2048
58 #define MAX_H 1184
59
60 /* required alignments */
61 #define S_ALIGN 0 /* multiple of 1 */
62 #define H_ALIGN 1 /* multiple of 2 */
63
64 /* flags that indicate a format can be used for capture/output */
65 #define VPE_FMT_TYPE_CAPTURE (1 << 0)
66 #define VPE_FMT_TYPE_OUTPUT (1 << 1)
67
68 /* used as plane indices */
69 #define VPE_MAX_PLANES 2
70 #define VPE_LUMA 0
71 #define VPE_CHROMA 1
72
73 /* per m2m context info */
74 #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
75
76 #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
77
78 /*
79 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
80 * 3 output descriptors, and 10 control descriptors
81 */
82 #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
83 13 * VPDMA_CFD_CTD_DESC_SIZE)
84
85 #define vpe_dbg(vpedev, fmt, arg...) \
86 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
87 #define vpe_err(vpedev, fmt, arg...) \
88 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
89
90 struct vpe_us_coeffs {
91 unsigned short anchor_fid0_c0;
92 unsigned short anchor_fid0_c1;
93 unsigned short anchor_fid0_c2;
94 unsigned short anchor_fid0_c3;
95 unsigned short interp_fid0_c0;
96 unsigned short interp_fid0_c1;
97 unsigned short interp_fid0_c2;
98 unsigned short interp_fid0_c3;
99 unsigned short anchor_fid1_c0;
100 unsigned short anchor_fid1_c1;
101 unsigned short anchor_fid1_c2;
102 unsigned short anchor_fid1_c3;
103 unsigned short interp_fid1_c0;
104 unsigned short interp_fid1_c1;
105 unsigned short interp_fid1_c2;
106 unsigned short interp_fid1_c3;
107 };
108
109 /*
110 * Default upsampler coefficients
111 */
112 static const struct vpe_us_coeffs us_coeffs[] = {
113 {
114 /* Coefficients for progressive input */
115 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
116 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
117 },
118 {
119 /* Coefficients for Top Field Interlaced input */
120 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
121 /* Coefficients for Bottom Field Interlaced input */
122 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
123 },
124 };
125
126 /*
127 * the following registers are for configuring some of the parameters of the
128 * motion and edge detection blocks inside DEI, these generally remain the same,
129 * these could be passed later via userspace if some one needs to tweak these.
130 */
131 struct vpe_dei_regs {
132 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
133 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
134 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
135 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
136 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
137 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
138 };
139
140 /*
141 * default expert DEI register values, unlikely to be modified.
142 */
143 static const struct vpe_dei_regs dei_regs = {
144 .mdt_spacial_freq_thr_reg = 0x020C0804u,
145 .edi_config_reg = 0x0118100Cu,
146 .edi_lut_reg0 = 0x08040200u,
147 .edi_lut_reg1 = 0x1010100Cu,
148 .edi_lut_reg2 = 0x10101010u,
149 .edi_lut_reg3 = 0x10101010u,
150 };
151
152 /*
153 * The port_data structure contains per-port data.
154 */
155 struct vpe_port_data {
156 enum vpdma_channel channel; /* VPDMA channel */
157 u8 vb_index; /* input frame f, f-1, f-2 index */
158 u8 vb_part; /* plane index for co-panar formats */
159 };
160
161 /*
162 * Define indices into the port_data tables
163 */
164 #define VPE_PORT_LUMA1_IN 0
165 #define VPE_PORT_CHROMA1_IN 1
166 #define VPE_PORT_LUMA2_IN 2
167 #define VPE_PORT_CHROMA2_IN 3
168 #define VPE_PORT_LUMA3_IN 4
169 #define VPE_PORT_CHROMA3_IN 5
170 #define VPE_PORT_MV_IN 6
171 #define VPE_PORT_MV_OUT 7
172 #define VPE_PORT_LUMA_OUT 8
173 #define VPE_PORT_CHROMA_OUT 9
174 #define VPE_PORT_RGB_OUT 10
175
176 static const struct vpe_port_data port_data[11] = {
177 [VPE_PORT_LUMA1_IN] = {
178 .channel = VPE_CHAN_LUMA1_IN,
179 .vb_index = 0,
180 .vb_part = VPE_LUMA,
181 },
182 [VPE_PORT_CHROMA1_IN] = {
183 .channel = VPE_CHAN_CHROMA1_IN,
184 .vb_index = 0,
185 .vb_part = VPE_CHROMA,
186 },
187 [VPE_PORT_LUMA2_IN] = {
188 .channel = VPE_CHAN_LUMA2_IN,
189 .vb_index = 1,
190 .vb_part = VPE_LUMA,
191 },
192 [VPE_PORT_CHROMA2_IN] = {
193 .channel = VPE_CHAN_CHROMA2_IN,
194 .vb_index = 1,
195 .vb_part = VPE_CHROMA,
196 },
197 [VPE_PORT_LUMA3_IN] = {
198 .channel = VPE_CHAN_LUMA3_IN,
199 .vb_index = 2,
200 .vb_part = VPE_LUMA,
201 },
202 [VPE_PORT_CHROMA3_IN] = {
203 .channel = VPE_CHAN_CHROMA3_IN,
204 .vb_index = 2,
205 .vb_part = VPE_CHROMA,
206 },
207 [VPE_PORT_MV_IN] = {
208 .channel = VPE_CHAN_MV_IN,
209 },
210 [VPE_PORT_MV_OUT] = {
211 .channel = VPE_CHAN_MV_OUT,
212 },
213 [VPE_PORT_LUMA_OUT] = {
214 .channel = VPE_CHAN_LUMA_OUT,
215 .vb_part = VPE_LUMA,
216 },
217 [VPE_PORT_CHROMA_OUT] = {
218 .channel = VPE_CHAN_CHROMA_OUT,
219 .vb_part = VPE_CHROMA,
220 },
221 [VPE_PORT_RGB_OUT] = {
222 .channel = VPE_CHAN_RGB_OUT,
223 .vb_part = VPE_LUMA,
224 },
225 };
226
227
228 /* driver info for each of the supported video formats */
229 struct vpe_fmt {
230 char *name; /* human-readable name */
231 u32 fourcc; /* standard format identifier */
232 u8 types; /* CAPTURE and/or OUTPUT */
233 u8 coplanar; /* set for unpacked Luma and Chroma */
234 /* vpdma format info for each plane */
235 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
236 };
237
238 static struct vpe_fmt vpe_formats[] = {
239 {
240 .name = "YUV 422 co-planar",
241 .fourcc = V4L2_PIX_FMT_NV16,
242 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
243 .coplanar = 1,
244 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
245 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
246 },
247 },
248 {
249 .name = "YUV 420 co-planar",
250 .fourcc = V4L2_PIX_FMT_NV12,
251 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
252 .coplanar = 1,
253 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
254 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
255 },
256 },
257 {
258 .name = "YUYV 422 packed",
259 .fourcc = V4L2_PIX_FMT_YUYV,
260 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
261 .coplanar = 0,
262 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422],
263 },
264 },
265 {
266 .name = "UYVY 422 packed",
267 .fourcc = V4L2_PIX_FMT_UYVY,
268 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
269 .coplanar = 0,
270 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422],
271 },
272 },
273 {
274 .name = "RGB888 packed",
275 .fourcc = V4L2_PIX_FMT_RGB24,
276 .types = VPE_FMT_TYPE_CAPTURE,
277 .coplanar = 0,
278 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
279 },
280 },
281 {
282 .name = "ARGB32",
283 .fourcc = V4L2_PIX_FMT_RGB32,
284 .types = VPE_FMT_TYPE_CAPTURE,
285 .coplanar = 0,
286 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
287 },
288 },
289 {
290 .name = "BGR888 packed",
291 .fourcc = V4L2_PIX_FMT_BGR24,
292 .types = VPE_FMT_TYPE_CAPTURE,
293 .coplanar = 0,
294 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
295 },
296 },
297 {
298 .name = "ABGR32",
299 .fourcc = V4L2_PIX_FMT_BGR32,
300 .types = VPE_FMT_TYPE_CAPTURE,
301 .coplanar = 0,
302 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
303 },
304 },
305 {
306 .name = "RGB565",
307 .fourcc = V4L2_PIX_FMT_RGB565,
308 .types = VPE_FMT_TYPE_CAPTURE,
309 .coplanar = 0,
310 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
311 },
312 },
313 {
314 .name = "RGB5551",
315 .fourcc = V4L2_PIX_FMT_RGB555,
316 .types = VPE_FMT_TYPE_CAPTURE,
317 .coplanar = 0,
318 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
319 },
320 },
321 };
322
323 /*
324 * per-queue, driver-specific private data.
325 * there is one source queue and one destination queue for each m2m context.
326 */
327 struct vpe_q_data {
328 unsigned int width; /* frame width */
329 unsigned int height; /* frame height */
330 unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
331 enum v4l2_colorspace colorspace;
332 enum v4l2_field field; /* supported field value */
333 unsigned int flags;
334 unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
335 struct v4l2_rect c_rect; /* crop/compose rectangle */
336 struct vpe_fmt *fmt; /* format info */
337 };
338
339 /* vpe_q_data flag bits */
340 #define Q_DATA_FRAME_1D BIT(0)
341 #define Q_DATA_MODE_TILED BIT(1)
342 #define Q_DATA_INTERLACED_ALTERNATE BIT(2)
343 #define Q_DATA_INTERLACED_SEQ_TB BIT(3)
344
345 #define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \
346 Q_DATA_INTERLACED_SEQ_TB)
347
348 enum {
349 Q_DATA_SRC = 0,
350 Q_DATA_DST = 1,
351 };
352
353 /* find our format description corresponding to the passed v4l2_format */
354 static struct vpe_fmt *find_format(struct v4l2_format *f)
355 {
356 struct vpe_fmt *fmt;
357 unsigned int k;
358
359 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
360 fmt = &vpe_formats[k];
361 if (fmt->fourcc == f->fmt.pix.pixelformat)
362 return fmt;
363 }
364
365 return NULL;
366 }
367
368 /*
369 * there is one vpe_dev structure in the driver, it is shared by
370 * all instances.
371 */
372 struct vpe_dev {
373 struct v4l2_device v4l2_dev;
374 struct video_device vfd;
375 struct v4l2_m2m_dev *m2m_dev;
376
377 atomic_t num_instances; /* count of driver instances */
378 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
379 struct mutex dev_mutex;
380 spinlock_t lock;
381
382 int irq;
383 void __iomem *base;
384 struct resource *res;
385
386 struct vpdma_data *vpdma; /* vpdma data handle */
387 struct sc_data *sc; /* scaler data handle */
388 struct csc_data *csc; /* csc data handle */
389 };
390
391 /*
392 * There is one vpe_ctx structure for each m2m context.
393 */
394 struct vpe_ctx {
395 struct v4l2_fh fh;
396 struct vpe_dev *dev;
397 struct v4l2_ctrl_handler hdl;
398
399 unsigned int field; /* current field */
400 unsigned int sequence; /* current frame/field seq */
401 unsigned int aborting; /* abort after next irq */
402
403 unsigned int bufs_per_job; /* input buffers per batch */
404 unsigned int bufs_completed; /* bufs done in this batch */
405
406 struct vpe_q_data q_data[2]; /* src & dst queue data */
407 struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
408 struct vb2_v4l2_buffer *dst_vb;
409
410 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
411 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
412 size_t mv_buf_size; /* current motion vector buffer size */
413 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
414 struct vpdma_buf sc_coeff_h; /* h coeff buffer */
415 struct vpdma_buf sc_coeff_v; /* v coeff buffer */
416 struct vpdma_desc_list desc_list; /* DMA descriptor list */
417
418 bool deinterlacing; /* using de-interlacer */
419 bool load_mmrs; /* have new shadow reg values */
420
421 unsigned int src_mv_buf_selector;
422 };
423
424
425 /*
426 * M2M devices get 2 queues.
427 * Return the queue given the type.
428 */
429 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
430 enum v4l2_buf_type type)
431 {
432 switch (type) {
433 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
434 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
435 return &ctx->q_data[Q_DATA_SRC];
436 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
437 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
438 return &ctx->q_data[Q_DATA_DST];
439 default:
440 return NULL;
441 }
442 return NULL;
443 }
444
445 static u32 read_reg(struct vpe_dev *dev, int offset)
446 {
447 return ioread32(dev->base + offset);
448 }
449
450 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
451 {
452 iowrite32(value, dev->base + offset);
453 }
454
455 /* register field read/write helpers */
456 static int get_field(u32 value, u32 mask, int shift)
457 {
458 return (value & (mask << shift)) >> shift;
459 }
460
461 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
462 {
463 return get_field(read_reg(dev, offset), mask, shift);
464 }
465
466 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
467 {
468 u32 val = *valp;
469
470 val &= ~(mask << shift);
471 val |= (field & mask) << shift;
472 *valp = val;
473 }
474
475 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
476 u32 mask, int shift)
477 {
478 u32 val = read_reg(dev, offset);
479
480 write_field(&val, field, mask, shift);
481
482 write_reg(dev, offset, val);
483 }
484
485 /*
486 * DMA address/data block for the shadow registers
487 */
488 struct vpe_mmr_adb {
489 struct vpdma_adb_hdr out_fmt_hdr;
490 u32 out_fmt_reg[1];
491 u32 out_fmt_pad[3];
492 struct vpdma_adb_hdr us1_hdr;
493 u32 us1_regs[8];
494 struct vpdma_adb_hdr us2_hdr;
495 u32 us2_regs[8];
496 struct vpdma_adb_hdr us3_hdr;
497 u32 us3_regs[8];
498 struct vpdma_adb_hdr dei_hdr;
499 u32 dei_regs[8];
500 struct vpdma_adb_hdr sc_hdr0;
501 u32 sc_regs0[7];
502 u32 sc_pad0[1];
503 struct vpdma_adb_hdr sc_hdr8;
504 u32 sc_regs8[6];
505 u32 sc_pad8[2];
506 struct vpdma_adb_hdr sc_hdr17;
507 u32 sc_regs17[9];
508 u32 sc_pad17[3];
509 struct vpdma_adb_hdr csc_hdr;
510 u32 csc_regs[6];
511 u32 csc_pad[2];
512 };
513
514 #define GET_OFFSET_TOP(ctx, obj, reg) \
515 ((obj)->res->start - ctx->dev->res->start + reg)
516
517 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
518 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
519 /*
520 * Set the headers for all of the address/data block structures.
521 */
522 static void init_adb_hdrs(struct vpe_ctx *ctx)
523 {
524 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
525 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
526 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
527 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
528 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
529 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
530 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
531 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
532 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
533 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
534 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
535 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
536 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
537 };
538
539 /*
540 * Allocate or re-allocate the motion vector DMA buffers
541 * There are two buffers, one for input and one for output.
542 * However, the roles are reversed after each field is processed.
543 * In other words, after each field is processed, the previous
544 * output (dst) MV buffer becomes the new input (src) MV buffer.
545 */
546 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
547 {
548 struct device *dev = ctx->dev->v4l2_dev.dev;
549
550 if (ctx->mv_buf_size == size)
551 return 0;
552
553 if (ctx->mv_buf[0])
554 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
555 ctx->mv_buf_dma[0]);
556
557 if (ctx->mv_buf[1])
558 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
559 ctx->mv_buf_dma[1]);
560
561 if (size == 0)
562 return 0;
563
564 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
565 GFP_KERNEL);
566 if (!ctx->mv_buf[0]) {
567 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
568 return -ENOMEM;
569 }
570
571 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
572 GFP_KERNEL);
573 if (!ctx->mv_buf[1]) {
574 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
575 dma_free_coherent(dev, size, ctx->mv_buf[0],
576 ctx->mv_buf_dma[0]);
577
578 return -ENOMEM;
579 }
580
581 ctx->mv_buf_size = size;
582 ctx->src_mv_buf_selector = 0;
583
584 return 0;
585 }
586
587 static void free_mv_buffers(struct vpe_ctx *ctx)
588 {
589 realloc_mv_buffers(ctx, 0);
590 }
591
592 /*
593 * While de-interlacing, we keep the two most recent input buffers
594 * around. This function frees those two buffers when we have
595 * finished processing the current stream.
596 */
597 static void free_vbs(struct vpe_ctx *ctx)
598 {
599 struct vpe_dev *dev = ctx->dev;
600 unsigned long flags;
601
602 if (ctx->src_vbs[2] == NULL)
603 return;
604
605 spin_lock_irqsave(&dev->lock, flags);
606 if (ctx->src_vbs[2]) {
607 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
608 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
609 }
610 spin_unlock_irqrestore(&dev->lock, flags);
611 }
612
613 /*
614 * Enable or disable the VPE clocks
615 */
616 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
617 {
618 u32 val = 0;
619
620 if (on)
621 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
622 write_reg(dev, VPE_CLK_ENABLE, val);
623 }
624
625 static void vpe_top_reset(struct vpe_dev *dev)
626 {
627
628 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
629 VPE_DATA_PATH_CLK_RESET_SHIFT);
630
631 usleep_range(100, 150);
632
633 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
634 VPE_DATA_PATH_CLK_RESET_SHIFT);
635 }
636
637 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
638 {
639 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
640 VPE_VPDMA_CLK_RESET_SHIFT);
641
642 usleep_range(100, 150);
643
644 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
645 VPE_VPDMA_CLK_RESET_SHIFT);
646 }
647
648 /*
649 * Load the correct of upsampler coefficients into the shadow MMRs
650 */
651 static void set_us_coefficients(struct vpe_ctx *ctx)
652 {
653 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
654 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
655 u32 *us1_reg = &mmr_adb->us1_regs[0];
656 u32 *us2_reg = &mmr_adb->us2_regs[0];
657 u32 *us3_reg = &mmr_adb->us3_regs[0];
658 const unsigned short *cp, *end_cp;
659
660 cp = &us_coeffs[0].anchor_fid0_c0;
661
662 if (s_q_data->flags & Q_IS_INTERLACED) /* interlaced */
663 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
664
665 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
666
667 while (cp < end_cp) {
668 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
669 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
670 *us2_reg++ = *us1_reg;
671 *us3_reg++ = *us1_reg++;
672 }
673 ctx->load_mmrs = true;
674 }
675
676 /*
677 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
678 */
679 static void set_cfg_modes(struct vpe_ctx *ctx)
680 {
681 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
682 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
683 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
684 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
685 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
686 int cfg_mode = 1;
687
688 /*
689 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
690 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
691 */
692
693 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
694 cfg_mode = 0;
695
696 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
697 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
698 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
699
700 ctx->load_mmrs = true;
701 }
702
703 static void set_line_modes(struct vpe_ctx *ctx)
704 {
705 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
706 int line_mode = 1;
707
708 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
709 line_mode = 0; /* double lines to line buffer */
710
711 /* regs for now */
712 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
713 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
714 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
715
716 /* frame start for input luma */
717 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
718 VPE_CHAN_LUMA1_IN);
719 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
720 VPE_CHAN_LUMA2_IN);
721 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
722 VPE_CHAN_LUMA3_IN);
723
724 /* frame start for input chroma */
725 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
726 VPE_CHAN_CHROMA1_IN);
727 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
728 VPE_CHAN_CHROMA2_IN);
729 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
730 VPE_CHAN_CHROMA3_IN);
731
732 /* frame start for MV in client */
733 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
734 VPE_CHAN_MV_IN);
735 }
736
737 /*
738 * Set the shadow registers that are modified when the source
739 * format changes.
740 */
741 static void set_src_registers(struct vpe_ctx *ctx)
742 {
743 set_us_coefficients(ctx);
744 }
745
746 /*
747 * Set the shadow registers that are modified when the destination
748 * format changes.
749 */
750 static void set_dst_registers(struct vpe_ctx *ctx)
751 {
752 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
753 enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
754 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
755 u32 val = 0;
756
757 if (clrspc == V4L2_COLORSPACE_SRGB) {
758 val |= VPE_RGB_OUT_SELECT;
759 vpdma_set_bg_color(ctx->dev->vpdma,
760 (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
761 } else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
762 val |= VPE_COLOR_SEPARATE_422;
763
764 /*
765 * the source of CHR_DS and CSC is always the scaler, irrespective of
766 * whether it's used or not
767 */
768 val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
769
770 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
771 val |= VPE_DS_BYPASS;
772
773 mmr_adb->out_fmt_reg[0] = val;
774
775 ctx->load_mmrs = true;
776 }
777
778 /*
779 * Set the de-interlacer shadow register values
780 */
781 static void set_dei_regs(struct vpe_ctx *ctx)
782 {
783 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
784 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
785 unsigned int src_h = s_q_data->c_rect.height;
786 unsigned int src_w = s_q_data->c_rect.width;
787 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
788 bool deinterlace = true;
789 u32 val = 0;
790
791 /*
792 * according to TRM, we should set DEI in progressive bypass mode when
793 * the input content is progressive, however, DEI is bypassed correctly
794 * for both progressive and interlace content in interlace bypass mode.
795 * It has been recommended not to use progressive bypass mode.
796 */
797 if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
798 deinterlace = false;
799 val = VPE_DEI_INTERLACE_BYPASS;
800 }
801
802 src_h = deinterlace ? src_h * 2 : src_h;
803
804 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
805 (src_w << VPE_DEI_WIDTH_SHIFT) |
806 VPE_DEI_FIELD_FLUSH;
807
808 *dei_mmr0 = val;
809
810 ctx->load_mmrs = true;
811 }
812
813 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
814 {
815 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
816 u32 *dei_mmr = &mmr_adb->dei_regs[0];
817 const struct vpe_dei_regs *cur = &dei_regs;
818
819 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
820 dei_mmr[3] = cur->edi_config_reg;
821 dei_mmr[4] = cur->edi_lut_reg0;
822 dei_mmr[5] = cur->edi_lut_reg1;
823 dei_mmr[6] = cur->edi_lut_reg2;
824 dei_mmr[7] = cur->edi_lut_reg3;
825
826 ctx->load_mmrs = true;
827 }
828
829 static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
830 {
831 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
832 u32 *edi_config_reg = &mmr_adb->dei_regs[3];
833
834 if (mode & 0x2)
835 write_field(edi_config_reg, 1, 1, 2); /* EDI_ENABLE_3D */
836
837 if (mode & 0x3)
838 write_field(edi_config_reg, 1, 1, 3); /* EDI_CHROMA_3D */
839
840 write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
841 VPE_EDI_INP_MODE_SHIFT);
842
843 ctx->load_mmrs = true;
844 }
845
846 /*
847 * Set the shadow registers whose values are modified when either the
848 * source or destination format is changed.
849 */
850 static int set_srcdst_params(struct vpe_ctx *ctx)
851 {
852 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
853 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
854 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
855 unsigned int src_w = s_q_data->c_rect.width;
856 unsigned int src_h = s_q_data->c_rect.height;
857 unsigned int dst_w = d_q_data->c_rect.width;
858 unsigned int dst_h = d_q_data->c_rect.height;
859 size_t mv_buf_size;
860 int ret;
861
862 ctx->sequence = 0;
863 ctx->field = V4L2_FIELD_TOP;
864
865 if ((s_q_data->flags & Q_IS_INTERLACED) &&
866 !(d_q_data->flags & Q_IS_INTERLACED)) {
867 int bytes_per_line;
868 const struct vpdma_data_format *mv =
869 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
870
871 /*
872 * we make sure that the source image has a 16 byte aligned
873 * stride, we need to do the same for the motion vector buffer
874 * by aligning it's stride to the next 16 byte boundry. this
875 * extra space will not be used by the de-interlacer, but will
876 * ensure that vpdma operates correctly
877 */
878 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
879 VPDMA_STRIDE_ALIGN);
880 mv_buf_size = bytes_per_line * s_q_data->height;
881
882 ctx->deinterlacing = true;
883 src_h <<= 1;
884 } else {
885 ctx->deinterlacing = false;
886 mv_buf_size = 0;
887 }
888
889 free_vbs(ctx);
890 ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
891
892 ret = realloc_mv_buffers(ctx, mv_buf_size);
893 if (ret)
894 return ret;
895
896 set_cfg_modes(ctx);
897 set_dei_regs(ctx);
898
899 csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
900 s_q_data->colorspace, d_q_data->colorspace);
901
902 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
903 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
904
905 sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
906 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
907 src_w, src_h, dst_w, dst_h);
908
909 return 0;
910 }
911
912 /*
913 * Return the vpe_ctx structure for a given struct file
914 */
915 static struct vpe_ctx *file2ctx(struct file *file)
916 {
917 return container_of(file->private_data, struct vpe_ctx, fh);
918 }
919
920 /*
921 * mem2mem callbacks
922 */
923
924 /**
925 * job_ready() - check whether an instance is ready to be scheduled to run
926 */
927 static int job_ready(void *priv)
928 {
929 struct vpe_ctx *ctx = priv;
930
931 /*
932 * This check is needed as this might be called directly from driver
933 * When called by m2m framework, this will always satisfy, but when
934 * called from vpe_irq, this might fail. (src stream with zero buffers)
935 */
936 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
937 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
938 return 0;
939
940 return 1;
941 }
942
943 static void job_abort(void *priv)
944 {
945 struct vpe_ctx *ctx = priv;
946
947 /* Will cancel the transaction in the next interrupt handler */
948 ctx->aborting = 1;
949 }
950
951 /*
952 * Lock access to the device
953 */
954 static void vpe_lock(void *priv)
955 {
956 struct vpe_ctx *ctx = priv;
957 struct vpe_dev *dev = ctx->dev;
958 mutex_lock(&dev->dev_mutex);
959 }
960
961 static void vpe_unlock(void *priv)
962 {
963 struct vpe_ctx *ctx = priv;
964 struct vpe_dev *dev = ctx->dev;
965 mutex_unlock(&dev->dev_mutex);
966 }
967
968 static void vpe_dump_regs(struct vpe_dev *dev)
969 {
970 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
971
972 vpe_dbg(dev, "VPE Registers:\n");
973
974 DUMPREG(PID);
975 DUMPREG(SYSCONFIG);
976 DUMPREG(INT0_STATUS0_RAW);
977 DUMPREG(INT0_STATUS0);
978 DUMPREG(INT0_ENABLE0);
979 DUMPREG(INT0_STATUS1_RAW);
980 DUMPREG(INT0_STATUS1);
981 DUMPREG(INT0_ENABLE1);
982 DUMPREG(CLK_ENABLE);
983 DUMPREG(CLK_RESET);
984 DUMPREG(CLK_FORMAT_SELECT);
985 DUMPREG(CLK_RANGE_MAP);
986 DUMPREG(US1_R0);
987 DUMPREG(US1_R1);
988 DUMPREG(US1_R2);
989 DUMPREG(US1_R3);
990 DUMPREG(US1_R4);
991 DUMPREG(US1_R5);
992 DUMPREG(US1_R6);
993 DUMPREG(US1_R7);
994 DUMPREG(US2_R0);
995 DUMPREG(US2_R1);
996 DUMPREG(US2_R2);
997 DUMPREG(US2_R3);
998 DUMPREG(US2_R4);
999 DUMPREG(US2_R5);
1000 DUMPREG(US2_R6);
1001 DUMPREG(US2_R7);
1002 DUMPREG(US3_R0);
1003 DUMPREG(US3_R1);
1004 DUMPREG(US3_R2);
1005 DUMPREG(US3_R3);
1006 DUMPREG(US3_R4);
1007 DUMPREG(US3_R5);
1008 DUMPREG(US3_R6);
1009 DUMPREG(US3_R7);
1010 DUMPREG(DEI_FRAME_SIZE);
1011 DUMPREG(MDT_BYPASS);
1012 DUMPREG(MDT_SF_THRESHOLD);
1013 DUMPREG(EDI_CONFIG);
1014 DUMPREG(DEI_EDI_LUT_R0);
1015 DUMPREG(DEI_EDI_LUT_R1);
1016 DUMPREG(DEI_EDI_LUT_R2);
1017 DUMPREG(DEI_EDI_LUT_R3);
1018 DUMPREG(DEI_FMD_WINDOW_R0);
1019 DUMPREG(DEI_FMD_WINDOW_R1);
1020 DUMPREG(DEI_FMD_CONTROL_R0);
1021 DUMPREG(DEI_FMD_CONTROL_R1);
1022 DUMPREG(DEI_FMD_STATUS_R0);
1023 DUMPREG(DEI_FMD_STATUS_R1);
1024 DUMPREG(DEI_FMD_STATUS_R2);
1025 #undef DUMPREG
1026
1027 sc_dump_regs(dev->sc);
1028 csc_dump_regs(dev->csc);
1029 }
1030
1031 static void add_out_dtd(struct vpe_ctx *ctx, int port)
1032 {
1033 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1034 const struct vpe_port_data *p_data = &port_data[port];
1035 struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1036 struct vpe_fmt *fmt = q_data->fmt;
1037 const struct vpdma_data_format *vpdma_fmt;
1038 int mv_buf_selector = !ctx->src_mv_buf_selector;
1039 dma_addr_t dma_addr;
1040 u32 flags = 0;
1041
1042 if (port == VPE_PORT_MV_OUT) {
1043 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1044 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1045 } else {
1046 /* to incorporate interleaved formats */
1047 int plane = fmt->coplanar ? p_data->vb_part : 0;
1048
1049 vpdma_fmt = fmt->vpdma_fmt[plane];
1050 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1051 if (!dma_addr) {
1052 vpe_err(ctx->dev,
1053 "acquiring output buffer(%d) dma_addr failed\n",
1054 port);
1055 return;
1056 }
1057 }
1058
1059 if (q_data->flags & Q_DATA_FRAME_1D)
1060 flags |= VPDMA_DATA_FRAME_1D;
1061 if (q_data->flags & Q_DATA_MODE_TILED)
1062 flags |= VPDMA_DATA_MODE_TILED;
1063
1064 vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1065 MAX_W, MAX_H);
1066
1067 vpdma_add_out_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1068 vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1069 MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1070 }
1071
1072 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1073 {
1074 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1075 const struct vpe_port_data *p_data = &port_data[port];
1076 struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1077 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1078 struct vpe_fmt *fmt = q_data->fmt;
1079 const struct vpdma_data_format *vpdma_fmt;
1080 int mv_buf_selector = ctx->src_mv_buf_selector;
1081 int field = vbuf->field == V4L2_FIELD_BOTTOM;
1082 int frame_width, frame_height;
1083 dma_addr_t dma_addr;
1084 u32 flags = 0;
1085
1086 if (port == VPE_PORT_MV_IN) {
1087 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1088 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1089 } else {
1090 /* to incorporate interleaved formats */
1091 int plane = fmt->coplanar ? p_data->vb_part : 0;
1092
1093 vpdma_fmt = fmt->vpdma_fmt[plane];
1094
1095 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1096 if (!dma_addr) {
1097 vpe_err(ctx->dev,
1098 "acquiring input buffer(%d) dma_addr failed\n",
1099 port);
1100 return;
1101 }
1102
1103 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) {
1104 /*
1105 * Use top or bottom field from same vb alternately
1106 * f,f-1,f-2 = TBT when seq is even
1107 * f,f-1,f-2 = BTB when seq is odd
1108 */
1109 field = (p_data->vb_index + (ctx->sequence % 2)) % 2;
1110
1111 if (field) {
1112 /*
1113 * bottom field of a SEQ_TB buffer
1114 * Skip the top field data by
1115 */
1116 int height = q_data->height / 2;
1117 int bpp = fmt->fourcc == V4L2_PIX_FMT_NV12 ?
1118 1 : (vpdma_fmt->depth >> 3);
1119 if (plane)
1120 height /= 2;
1121 dma_addr += q_data->width * height * bpp;
1122 }
1123 }
1124 }
1125
1126 if (q_data->flags & Q_DATA_FRAME_1D)
1127 flags |= VPDMA_DATA_FRAME_1D;
1128 if (q_data->flags & Q_DATA_MODE_TILED)
1129 flags |= VPDMA_DATA_MODE_TILED;
1130
1131 frame_width = q_data->c_rect.width;
1132 frame_height = q_data->c_rect.height;
1133
1134 if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1135 frame_height /= 2;
1136
1137 vpdma_add_in_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1138 vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width,
1139 frame_height, 0, 0);
1140 }
1141
1142 /*
1143 * Enable the expected IRQ sources
1144 */
1145 static void enable_irqs(struct vpe_ctx *ctx)
1146 {
1147 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1148 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1149 VPE_DS1_UV_ERROR_INT);
1150
1151 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1152 }
1153
1154 static void disable_irqs(struct vpe_ctx *ctx)
1155 {
1156 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1157 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1158
1159 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1160 }
1161
1162 /* device_run() - prepares and starts the device
1163 *
1164 * This function is only called when both the source and destination
1165 * buffers are in place.
1166 */
1167 static void device_run(void *priv)
1168 {
1169 struct vpe_ctx *ctx = priv;
1170 struct sc_data *sc = ctx->dev->sc;
1171 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1172 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1173
1174 if (ctx->deinterlacing && s_q_data->flags & Q_DATA_INTERLACED_SEQ_TB &&
1175 ctx->sequence % 2 == 0) {
1176 /* When using SEQ_TB buffers, When using it first time,
1177 * No need to remove the buffer as the next field is present
1178 * in the same buffer. (so that job_ready won't fail)
1179 * It will be removed when using bottom field
1180 */
1181 ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1182 WARN_ON(ctx->src_vbs[0] == NULL);
1183 } else {
1184 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1185 WARN_ON(ctx->src_vbs[0] == NULL);
1186 }
1187
1188 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1189 WARN_ON(ctx->dst_vb == NULL);
1190
1191 if (ctx->deinterlacing) {
1192
1193 if (ctx->src_vbs[2] == NULL) {
1194 ctx->src_vbs[2] = ctx->src_vbs[0];
1195 WARN_ON(ctx->src_vbs[2] == NULL);
1196 ctx->src_vbs[1] = ctx->src_vbs[0];
1197 WARN_ON(ctx->src_vbs[1] == NULL);
1198 }
1199
1200 /*
1201 * we have output the first 2 frames through line average, we
1202 * now switch to EDI de-interlacer
1203 */
1204 if (ctx->sequence == 2)
1205 config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */
1206 }
1207
1208 /* config descriptors */
1209 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1210 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1211 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1212
1213 set_line_modes(ctx);
1214
1215 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1216 ctx->load_mmrs = false;
1217 }
1218
1219 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1220 sc->load_coeff_h) {
1221 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1222 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1223 &ctx->sc_coeff_h, 0);
1224
1225 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1226 sc->load_coeff_h = false;
1227 }
1228
1229 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1230 sc->load_coeff_v) {
1231 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1232 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1233 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1234
1235 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1236 sc->load_coeff_v = false;
1237 }
1238
1239 /* output data descriptors */
1240 if (ctx->deinterlacing)
1241 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1242
1243 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1244 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1245 } else {
1246 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1247 if (d_q_data->fmt->coplanar)
1248 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1249 }
1250
1251 /* input data descriptors */
1252 if (ctx->deinterlacing) {
1253 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1254 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1255
1256 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1257 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1258 }
1259
1260 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1261 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1262
1263 if (ctx->deinterlacing)
1264 add_in_dtd(ctx, VPE_PORT_MV_IN);
1265
1266 /* sync on channel control descriptors for input ports */
1267 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1268 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1269
1270 if (ctx->deinterlacing) {
1271 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1272 VPE_CHAN_LUMA2_IN);
1273 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1274 VPE_CHAN_CHROMA2_IN);
1275
1276 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1277 VPE_CHAN_LUMA3_IN);
1278 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1279 VPE_CHAN_CHROMA3_IN);
1280
1281 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1282 }
1283
1284 /* sync on channel control descriptors for output ports */
1285 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1286 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1287 VPE_CHAN_RGB_OUT);
1288 } else {
1289 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1290 VPE_CHAN_LUMA_OUT);
1291 if (d_q_data->fmt->coplanar)
1292 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1293 VPE_CHAN_CHROMA_OUT);
1294 }
1295
1296 if (ctx->deinterlacing)
1297 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1298
1299 enable_irqs(ctx);
1300
1301 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1302 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1303 }
1304
1305 static void dei_error(struct vpe_ctx *ctx)
1306 {
1307 dev_warn(ctx->dev->v4l2_dev.dev,
1308 "received DEI error interrupt\n");
1309 }
1310
1311 static void ds1_uv_error(struct vpe_ctx *ctx)
1312 {
1313 dev_warn(ctx->dev->v4l2_dev.dev,
1314 "received downsampler error interrupt\n");
1315 }
1316
1317 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1318 {
1319 struct vpe_dev *dev = (struct vpe_dev *)data;
1320 struct vpe_ctx *ctx;
1321 struct vpe_q_data *d_q_data;
1322 struct vb2_v4l2_buffer *s_vb, *d_vb;
1323 unsigned long flags;
1324 u32 irqst0, irqst1;
1325 bool list_complete = false;
1326
1327 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1328 if (irqst0) {
1329 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1330 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1331 }
1332
1333 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1334 if (irqst1) {
1335 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1336 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1337 }
1338
1339 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1340 if (!ctx) {
1341 vpe_err(dev, "instance released before end of transaction\n");
1342 goto handled;
1343 }
1344
1345 if (irqst1) {
1346 if (irqst1 & VPE_DEI_ERROR_INT) {
1347 irqst1 &= ~VPE_DEI_ERROR_INT;
1348 dei_error(ctx);
1349 }
1350 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1351 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1352 ds1_uv_error(ctx);
1353 }
1354 }
1355
1356 if (irqst0) {
1357 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1358 vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1359
1360 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1361 list_complete = true;
1362 }
1363
1364 if (irqst0 | irqst1) {
1365 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1366 irqst0, irqst1);
1367 }
1368
1369 /*
1370 * Setup next operation only when list complete IRQ occurs
1371 * otherwise, skip the following code
1372 */
1373 if (!list_complete)
1374 goto handled;
1375
1376 disable_irqs(ctx);
1377
1378 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1379 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1380 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1381 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1382
1383 vpdma_reset_desc_list(&ctx->desc_list);
1384
1385 /* the previous dst mv buffer becomes the next src mv buffer */
1386 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1387
1388 if (ctx->aborting)
1389 goto finished;
1390
1391 s_vb = ctx->src_vbs[0];
1392 d_vb = ctx->dst_vb;
1393
1394 d_vb->flags = s_vb->flags;
1395 d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1396
1397 if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1398 d_vb->timecode = s_vb->timecode;
1399
1400 d_vb->sequence = ctx->sequence;
1401
1402 d_q_data = &ctx->q_data[Q_DATA_DST];
1403 if (d_q_data->flags & Q_IS_INTERLACED) {
1404 d_vb->field = ctx->field;
1405 if (ctx->field == V4L2_FIELD_BOTTOM) {
1406 ctx->sequence++;
1407 ctx->field = V4L2_FIELD_TOP;
1408 } else {
1409 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1410 ctx->field = V4L2_FIELD_BOTTOM;
1411 }
1412 } else {
1413 d_vb->field = V4L2_FIELD_NONE;
1414 ctx->sequence++;
1415 }
1416
1417 if (ctx->deinterlacing) {
1418 /*
1419 * Allow source buffer to be dequeued only if it won't be used
1420 * in the next iteration. All vbs are initialized to first
1421 * buffer and we are shifting buffers every iteration, for the
1422 * first two iterations, no buffer will be dequeued.
1423 * This ensures that driver will keep (n-2)th (n-1)th and (n)th
1424 * field when deinterlacing is enabled
1425 */
1426 if (ctx->src_vbs[2] != ctx->src_vbs[1])
1427 s_vb = ctx->src_vbs[2];
1428 else
1429 s_vb = NULL;
1430 }
1431
1432 spin_lock_irqsave(&dev->lock, flags);
1433
1434 if (s_vb)
1435 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1436
1437 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1438
1439 spin_unlock_irqrestore(&dev->lock, flags);
1440
1441 if (ctx->deinterlacing) {
1442 ctx->src_vbs[2] = ctx->src_vbs[1];
1443 ctx->src_vbs[1] = ctx->src_vbs[0];
1444 }
1445
1446 ctx->bufs_completed++;
1447 if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1448 device_run(ctx);
1449 goto handled;
1450 }
1451
1452 finished:
1453 vpe_dbg(ctx->dev, "finishing transaction\n");
1454 ctx->bufs_completed = 0;
1455 v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1456 handled:
1457 return IRQ_HANDLED;
1458 }
1459
1460 /*
1461 * video ioctls
1462 */
1463 static int vpe_querycap(struct file *file, void *priv,
1464 struct v4l2_capability *cap)
1465 {
1466 strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1467 strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1468 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1469 VPE_MODULE_NAME);
1470 cap->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1471 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1472 return 0;
1473 }
1474
1475 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1476 {
1477 int i, index;
1478 struct vpe_fmt *fmt = NULL;
1479
1480 index = 0;
1481 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1482 if (vpe_formats[i].types & type) {
1483 if (index == f->index) {
1484 fmt = &vpe_formats[i];
1485 break;
1486 }
1487 index++;
1488 }
1489 }
1490
1491 if (!fmt)
1492 return -EINVAL;
1493
1494 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1495 f->pixelformat = fmt->fourcc;
1496 return 0;
1497 }
1498
1499 static int vpe_enum_fmt(struct file *file, void *priv,
1500 struct v4l2_fmtdesc *f)
1501 {
1502 if (V4L2_TYPE_IS_OUTPUT(f->type))
1503 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1504
1505 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1506 }
1507
1508 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1509 {
1510 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1511 struct vpe_ctx *ctx = file2ctx(file);
1512 struct vb2_queue *vq;
1513 struct vpe_q_data *q_data;
1514 int i;
1515
1516 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1517 if (!vq)
1518 return -EINVAL;
1519
1520 q_data = get_q_data(ctx, f->type);
1521
1522 pix->width = q_data->width;
1523 pix->height = q_data->height;
1524 pix->pixelformat = q_data->fmt->fourcc;
1525 pix->field = q_data->field;
1526
1527 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1528 pix->colorspace = q_data->colorspace;
1529 } else {
1530 struct vpe_q_data *s_q_data;
1531
1532 /* get colorspace from the source queue */
1533 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1534
1535 pix->colorspace = s_q_data->colorspace;
1536 }
1537
1538 pix->num_planes = q_data->fmt->coplanar ? 2 : 1;
1539
1540 for (i = 0; i < pix->num_planes; i++) {
1541 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1542 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1543 }
1544
1545 return 0;
1546 }
1547
1548 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1549 struct vpe_fmt *fmt, int type)
1550 {
1551 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1552 struct v4l2_plane_pix_format *plane_fmt;
1553 unsigned int w_align;
1554 int i, depth, depth_bytes, height;
1555
1556 if (!fmt || !(fmt->types & type)) {
1557 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1558 pix->pixelformat);
1559 return -EINVAL;
1560 }
1561
1562 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE
1563 && pix->field != V4L2_FIELD_SEQ_TB)
1564 pix->field = V4L2_FIELD_NONE;
1565
1566 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1567
1568 /*
1569 * the line stride should 16 byte aligned for VPDMA to work, based on
1570 * the bytes per pixel, figure out how much the width should be aligned
1571 * to make sure line stride is 16 byte aligned
1572 */
1573 depth_bytes = depth >> 3;
1574
1575 if (depth_bytes == 3)
1576 /*
1577 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1578 * really help in ensuring line stride is 16 byte aligned
1579 */
1580 w_align = 4;
1581 else
1582 /*
1583 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1584 * can ensure a line stride alignment of 16 bytes. For example,
1585 * if bpp is 2, then the line stride can be 16 byte aligned if
1586 * the width is 8 byte aligned
1587 */
1588 w_align = order_base_2(VPDMA_DESC_ALIGN / depth_bytes);
1589
1590 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1591 &pix->height, MIN_H, MAX_H, H_ALIGN,
1592 S_ALIGN);
1593
1594 pix->num_planes = fmt->coplanar ? 2 : 1;
1595 pix->pixelformat = fmt->fourcc;
1596
1597 /*
1598 * For the actual image parameters, we need to consider the field
1599 * height of the image for SEQ_TB buffers.
1600 */
1601 if (pix->field == V4L2_FIELD_SEQ_TB)
1602 height = pix->height / 2;
1603 else
1604 height = pix->height;
1605
1606 if (!pix->colorspace) {
1607 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1608 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1609 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1610 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1611 pix->colorspace = V4L2_COLORSPACE_SRGB;
1612 } else {
1613 if (height > 1280) /* HD */
1614 pix->colorspace = V4L2_COLORSPACE_REC709;
1615 else /* SD */
1616 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1617 }
1618 }
1619
1620 memset(pix->reserved, 0, sizeof(pix->reserved));
1621 for (i = 0; i < pix->num_planes; i++) {
1622 plane_fmt = &pix->plane_fmt[i];
1623 depth = fmt->vpdma_fmt[i]->depth;
1624
1625 if (i == VPE_LUMA)
1626 plane_fmt->bytesperline = (pix->width * depth) >> 3;
1627 else
1628 plane_fmt->bytesperline = pix->width;
1629
1630 plane_fmt->sizeimage =
1631 (pix->height * pix->width * depth) >> 3;
1632
1633 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1634 }
1635
1636 return 0;
1637 }
1638
1639 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1640 {
1641 struct vpe_ctx *ctx = file2ctx(file);
1642 struct vpe_fmt *fmt = find_format(f);
1643
1644 if (V4L2_TYPE_IS_OUTPUT(f->type))
1645 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1646 else
1647 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1648 }
1649
1650 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1651 {
1652 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1653 struct v4l2_plane_pix_format *plane_fmt;
1654 struct vpe_q_data *q_data;
1655 struct vb2_queue *vq;
1656 int i;
1657
1658 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1659 if (!vq)
1660 return -EINVAL;
1661
1662 if (vb2_is_busy(vq)) {
1663 vpe_err(ctx->dev, "queue busy\n");
1664 return -EBUSY;
1665 }
1666
1667 q_data = get_q_data(ctx, f->type);
1668 if (!q_data)
1669 return -EINVAL;
1670
1671 q_data->fmt = find_format(f);
1672 q_data->width = pix->width;
1673 q_data->height = pix->height;
1674 q_data->colorspace = pix->colorspace;
1675 q_data->field = pix->field;
1676
1677 for (i = 0; i < pix->num_planes; i++) {
1678 plane_fmt = &pix->plane_fmt[i];
1679
1680 q_data->bytesperline[i] = plane_fmt->bytesperline;
1681 q_data->sizeimage[i] = plane_fmt->sizeimage;
1682 }
1683
1684 q_data->c_rect.left = 0;
1685 q_data->c_rect.top = 0;
1686 q_data->c_rect.width = q_data->width;
1687 q_data->c_rect.height = q_data->height;
1688
1689 if (q_data->field == V4L2_FIELD_ALTERNATE)
1690 q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1691 else if (q_data->field == V4L2_FIELD_SEQ_TB)
1692 q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1693 else
1694 q_data->flags &= ~Q_IS_INTERLACED;
1695
1696 /* the crop height is halved for the case of SEQ_TB buffers */
1697 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1698 q_data->c_rect.height /= 2;
1699
1700 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1701 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1702 q_data->bytesperline[VPE_LUMA]);
1703 if (q_data->fmt->coplanar)
1704 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1705 q_data->bytesperline[VPE_CHROMA]);
1706
1707 return 0;
1708 }
1709
1710 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1711 {
1712 int ret;
1713 struct vpe_ctx *ctx = file2ctx(file);
1714
1715 ret = vpe_try_fmt(file, priv, f);
1716 if (ret)
1717 return ret;
1718
1719 ret = __vpe_s_fmt(ctx, f);
1720 if (ret)
1721 return ret;
1722
1723 if (V4L2_TYPE_IS_OUTPUT(f->type))
1724 set_src_registers(ctx);
1725 else
1726 set_dst_registers(ctx);
1727
1728 return set_srcdst_params(ctx);
1729 }
1730
1731 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1732 {
1733 struct vpe_q_data *q_data;
1734 int height;
1735
1736 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1737 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1738 return -EINVAL;
1739
1740 q_data = get_q_data(ctx, s->type);
1741 if (!q_data)
1742 return -EINVAL;
1743
1744 switch (s->target) {
1745 case V4L2_SEL_TGT_COMPOSE:
1746 /*
1747 * COMPOSE target is only valid for capture buffer type, return
1748 * error for output buffer type
1749 */
1750 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1751 return -EINVAL;
1752 break;
1753 case V4L2_SEL_TGT_CROP:
1754 /*
1755 * CROP target is only valid for output buffer type, return
1756 * error for capture buffer type
1757 */
1758 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1759 return -EINVAL;
1760 break;
1761 /*
1762 * bound and default crop/compose targets are invalid targets to
1763 * try/set
1764 */
1765 default:
1766 return -EINVAL;
1767 }
1768
1769 /*
1770 * For SEQ_TB buffers, crop height should be less than the height of
1771 * the field height, not the buffer height
1772 */
1773 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1774 height = q_data->height / 2;
1775 else
1776 height = q_data->height;
1777
1778 if (s->r.top < 0 || s->r.left < 0) {
1779 vpe_err(ctx->dev, "negative values for top and left\n");
1780 s->r.top = s->r.left = 0;
1781 }
1782
1783 v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1784 &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1785
1786 /* adjust left/top if cropping rectangle is out of bounds */
1787 if (s->r.left + s->r.width > q_data->width)
1788 s->r.left = q_data->width - s->r.width;
1789 if (s->r.top + s->r.height > q_data->height)
1790 s->r.top = q_data->height - s->r.height;
1791
1792 return 0;
1793 }
1794
1795 static int vpe_g_selection(struct file *file, void *fh,
1796 struct v4l2_selection *s)
1797 {
1798 struct vpe_ctx *ctx = file2ctx(file);
1799 struct vpe_q_data *q_data;
1800 bool use_c_rect = false;
1801
1802 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1803 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1804 return -EINVAL;
1805
1806 q_data = get_q_data(ctx, s->type);
1807 if (!q_data)
1808 return -EINVAL;
1809
1810 switch (s->target) {
1811 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1812 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1813 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1814 return -EINVAL;
1815 break;
1816 case V4L2_SEL_TGT_CROP_BOUNDS:
1817 case V4L2_SEL_TGT_CROP_DEFAULT:
1818 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1819 return -EINVAL;
1820 break;
1821 case V4L2_SEL_TGT_COMPOSE:
1822 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1823 return -EINVAL;
1824 use_c_rect = true;
1825 break;
1826 case V4L2_SEL_TGT_CROP:
1827 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1828 return -EINVAL;
1829 use_c_rect = true;
1830 break;
1831 default:
1832 return -EINVAL;
1833 }
1834
1835 if (use_c_rect) {
1836 /*
1837 * for CROP/COMPOSE target type, return c_rect params from the
1838 * respective buffer type
1839 */
1840 s->r = q_data->c_rect;
1841 } else {
1842 /*
1843 * for DEFAULT/BOUNDS target type, return width and height from
1844 * S_FMT of the respective buffer type
1845 */
1846 s->r.left = 0;
1847 s->r.top = 0;
1848 s->r.width = q_data->width;
1849 s->r.height = q_data->height;
1850 }
1851
1852 return 0;
1853 }
1854
1855
1856 static int vpe_s_selection(struct file *file, void *fh,
1857 struct v4l2_selection *s)
1858 {
1859 struct vpe_ctx *ctx = file2ctx(file);
1860 struct vpe_q_data *q_data;
1861 struct v4l2_selection sel = *s;
1862 int ret;
1863
1864 ret = __vpe_try_selection(ctx, &sel);
1865 if (ret)
1866 return ret;
1867
1868 q_data = get_q_data(ctx, sel.type);
1869 if (!q_data)
1870 return -EINVAL;
1871
1872 if ((q_data->c_rect.left == sel.r.left) &&
1873 (q_data->c_rect.top == sel.r.top) &&
1874 (q_data->c_rect.width == sel.r.width) &&
1875 (q_data->c_rect.height == sel.r.height)) {
1876 vpe_dbg(ctx->dev,
1877 "requested crop/compose values are already set\n");
1878 return 0;
1879 }
1880
1881 q_data->c_rect = sel.r;
1882
1883 return set_srcdst_params(ctx);
1884 }
1885
1886 /*
1887 * defines number of buffers/frames a context can process with VPE before
1888 * switching to a different context. default value is 1 buffer per context
1889 */
1890 #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1891
1892 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1893 {
1894 struct vpe_ctx *ctx =
1895 container_of(ctrl->handler, struct vpe_ctx, hdl);
1896
1897 switch (ctrl->id) {
1898 case V4L2_CID_VPE_BUFS_PER_JOB:
1899 ctx->bufs_per_job = ctrl->val;
1900 break;
1901
1902 default:
1903 vpe_err(ctx->dev, "Invalid control\n");
1904 return -EINVAL;
1905 }
1906
1907 return 0;
1908 }
1909
1910 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1911 .s_ctrl = vpe_s_ctrl,
1912 };
1913
1914 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1915 .vidioc_querycap = vpe_querycap,
1916
1917 .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1918 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1919 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1920 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1921
1922 .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1923 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1924 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1925 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1926
1927 .vidioc_g_selection = vpe_g_selection,
1928 .vidioc_s_selection = vpe_s_selection,
1929
1930 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1931 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1932 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1933 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1934 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1935 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1936
1937 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1938 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1939 };
1940
1941 /*
1942 * Queue operations
1943 */
1944 static int vpe_queue_setup(struct vb2_queue *vq,
1945 unsigned int *nbuffers, unsigned int *nplanes,
1946 unsigned int sizes[], struct device *alloc_devs[])
1947 {
1948 int i;
1949 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
1950 struct vpe_q_data *q_data;
1951
1952 q_data = get_q_data(ctx, vq->type);
1953
1954 *nplanes = q_data->fmt->coplanar ? 2 : 1;
1955
1956 for (i = 0; i < *nplanes; i++)
1957 sizes[i] = q_data->sizeimage[i];
1958
1959 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
1960 sizes[VPE_LUMA]);
1961 if (q_data->fmt->coplanar)
1962 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
1963
1964 return 0;
1965 }
1966
1967 static int vpe_buf_prepare(struct vb2_buffer *vb)
1968 {
1969 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1970 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1971 struct vpe_q_data *q_data;
1972 int i, num_planes;
1973
1974 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1975
1976 q_data = get_q_data(ctx, vb->vb2_queue->type);
1977 num_planes = q_data->fmt->coplanar ? 2 : 1;
1978
1979 if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1980 if (!(q_data->flags & Q_IS_INTERLACED)) {
1981 vbuf->field = V4L2_FIELD_NONE;
1982 } else {
1983 if (vbuf->field != V4L2_FIELD_TOP &&
1984 vbuf->field != V4L2_FIELD_BOTTOM &&
1985 vbuf->field != V4L2_FIELD_SEQ_TB)
1986 return -EINVAL;
1987 }
1988 }
1989
1990 for (i = 0; i < num_planes; i++) {
1991 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
1992 vpe_err(ctx->dev,
1993 "data will not fit into plane (%lu < %lu)\n",
1994 vb2_plane_size(vb, i),
1995 (long) q_data->sizeimage[i]);
1996 return -EINVAL;
1997 }
1998 }
1999
2000 for (i = 0; i < num_planes; i++)
2001 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
2002
2003 return 0;
2004 }
2005
2006 static void vpe_buf_queue(struct vb2_buffer *vb)
2007 {
2008 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2009 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2010
2011 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2012 }
2013
2014 static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2015 {
2016 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2017
2018 if (ctx->deinterlacing)
2019 config_edi_input_mode(ctx, 0x0);
2020
2021 if (ctx->sequence != 0)
2022 set_srcdst_params(ctx);
2023
2024 return 0;
2025 }
2026
2027 static void vpe_stop_streaming(struct vb2_queue *q)
2028 {
2029 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2030
2031 vpe_dump_regs(ctx->dev);
2032 vpdma_dump_regs(ctx->dev->vpdma);
2033 }
2034
2035 static const struct vb2_ops vpe_qops = {
2036 .queue_setup = vpe_queue_setup,
2037 .buf_prepare = vpe_buf_prepare,
2038 .buf_queue = vpe_buf_queue,
2039 .wait_prepare = vb2_ops_wait_prepare,
2040 .wait_finish = vb2_ops_wait_finish,
2041 .start_streaming = vpe_start_streaming,
2042 .stop_streaming = vpe_stop_streaming,
2043 };
2044
2045 static int queue_init(void *priv, struct vb2_queue *src_vq,
2046 struct vb2_queue *dst_vq)
2047 {
2048 struct vpe_ctx *ctx = priv;
2049 struct vpe_dev *dev = ctx->dev;
2050 int ret;
2051
2052 memset(src_vq, 0, sizeof(*src_vq));
2053 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2054 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2055 src_vq->drv_priv = ctx;
2056 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2057 src_vq->ops = &vpe_qops;
2058 src_vq->mem_ops = &vb2_dma_contig_memops;
2059 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2060 src_vq->lock = &dev->dev_mutex;
2061 src_vq->dev = dev->v4l2_dev.dev;
2062
2063 ret = vb2_queue_init(src_vq);
2064 if (ret)
2065 return ret;
2066
2067 memset(dst_vq, 0, sizeof(*dst_vq));
2068 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2069 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2070 dst_vq->drv_priv = ctx;
2071 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2072 dst_vq->ops = &vpe_qops;
2073 dst_vq->mem_ops = &vb2_dma_contig_memops;
2074 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2075 dst_vq->lock = &dev->dev_mutex;
2076 dst_vq->dev = dev->v4l2_dev.dev;
2077
2078 return vb2_queue_init(dst_vq);
2079 }
2080
2081 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2082 .ops = &vpe_ctrl_ops,
2083 .id = V4L2_CID_VPE_BUFS_PER_JOB,
2084 .name = "Buffers Per Transaction",
2085 .type = V4L2_CTRL_TYPE_INTEGER,
2086 .def = VPE_DEF_BUFS_PER_JOB,
2087 .min = 1,
2088 .max = VIDEO_MAX_FRAME,
2089 .step = 1,
2090 };
2091
2092 /*
2093 * File operations
2094 */
2095 static int vpe_open(struct file *file)
2096 {
2097 struct vpe_dev *dev = video_drvdata(file);
2098 struct vpe_q_data *s_q_data;
2099 struct v4l2_ctrl_handler *hdl;
2100 struct vpe_ctx *ctx;
2101 int ret;
2102
2103 vpe_dbg(dev, "vpe_open\n");
2104
2105 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2106 if (!ctx)
2107 return -ENOMEM;
2108
2109 ctx->dev = dev;
2110
2111 if (mutex_lock_interruptible(&dev->dev_mutex)) {
2112 ret = -ERESTARTSYS;
2113 goto free_ctx;
2114 }
2115
2116 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2117 VPDMA_LIST_TYPE_NORMAL);
2118 if (ret != 0)
2119 goto unlock;
2120
2121 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2122 if (ret != 0)
2123 goto free_desc_list;
2124
2125 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2126 if (ret != 0)
2127 goto free_mmr_adb;
2128
2129 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2130 if (ret != 0)
2131 goto free_sc_h;
2132
2133 init_adb_hdrs(ctx);
2134
2135 v4l2_fh_init(&ctx->fh, video_devdata(file));
2136 file->private_data = &ctx->fh;
2137
2138 hdl = &ctx->hdl;
2139 v4l2_ctrl_handler_init(hdl, 1);
2140 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2141 if (hdl->error) {
2142 ret = hdl->error;
2143 goto exit_fh;
2144 }
2145 ctx->fh.ctrl_handler = hdl;
2146 v4l2_ctrl_handler_setup(hdl);
2147
2148 s_q_data = &ctx->q_data[Q_DATA_SRC];
2149 s_q_data->fmt = &vpe_formats[2];
2150 s_q_data->width = 1920;
2151 s_q_data->height = 1080;
2152 s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2153 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2154 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2155 s_q_data->height);
2156 s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2157 s_q_data->field = V4L2_FIELD_NONE;
2158 s_q_data->c_rect.left = 0;
2159 s_q_data->c_rect.top = 0;
2160 s_q_data->c_rect.width = s_q_data->width;
2161 s_q_data->c_rect.height = s_q_data->height;
2162 s_q_data->flags = 0;
2163
2164 ctx->q_data[Q_DATA_DST] = *s_q_data;
2165
2166 set_dei_shadow_registers(ctx);
2167 set_src_registers(ctx);
2168 set_dst_registers(ctx);
2169 ret = set_srcdst_params(ctx);
2170 if (ret)
2171 goto exit_fh;
2172
2173 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2174
2175 if (IS_ERR(ctx->fh.m2m_ctx)) {
2176 ret = PTR_ERR(ctx->fh.m2m_ctx);
2177 goto exit_fh;
2178 }
2179
2180 v4l2_fh_add(&ctx->fh);
2181
2182 /*
2183 * for now, just report the creation of the first instance, we can later
2184 * optimize the driver to enable or disable clocks when the first
2185 * instance is created or the last instance released
2186 */
2187 if (atomic_inc_return(&dev->num_instances) == 1)
2188 vpe_dbg(dev, "first instance created\n");
2189
2190 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2191
2192 ctx->load_mmrs = true;
2193
2194 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2195 ctx, ctx->fh.m2m_ctx);
2196
2197 mutex_unlock(&dev->dev_mutex);
2198
2199 return 0;
2200 exit_fh:
2201 v4l2_ctrl_handler_free(hdl);
2202 v4l2_fh_exit(&ctx->fh);
2203 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2204 free_sc_h:
2205 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2206 free_mmr_adb:
2207 vpdma_free_desc_buf(&ctx->mmr_adb);
2208 free_desc_list:
2209 vpdma_free_desc_list(&ctx->desc_list);
2210 unlock:
2211 mutex_unlock(&dev->dev_mutex);
2212 free_ctx:
2213 kfree(ctx);
2214 return ret;
2215 }
2216
2217 static int vpe_release(struct file *file)
2218 {
2219 struct vpe_dev *dev = video_drvdata(file);
2220 struct vpe_ctx *ctx = file2ctx(file);
2221
2222 vpe_dbg(dev, "releasing instance %p\n", ctx);
2223
2224 mutex_lock(&dev->dev_mutex);
2225 free_vbs(ctx);
2226 free_mv_buffers(ctx);
2227 vpdma_free_desc_list(&ctx->desc_list);
2228 vpdma_free_desc_buf(&ctx->mmr_adb);
2229
2230 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2231 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2232
2233 v4l2_fh_del(&ctx->fh);
2234 v4l2_fh_exit(&ctx->fh);
2235 v4l2_ctrl_handler_free(&ctx->hdl);
2236 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2237
2238 kfree(ctx);
2239
2240 /*
2241 * for now, just report the release of the last instance, we can later
2242 * optimize the driver to enable or disable clocks when the first
2243 * instance is created or the last instance released
2244 */
2245 if (atomic_dec_return(&dev->num_instances) == 0)
2246 vpe_dbg(dev, "last instance released\n");
2247
2248 mutex_unlock(&dev->dev_mutex);
2249
2250 return 0;
2251 }
2252
2253 static const struct v4l2_file_operations vpe_fops = {
2254 .owner = THIS_MODULE,
2255 .open = vpe_open,
2256 .release = vpe_release,
2257 .poll = v4l2_m2m_fop_poll,
2258 .unlocked_ioctl = video_ioctl2,
2259 .mmap = v4l2_m2m_fop_mmap,
2260 };
2261
2262 static struct video_device vpe_videodev = {
2263 .name = VPE_MODULE_NAME,
2264 .fops = &vpe_fops,
2265 .ioctl_ops = &vpe_ioctl_ops,
2266 .minor = -1,
2267 .release = video_device_release_empty,
2268 .vfl_dir = VFL_DIR_M2M,
2269 };
2270
2271 static struct v4l2_m2m_ops m2m_ops = {
2272 .device_run = device_run,
2273 .job_ready = job_ready,
2274 .job_abort = job_abort,
2275 .lock = vpe_lock,
2276 .unlock = vpe_unlock,
2277 };
2278
2279 static int vpe_runtime_get(struct platform_device *pdev)
2280 {
2281 int r;
2282
2283 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2284
2285 r = pm_runtime_get_sync(&pdev->dev);
2286 WARN_ON(r < 0);
2287 return r < 0 ? r : 0;
2288 }
2289
2290 static void vpe_runtime_put(struct platform_device *pdev)
2291 {
2292
2293 int r;
2294
2295 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2296
2297 r = pm_runtime_put_sync(&pdev->dev);
2298 WARN_ON(r < 0 && r != -ENOSYS);
2299 }
2300
2301 static void vpe_fw_cb(struct platform_device *pdev)
2302 {
2303 struct vpe_dev *dev = platform_get_drvdata(pdev);
2304 struct video_device *vfd;
2305 int ret;
2306
2307 vfd = &dev->vfd;
2308 *vfd = vpe_videodev;
2309 vfd->lock = &dev->dev_mutex;
2310 vfd->v4l2_dev = &dev->v4l2_dev;
2311
2312 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2313 if (ret) {
2314 vpe_err(dev, "Failed to register video device\n");
2315
2316 vpe_set_clock_enable(dev, 0);
2317 vpe_runtime_put(pdev);
2318 pm_runtime_disable(&pdev->dev);
2319 v4l2_m2m_release(dev->m2m_dev);
2320 v4l2_device_unregister(&dev->v4l2_dev);
2321
2322 return;
2323 }
2324
2325 video_set_drvdata(vfd, dev);
2326 snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
2327 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2328 vfd->num);
2329 }
2330
2331 static int vpe_probe(struct platform_device *pdev)
2332 {
2333 struct vpe_dev *dev;
2334 int ret, irq, func;
2335
2336 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2337 if (!dev)
2338 return -ENOMEM;
2339
2340 spin_lock_init(&dev->lock);
2341
2342 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2343 if (ret)
2344 return ret;
2345
2346 atomic_set(&dev->num_instances, 0);
2347 mutex_init(&dev->dev_mutex);
2348
2349 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2350 "vpe_top");
2351 /*
2352 * HACK: we get resource info from device tree in the form of a list of
2353 * VPE sub blocks, the driver currently uses only the base of vpe_top
2354 * for register access, the driver should be changed later to access
2355 * registers based on the sub block base addresses
2356 */
2357 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2358 if (!dev->base) {
2359 ret = -ENOMEM;
2360 goto v4l2_dev_unreg;
2361 }
2362
2363 irq = platform_get_irq(pdev, 0);
2364 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2365 dev);
2366 if (ret)
2367 goto v4l2_dev_unreg;
2368
2369 platform_set_drvdata(pdev, dev);
2370
2371 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2372 if (IS_ERR(dev->m2m_dev)) {
2373 vpe_err(dev, "Failed to init mem2mem device\n");
2374 ret = PTR_ERR(dev->m2m_dev);
2375 goto v4l2_dev_unreg;
2376 }
2377
2378 pm_runtime_enable(&pdev->dev);
2379
2380 ret = vpe_runtime_get(pdev);
2381 if (ret)
2382 goto rel_m2m;
2383
2384 /* Perform clk enable followed by reset */
2385 vpe_set_clock_enable(dev, 1);
2386
2387 vpe_top_reset(dev);
2388
2389 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2390 VPE_PID_FUNC_SHIFT);
2391 vpe_dbg(dev, "VPE PID function %x\n", func);
2392
2393 vpe_top_vpdma_reset(dev);
2394
2395 dev->sc = sc_create(pdev);
2396 if (IS_ERR(dev->sc)) {
2397 ret = PTR_ERR(dev->sc);
2398 goto runtime_put;
2399 }
2400
2401 dev->csc = csc_create(pdev);
2402 if (IS_ERR(dev->csc)) {
2403 ret = PTR_ERR(dev->csc);
2404 goto runtime_put;
2405 }
2406
2407 dev->vpdma = vpdma_create(pdev, vpe_fw_cb);
2408 if (IS_ERR(dev->vpdma)) {
2409 ret = PTR_ERR(dev->vpdma);
2410 goto runtime_put;
2411 }
2412
2413 return 0;
2414
2415 runtime_put:
2416 vpe_runtime_put(pdev);
2417 rel_m2m:
2418 pm_runtime_disable(&pdev->dev);
2419 v4l2_m2m_release(dev->m2m_dev);
2420 v4l2_dev_unreg:
2421 v4l2_device_unregister(&dev->v4l2_dev);
2422
2423 return ret;
2424 }
2425
2426 static int vpe_remove(struct platform_device *pdev)
2427 {
2428 struct vpe_dev *dev = platform_get_drvdata(pdev);
2429
2430 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2431
2432 v4l2_m2m_release(dev->m2m_dev);
2433 video_unregister_device(&dev->vfd);
2434 v4l2_device_unregister(&dev->v4l2_dev);
2435
2436 vpe_set_clock_enable(dev, 0);
2437 vpe_runtime_put(pdev);
2438 pm_runtime_disable(&pdev->dev);
2439
2440 return 0;
2441 }
2442
2443 #if defined(CONFIG_OF)
2444 static const struct of_device_id vpe_of_match[] = {
2445 {
2446 .compatible = "ti,vpe",
2447 },
2448 {},
2449 };
2450 #endif
2451
2452 static struct platform_driver vpe_pdrv = {
2453 .probe = vpe_probe,
2454 .remove = vpe_remove,
2455 .driver = {
2456 .name = VPE_MODULE_NAME,
2457 .of_match_table = of_match_ptr(vpe_of_match),
2458 },
2459 };
2460
2461 module_platform_driver(vpe_pdrv);
2462
2463 MODULE_DESCRIPTION("TI VPE driver");
2464 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2465 MODULE_LICENSE("GPL");
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