drivers/media/platform/vsp1/vsp1_pipe.c

   1 /*
   2  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/list.h>
  16 #include <linux/sched.h>
  17 #include <linux/wait.h>
  18
  19 #include <media/media-entity.h>
  20 #include <media/v4l2-subdev.h>
  21
  22 #include "vsp1.h"
  23 #include "vsp1_bru.h"
  24 #include "vsp1_dl.h"
  25 #include "vsp1_entity.h"
  26 #include "vsp1_pipe.h"
  27 #include "vsp1_rwpf.h"
  28 #include "vsp1_uds.h"
  29
  30 /* -----------------------------------------------------------------------------
  31  * Helper Functions
  32  */
  33
  34 static const struct vsp1_format_info vsp1_video_formats[] = {
  35         { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
  36           VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  37           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  38           1, { 8, 0, 0 }, false, false, 1, 1, false },
  39         { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  40           VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  41           VI6_RPF_DSWAP_P_WDS,
  42           1, { 16, 0, 0 }, false, false, 1, 1, true },
  43         { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  44           VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  45           VI6_RPF_DSWAP_P_WDS,
  46           1, { 16, 0, 0 }, false, false, 1, 1, false },
  47         { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  48           VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  49           VI6_RPF_DSWAP_P_WDS,
  50           1, { 16, 0, 0 }, false, false, 1, 1, true },
  51         { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  52           VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  53           VI6_RPF_DSWAP_P_WDS,
  54           1, { 16, 0, 0 }, false, false, 1, 1, false },
  55         { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
  56           VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  57           VI6_RPF_DSWAP_P_WDS,
  58           1, { 16, 0, 0 }, false, false, 1, 1, false },
  59         { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
  60           VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  61           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  62           1, { 24, 0, 0 }, false, false, 1, 1, false },
  63         { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
  64           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  65           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  66           1, { 24, 0, 0 }, false, false, 1, 1, false },
  67         { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  68           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  69           1, { 32, 0, 0 }, false, false, 1, 1, true },
  70         { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  71           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  72           1, { 32, 0, 0 }, false, false, 1, 1, false },
  73         { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  74           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  75           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  76           1, { 32, 0, 0 }, false, false, 1, 1, true },
  77         { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  78           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  79           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  80           1, { 32, 0, 0 }, false, false, 1, 1, false },
  81         { V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32,
  82           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  83           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  84           1, { 24, 0, 0 }, false, false, 1, 1, false },
  85         { V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32,
  86           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  87           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  88           1, { 32, 0, 0 }, false, false, 1, 1, false },
  89         { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
  90           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  91           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  92           1, { 16, 0, 0 }, false, false, 2, 1, false },
  93         { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
  94           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  95           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  96           1, { 16, 0, 0 }, false, true, 2, 1, false },
  97         { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
  98           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  99           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 100           1, { 16, 0, 0 }, true, false, 2, 1, false },
 101         { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
 102           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 103           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 104           1, { 16, 0, 0 }, true, true, 2, 1, false },
 105         { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
 106           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 107           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 108           2, { 8, 16, 0 }, false, false, 2, 2, false },
 109         { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
 110           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 111           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 112           2, { 8, 16, 0 }, false, true, 2, 2, false },
 113         { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
 114           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 115           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 116           2, { 8, 16, 0 }, false, false, 2, 1, false },
 117         { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
 118           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 119           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 120           2, { 8, 16, 0 }, false, true, 2, 1, false },
 121         { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
 122           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 123           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 124           3, { 8, 8, 8 }, false, false, 2, 2, false },
 125         { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
 126           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 127           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 128           3, { 8, 8, 8 }, false, true, 2, 2, false },
 129         { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
 130           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 131           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 132           3, { 8, 8, 8 }, false, false, 2, 1, false },
 133         { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
 134           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 135           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 136           3, { 8, 8, 8 }, false, true, 2, 1, false },
 137         { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
 138           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 139           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 140           3, { 8, 8, 8 }, false, false, 1, 1, false },
 141         { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
 142           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 143           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 144           3, { 8, 8, 8 }, false, true, 1, 1, false },
 145 };
 146
 147 /**
 148  * vsp1_get_format_info - Retrieve format information for a 4CC
 149  * @vsp1: the VSP1 device
 150  * @fourcc: the format 4CC
 151  *
 152  * Return a pointer to the format information structure corresponding to the
 153  * given V4L2 format 4CC, or NULL if no corresponding format can be found.
 154  */
 155 const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
 156                                                     u32 fourcc)
 157 {
 158         unsigned int i;
 159
 160         /* Special case, the VYUY format is supported on Gen2 only. */
 161         if (vsp1->info->gen != 2 && fourcc == V4L2_PIX_FMT_VYUY)
 162                 return NULL;
 163
 164         for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
 165                 const struct vsp1_format_info *info = &vsp1_video_formats[i];
 166
 167                 if (info->fourcc == fourcc)
 168                         return info;
 169         }
 170
 171         return NULL;
 172 }
 173
 174 /* -----------------------------------------------------------------------------
 175  * Pipeline Management
 176  */
 177
 178 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
 179 {
 180         unsigned int i;
 181
 182         if (pipe->bru) {
 183                 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
 184
 185                 for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
 186                         bru->inputs[i].rpf = NULL;
 187         }
 188
 189         for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
 190                 if (pipe->inputs[i]) {
 191                         pipe->inputs[i]->pipe = NULL;
 192                         pipe->inputs[i] = NULL;
 193                 }
 194         }
 195
 196         if (pipe->output) {
 197                 pipe->output->pipe = NULL;
 198                 pipe->output = NULL;
 199         }
 200
 201         INIT_LIST_HEAD(&pipe->entities);
 202         pipe->state = VSP1_PIPELINE_STOPPED;
 203         pipe->buffers_ready = 0;
 204         pipe->num_inputs = 0;
 205         pipe->bru = NULL;
 206         pipe->lif = NULL;
 207         pipe->uds = NULL;
 208 }
 209
 210 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
 211 {
 212         mutex_init(&pipe->lock);
 213         spin_lock_init(&pipe->irqlock);
 214         init_waitqueue_head(&pipe->wq);
 215         kref_init(&pipe->kref);
 216
 217         INIT_LIST_HEAD(&pipe->entities);
 218         pipe->state = VSP1_PIPELINE_STOPPED;
 219 }
 220
 221 /* Must be called with the pipe irqlock held. */
 222 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
 223 {
 224         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 225
 226         if (pipe->state == VSP1_PIPELINE_STOPPED) {
 227                 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
 228                            VI6_CMD_STRCMD);
 229                 pipe->state = VSP1_PIPELINE_RUNNING;
 230         }
 231
 232         pipe->buffers_ready = 0;
 233 }
 234
 235 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
 236 {
 237         unsigned long flags;
 238         bool stopped;
 239
 240         spin_lock_irqsave(&pipe->irqlock, flags);
 241         stopped = pipe->state == VSP1_PIPELINE_STOPPED;
 242         spin_unlock_irqrestore(&pipe->irqlock, flags);
 243
 244         return stopped;
 245 }
 246
 247 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 248 {
 249         struct vsp1_entity *entity;
 250         unsigned long flags;
 251         int ret;
 252
 253         if (pipe->lif) {
 254                 /* When using display lists in continuous frame mode the only
 255                  * way to stop the pipeline is to reset the hardware.
 256                  */
 257                 ret = vsp1_reset_wpf(pipe->output->entity.vsp1,
 258                                      pipe->output->entity.index);
 259                 if (ret == 0) {
 260                         spin_lock_irqsave(&pipe->irqlock, flags);
 261                         pipe->state = VSP1_PIPELINE_STOPPED;
 262                         spin_unlock_irqrestore(&pipe->irqlock, flags);
 263                 }
 264         } else {
 265                 /* Otherwise just request a stop and wait. */
 266                 spin_lock_irqsave(&pipe->irqlock, flags);
 267                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 268                         pipe->state = VSP1_PIPELINE_STOPPING;
 269                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 270
 271                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 272                                          msecs_to_jiffies(500));
 273                 ret = ret == 0 ? -ETIMEDOUT : 0;
 274         }
 275
 276         list_for_each_entry(entity, &pipe->entities, list_pipe) {
 277                 if (entity->route && entity->route->reg)
 278                         vsp1_write(entity->vsp1, entity->route->reg,
 279                                    VI6_DPR_NODE_UNUSED);
 280         }
 281
 282         v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);
 283
 284         return ret;
 285 }
 286
 287 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
 288 {
 289         unsigned int mask;
 290
 291         mask = ((1 << pipe->num_inputs) - 1) << 1;
 292         if (!pipe->lif)
 293                 mask |= 1 << 0;
 294
 295         return pipe->buffers_ready == mask;
 296 }
 297
 298 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
 299 {
 300         if (pipe == NULL)
 301                 return;
 302
 303         vsp1_dlm_irq_frame_end(pipe->output->dlm);
 304
 305         if (pipe->frame_end)
 306                 pipe->frame_end(pipe);
 307
 308         pipe->sequence++;
 309 }
 310
 311 /*
 312  * Propagate the alpha value through the pipeline.
 313  *
 314  * As the UDS has restricted scaling capabilities when the alpha component needs
 315  * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
 316  * value. The UDS then outputs a fixed alpha value which needs to be programmed
 317  * from the input RPF alpha.
 318  */
 319 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
 320                                    struct vsp1_dl_list *dl, unsigned int alpha)
 321 {
 322         if (!pipe->uds)
 323                 return;
 324
 325         /* The BRU background color has a fixed alpha value set to 255, the
 326          * output alpha value is thus always equal to 255.
 327          */
 328         if (pipe->uds_input->type == VSP1_ENTITY_BRU)
 329                 alpha = 255;
 330
 331         vsp1_uds_set_alpha(pipe->uds, dl, alpha);
 332 }
 333
 334 void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
 335 {
 336         unsigned long flags;
 337         unsigned int i;
 338         int ret;
 339
 340         /* To avoid increasing the system suspend time needlessly, loop over the
 341          * pipelines twice, first to set them all to the stopping state, and
 342          * then to wait for the stop to complete.
 343          */
 344         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 345                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 346                 struct vsp1_pipeline *pipe;
 347
 348                 if (wpf == NULL)
 349                         continue;
 350
 351                 pipe = wpf->pipe;
 352                 if (pipe == NULL)
 353                         continue;
 354
 355                 spin_lock_irqsave(&pipe->irqlock, flags);
 356                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 357                         pipe->state = VSP1_PIPELINE_STOPPING;
 358                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 359         }
 360
 361         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 362                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 363                 struct vsp1_pipeline *pipe;
 364
 365                 if (wpf == NULL)
 366                         continue;
 367
 368                 pipe = wpf->pipe;
 369                 if (pipe == NULL)
 370                         continue;
 371
 372                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 373                                          msecs_to_jiffies(500));
 374                 if (ret == 0)
 375                         dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
 376                                  wpf->entity.index);
 377         }
 378 }
 379
 380 void vsp1_pipelines_resume(struct vsp1_device *vsp1)
 381 {
 382         unsigned long flags;
 383         unsigned int i;
 384
 385         /* Resume all running pipelines. */
 386         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 387                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 388                 struct vsp1_pipeline *pipe;
 389
 390                 if (wpf == NULL)
 391                         continue;
 392
 393                 pipe = wpf->pipe;
 394                 if (pipe == NULL)
 395                         continue;
 396
 397                 spin_lock_irqsave(&pipe->irqlock, flags);
 398                 if (vsp1_pipeline_ready(pipe))
 399                         vsp1_pipeline_run(pipe);
 400                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 401         }
 402 }