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[mirror_ubuntu-artful-kernel.git] / drivers / media / rc / winbond-cir.c
1 /*
2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
3 * SuperI/O chips.
4 *
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
8 *
9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2012 Sean Young <sean@mess.org>
11 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
12 *
13 * Dedicated to my daughter Matilda, without whose loving attention this
14 * driver would have been finished in half the time and with a fraction
15 * of the bugs.
16 *
17 * Written using:
18 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
19 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
20 * o DSDT dumps
21 *
22 * Supported features:
23 * o IR Receive
24 * o IR Transmit
25 * o Wake-On-CIR functionality
26 * o Carrier detection
27 *
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License as published by
30 * the Free Software Foundation; either version 2 of the License, or
31 * (at your option) any later version.
32 *
33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
37 */
38
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40
41 #include <linux/module.h>
42 #include <linux/pnp.h>
43 #include <linux/interrupt.h>
44 #include <linux/timer.h>
45 #include <linux/leds.h>
46 #include <linux/spinlock.h>
47 #include <linux/pci_ids.h>
48 #include <linux/io.h>
49 #include <linux/bitrev.h>
50 #include <linux/slab.h>
51 #include <linux/wait.h>
52 #include <linux/sched.h>
53 #include <media/rc-core.h>
54
55 #define DRVNAME "winbond-cir"
56
57 /* CEIR Wake-Up Registers, relative to data->wbase */
58 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
59 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
60 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
61 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
62 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
63 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
64 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
65 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
66 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
67 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
68
69 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
70 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
71 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
72 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
73 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
74 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
75
76 /* SP3 Banked Registers, relative to data->sbase */
77 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
78 /* Bank 0 */
79 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
80 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
81 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
82 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
83 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
84 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
85 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
86 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
87 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
88 /* Bank 2 */
89 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
90 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
91 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
92 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
93 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
94 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
95 /* Bank 3 */
96 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
97 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
98 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
99 /* Bank 4 */
100 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
101 /* Bank 5 */
102 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
103 /* Bank 6 */
104 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
105 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
106 /* Bank 7 */
107 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
108 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
109 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
110 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
111 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
112
113 /*
114 * Magic values follow
115 */
116
117 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
118 #define WBCIR_IRQ_NONE 0x00
119 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
120 #define WBCIR_IRQ_RX 0x01
121 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
122 #define WBCIR_IRQ_TX_LOW 0x02
123 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
124 #define WBCIR_IRQ_ERR 0x04
125 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
126 #define WBCIR_IRQ_TX_EMPTY 0x20
127 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
128 #define WBCIR_LED_ENABLE 0x80
129 /* RX data available bit for WBCIR_REG_SP3_LSR */
130 #define WBCIR_RX_AVAIL 0x01
131 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
132 #define WBCIR_RX_OVERRUN 0x02
133 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
134 #define WBCIR_TX_EOT 0x04
135 /* RX disable bit for WBCIR_REG_SP3_ASCR */
136 #define WBCIR_RX_DISABLE 0x20
137 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
138 #define WBCIR_TX_UNDERRUN 0x40
139 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
140 #define WBCIR_EXT_ENABLE 0x01
141 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
142 #define WBCIR_REGSEL_COMPARE 0x10
143 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
144 #define WBCIR_REGSEL_MASK 0x20
145 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
146 #define WBCIR_REG_ADDR0 0x00
147 /* Enable carrier counter */
148 #define WBCIR_CNTR_EN 0x01
149 /* Reset carrier counter */
150 #define WBCIR_CNTR_R 0x02
151 /* Invert TX */
152 #define WBCIR_IRTX_INV 0x04
153 /* Receiver oversampling */
154 #define WBCIR_RX_T_OV 0x40
155
156 /* Valid banks for the SP3 UART */
157 enum wbcir_bank {
158 WBCIR_BANK_0 = 0x00,
159 WBCIR_BANK_1 = 0x80,
160 WBCIR_BANK_2 = 0xE0,
161 WBCIR_BANK_3 = 0xE4,
162 WBCIR_BANK_4 = 0xE8,
163 WBCIR_BANK_5 = 0xEC,
164 WBCIR_BANK_6 = 0xF0,
165 WBCIR_BANK_7 = 0xF4,
166 };
167
168 /* Supported power-on IR Protocols */
169 enum wbcir_protocol {
170 IR_PROTOCOL_RC5 = 0x0,
171 IR_PROTOCOL_NEC = 0x1,
172 IR_PROTOCOL_RC6 = 0x2,
173 };
174
175 /* Possible states for IR reception */
176 enum wbcir_rxstate {
177 WBCIR_RXSTATE_INACTIVE = 0,
178 WBCIR_RXSTATE_ACTIVE,
179 WBCIR_RXSTATE_ERROR
180 };
181
182 /* Possible states for IR transmission */
183 enum wbcir_txstate {
184 WBCIR_TXSTATE_INACTIVE = 0,
185 WBCIR_TXSTATE_ACTIVE,
186 WBCIR_TXSTATE_ERROR
187 };
188
189 /* Misc */
190 #define WBCIR_NAME "Winbond CIR"
191 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
192 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
193 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
194 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
195 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
196 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
197
198 /* Per-device data */
199 struct wbcir_data {
200 spinlock_t spinlock;
201 struct rc_dev *dev;
202 struct led_classdev led;
203
204 unsigned long wbase; /* Wake-Up Baseaddr */
205 unsigned long ebase; /* Enhanced Func. Baseaddr */
206 unsigned long sbase; /* Serial Port Baseaddr */
207 unsigned int irq; /* Serial Port IRQ */
208 u8 irqmask;
209
210 /* RX state */
211 enum wbcir_rxstate rxstate;
212 int carrier_report_enabled;
213 u32 pulse_duration;
214
215 /* TX state */
216 enum wbcir_txstate txstate;
217 u32 txlen;
218 u32 txoff;
219 u32 *txbuf;
220 u8 txmask;
221 u32 txcarrier;
222 };
223
224 static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
225 module_param(protocol, uint, 0444);
226 MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command (0 = RC5, 1 = NEC, 2 = RC6A, default)");
227
228 static bool invert; /* default = 0 */
229 module_param(invert, bool, 0444);
230 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
231
232 static bool txandrx; /* default = 0 */
233 module_param(txandrx, bool, 0444);
234 MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
235
236 static unsigned int wake_sc = 0x800F040C;
237 module_param(wake_sc, uint, 0644);
238 MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
239
240 static unsigned int wake_rc6mode = 6;
241 module_param(wake_rc6mode, uint, 0644);
242 MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command (0 = 0, 6 = 6A, default)");
243
244
245
246 /*****************************************************************************
247 *
248 * UTILITY FUNCTIONS
249 *
250 *****************************************************************************/
251
252 /* Caller needs to hold wbcir_lock */
253 static void
254 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
255 {
256 u8 val;
257
258 val = inb(addr);
259 val = ((val & ~mask) | (bits & mask));
260 outb(val, addr);
261 }
262
263 /* Selects the register bank for the serial port */
264 static inline void
265 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
266 {
267 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
268 }
269
270 static inline void
271 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
272 {
273 if (data->irqmask == irqmask)
274 return;
275
276 wbcir_select_bank(data, WBCIR_BANK_0);
277 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
278 data->irqmask = irqmask;
279 }
280
281 static enum led_brightness
282 wbcir_led_brightness_get(struct led_classdev *led_cdev)
283 {
284 struct wbcir_data *data = container_of(led_cdev,
285 struct wbcir_data,
286 led);
287
288 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
289 return LED_FULL;
290 else
291 return LED_OFF;
292 }
293
294 static void
295 wbcir_led_brightness_set(struct led_classdev *led_cdev,
296 enum led_brightness brightness)
297 {
298 struct wbcir_data *data = container_of(led_cdev,
299 struct wbcir_data,
300 led);
301
302 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
303 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
304 WBCIR_LED_ENABLE);
305 }
306
307 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
308 static u8
309 wbcir_to_rc6cells(u8 val)
310 {
311 u8 coded = 0x00;
312 int i;
313
314 val &= 0x0F;
315 for (i = 0; i < 4; i++) {
316 if (val & 0x01)
317 coded |= 0x02 << (i * 2);
318 else
319 coded |= 0x01 << (i * 2);
320 val >>= 1;
321 }
322
323 return coded;
324 }
325
326 /*****************************************************************************
327 *
328 * INTERRUPT FUNCTIONS
329 *
330 *****************************************************************************/
331
332 static void
333 wbcir_carrier_report(struct wbcir_data *data)
334 {
335 unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) |
336 inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8;
337
338 if (counter > 0 && counter < 0xffff) {
339 DEFINE_IR_RAW_EVENT(ev);
340
341 ev.carrier_report = 1;
342 ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u,
343 data->pulse_duration);
344
345 ir_raw_event_store(data->dev, &ev);
346 }
347
348 /* reset and restart the counter */
349 data->pulse_duration = 0;
350 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
351 WBCIR_CNTR_EN | WBCIR_CNTR_R);
352 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN,
353 WBCIR_CNTR_EN | WBCIR_CNTR_R);
354 }
355
356 static void
357 wbcir_idle_rx(struct rc_dev *dev, bool idle)
358 {
359 struct wbcir_data *data = dev->priv;
360
361 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE)
362 data->rxstate = WBCIR_RXSTATE_ACTIVE;
363
364 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) {
365 data->rxstate = WBCIR_RXSTATE_INACTIVE;
366
367 if (data->carrier_report_enabled)
368 wbcir_carrier_report(data);
369
370 /* Tell hardware to go idle by setting RXINACTIVE */
371 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
372 }
373 }
374
375 static void
376 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
377 {
378 u8 irdata;
379 DEFINE_IR_RAW_EVENT(rawir);
380 unsigned duration;
381
382 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
383 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
384 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
385 if (data->rxstate == WBCIR_RXSTATE_ERROR)
386 continue;
387
388 duration = ((irdata & 0x7F) + 1) *
389 (data->carrier_report_enabled ? 2 : 10);
390 rawir.pulse = irdata & 0x80 ? false : true;
391 rawir.duration = US_TO_NS(duration);
392
393 if (rawir.pulse)
394 data->pulse_duration += duration;
395
396 ir_raw_event_store_with_filter(data->dev, &rawir);
397 }
398
399 ir_raw_event_handle(data->dev);
400 }
401
402 static void
403 wbcir_irq_tx(struct wbcir_data *data)
404 {
405 unsigned int space;
406 unsigned int used;
407 u8 bytes[16];
408 u8 byte;
409
410 if (!data->txbuf)
411 return;
412
413 switch (data->txstate) {
414 case WBCIR_TXSTATE_INACTIVE:
415 /* TX FIFO empty */
416 space = 16;
417 break;
418 case WBCIR_TXSTATE_ACTIVE:
419 /* TX FIFO low (3 bytes or less) */
420 space = 13;
421 break;
422 case WBCIR_TXSTATE_ERROR:
423 space = 0;
424 break;
425 default:
426 return;
427 }
428
429 /*
430 * TX data is run-length coded in bytes: YXXXXXXX
431 * Y = space (1) or pulse (0)
432 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
433 */
434 for (used = 0; used < space && data->txoff != data->txlen; used++) {
435 if (data->txbuf[data->txoff] == 0) {
436 data->txoff++;
437 continue;
438 }
439 byte = min((u32)0x80, data->txbuf[data->txoff]);
440 data->txbuf[data->txoff] -= byte;
441 byte--;
442 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
443 bytes[used] = byte;
444 }
445
446 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
447 data->txoff++;
448
449 if (used == 0) {
450 /* Finished */
451 if (data->txstate == WBCIR_TXSTATE_ERROR)
452 /* Clear TX underrun bit */
453 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
454 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
455 kfree(data->txbuf);
456 data->txbuf = NULL;
457 data->txstate = WBCIR_TXSTATE_INACTIVE;
458 } else if (data->txoff == data->txlen) {
459 /* At the end of transmission, tell the hw before last byte */
460 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
461 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
462 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
463 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
464 WBCIR_IRQ_TX_EMPTY);
465 } else {
466 /* More data to follow... */
467 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
468 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
469 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
470 WBCIR_IRQ_TX_LOW);
471 data->txstate = WBCIR_TXSTATE_ACTIVE;
472 }
473 }
474 }
475
476 static irqreturn_t
477 wbcir_irq_handler(int irqno, void *cookie)
478 {
479 struct pnp_dev *device = cookie;
480 struct wbcir_data *data = pnp_get_drvdata(device);
481 unsigned long flags;
482 u8 status;
483
484 spin_lock_irqsave(&data->spinlock, flags);
485 wbcir_select_bank(data, WBCIR_BANK_0);
486 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
487 status &= data->irqmask;
488
489 if (!status) {
490 spin_unlock_irqrestore(&data->spinlock, flags);
491 return IRQ_NONE;
492 }
493
494 if (status & WBCIR_IRQ_ERR) {
495 /* RX overflow? (read clears bit) */
496 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
497 data->rxstate = WBCIR_RXSTATE_ERROR;
498 ir_raw_event_reset(data->dev);
499 }
500
501 /* TX underflow? */
502 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
503 data->txstate = WBCIR_TXSTATE_ERROR;
504 }
505
506 if (status & WBCIR_IRQ_RX)
507 wbcir_irq_rx(data, device);
508
509 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
510 wbcir_irq_tx(data);
511
512 spin_unlock_irqrestore(&data->spinlock, flags);
513 return IRQ_HANDLED;
514 }
515
516 /*****************************************************************************
517 *
518 * RC-CORE INTERFACE FUNCTIONS
519 *
520 *****************************************************************************/
521
522 static int
523 wbcir_set_carrier_report(struct rc_dev *dev, int enable)
524 {
525 struct wbcir_data *data = dev->priv;
526 unsigned long flags;
527
528 spin_lock_irqsave(&data->spinlock, flags);
529
530 if (data->carrier_report_enabled == enable) {
531 spin_unlock_irqrestore(&data->spinlock, flags);
532 return 0;
533 }
534
535 data->pulse_duration = 0;
536 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
537 WBCIR_CNTR_EN | WBCIR_CNTR_R);
538
539 if (enable && data->dev->idle)
540 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL,
541 WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R);
542
543 /* Set a higher sampling resolution if carrier reports are enabled */
544 wbcir_select_bank(data, WBCIR_BANK_2);
545 data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10);
546 outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
547 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
548
549 /* Enable oversampling if carrier reports are enabled */
550 wbcir_select_bank(data, WBCIR_BANK_7);
551 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG,
552 enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV);
553
554 data->carrier_report_enabled = enable;
555 spin_unlock_irqrestore(&data->spinlock, flags);
556
557 return 0;
558 }
559
560 static int
561 wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
562 {
563 struct wbcir_data *data = dev->priv;
564 unsigned long flags;
565 u8 val;
566 u32 freq;
567
568 freq = DIV_ROUND_CLOSEST(carrier, 1000);
569 if (freq < 30 || freq > 60)
570 return -EINVAL;
571
572 switch (freq) {
573 case 58:
574 case 59:
575 case 60:
576 val = freq - 58;
577 freq *= 1000;
578 break;
579 case 57:
580 val = freq - 27;
581 freq = 56900;
582 break;
583 default:
584 val = freq - 27;
585 freq *= 1000;
586 break;
587 }
588
589 spin_lock_irqsave(&data->spinlock, flags);
590 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
591 spin_unlock_irqrestore(&data->spinlock, flags);
592 return -EBUSY;
593 }
594
595 if (data->txcarrier != freq) {
596 wbcir_select_bank(data, WBCIR_BANK_7);
597 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
598 data->txcarrier = freq;
599 }
600
601 spin_unlock_irqrestore(&data->spinlock, flags);
602 return 0;
603 }
604
605 static int
606 wbcir_txmask(struct rc_dev *dev, u32 mask)
607 {
608 struct wbcir_data *data = dev->priv;
609 unsigned long flags;
610 u8 val;
611
612 /* return the number of transmitters */
613 if (mask > 15)
614 return 4;
615
616 /* Four outputs, only one output can be enabled at a time */
617 switch (mask) {
618 case 0x1:
619 val = 0x0;
620 break;
621 case 0x2:
622 val = 0x1;
623 break;
624 case 0x4:
625 val = 0x2;
626 break;
627 case 0x8:
628 val = 0x3;
629 break;
630 default:
631 return -EINVAL;
632 }
633
634 spin_lock_irqsave(&data->spinlock, flags);
635 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
636 spin_unlock_irqrestore(&data->spinlock, flags);
637 return -EBUSY;
638 }
639
640 if (data->txmask != mask) {
641 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
642 data->txmask = mask;
643 }
644
645 spin_unlock_irqrestore(&data->spinlock, flags);
646 return 0;
647 }
648
649 static int
650 wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
651 {
652 struct wbcir_data *data = dev->priv;
653 unsigned *buf;
654 unsigned i;
655 unsigned long flags;
656
657 buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL);
658 if (!buf)
659 return -ENOMEM;
660
661 /* Convert values to multiples of 10us */
662 for (i = 0; i < count; i++)
663 buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
664
665 /* Not sure if this is possible, but better safe than sorry */
666 spin_lock_irqsave(&data->spinlock, flags);
667 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
668 spin_unlock_irqrestore(&data->spinlock, flags);
669 kfree(buf);
670 return -EBUSY;
671 }
672
673 /* Fill the TX fifo once, the irq handler will do the rest */
674 data->txbuf = buf;
675 data->txlen = count;
676 data->txoff = 0;
677 wbcir_irq_tx(data);
678
679 /* We're done */
680 spin_unlock_irqrestore(&data->spinlock, flags);
681 return count;
682 }
683
684 /*****************************************************************************
685 *
686 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
687 *
688 *****************************************************************************/
689
690 static void
691 wbcir_shutdown(struct pnp_dev *device)
692 {
693 struct device *dev = &device->dev;
694 struct wbcir_data *data = pnp_get_drvdata(device);
695 bool do_wake = true;
696 u8 match[11];
697 u8 mask[11];
698 u8 rc6_csl = 0;
699 int i;
700
701 memset(match, 0, sizeof(match));
702 memset(mask, 0, sizeof(mask));
703
704 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
705 do_wake = false;
706 goto finish;
707 }
708
709 switch (protocol) {
710 case IR_PROTOCOL_RC5:
711 if (wake_sc > 0xFFF) {
712 do_wake = false;
713 dev_err(dev, "RC5 - Invalid wake scancode\n");
714 break;
715 }
716
717 /* Mask = 13 bits, ex toggle */
718 mask[0] = 0xFF;
719 mask[1] = 0x17;
720
721 match[0] = (wake_sc & 0x003F); /* 6 command bits */
722 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
723 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
724 if (!(wake_sc & 0x0040)) /* 2nd start bit */
725 match[1] |= 0x10;
726
727 break;
728
729 case IR_PROTOCOL_NEC:
730 if (wake_sc > 0xFFFFFF) {
731 do_wake = false;
732 dev_err(dev, "NEC - Invalid wake scancode\n");
733 break;
734 }
735
736 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
737
738 match[1] = bitrev8((wake_sc & 0xFF));
739 match[0] = ~match[1];
740
741 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
742 if (wake_sc > 0xFFFF)
743 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
744 else
745 match[2] = ~match[3];
746
747 break;
748
749 case IR_PROTOCOL_RC6:
750
751 if (wake_rc6mode == 0) {
752 if (wake_sc > 0xFFFF) {
753 do_wake = false;
754 dev_err(dev, "RC6 - Invalid wake scancode\n");
755 break;
756 }
757
758 /* Command */
759 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
760 mask[0] = 0xFF;
761 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
762 mask[1] = 0xFF;
763
764 /* Address */
765 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
766 mask[2] = 0xFF;
767 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
768 mask[3] = 0xFF;
769
770 /* Header */
771 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
772 mask[4] = 0xF0;
773 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
774 mask[5] = 0x0F;
775
776 rc6_csl = 44;
777
778 } else if (wake_rc6mode == 6) {
779 i = 0;
780
781 /* Command */
782 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
783 mask[i++] = 0xFF;
784 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
785 mask[i++] = 0xFF;
786
787 /* Address + Toggle */
788 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
789 mask[i++] = 0xFF;
790 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
791 mask[i++] = 0x3F;
792
793 /* Customer bits 7 - 0 */
794 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
795 mask[i++] = 0xFF;
796 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
797 mask[i++] = 0xFF;
798
799 if (wake_sc & 0x80000000) {
800 /* Customer range bit and bits 15 - 8 */
801 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
802 mask[i++] = 0xFF;
803 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
804 mask[i++] = 0xFF;
805 rc6_csl = 76;
806 } else if (wake_sc <= 0x007FFFFF) {
807 rc6_csl = 60;
808 } else {
809 do_wake = false;
810 dev_err(dev, "RC6 - Invalid wake scancode\n");
811 break;
812 }
813
814 /* Header */
815 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
816 mask[i++] = 0xFF;
817 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
818 mask[i++] = 0x0F;
819
820 } else {
821 do_wake = false;
822 dev_err(dev, "RC6 - Invalid wake mode\n");
823 }
824
825 break;
826
827 default:
828 do_wake = false;
829 break;
830 }
831
832 finish:
833 if (do_wake) {
834 /* Set compare and compare mask */
835 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
836 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
837 0x3F);
838 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
839 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
840 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
841 0x3F);
842 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
843
844 /* RC6 Compare String Len */
845 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
846
847 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
848 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
849
850 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
851 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
852
853 /* Set CEIR_EN */
854 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
855
856 } else {
857 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
858 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
859
860 /* Clear CEIR_EN */
861 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
862 }
863
864 /*
865 * ACPI will set the HW disable bit for SP3 which means that the
866 * output signals are left in an undefined state which may cause
867 * spurious interrupts which we need to ignore until the hardware
868 * is reinitialized.
869 */
870 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
871 disable_irq(data->irq);
872 }
873
874 static int
875 wbcir_suspend(struct pnp_dev *device, pm_message_t state)
876 {
877 struct wbcir_data *data = pnp_get_drvdata(device);
878 led_classdev_suspend(&data->led);
879 wbcir_shutdown(device);
880 return 0;
881 }
882
883 static void
884 wbcir_init_hw(struct wbcir_data *data)
885 {
886 u8 tmp;
887
888 /* Disable interrupts */
889 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
890
891 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
892 tmp = protocol << 4;
893 if (invert)
894 tmp |= 0x08;
895 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
896
897 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
898 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
899
900 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
901 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
902
903 /* Set RC5 cell time to correspond to 36 kHz */
904 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
905
906 /* Set IRTX_INV */
907 if (invert)
908 outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL);
909 else
910 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
911
912 /*
913 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
914 * set SP3_IRRX_SW to binary 01, helpfully not documented
915 */
916 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
917 data->txmask = 0x1;
918
919 /* Enable extended mode */
920 wbcir_select_bank(data, WBCIR_BANK_2);
921 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
922
923 /*
924 * Configure baud generator, IR data will be sampled at
925 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
926 *
927 * The ECIR registers include a flag to change the
928 * 24Mhz clock freq to 48Mhz.
929 *
930 * It's not documented in the specs, but fifo levels
931 * other than 16 seems to be unsupported.
932 */
933
934 /* prescaler 1.0, tx/rx fifo lvl 16 */
935 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
936
937 /* Set baud divisor to sample every 10 us */
938 outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
939 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
940
941 /* Set CEIR mode */
942 wbcir_select_bank(data, WBCIR_BANK_0);
943 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
944 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
945 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
946
947 /* Disable RX demod, enable run-length enc/dec, set freq span */
948 wbcir_select_bank(data, WBCIR_BANK_7);
949 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
950
951 /* Disable timer */
952 wbcir_select_bank(data, WBCIR_BANK_4);
953 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
954
955 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
956 wbcir_select_bank(data, WBCIR_BANK_5);
957 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
958
959 /* Disable CRC */
960 wbcir_select_bank(data, WBCIR_BANK_6);
961 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
962
963 /* Set RX demodulation freq, not really used */
964 wbcir_select_bank(data, WBCIR_BANK_7);
965 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
966
967 /* Set TX modulation, 36kHz, 7us pulse width */
968 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
969 data->txcarrier = 36000;
970
971 /* Set invert and pin direction */
972 if (invert)
973 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
974 else
975 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
976
977 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
978 wbcir_select_bank(data, WBCIR_BANK_0);
979 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
980
981 /* Clear AUX status bits */
982 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
983
984 /* Clear RX state */
985 data->rxstate = WBCIR_RXSTATE_INACTIVE;
986 ir_raw_event_reset(data->dev);
987 ir_raw_event_set_idle(data->dev, true);
988
989 /* Clear TX state */
990 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
991 kfree(data->txbuf);
992 data->txbuf = NULL;
993 data->txstate = WBCIR_TXSTATE_INACTIVE;
994 }
995
996 /* Enable interrupts */
997 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
998 }
999
1000 static int
1001 wbcir_resume(struct pnp_dev *device)
1002 {
1003 struct wbcir_data *data = pnp_get_drvdata(device);
1004
1005 wbcir_init_hw(data);
1006 enable_irq(data->irq);
1007 led_classdev_resume(&data->led);
1008
1009 return 0;
1010 }
1011
1012 static int
1013 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
1014 {
1015 struct device *dev = &device->dev;
1016 struct wbcir_data *data;
1017 int err;
1018
1019 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
1020 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
1021 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
1022 dev_err(dev, "Invalid resources\n");
1023 return -ENODEV;
1024 }
1025
1026 data = kzalloc(sizeof(*data), GFP_KERNEL);
1027 if (!data) {
1028 err = -ENOMEM;
1029 goto exit;
1030 }
1031
1032 pnp_set_drvdata(device, data);
1033
1034 spin_lock_init(&data->spinlock);
1035 data->ebase = pnp_port_start(device, 0);
1036 data->wbase = pnp_port_start(device, 1);
1037 data->sbase = pnp_port_start(device, 2);
1038 data->irq = pnp_irq(device, 0);
1039
1040 if (data->wbase == 0 || data->ebase == 0 ||
1041 data->sbase == 0 || data->irq == 0) {
1042 err = -ENODEV;
1043 dev_err(dev, "Invalid resources\n");
1044 goto exit_free_data;
1045 }
1046
1047 dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1048 data->wbase, data->ebase, data->sbase, data->irq);
1049
1050 data->led.name = "cir::activity";
1051 data->led.default_trigger = "rc-feedback";
1052 data->led.brightness_set = wbcir_led_brightness_set;
1053 data->led.brightness_get = wbcir_led_brightness_get;
1054 err = led_classdev_register(&device->dev, &data->led);
1055 if (err)
1056 goto exit_free_data;
1057
1058 data->dev = rc_allocate_device();
1059 if (!data->dev) {
1060 err = -ENOMEM;
1061 goto exit_unregister_led;
1062 }
1063
1064 data->dev->driver_type = RC_DRIVER_IR_RAW;
1065 data->dev->driver_name = DRVNAME;
1066 data->dev->input_name = WBCIR_NAME;
1067 data->dev->input_phys = "wbcir/cir0";
1068 data->dev->input_id.bustype = BUS_HOST;
1069 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1070 data->dev->input_id.product = WBCIR_ID_FAMILY;
1071 data->dev->input_id.version = WBCIR_ID_CHIP;
1072 data->dev->map_name = RC_MAP_RC6_MCE;
1073 data->dev->s_idle = wbcir_idle_rx;
1074 data->dev->s_carrier_report = wbcir_set_carrier_report;
1075 data->dev->s_tx_mask = wbcir_txmask;
1076 data->dev->s_tx_carrier = wbcir_txcarrier;
1077 data->dev->tx_ir = wbcir_tx;
1078 data->dev->priv = data;
1079 data->dev->dev.parent = &device->dev;
1080 data->dev->timeout = MS_TO_NS(100);
1081 data->dev->rx_resolution = US_TO_NS(2);
1082 data->dev->allowed_protocols = RC_BIT_ALL;
1083
1084 err = rc_register_device(data->dev);
1085 if (err)
1086 goto exit_free_rc;
1087
1088 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1089 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1090 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1091 err = -EBUSY;
1092 goto exit_unregister_device;
1093 }
1094
1095 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1096 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1097 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1098 err = -EBUSY;
1099 goto exit_release_wbase;
1100 }
1101
1102 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1103 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1104 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1105 err = -EBUSY;
1106 goto exit_release_ebase;
1107 }
1108
1109 err = request_irq(data->irq, wbcir_irq_handler,
1110 0, DRVNAME, device);
1111 if (err) {
1112 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1113 err = -EBUSY;
1114 goto exit_release_sbase;
1115 }
1116
1117 device_init_wakeup(&device->dev, 1);
1118
1119 wbcir_init_hw(data);
1120
1121 return 0;
1122
1123 exit_release_sbase:
1124 release_region(data->sbase, SP_IOMEM_LEN);
1125 exit_release_ebase:
1126 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1127 exit_release_wbase:
1128 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1129 exit_unregister_device:
1130 rc_unregister_device(data->dev);
1131 data->dev = NULL;
1132 exit_free_rc:
1133 rc_free_device(data->dev);
1134 exit_unregister_led:
1135 led_classdev_unregister(&data->led);
1136 exit_free_data:
1137 kfree(data);
1138 pnp_set_drvdata(device, NULL);
1139 exit:
1140 return err;
1141 }
1142
1143 static void
1144 wbcir_remove(struct pnp_dev *device)
1145 {
1146 struct wbcir_data *data = pnp_get_drvdata(device);
1147
1148 /* Disable interrupts */
1149 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1150 free_irq(data->irq, device);
1151
1152 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1153 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1154
1155 /* Clear CEIR_EN */
1156 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1157
1158 /* Clear BUFF_EN, END_EN, MATCH_EN */
1159 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1160
1161 rc_unregister_device(data->dev);
1162
1163 led_classdev_unregister(&data->led);
1164
1165 /* This is ok since &data->led isn't actually used */
1166 wbcir_led_brightness_set(&data->led, LED_OFF);
1167
1168 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1169 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1170 release_region(data->sbase, SP_IOMEM_LEN);
1171
1172 kfree(data);
1173
1174 pnp_set_drvdata(device, NULL);
1175 }
1176
1177 static const struct pnp_device_id wbcir_ids[] = {
1178 { "WEC1022", 0 },
1179 { "", 0 }
1180 };
1181 MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1182
1183 static struct pnp_driver wbcir_driver = {
1184 .name = DRVNAME,
1185 .id_table = wbcir_ids,
1186 .probe = wbcir_probe,
1187 .remove = wbcir_remove,
1188 .suspend = wbcir_suspend,
1189 .resume = wbcir_resume,
1190 .shutdown = wbcir_shutdown
1191 };
1192
1193 static int __init
1194 wbcir_init(void)
1195 {
1196 int ret;
1197
1198 switch (protocol) {
1199 case IR_PROTOCOL_RC5:
1200 case IR_PROTOCOL_NEC:
1201 case IR_PROTOCOL_RC6:
1202 break;
1203 default:
1204 pr_err("Invalid power-on protocol\n");
1205 }
1206
1207 ret = pnp_register_driver(&wbcir_driver);
1208 if (ret)
1209 pr_err("Unable to register driver\n");
1210
1211 return ret;
1212 }
1213
1214 static void __exit
1215 wbcir_exit(void)
1216 {
1217 pnp_unregister_driver(&wbcir_driver);
1218 }
1219
1220 module_init(wbcir_init);
1221 module_exit(wbcir_exit);
1222
1223 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1224 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1225 MODULE_LICENSE("GPL");
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