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[mirror_ubuntu-artful-kernel.git] / drivers / media / rc / winbond-cir.c
1 /*
2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
3 * SuperI/O chips.
4 *
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
8 *
9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2012 Sean Young <sean@mess.org>
11 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
12 *
13 * Dedicated to my daughter Matilda, without whose loving attention this
14 * driver would have been finished in half the time and with a fraction
15 * of the bugs.
16 *
17 * Written using:
18 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
19 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
20 * o DSDT dumps
21 *
22 * Supported features:
23 * o IR Receive
24 * o IR Transmit
25 * o Wake-On-CIR functionality
26 * o Carrier detection
27 *
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License as published by
30 * the Free Software Foundation; either version 2 of the License, or
31 * (at your option) any later version.
32 *
33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #include <linux/module.h>
46 #include <linux/pnp.h>
47 #include <linux/interrupt.h>
48 #include <linux/timer.h>
49 #include <linux/leds.h>
50 #include <linux/spinlock.h>
51 #include <linux/pci_ids.h>
52 #include <linux/io.h>
53 #include <linux/bitrev.h>
54 #include <linux/slab.h>
55 #include <linux/wait.h>
56 #include <linux/sched.h>
57 #include <media/rc-core.h>
58
59 #define DRVNAME "winbond-cir"
60
61 /* CEIR Wake-Up Registers, relative to data->wbase */
62 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
63 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
64 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
65 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
66 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
67 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
68 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
69 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
70 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
71 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
72
73 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
74 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
75 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
76 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
77 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
78 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
79
80 /* SP3 Banked Registers, relative to data->sbase */
81 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
82 /* Bank 0 */
83 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
84 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
85 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
86 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
87 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
88 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
89 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
90 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
91 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
92 /* Bank 2 */
93 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
94 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
95 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
96 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
97 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
98 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
99 /* Bank 3 */
100 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
101 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
102 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
103 /* Bank 4 */
104 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
105 /* Bank 5 */
106 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
107 /* Bank 6 */
108 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
109 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
110 /* Bank 7 */
111 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
112 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
113 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
114 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
115 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
116
117 /*
118 * Magic values follow
119 */
120
121 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
122 #define WBCIR_IRQ_NONE 0x00
123 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
124 #define WBCIR_IRQ_RX 0x01
125 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
126 #define WBCIR_IRQ_TX_LOW 0x02
127 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
128 #define WBCIR_IRQ_ERR 0x04
129 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
130 #define WBCIR_IRQ_TX_EMPTY 0x20
131 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
132 #define WBCIR_LED_ENABLE 0x80
133 /* RX data available bit for WBCIR_REG_SP3_LSR */
134 #define WBCIR_RX_AVAIL 0x01
135 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
136 #define WBCIR_RX_OVERRUN 0x02
137 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
138 #define WBCIR_TX_EOT 0x04
139 /* RX disable bit for WBCIR_REG_SP3_ASCR */
140 #define WBCIR_RX_DISABLE 0x20
141 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
142 #define WBCIR_TX_UNDERRUN 0x40
143 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
144 #define WBCIR_EXT_ENABLE 0x01
145 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
146 #define WBCIR_REGSEL_COMPARE 0x10
147 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
148 #define WBCIR_REGSEL_MASK 0x20
149 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
150 #define WBCIR_REG_ADDR0 0x00
151 /* Enable carrier counter */
152 #define WBCIR_CNTR_EN 0x01
153 /* Reset carrier counter */
154 #define WBCIR_CNTR_R 0x02
155 /* Invert TX */
156 #define WBCIR_IRTX_INV 0x04
157 /* Receiver oversampling */
158 #define WBCIR_RX_T_OV 0x40
159
160 /* Valid banks for the SP3 UART */
161 enum wbcir_bank {
162 WBCIR_BANK_0 = 0x00,
163 WBCIR_BANK_1 = 0x80,
164 WBCIR_BANK_2 = 0xE0,
165 WBCIR_BANK_3 = 0xE4,
166 WBCIR_BANK_4 = 0xE8,
167 WBCIR_BANK_5 = 0xEC,
168 WBCIR_BANK_6 = 0xF0,
169 WBCIR_BANK_7 = 0xF4,
170 };
171
172 /* Supported power-on IR Protocols */
173 enum wbcir_protocol {
174 IR_PROTOCOL_RC5 = 0x0,
175 IR_PROTOCOL_NEC = 0x1,
176 IR_PROTOCOL_RC6 = 0x2,
177 };
178
179 /* Possible states for IR reception */
180 enum wbcir_rxstate {
181 WBCIR_RXSTATE_INACTIVE = 0,
182 WBCIR_RXSTATE_ACTIVE,
183 WBCIR_RXSTATE_ERROR
184 };
185
186 /* Possible states for IR transmission */
187 enum wbcir_txstate {
188 WBCIR_TXSTATE_INACTIVE = 0,
189 WBCIR_TXSTATE_ACTIVE,
190 WBCIR_TXSTATE_ERROR
191 };
192
193 /* Misc */
194 #define WBCIR_NAME "Winbond CIR"
195 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
196 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
197 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
198 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
199 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
200 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
201
202 /* Per-device data */
203 struct wbcir_data {
204 spinlock_t spinlock;
205 struct rc_dev *dev;
206 struct led_classdev led;
207
208 unsigned long wbase; /* Wake-Up Baseaddr */
209 unsigned long ebase; /* Enhanced Func. Baseaddr */
210 unsigned long sbase; /* Serial Port Baseaddr */
211 unsigned int irq; /* Serial Port IRQ */
212 u8 irqmask;
213
214 /* RX state */
215 enum wbcir_rxstate rxstate;
216 int carrier_report_enabled;
217 u32 pulse_duration;
218
219 /* TX state */
220 enum wbcir_txstate txstate;
221 u32 txlen;
222 u32 txoff;
223 u32 *txbuf;
224 u8 txmask;
225 u32 txcarrier;
226 };
227
228 static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
229 module_param(protocol, uint, 0444);
230 MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command (0 = RC5, 1 = NEC, 2 = RC6A, default)");
231
232 static bool invert; /* default = 0 */
233 module_param(invert, bool, 0444);
234 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
235
236 static bool txandrx; /* default = 0 */
237 module_param(txandrx, bool, 0444);
238 MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
239
240 static unsigned int wake_sc = 0x800F040C;
241 module_param(wake_sc, uint, 0644);
242 MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
243
244 static unsigned int wake_rc6mode = 6;
245 module_param(wake_rc6mode, uint, 0644);
246 MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command (0 = 0, 6 = 6A, default)");
247
248
249
250 /*****************************************************************************
251 *
252 * UTILITY FUNCTIONS
253 *
254 *****************************************************************************/
255
256 /* Caller needs to hold wbcir_lock */
257 static void
258 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
259 {
260 u8 val;
261
262 val = inb(addr);
263 val = ((val & ~mask) | (bits & mask));
264 outb(val, addr);
265 }
266
267 /* Selects the register bank for the serial port */
268 static inline void
269 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
270 {
271 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
272 }
273
274 static inline void
275 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
276 {
277 if (data->irqmask == irqmask)
278 return;
279
280 wbcir_select_bank(data, WBCIR_BANK_0);
281 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
282 data->irqmask = irqmask;
283 }
284
285 static enum led_brightness
286 wbcir_led_brightness_get(struct led_classdev *led_cdev)
287 {
288 struct wbcir_data *data = container_of(led_cdev,
289 struct wbcir_data,
290 led);
291
292 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
293 return LED_FULL;
294 else
295 return LED_OFF;
296 }
297
298 static void
299 wbcir_led_brightness_set(struct led_classdev *led_cdev,
300 enum led_brightness brightness)
301 {
302 struct wbcir_data *data = container_of(led_cdev,
303 struct wbcir_data,
304 led);
305
306 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
307 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
308 WBCIR_LED_ENABLE);
309 }
310
311 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
312 static u8
313 wbcir_to_rc6cells(u8 val)
314 {
315 u8 coded = 0x00;
316 int i;
317
318 val &= 0x0F;
319 for (i = 0; i < 4; i++) {
320 if (val & 0x01)
321 coded |= 0x02 << (i * 2);
322 else
323 coded |= 0x01 << (i * 2);
324 val >>= 1;
325 }
326
327 return coded;
328 }
329
330 /*****************************************************************************
331 *
332 * INTERRUPT FUNCTIONS
333 *
334 *****************************************************************************/
335
336 static void
337 wbcir_carrier_report(struct wbcir_data *data)
338 {
339 unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) |
340 inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8;
341
342 if (counter > 0 && counter < 0xffff) {
343 DEFINE_IR_RAW_EVENT(ev);
344
345 ev.carrier_report = 1;
346 ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u,
347 data->pulse_duration);
348
349 ir_raw_event_store(data->dev, &ev);
350 }
351
352 /* reset and restart the counter */
353 data->pulse_duration = 0;
354 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
355 WBCIR_CNTR_EN | WBCIR_CNTR_R);
356 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN,
357 WBCIR_CNTR_EN | WBCIR_CNTR_R);
358 }
359
360 static void
361 wbcir_idle_rx(struct rc_dev *dev, bool idle)
362 {
363 struct wbcir_data *data = dev->priv;
364
365 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE)
366 data->rxstate = WBCIR_RXSTATE_ACTIVE;
367
368 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) {
369 data->rxstate = WBCIR_RXSTATE_INACTIVE;
370
371 if (data->carrier_report_enabled)
372 wbcir_carrier_report(data);
373
374 /* Tell hardware to go idle by setting RXINACTIVE */
375 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
376 }
377 }
378
379 static void
380 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
381 {
382 u8 irdata;
383 DEFINE_IR_RAW_EVENT(rawir);
384 unsigned duration;
385
386 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
387 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
388 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
389 if (data->rxstate == WBCIR_RXSTATE_ERROR)
390 continue;
391
392 duration = ((irdata & 0x7F) + 1) *
393 (data->carrier_report_enabled ? 2 : 10);
394 rawir.pulse = irdata & 0x80 ? false : true;
395 rawir.duration = US_TO_NS(duration);
396
397 if (rawir.pulse)
398 data->pulse_duration += duration;
399
400 ir_raw_event_store_with_filter(data->dev, &rawir);
401 }
402
403 ir_raw_event_handle(data->dev);
404 }
405
406 static void
407 wbcir_irq_tx(struct wbcir_data *data)
408 {
409 unsigned int space;
410 unsigned int used;
411 u8 bytes[16];
412 u8 byte;
413
414 if (!data->txbuf)
415 return;
416
417 switch (data->txstate) {
418 case WBCIR_TXSTATE_INACTIVE:
419 /* TX FIFO empty */
420 space = 16;
421 break;
422 case WBCIR_TXSTATE_ACTIVE:
423 /* TX FIFO low (3 bytes or less) */
424 space = 13;
425 break;
426 case WBCIR_TXSTATE_ERROR:
427 space = 0;
428 break;
429 default:
430 return;
431 }
432
433 /*
434 * TX data is run-length coded in bytes: YXXXXXXX
435 * Y = space (1) or pulse (0)
436 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
437 */
438 for (used = 0; used < space && data->txoff != data->txlen; used++) {
439 if (data->txbuf[data->txoff] == 0) {
440 data->txoff++;
441 continue;
442 }
443 byte = min((u32)0x80, data->txbuf[data->txoff]);
444 data->txbuf[data->txoff] -= byte;
445 byte--;
446 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
447 bytes[used] = byte;
448 }
449
450 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
451 data->txoff++;
452
453 if (used == 0) {
454 /* Finished */
455 if (data->txstate == WBCIR_TXSTATE_ERROR)
456 /* Clear TX underrun bit */
457 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
458 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
459 kfree(data->txbuf);
460 data->txbuf = NULL;
461 data->txstate = WBCIR_TXSTATE_INACTIVE;
462 } else if (data->txoff == data->txlen) {
463 /* At the end of transmission, tell the hw before last byte */
464 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
465 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
466 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
467 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
468 WBCIR_IRQ_TX_EMPTY);
469 } else {
470 /* More data to follow... */
471 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
472 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
473 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
474 WBCIR_IRQ_TX_LOW);
475 data->txstate = WBCIR_TXSTATE_ACTIVE;
476 }
477 }
478 }
479
480 static irqreturn_t
481 wbcir_irq_handler(int irqno, void *cookie)
482 {
483 struct pnp_dev *device = cookie;
484 struct wbcir_data *data = pnp_get_drvdata(device);
485 unsigned long flags;
486 u8 status;
487
488 spin_lock_irqsave(&data->spinlock, flags);
489 wbcir_select_bank(data, WBCIR_BANK_0);
490 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
491 status &= data->irqmask;
492
493 if (!status) {
494 spin_unlock_irqrestore(&data->spinlock, flags);
495 return IRQ_NONE;
496 }
497
498 if (status & WBCIR_IRQ_ERR) {
499 /* RX overflow? (read clears bit) */
500 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
501 data->rxstate = WBCIR_RXSTATE_ERROR;
502 ir_raw_event_reset(data->dev);
503 }
504
505 /* TX underflow? */
506 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
507 data->txstate = WBCIR_TXSTATE_ERROR;
508 }
509
510 if (status & WBCIR_IRQ_RX)
511 wbcir_irq_rx(data, device);
512
513 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
514 wbcir_irq_tx(data);
515
516 spin_unlock_irqrestore(&data->spinlock, flags);
517 return IRQ_HANDLED;
518 }
519
520 /*****************************************************************************
521 *
522 * RC-CORE INTERFACE FUNCTIONS
523 *
524 *****************************************************************************/
525
526 static int
527 wbcir_set_carrier_report(struct rc_dev *dev, int enable)
528 {
529 struct wbcir_data *data = dev->priv;
530 unsigned long flags;
531
532 spin_lock_irqsave(&data->spinlock, flags);
533
534 if (data->carrier_report_enabled == enable) {
535 spin_unlock_irqrestore(&data->spinlock, flags);
536 return 0;
537 }
538
539 data->pulse_duration = 0;
540 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
541 WBCIR_CNTR_EN | WBCIR_CNTR_R);
542
543 if (enable && data->dev->idle)
544 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL,
545 WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R);
546
547 /* Set a higher sampling resolution if carrier reports are enabled */
548 wbcir_select_bank(data, WBCIR_BANK_2);
549 data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10);
550 outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
551 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
552
553 /* Enable oversampling if carrier reports are enabled */
554 wbcir_select_bank(data, WBCIR_BANK_7);
555 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG,
556 enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV);
557
558 data->carrier_report_enabled = enable;
559 spin_unlock_irqrestore(&data->spinlock, flags);
560
561 return 0;
562 }
563
564 static int
565 wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
566 {
567 struct wbcir_data *data = dev->priv;
568 unsigned long flags;
569 u8 val;
570 u32 freq;
571
572 freq = DIV_ROUND_CLOSEST(carrier, 1000);
573 if (freq < 30 || freq > 60)
574 return -EINVAL;
575
576 switch (freq) {
577 case 58:
578 case 59:
579 case 60:
580 val = freq - 58;
581 freq *= 1000;
582 break;
583 case 57:
584 val = freq - 27;
585 freq = 56900;
586 break;
587 default:
588 val = freq - 27;
589 freq *= 1000;
590 break;
591 }
592
593 spin_lock_irqsave(&data->spinlock, flags);
594 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
595 spin_unlock_irqrestore(&data->spinlock, flags);
596 return -EBUSY;
597 }
598
599 if (data->txcarrier != freq) {
600 wbcir_select_bank(data, WBCIR_BANK_7);
601 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
602 data->txcarrier = freq;
603 }
604
605 spin_unlock_irqrestore(&data->spinlock, flags);
606 return 0;
607 }
608
609 static int
610 wbcir_txmask(struct rc_dev *dev, u32 mask)
611 {
612 struct wbcir_data *data = dev->priv;
613 unsigned long flags;
614 u8 val;
615
616 /* return the number of transmitters */
617 if (mask > 15)
618 return 4;
619
620 /* Four outputs, only one output can be enabled at a time */
621 switch (mask) {
622 case 0x1:
623 val = 0x0;
624 break;
625 case 0x2:
626 val = 0x1;
627 break;
628 case 0x4:
629 val = 0x2;
630 break;
631 case 0x8:
632 val = 0x3;
633 break;
634 default:
635 return -EINVAL;
636 }
637
638 spin_lock_irqsave(&data->spinlock, flags);
639 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
640 spin_unlock_irqrestore(&data->spinlock, flags);
641 return -EBUSY;
642 }
643
644 if (data->txmask != mask) {
645 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
646 data->txmask = mask;
647 }
648
649 spin_unlock_irqrestore(&data->spinlock, flags);
650 return 0;
651 }
652
653 static int
654 wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
655 {
656 struct wbcir_data *data = dev->priv;
657 unsigned *buf;
658 unsigned i;
659 unsigned long flags;
660
661 buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL);
662 if (!buf)
663 return -ENOMEM;
664
665 /* Convert values to multiples of 10us */
666 for (i = 0; i < count; i++)
667 buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
668
669 /* Not sure if this is possible, but better safe than sorry */
670 spin_lock_irqsave(&data->spinlock, flags);
671 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
672 spin_unlock_irqrestore(&data->spinlock, flags);
673 kfree(buf);
674 return -EBUSY;
675 }
676
677 /* Fill the TX fifo once, the irq handler will do the rest */
678 data->txbuf = buf;
679 data->txlen = count;
680 data->txoff = 0;
681 wbcir_irq_tx(data);
682
683 /* We're done */
684 spin_unlock_irqrestore(&data->spinlock, flags);
685 return count;
686 }
687
688 /*****************************************************************************
689 *
690 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
691 *
692 *****************************************************************************/
693
694 static void
695 wbcir_shutdown(struct pnp_dev *device)
696 {
697 struct device *dev = &device->dev;
698 struct wbcir_data *data = pnp_get_drvdata(device);
699 bool do_wake = true;
700 u8 match[11];
701 u8 mask[11];
702 u8 rc6_csl = 0;
703 int i;
704
705 memset(match, 0, sizeof(match));
706 memset(mask, 0, sizeof(mask));
707
708 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
709 do_wake = false;
710 goto finish;
711 }
712
713 switch (protocol) {
714 case IR_PROTOCOL_RC5:
715 if (wake_sc > 0xFFF) {
716 do_wake = false;
717 dev_err(dev, "RC5 - Invalid wake scancode\n");
718 break;
719 }
720
721 /* Mask = 13 bits, ex toggle */
722 mask[0] = 0xFF;
723 mask[1] = 0x17;
724
725 match[0] = (wake_sc & 0x003F); /* 6 command bits */
726 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
727 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
728 if (!(wake_sc & 0x0040)) /* 2nd start bit */
729 match[1] |= 0x10;
730
731 break;
732
733 case IR_PROTOCOL_NEC:
734 if (wake_sc > 0xFFFFFF) {
735 do_wake = false;
736 dev_err(dev, "NEC - Invalid wake scancode\n");
737 break;
738 }
739
740 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
741
742 match[1] = bitrev8((wake_sc & 0xFF));
743 match[0] = ~match[1];
744
745 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
746 if (wake_sc > 0xFFFF)
747 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
748 else
749 match[2] = ~match[3];
750
751 break;
752
753 case IR_PROTOCOL_RC6:
754
755 if (wake_rc6mode == 0) {
756 if (wake_sc > 0xFFFF) {
757 do_wake = false;
758 dev_err(dev, "RC6 - Invalid wake scancode\n");
759 break;
760 }
761
762 /* Command */
763 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
764 mask[0] = 0xFF;
765 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
766 mask[1] = 0xFF;
767
768 /* Address */
769 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
770 mask[2] = 0xFF;
771 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
772 mask[3] = 0xFF;
773
774 /* Header */
775 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
776 mask[4] = 0xF0;
777 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
778 mask[5] = 0x0F;
779
780 rc6_csl = 44;
781
782 } else if (wake_rc6mode == 6) {
783 i = 0;
784
785 /* Command */
786 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
787 mask[i++] = 0xFF;
788 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
789 mask[i++] = 0xFF;
790
791 /* Address + Toggle */
792 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
793 mask[i++] = 0xFF;
794 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
795 mask[i++] = 0x3F;
796
797 /* Customer bits 7 - 0 */
798 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
799 mask[i++] = 0xFF;
800 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
801 mask[i++] = 0xFF;
802
803 if (wake_sc & 0x80000000) {
804 /* Customer range bit and bits 15 - 8 */
805 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
806 mask[i++] = 0xFF;
807 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
808 mask[i++] = 0xFF;
809 rc6_csl = 76;
810 } else if (wake_sc <= 0x007FFFFF) {
811 rc6_csl = 60;
812 } else {
813 do_wake = false;
814 dev_err(dev, "RC6 - Invalid wake scancode\n");
815 break;
816 }
817
818 /* Header */
819 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
820 mask[i++] = 0xFF;
821 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
822 mask[i++] = 0x0F;
823
824 } else {
825 do_wake = false;
826 dev_err(dev, "RC6 - Invalid wake mode\n");
827 }
828
829 break;
830
831 default:
832 do_wake = false;
833 break;
834 }
835
836 finish:
837 if (do_wake) {
838 /* Set compare and compare mask */
839 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
840 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
841 0x3F);
842 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
843 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
844 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
845 0x3F);
846 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
847
848 /* RC6 Compare String Len */
849 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
850
851 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
852 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
853
854 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
855 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
856
857 /* Set CEIR_EN */
858 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
859
860 } else {
861 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
862 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
863
864 /* Clear CEIR_EN */
865 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
866 }
867
868 /*
869 * ACPI will set the HW disable bit for SP3 which means that the
870 * output signals are left in an undefined state which may cause
871 * spurious interrupts which we need to ignore until the hardware
872 * is reinitialized.
873 */
874 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
875 disable_irq(data->irq);
876 }
877
878 static int
879 wbcir_suspend(struct pnp_dev *device, pm_message_t state)
880 {
881 struct wbcir_data *data = pnp_get_drvdata(device);
882 led_classdev_suspend(&data->led);
883 wbcir_shutdown(device);
884 return 0;
885 }
886
887 static void
888 wbcir_init_hw(struct wbcir_data *data)
889 {
890 u8 tmp;
891
892 /* Disable interrupts */
893 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
894
895 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
896 tmp = protocol << 4;
897 if (invert)
898 tmp |= 0x08;
899 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
900
901 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
902 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
903
904 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
905 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
906
907 /* Set RC5 cell time to correspond to 36 kHz */
908 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
909
910 /* Set IRTX_INV */
911 if (invert)
912 outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL);
913 else
914 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
915
916 /*
917 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
918 * set SP3_IRRX_SW to binary 01, helpfully not documented
919 */
920 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
921 data->txmask = 0x1;
922
923 /* Enable extended mode */
924 wbcir_select_bank(data, WBCIR_BANK_2);
925 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
926
927 /*
928 * Configure baud generator, IR data will be sampled at
929 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
930 *
931 * The ECIR registers include a flag to change the
932 * 24Mhz clock freq to 48Mhz.
933 *
934 * It's not documented in the specs, but fifo levels
935 * other than 16 seems to be unsupported.
936 */
937
938 /* prescaler 1.0, tx/rx fifo lvl 16 */
939 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
940
941 /* Set baud divisor to sample every 10 us */
942 outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
943 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
944
945 /* Set CEIR mode */
946 wbcir_select_bank(data, WBCIR_BANK_0);
947 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
948 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
949 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
950
951 /* Disable RX demod, enable run-length enc/dec, set freq span */
952 wbcir_select_bank(data, WBCIR_BANK_7);
953 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
954
955 /* Disable timer */
956 wbcir_select_bank(data, WBCIR_BANK_4);
957 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
958
959 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
960 wbcir_select_bank(data, WBCIR_BANK_5);
961 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
962
963 /* Disable CRC */
964 wbcir_select_bank(data, WBCIR_BANK_6);
965 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
966
967 /* Set RX demodulation freq, not really used */
968 wbcir_select_bank(data, WBCIR_BANK_7);
969 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
970
971 /* Set TX modulation, 36kHz, 7us pulse width */
972 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
973 data->txcarrier = 36000;
974
975 /* Set invert and pin direction */
976 if (invert)
977 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
978 else
979 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
980
981 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
982 wbcir_select_bank(data, WBCIR_BANK_0);
983 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
984
985 /* Clear AUX status bits */
986 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
987
988 /* Clear RX state */
989 data->rxstate = WBCIR_RXSTATE_INACTIVE;
990 ir_raw_event_reset(data->dev);
991 ir_raw_event_set_idle(data->dev, true);
992
993 /* Clear TX state */
994 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
995 kfree(data->txbuf);
996 data->txbuf = NULL;
997 data->txstate = WBCIR_TXSTATE_INACTIVE;
998 }
999
1000 /* Enable interrupts */
1001 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
1002 }
1003
1004 static int
1005 wbcir_resume(struct pnp_dev *device)
1006 {
1007 struct wbcir_data *data = pnp_get_drvdata(device);
1008
1009 wbcir_init_hw(data);
1010 enable_irq(data->irq);
1011 led_classdev_resume(&data->led);
1012
1013 return 0;
1014 }
1015
1016 static int
1017 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
1018 {
1019 struct device *dev = &device->dev;
1020 struct wbcir_data *data;
1021 int err;
1022
1023 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
1024 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
1025 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
1026 dev_err(dev, "Invalid resources\n");
1027 return -ENODEV;
1028 }
1029
1030 data = kzalloc(sizeof(*data), GFP_KERNEL);
1031 if (!data) {
1032 err = -ENOMEM;
1033 goto exit;
1034 }
1035
1036 pnp_set_drvdata(device, data);
1037
1038 spin_lock_init(&data->spinlock);
1039 data->ebase = pnp_port_start(device, 0);
1040 data->wbase = pnp_port_start(device, 1);
1041 data->sbase = pnp_port_start(device, 2);
1042 data->irq = pnp_irq(device, 0);
1043
1044 if (data->wbase == 0 || data->ebase == 0 ||
1045 data->sbase == 0 || data->irq == 0) {
1046 err = -ENODEV;
1047 dev_err(dev, "Invalid resources\n");
1048 goto exit_free_data;
1049 }
1050
1051 dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1052 data->wbase, data->ebase, data->sbase, data->irq);
1053
1054 data->led.name = "cir::activity";
1055 data->led.default_trigger = "rc-feedback";
1056 data->led.brightness_set = wbcir_led_brightness_set;
1057 data->led.brightness_get = wbcir_led_brightness_get;
1058 err = led_classdev_register(&device->dev, &data->led);
1059 if (err)
1060 goto exit_free_data;
1061
1062 data->dev = rc_allocate_device();
1063 if (!data->dev) {
1064 err = -ENOMEM;
1065 goto exit_unregister_led;
1066 }
1067
1068 data->dev->driver_type = RC_DRIVER_IR_RAW;
1069 data->dev->driver_name = DRVNAME;
1070 data->dev->input_name = WBCIR_NAME;
1071 data->dev->input_phys = "wbcir/cir0";
1072 data->dev->input_id.bustype = BUS_HOST;
1073 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1074 data->dev->input_id.product = WBCIR_ID_FAMILY;
1075 data->dev->input_id.version = WBCIR_ID_CHIP;
1076 data->dev->map_name = RC_MAP_RC6_MCE;
1077 data->dev->s_idle = wbcir_idle_rx;
1078 data->dev->s_carrier_report = wbcir_set_carrier_report;
1079 data->dev->s_tx_mask = wbcir_txmask;
1080 data->dev->s_tx_carrier = wbcir_txcarrier;
1081 data->dev->tx_ir = wbcir_tx;
1082 data->dev->priv = data;
1083 data->dev->dev.parent = &device->dev;
1084 data->dev->timeout = MS_TO_NS(100);
1085 data->dev->rx_resolution = US_TO_NS(2);
1086 data->dev->allowed_protocols = RC_BIT_ALL;
1087
1088 err = rc_register_device(data->dev);
1089 if (err)
1090 goto exit_free_rc;
1091
1092 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1093 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1094 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1095 err = -EBUSY;
1096 goto exit_unregister_device;
1097 }
1098
1099 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1100 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1101 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1102 err = -EBUSY;
1103 goto exit_release_wbase;
1104 }
1105
1106 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1107 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1108 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1109 err = -EBUSY;
1110 goto exit_release_ebase;
1111 }
1112
1113 err = request_irq(data->irq, wbcir_irq_handler,
1114 0, DRVNAME, device);
1115 if (err) {
1116 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1117 err = -EBUSY;
1118 goto exit_release_sbase;
1119 }
1120
1121 device_init_wakeup(&device->dev, 1);
1122
1123 wbcir_init_hw(data);
1124
1125 return 0;
1126
1127 exit_release_sbase:
1128 release_region(data->sbase, SP_IOMEM_LEN);
1129 exit_release_ebase:
1130 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1131 exit_release_wbase:
1132 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1133 exit_unregister_device:
1134 rc_unregister_device(data->dev);
1135 data->dev = NULL;
1136 exit_free_rc:
1137 rc_free_device(data->dev);
1138 exit_unregister_led:
1139 led_classdev_unregister(&data->led);
1140 exit_free_data:
1141 kfree(data);
1142 pnp_set_drvdata(device, NULL);
1143 exit:
1144 return err;
1145 }
1146
1147 static void
1148 wbcir_remove(struct pnp_dev *device)
1149 {
1150 struct wbcir_data *data = pnp_get_drvdata(device);
1151
1152 /* Disable interrupts */
1153 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1154 free_irq(data->irq, device);
1155
1156 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1157 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1158
1159 /* Clear CEIR_EN */
1160 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1161
1162 /* Clear BUFF_EN, END_EN, MATCH_EN */
1163 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1164
1165 rc_unregister_device(data->dev);
1166
1167 led_classdev_unregister(&data->led);
1168
1169 /* This is ok since &data->led isn't actually used */
1170 wbcir_led_brightness_set(&data->led, LED_OFF);
1171
1172 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1173 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1174 release_region(data->sbase, SP_IOMEM_LEN);
1175
1176 kfree(data);
1177
1178 pnp_set_drvdata(device, NULL);
1179 }
1180
1181 static const struct pnp_device_id wbcir_ids[] = {
1182 { "WEC1022", 0 },
1183 { "", 0 }
1184 };
1185 MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1186
1187 static struct pnp_driver wbcir_driver = {
1188 .name = DRVNAME,
1189 .id_table = wbcir_ids,
1190 .probe = wbcir_probe,
1191 .remove = wbcir_remove,
1192 .suspend = wbcir_suspend,
1193 .resume = wbcir_resume,
1194 .shutdown = wbcir_shutdown
1195 };
1196
1197 static int __init
1198 wbcir_init(void)
1199 {
1200 int ret;
1201
1202 switch (protocol) {
1203 case IR_PROTOCOL_RC5:
1204 case IR_PROTOCOL_NEC:
1205 case IR_PROTOCOL_RC6:
1206 break;
1207 default:
1208 pr_err("Invalid power-on protocol\n");
1209 }
1210
1211 ret = pnp_register_driver(&wbcir_driver);
1212 if (ret)
1213 pr_err("Unable to register driver\n");
1214
1215 return ret;
1216 }
1217
1218 static void __exit
1219 wbcir_exit(void)
1220 {
1221 pnp_unregister_driver(&wbcir_driver);
1222 }
1223
1224 module_init(wbcir_init);
1225 module_exit(wbcir_exit);
1226
1227 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1228 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1229 MODULE_LICENSE("GPL");
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