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[mirror_ubuntu-artful-kernel.git] / drivers / media / usb / cx231xx / cx231xx-avcore.c
1 /*
2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
32 #include <linux/mm.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
35
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38
39 #include "cx231xx.h"
40 #include "cx231xx-dif.h"
41
42 #define TUNER_MODE_FM_RADIO 0
43 /******************************************************************************
44 -: BLOCK ARRANGEMENT :-
45 I2S block ----------------------|
46 [I2S audio] |
47 |
48 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
49 [video & audio] | [Audio]
50 |
51 |-> Cx25840 --> Video
52 [Video]
53
54 *******************************************************************************/
55 /******************************************************************************
56 * VERVE REGISTER *
57 * *
58 ******************************************************************************/
59 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
60 {
61 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
62 saddr, 1, data, 1);
63 }
64
65 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
66 {
67 int status;
68 u32 temp = 0;
69
70 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
71 saddr, 1, &temp, 1);
72 *data = (u8) temp;
73 return status;
74 }
75 void initGPIO(struct cx231xx *dev)
76 {
77 u32 _gpio_direction = 0;
78 u32 value = 0;
79 u8 val = 0;
80
81 _gpio_direction = _gpio_direction & 0xFC0003FF;
82 _gpio_direction = _gpio_direction | 0x03FDFC00;
83 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
84
85 verve_read_byte(dev, 0x07, &val);
86 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
87 verve_write_byte(dev, 0x07, 0xF4);
88 verve_read_byte(dev, 0x07, &val);
89 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
90
91 cx231xx_capture_start(dev, 1, Vbi);
92
93 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
94 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
95
96 }
97 void uninitGPIO(struct cx231xx *dev)
98 {
99 u8 value[4] = { 0, 0, 0, 0 };
100
101 cx231xx_capture_start(dev, 0, Vbi);
102 verve_write_byte(dev, 0x07, 0x14);
103 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
104 0x68, value, 4);
105 }
106
107 /******************************************************************************
108 * A F E - B L O C K C O N T R O L functions *
109 * [ANALOG FRONT END] *
110 ******************************************************************************/
111 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
112 {
113 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
114 saddr, 2, data, 1);
115 }
116
117 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
118 {
119 int status;
120 u32 temp = 0;
121
122 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
123 saddr, 2, &temp, 1);
124 *data = (u8) temp;
125 return status;
126 }
127
128 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
129 {
130 int status = 0;
131 u8 temp = 0;
132 u8 afe_power_status = 0;
133 int i = 0;
134
135 /* super block initialize */
136 temp = (u8) (ref_count & 0xff);
137 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
138 if (status < 0)
139 return status;
140
141 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
142 if (status < 0)
143 return status;
144
145 temp = (u8) ((ref_count & 0x300) >> 8);
146 temp |= 0x40;
147 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
148 if (status < 0)
149 return status;
150
151 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
152 if (status < 0)
153 return status;
154
155 /* enable pll */
156 while (afe_power_status != 0x18) {
157 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
158 if (status < 0) {
159 cx231xx_info(
160 ": Init Super Block failed in send cmd\n");
161 break;
162 }
163
164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
165 afe_power_status &= 0xff;
166 if (status < 0) {
167 cx231xx_info(
168 ": Init Super Block failed in receive cmd\n");
169 break;
170 }
171 i++;
172 if (i == 10) {
173 cx231xx_info(
174 ": Init Super Block force break in loop !!!!\n");
175 status = -1;
176 break;
177 }
178 }
179
180 if (status < 0)
181 return status;
182
183 /* start tuning filter */
184 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
185 if (status < 0)
186 return status;
187
188 msleep(5);
189
190 /* exit tuning */
191 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
192
193 return status;
194 }
195
196 int cx231xx_afe_init_channels(struct cx231xx *dev)
197 {
198 int status = 0;
199
200 /* power up all 3 channels, clear pd_buffer */
201 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
204
205 /* Enable quantizer calibration */
206 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
207
208 /* channel initialize, force modulator (fb) reset */
209 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
212
213 /* start quantilizer calibration */
214 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
217 msleep(5);
218
219 /* exit modulator (fb) reset */
220 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
223
224 /* enable the pre_clamp in each channel for single-ended input */
225 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
228
229 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
230 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
231 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
233 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
235 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
236
237 /* dynamic element matching off */
238 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
241
242 return status;
243 }
244
245 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
246 {
247 u8 c_value = 0;
248 int status = 0;
249
250 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
251 c_value &= (~(0x50));
252 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
253
254 return status;
255 }
256
257 /*
258 The Analog Front End in Cx231xx has 3 channels. These
259 channels are used to share between different inputs
260 like tuner, s-video and composite inputs.
261
262 channel 1 ----- pin 1 to pin4(in reg is 1-4)
263 channel 2 ----- pin 5 to pin8(in reg is 5-8)
264 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
265 */
266 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
267 {
268 u8 ch1_setting = (u8) input_mux;
269 u8 ch2_setting = (u8) (input_mux >> 8);
270 u8 ch3_setting = (u8) (input_mux >> 16);
271 int status = 0;
272 u8 value = 0;
273
274 if (ch1_setting != 0) {
275 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
276 value &= ~INPUT_SEL_MASK;
277 value |= (ch1_setting - 1) << 4;
278 value &= 0xff;
279 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
280 }
281
282 if (ch2_setting != 0) {
283 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
284 value &= ~INPUT_SEL_MASK;
285 value |= (ch2_setting - 1) << 4;
286 value &= 0xff;
287 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
288 }
289
290 /* For ch3_setting, the value to put in the register is
291 7 less than the input number */
292 if (ch3_setting != 0) {
293 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
294 value &= ~INPUT_SEL_MASK;
295 value |= (ch3_setting - 1) << 4;
296 value &= 0xff;
297 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
298 }
299
300 return status;
301 }
302
303 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
304 {
305 int status = 0;
306
307 /*
308 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
309 * Currently, only baseband works.
310 */
311
312 switch (mode) {
313 case AFE_MODE_LOW_IF:
314 cx231xx_Setup_AFE_for_LowIF(dev);
315 break;
316 case AFE_MODE_BASEBAND:
317 status = cx231xx_afe_setup_AFE_for_baseband(dev);
318 break;
319 case AFE_MODE_EU_HI_IF:
320 /* SetupAFEforEuHiIF(); */
321 break;
322 case AFE_MODE_US_HI_IF:
323 /* SetupAFEforUsHiIF(); */
324 break;
325 case AFE_MODE_JAPAN_HI_IF:
326 /* SetupAFEforJapanHiIF(); */
327 break;
328 }
329
330 if ((mode != dev->afe_mode) &&
331 (dev->video_input == CX231XX_VMUX_TELEVISION))
332 status = cx231xx_afe_adjust_ref_count(dev,
333 CX231XX_VMUX_TELEVISION);
334
335 dev->afe_mode = mode;
336
337 return status;
338 }
339
340 int cx231xx_afe_update_power_control(struct cx231xx *dev,
341 enum AV_MODE avmode)
342 {
343 u8 afe_power_status = 0;
344 int status = 0;
345
346 switch (dev->model) {
347 case CX231XX_BOARD_CNXT_CARRAERA:
348 case CX231XX_BOARD_CNXT_RDE_250:
349 case CX231XX_BOARD_CNXT_SHELBY:
350 case CX231XX_BOARD_CNXT_RDU_250:
351 case CX231XX_BOARD_CNXT_RDE_253S:
352 case CX231XX_BOARD_CNXT_RDU_253S:
353 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
354 case CX231XX_BOARD_HAUPPAUGE_EXETER:
355 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
358 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
359 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
360 case CX231XX_BOARD_OTG102:
361 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
362 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
363 FLD_PWRDN_ENABLE_PLL)) {
364 status = afe_write_byte(dev, SUP_BLK_PWRDN,
365 FLD_PWRDN_TUNING_BIAS |
366 FLD_PWRDN_ENABLE_PLL);
367 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
368 &afe_power_status);
369 if (status < 0)
370 break;
371 }
372
373 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
374 0x00);
375 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
376 0x00);
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
378 0x00);
379 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
380 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
381 0x70);
382 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
383 0x70);
384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
385 0x70);
386
387 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
388 &afe_power_status);
389 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
390 FLD_PWRDN_PD_BIAS |
391 FLD_PWRDN_PD_TUNECK;
392 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
393 afe_power_status);
394 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
395 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
396 FLD_PWRDN_ENABLE_PLL)) {
397 status = afe_write_byte(dev, SUP_BLK_PWRDN,
398 FLD_PWRDN_TUNING_BIAS |
399 FLD_PWRDN_ENABLE_PLL);
400 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
401 &afe_power_status);
402 if (status < 0)
403 break;
404 }
405
406 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
407 0x00);
408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
409 0x00);
410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
411 0x00);
412 } else {
413 cx231xx_info("Invalid AV mode input\n");
414 status = -1;
415 }
416 break;
417 default:
418 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
419 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
420 FLD_PWRDN_ENABLE_PLL)) {
421 status = afe_write_byte(dev, SUP_BLK_PWRDN,
422 FLD_PWRDN_TUNING_BIAS |
423 FLD_PWRDN_ENABLE_PLL);
424 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
425 &afe_power_status);
426 if (status < 0)
427 break;
428 }
429
430 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
431 0x40);
432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
433 0x40);
434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
435 0x00);
436 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
437 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
438 0x70);
439 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
440 0x70);
441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
442 0x70);
443
444 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
445 &afe_power_status);
446 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
447 FLD_PWRDN_PD_BIAS |
448 FLD_PWRDN_PD_TUNECK;
449 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
450 afe_power_status);
451 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
452 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
453 FLD_PWRDN_ENABLE_PLL)) {
454 status = afe_write_byte(dev, SUP_BLK_PWRDN,
455 FLD_PWRDN_TUNING_BIAS |
456 FLD_PWRDN_ENABLE_PLL);
457 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
458 &afe_power_status);
459 if (status < 0)
460 break;
461 }
462
463 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
464 0x00);
465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
466 0x00);
467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
468 0x40);
469 } else {
470 cx231xx_info("Invalid AV mode input\n");
471 status = -1;
472 }
473 } /* switch */
474
475 return status;
476 }
477
478 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
479 {
480 u8 input_mode = 0;
481 u8 ntf_mode = 0;
482 int status = 0;
483
484 dev->video_input = video_input;
485
486 if (video_input == CX231XX_VMUX_TELEVISION) {
487 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
488 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
489 &ntf_mode);
490 } else {
491 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
492 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
493 &ntf_mode);
494 }
495
496 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
497
498 switch (input_mode) {
499 case SINGLE_ENDED:
500 dev->afe_ref_count = 0x23C;
501 break;
502 case LOW_IF:
503 dev->afe_ref_count = 0x24C;
504 break;
505 case EU_IF:
506 dev->afe_ref_count = 0x258;
507 break;
508 case US_IF:
509 dev->afe_ref_count = 0x260;
510 break;
511 default:
512 break;
513 }
514
515 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
516
517 return status;
518 }
519
520 /******************************************************************************
521 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
522 ******************************************************************************/
523 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
524 {
525 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
526 saddr, 2, data, 1);
527 }
528
529 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
530 {
531 int status;
532 u32 temp = 0;
533
534 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
535 saddr, 2, &temp, 1);
536 *data = (u8) temp;
537 return status;
538 }
539
540 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
541 {
542 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
543 saddr, 2, data, 4);
544 }
545
546 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
547 {
548 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
549 saddr, 2, data, 4);
550 }
551 int cx231xx_check_fw(struct cx231xx *dev)
552 {
553 u8 temp = 0;
554 int status = 0;
555 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
556 if (status < 0)
557 return status;
558 else
559 return temp;
560
561 }
562
563 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
564 {
565 int status = 0;
566
567 switch (INPUT(input)->type) {
568 case CX231XX_VMUX_COMPOSITE1:
569 case CX231XX_VMUX_SVIDEO:
570 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
571 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
572 /* External AV */
573 status = cx231xx_set_power_mode(dev,
574 POLARIS_AVMODE_ENXTERNAL_AV);
575 if (status < 0) {
576 cx231xx_errdev("%s: set_power_mode : Failed to"
577 " set Power - errCode [%d]!\n",
578 __func__, status);
579 return status;
580 }
581 }
582 status = cx231xx_set_decoder_video_input(dev,
583 INPUT(input)->type,
584 INPUT(input)->vmux);
585 break;
586 case CX231XX_VMUX_TELEVISION:
587 case CX231XX_VMUX_CABLE:
588 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
589 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
590 /* Tuner */
591 status = cx231xx_set_power_mode(dev,
592 POLARIS_AVMODE_ANALOGT_TV);
593 if (status < 0) {
594 cx231xx_errdev("%s: set_power_mode:Failed"
595 " to set Power - errCode [%d]!\n",
596 __func__, status);
597 return status;
598 }
599 }
600 if (dev->tuner_type == TUNER_NXP_TDA18271)
601 status = cx231xx_set_decoder_video_input(dev,
602 CX231XX_VMUX_TELEVISION,
603 INPUT(input)->vmux);
604 else
605 status = cx231xx_set_decoder_video_input(dev,
606 CX231XX_VMUX_COMPOSITE1,
607 INPUT(input)->vmux);
608
609 break;
610 default:
611 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
612 __func__, INPUT(input)->type);
613 break;
614 }
615
616 /* save the selection */
617 dev->video_input = input;
618
619 return status;
620 }
621
622 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
623 u8 pin_type, u8 input)
624 {
625 int status = 0;
626 u32 value = 0;
627
628 if (pin_type != dev->video_input) {
629 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
630 if (status < 0) {
631 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
632 "AFE input mux - errCode [%d]!\n",
633 __func__, status);
634 return status;
635 }
636 }
637
638 /* call afe block to set video inputs */
639 status = cx231xx_afe_set_input_mux(dev, input);
640 if (status < 0) {
641 cx231xx_errdev("%s: set_input_mux :Failed to set"
642 " AFE input mux - errCode [%d]!\n",
643 __func__, status);
644 return status;
645 }
646
647 switch (pin_type) {
648 case CX231XX_VMUX_COMPOSITE1:
649 status = vid_blk_read_word(dev, AFE_CTRL, &value);
650 value |= (0 << 13) | (1 << 4);
651 value &= ~(1 << 5);
652
653 /* set [24:23] [22:15] to 0 */
654 value &= (~(0x1ff8000));
655 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
656 value |= 0x1000000;
657 status = vid_blk_write_word(dev, AFE_CTRL, value);
658
659 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
660 value |= (1 << 7);
661 status = vid_blk_write_word(dev, OUT_CTRL1, value);
662
663 /* Set output mode */
664 status = cx231xx_read_modify_write_i2c_dword(dev,
665 VID_BLK_I2C_ADDRESS,
666 OUT_CTRL1,
667 FLD_OUT_MODE,
668 dev->board.output_mode);
669
670 /* Tell DIF object to go to baseband mode */
671 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
672 if (status < 0) {
673 cx231xx_errdev("%s: cx231xx_dif set to By pass"
674 " mode- errCode [%d]!\n",
675 __func__, status);
676 return status;
677 }
678
679 /* Read the DFE_CTRL1 register */
680 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
681
682 /* enable the VBI_GATE_EN */
683 value |= FLD_VBI_GATE_EN;
684
685 /* Enable the auto-VGA enable */
686 value |= FLD_VGA_AUTO_EN;
687
688 /* Write it back */
689 status = vid_blk_write_word(dev, DFE_CTRL1, value);
690
691 /* Disable auto config of registers */
692 status = cx231xx_read_modify_write_i2c_dword(dev,
693 VID_BLK_I2C_ADDRESS,
694 MODE_CTRL, FLD_ACFG_DIS,
695 cx231xx_set_field(FLD_ACFG_DIS, 1));
696
697 /* Set CVBS input mode */
698 status = cx231xx_read_modify_write_i2c_dword(dev,
699 VID_BLK_I2C_ADDRESS,
700 MODE_CTRL, FLD_INPUT_MODE,
701 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
702 break;
703 case CX231XX_VMUX_SVIDEO:
704 /* Disable the use of DIF */
705
706 status = vid_blk_read_word(dev, AFE_CTRL, &value);
707
708 /* set [24:23] [22:15] to 0 */
709 value &= (~(0x1ff8000));
710 /* set FUNC_MODE[24:23] = 2
711 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
712 value |= 0x1000010;
713 status = vid_blk_write_word(dev, AFE_CTRL, value);
714
715 /* Tell DIF object to go to baseband mode */
716 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
717 if (status < 0) {
718 cx231xx_errdev("%s: cx231xx_dif set to By pass"
719 " mode- errCode [%d]!\n",
720 __func__, status);
721 return status;
722 }
723
724 /* Read the DFE_CTRL1 register */
725 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
726
727 /* enable the VBI_GATE_EN */
728 value |= FLD_VBI_GATE_EN;
729
730 /* Enable the auto-VGA enable */
731 value |= FLD_VGA_AUTO_EN;
732
733 /* Write it back */
734 status = vid_blk_write_word(dev, DFE_CTRL1, value);
735
736 /* Disable auto config of registers */
737 status = cx231xx_read_modify_write_i2c_dword(dev,
738 VID_BLK_I2C_ADDRESS,
739 MODE_CTRL, FLD_ACFG_DIS,
740 cx231xx_set_field(FLD_ACFG_DIS, 1));
741
742 /* Set YC input mode */
743 status = cx231xx_read_modify_write_i2c_dword(dev,
744 VID_BLK_I2C_ADDRESS,
745 MODE_CTRL,
746 FLD_INPUT_MODE,
747 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
748
749 /* Chroma to ADC2 */
750 status = vid_blk_read_word(dev, AFE_CTRL, &value);
751 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
752
753 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
754 This sets them to use video
755 rather than audio. Only one of the two will be in use. */
756 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
757
758 status = vid_blk_write_word(dev, AFE_CTRL, value);
759
760 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
761 break;
762 case CX231XX_VMUX_TELEVISION:
763 case CX231XX_VMUX_CABLE:
764 default:
765 /* TODO: Test if this is also needed for xc2028/xc3028 */
766 if (dev->board.tuner_type == TUNER_XC5000) {
767 /* Disable the use of DIF */
768
769 status = vid_blk_read_word(dev, AFE_CTRL, &value);
770 value |= (0 << 13) | (1 << 4);
771 value &= ~(1 << 5);
772
773 /* set [24:23] [22:15] to 0 */
774 value &= (~(0x1FF8000));
775 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
776 value |= 0x1000000;
777 status = vid_blk_write_word(dev, AFE_CTRL, value);
778
779 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
780 value |= (1 << 7);
781 status = vid_blk_write_word(dev, OUT_CTRL1, value);
782
783 /* Set output mode */
784 status = cx231xx_read_modify_write_i2c_dword(dev,
785 VID_BLK_I2C_ADDRESS,
786 OUT_CTRL1, FLD_OUT_MODE,
787 dev->board.output_mode);
788
789 /* Tell DIF object to go to baseband mode */
790 status = cx231xx_dif_set_standard(dev,
791 DIF_USE_BASEBAND);
792 if (status < 0) {
793 cx231xx_errdev("%s: cx231xx_dif set to By pass"
794 " mode- errCode [%d]!\n",
795 __func__, status);
796 return status;
797 }
798
799 /* Read the DFE_CTRL1 register */
800 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
801
802 /* enable the VBI_GATE_EN */
803 value |= FLD_VBI_GATE_EN;
804
805 /* Enable the auto-VGA enable */
806 value |= FLD_VGA_AUTO_EN;
807
808 /* Write it back */
809 status = vid_blk_write_word(dev, DFE_CTRL1, value);
810
811 /* Disable auto config of registers */
812 status = cx231xx_read_modify_write_i2c_dword(dev,
813 VID_BLK_I2C_ADDRESS,
814 MODE_CTRL, FLD_ACFG_DIS,
815 cx231xx_set_field(FLD_ACFG_DIS, 1));
816
817 /* Set CVBS input mode */
818 status = cx231xx_read_modify_write_i2c_dword(dev,
819 VID_BLK_I2C_ADDRESS,
820 MODE_CTRL, FLD_INPUT_MODE,
821 cx231xx_set_field(FLD_INPUT_MODE,
822 INPUT_MODE_CVBS_0));
823 } else {
824 /* Enable the DIF for the tuner */
825
826 /* Reinitialize the DIF */
827 status = cx231xx_dif_set_standard(dev, dev->norm);
828 if (status < 0) {
829 cx231xx_errdev("%s: cx231xx_dif set to By pass"
830 " mode- errCode [%d]!\n",
831 __func__, status);
832 return status;
833 }
834
835 /* Make sure bypass is cleared */
836 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
837
838 /* Clear the bypass bit */
839 value &= ~FLD_DIF_DIF_BYPASS;
840
841 /* Enable the use of the DIF block */
842 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
843
844 /* Read the DFE_CTRL1 register */
845 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
846
847 /* Disable the VBI_GATE_EN */
848 value &= ~FLD_VBI_GATE_EN;
849
850 /* Enable the auto-VGA enable, AGC, and
851 set the skip count to 2 */
852 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
853
854 /* Write it back */
855 status = vid_blk_write_word(dev, DFE_CTRL1, value);
856
857 /* Wait until AGC locks up */
858 msleep(1);
859
860 /* Disable the auto-VGA enable AGC */
861 value &= ~(FLD_VGA_AUTO_EN);
862
863 /* Write it back */
864 status = vid_blk_write_word(dev, DFE_CTRL1, value);
865
866 /* Enable Polaris B0 AGC output */
867 status = vid_blk_read_word(dev, PIN_CTRL, &value);
868 value |= (FLD_OEF_AGC_RF) |
869 (FLD_OEF_AGC_IFVGA) |
870 (FLD_OEF_AGC_IF);
871 status = vid_blk_write_word(dev, PIN_CTRL, value);
872
873 /* Set output mode */
874 status = cx231xx_read_modify_write_i2c_dword(dev,
875 VID_BLK_I2C_ADDRESS,
876 OUT_CTRL1, FLD_OUT_MODE,
877 dev->board.output_mode);
878
879 /* Disable auto config of registers */
880 status = cx231xx_read_modify_write_i2c_dword(dev,
881 VID_BLK_I2C_ADDRESS,
882 MODE_CTRL, FLD_ACFG_DIS,
883 cx231xx_set_field(FLD_ACFG_DIS, 1));
884
885 /* Set CVBS input mode */
886 status = cx231xx_read_modify_write_i2c_dword(dev,
887 VID_BLK_I2C_ADDRESS,
888 MODE_CTRL, FLD_INPUT_MODE,
889 cx231xx_set_field(FLD_INPUT_MODE,
890 INPUT_MODE_CVBS_0));
891
892 /* Set some bits in AFE_CTRL so that channel 2 or 3
893 * is ready to receive audio */
894 /* Clear clamp for channels 2 and 3 (bit 16-17) */
895 /* Clear droop comp (bit 19-20) */
896 /* Set VGA_SEL (for audio control) (bit 7-8) */
897 status = vid_blk_read_word(dev, AFE_CTRL, &value);
898
899 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
900 value &= (~(FLD_FUNC_MODE));
901 value |= 0x800000;
902
903 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
904
905 status = vid_blk_write_word(dev, AFE_CTRL, value);
906
907 if (dev->tuner_type == TUNER_NXP_TDA18271) {
908 status = vid_blk_read_word(dev, PIN_CTRL,
909 &value);
910 status = vid_blk_write_word(dev, PIN_CTRL,
911 (value & 0xFFFFFFEF));
912 }
913
914 break;
915
916 }
917 break;
918 }
919
920 /* Set raw VBI mode */
921 status = cx231xx_read_modify_write_i2c_dword(dev,
922 VID_BLK_I2C_ADDRESS,
923 OUT_CTRL1, FLD_VBIHACTRAW_EN,
924 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
925
926 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
927 if (value & 0x02) {
928 value |= (1 << 19);
929 status = vid_blk_write_word(dev, OUT_CTRL1, value);
930 }
931
932 return status;
933 }
934
935 void cx231xx_enable656(struct cx231xx *dev)
936 {
937 u8 temp = 0;
938 /*enable TS1 data[0:7] as output to export 656*/
939
940 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
941
942 /*enable TS1 clock as output to export 656*/
943
944 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
945 temp = temp|0x04;
946
947 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
948 }
949 EXPORT_SYMBOL_GPL(cx231xx_enable656);
950
951 void cx231xx_disable656(struct cx231xx *dev)
952 {
953 u8 temp = 0;
954
955 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
956
957 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
958 temp = temp&0xFB;
959
960 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
961 }
962 EXPORT_SYMBOL_GPL(cx231xx_disable656);
963
964 /*
965 * Handle any video-mode specific overrides that are different
966 * on a per video standards basis after touching the MODE_CTRL
967 * register which resets many values for autodetect
968 */
969 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
970 {
971 int status = 0;
972
973 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
974 (unsigned int)dev->norm);
975
976 /* Change the DFE_CTRL3 bp_percent to fix flagging */
977 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
978
979 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
980 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
981
982 /* Move the close caption lines out of active video,
983 adjust the active video start point */
984 status = cx231xx_read_modify_write_i2c_dword(dev,
985 VID_BLK_I2C_ADDRESS,
986 VERT_TIM_CTRL,
987 FLD_VBLANK_CNT, 0x18);
988 status = cx231xx_read_modify_write_i2c_dword(dev,
989 VID_BLK_I2C_ADDRESS,
990 VERT_TIM_CTRL,
991 FLD_VACTIVE_CNT,
992 0x1E7000);
993 status = cx231xx_read_modify_write_i2c_dword(dev,
994 VID_BLK_I2C_ADDRESS,
995 VERT_TIM_CTRL,
996 FLD_V656BLANK_CNT,
997 0x1C000000);
998
999 status = cx231xx_read_modify_write_i2c_dword(dev,
1000 VID_BLK_I2C_ADDRESS,
1001 HORIZ_TIM_CTRL,
1002 FLD_HBLANK_CNT,
1003 cx231xx_set_field
1004 (FLD_HBLANK_CNT, 0x79));
1005
1006 } else if (dev->norm & V4L2_STD_SECAM) {
1007 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1008 status = cx231xx_read_modify_write_i2c_dword(dev,
1009 VID_BLK_I2C_ADDRESS,
1010 VERT_TIM_CTRL,
1011 FLD_VBLANK_CNT, 0x20);
1012 status = cx231xx_read_modify_write_i2c_dword(dev,
1013 VID_BLK_I2C_ADDRESS,
1014 VERT_TIM_CTRL,
1015 FLD_VACTIVE_CNT,
1016 cx231xx_set_field
1017 (FLD_VACTIVE_CNT,
1018 0x244));
1019 status = cx231xx_read_modify_write_i2c_dword(dev,
1020 VID_BLK_I2C_ADDRESS,
1021 VERT_TIM_CTRL,
1022 FLD_V656BLANK_CNT,
1023 cx231xx_set_field
1024 (FLD_V656BLANK_CNT,
1025 0x24));
1026 /* Adjust the active video horizontal start point */
1027 status = cx231xx_read_modify_write_i2c_dword(dev,
1028 VID_BLK_I2C_ADDRESS,
1029 HORIZ_TIM_CTRL,
1030 FLD_HBLANK_CNT,
1031 cx231xx_set_field
1032 (FLD_HBLANK_CNT, 0x85));
1033 } else {
1034 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1035 status = cx231xx_read_modify_write_i2c_dword(dev,
1036 VID_BLK_I2C_ADDRESS,
1037 VERT_TIM_CTRL,
1038 FLD_VBLANK_CNT, 0x20);
1039 status = cx231xx_read_modify_write_i2c_dword(dev,
1040 VID_BLK_I2C_ADDRESS,
1041 VERT_TIM_CTRL,
1042 FLD_VACTIVE_CNT,
1043 cx231xx_set_field
1044 (FLD_VACTIVE_CNT,
1045 0x244));
1046 status = cx231xx_read_modify_write_i2c_dword(dev,
1047 VID_BLK_I2C_ADDRESS,
1048 VERT_TIM_CTRL,
1049 FLD_V656BLANK_CNT,
1050 cx231xx_set_field
1051 (FLD_V656BLANK_CNT,
1052 0x24));
1053 /* Adjust the active video horizontal start point */
1054 status = cx231xx_read_modify_write_i2c_dword(dev,
1055 VID_BLK_I2C_ADDRESS,
1056 HORIZ_TIM_CTRL,
1057 FLD_HBLANK_CNT,
1058 cx231xx_set_field
1059 (FLD_HBLANK_CNT, 0x85));
1060
1061 }
1062
1063 return status;
1064 }
1065
1066 int cx231xx_unmute_audio(struct cx231xx *dev)
1067 {
1068 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1069 }
1070 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1071
1072 static int stopAudioFirmware(struct cx231xx *dev)
1073 {
1074 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1075 }
1076
1077 static int restartAudioFirmware(struct cx231xx *dev)
1078 {
1079 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1080 }
1081
1082 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1083 {
1084 int status = 0;
1085 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1086
1087 switch (INPUT(input)->amux) {
1088 case CX231XX_AMUX_VIDEO:
1089 ainput = AUDIO_INPUT_TUNER_TV;
1090 break;
1091 case CX231XX_AMUX_LINE_IN:
1092 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1093 ainput = AUDIO_INPUT_LINE;
1094 break;
1095 default:
1096 break;
1097 }
1098
1099 status = cx231xx_set_audio_decoder_input(dev, ainput);
1100
1101 return status;
1102 }
1103
1104 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1105 enum AUDIO_INPUT audio_input)
1106 {
1107 u32 dwval;
1108 int status;
1109 u8 gen_ctrl;
1110 u32 value = 0;
1111
1112 /* Put it in soft reset */
1113 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1114 gen_ctrl |= 1;
1115 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1116
1117 switch (audio_input) {
1118 case AUDIO_INPUT_LINE:
1119 /* setup AUD_IO control from Merlin paralle output */
1120 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1121 AUD_CHAN_SRC_PARALLEL);
1122 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1123
1124 /* setup input to Merlin, SRC2 connect to AC97
1125 bypass upsample-by-2, slave mode, sony mode, left justify
1126 adr 091c, dat 01000000 */
1127 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1128
1129 status = vid_blk_write_word(dev, AC97_CTL,
1130 (dwval | FLD_AC97_UP2X_BYPASS));
1131
1132 /* select the parallel1 and SRC3 */
1133 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1134 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1135 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1136 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1137
1138 /* unmute all, AC97 in, independence mode
1139 adr 08d0, data 0x00063073 */
1140 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1141 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1142
1143 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1144 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1145 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1146 (dwval | FLD_PATH1_AVC_THRESHOLD));
1147
1148 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1149 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1150 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1151 (dwval | FLD_PATH1_SC_THRESHOLD));
1152 break;
1153
1154 case AUDIO_INPUT_TUNER_TV:
1155 default:
1156 status = stopAudioFirmware(dev);
1157 /* Setup SRC sources and clocks */
1158 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1159 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1160 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1161 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1162 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1163 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1164 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1165 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1166 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1167 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1168 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1169 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1170 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1171 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1172
1173 /* Setup the AUD_IO control */
1174 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1175 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1176 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1177 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1178 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1179 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1180
1181 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1182
1183 /* setAudioStandard(_audio_standard); */
1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1185
1186 status = restartAudioFirmware(dev);
1187
1188 switch (dev->board.tuner_type) {
1189 case TUNER_XC5000:
1190 /* SIF passthrough at 28.6363 MHz sample rate */
1191 status = cx231xx_read_modify_write_i2c_dword(dev,
1192 VID_BLK_I2C_ADDRESS,
1193 CHIP_CTRL,
1194 FLD_SIF_EN,
1195 cx231xx_set_field(FLD_SIF_EN, 1));
1196 break;
1197 case TUNER_NXP_TDA18271:
1198 /* Normal mode: SIF passthrough at 14.32 MHz */
1199 status = cx231xx_read_modify_write_i2c_dword(dev,
1200 VID_BLK_I2C_ADDRESS,
1201 CHIP_CTRL,
1202 FLD_SIF_EN,
1203 cx231xx_set_field(FLD_SIF_EN, 0));
1204 break;
1205 default:
1206 /* This is just a casual suggestion to people adding
1207 new boards in case they use a tuner type we don't
1208 currently know about */
1209 printk(KERN_INFO "Unknown tuner type configuring SIF");
1210 break;
1211 }
1212 break;
1213
1214 case AUDIO_INPUT_TUNER_FM:
1215 /* use SIF for FM radio
1216 setupFM();
1217 setAudioStandard(_audio_standard);
1218 */
1219 break;
1220
1221 case AUDIO_INPUT_MUTE:
1222 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1223 break;
1224 }
1225
1226 /* Take it out of soft reset */
1227 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1228 gen_ctrl &= ~1;
1229 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1230
1231 return status;
1232 }
1233
1234 /******************************************************************************
1235 * C H I P Specific C O N T R O L functions *
1236 ******************************************************************************/
1237 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1238 {
1239 u32 value;
1240 int status = 0;
1241
1242 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1243 value |= (~dev->board.ctl_pin_status_mask);
1244 status = vid_blk_write_word(dev, PIN_CTRL, value);
1245
1246 return status;
1247 }
1248
1249 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1250 u8 analog_or_digital)
1251 {
1252 int status = 0;
1253
1254 /* first set the direction to output */
1255 status = cx231xx_set_gpio_direction(dev,
1256 dev->board.
1257 agc_analog_digital_select_gpio, 1);
1258
1259 /* 0 - demod ; 1 - Analog mode */
1260 status = cx231xx_set_gpio_value(dev,
1261 dev->board.agc_analog_digital_select_gpio,
1262 analog_or_digital);
1263
1264 return status;
1265 }
1266
1267 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
1268 {
1269 u8 value[4] = { 0, 0, 0, 0 };
1270 int status = 0;
1271 bool current_is_port_3;
1272
1273 /*
1274 * Should this code check dev->port_3_switch_enabled first
1275 * to skip unnecessary reading of the register?
1276 * If yes, the flag dev->port_3_switch_enabled must be initialized
1277 * correctly.
1278 */
1279
1280 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1281 PWR_CTL_EN, value, 4);
1282 if (status < 0)
1283 return status;
1284
1285 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
1286
1287 /* Just return, if already using the right port */
1288 if (current_is_port_3 == is_port_3)
1289 return 0;
1290
1291 if (is_port_3)
1292 value[0] |= I2C_DEMOD_EN;
1293 else
1294 value[0] &= ~I2C_DEMOD_EN;
1295
1296 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1297 PWR_CTL_EN, value, 4);
1298
1299 /* remember status of the switch for usage in is_tuner */
1300 if (status >= 0)
1301 dev->port_3_switch_enabled = is_port_3;
1302
1303 return status;
1304
1305 }
1306 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
1307
1308 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1309 {
1310 /*
1311 u8 status = 0;
1312 u32 value = 0;
1313
1314 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1315 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1316 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1317
1318 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1319 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1320 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1321 */
1322 }
1323
1324 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1325 {
1326 u32 value = 0;
1327 u16 i = 0;
1328
1329 value = 0x45005390;
1330 vid_blk_write_word(dev, 0x104, value);
1331
1332 for (i = 0x100; i < 0x140; i++) {
1333 vid_blk_read_word(dev, i, &value);
1334 cx231xx_info("reg0x%x=0x%x\n", i, value);
1335 i = i+3;
1336 }
1337
1338 for (i = 0x300; i < 0x400; i++) {
1339 vid_blk_read_word(dev, i, &value);
1340 cx231xx_info("reg0x%x=0x%x\n", i, value);
1341 i = i+3;
1342 }
1343
1344 for (i = 0x400; i < 0x440; i++) {
1345 vid_blk_read_word(dev, i, &value);
1346 cx231xx_info("reg0x%x=0x%x\n", i, value);
1347 i = i+3;
1348 }
1349
1350 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1351 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1352 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1353 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1354 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1355 }
1356
1357 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1358 {
1359 u8 value[4] = { 0, 0, 0, 0 };
1360 cx231xx_info("cx231xx_dump_SC_reg!\n");
1361
1362 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1363 value, 4);
1364 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1365 value[1], value[2], value[3]);
1366 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1367 value, 4);
1368 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1369 value[1], value[2], value[3]);
1370 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1371 value, 4);
1372 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1373 value[1], value[2], value[3]);
1374 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1375 value, 4);
1376 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1377 value[1], value[2], value[3]);
1378
1379 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1380 value, 4);
1381 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1382 value[1], value[2], value[3]);
1383 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1384 value, 4);
1385 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1386 value[1], value[2], value[3]);
1387 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1388 value, 4);
1389 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1390 value[1], value[2], value[3]);
1391 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1392 value, 4);
1393 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1394 value[1], value[2], value[3]);
1395
1396 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1397 value, 4);
1398 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1399 value[1], value[2], value[3]);
1400 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1401 value, 4);
1402 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1403 value[1], value[2], value[3]);
1404 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1405 value, 4);
1406 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1407 value[1], value[2], value[3]);
1408 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1409 value, 4);
1410 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1411 value[1], value[2], value[3]);
1412
1413 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1414 value, 4);
1415 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1416 value[1], value[2], value[3]);
1417 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1418 value, 4);
1419 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1420 value[1], value[2], value[3]);
1421 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1422 value, 4);
1423 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1424 value[1], value[2], value[3]);
1425 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1426 value, 4);
1427 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1428 value[1], value[2], value[3]);
1429
1430 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1431 value, 4);
1432 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1433 value[1], value[2], value[3]);
1434 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1435 value, 4);
1436 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1437 value[1], value[2], value[3]);
1438
1439
1440 }
1441
1442 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1443
1444 {
1445 u8 value = 0;
1446
1447 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1448 value = (value & 0xFE)|0x01;
1449 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1450
1451 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1452 value = (value & 0xFE)|0x00;
1453 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1454
1455
1456 /*
1457 config colibri to lo-if mode
1458
1459 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1460 the diff IF input by half,
1461
1462 for low-if agc defect
1463 */
1464
1465 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1466 value = (value & 0xFC)|0x00;
1467 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1468
1469 afe_read_byte(dev, ADC_INPUT_CH3, &value);
1470 value = (value & 0xF9)|0x02;
1471 afe_write_byte(dev, ADC_INPUT_CH3, value);
1472
1473 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1474 value = (value & 0xFB)|0x04;
1475 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1476
1477 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1478 value = (value & 0xFC)|0x03;
1479 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1480
1481 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1482 value = (value & 0xFB)|0x04;
1483 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1484
1485 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1486 value = (value & 0xF8)|0x06;
1487 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1488
1489 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1490 value = (value & 0x8F)|0x40;
1491 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1492
1493 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1494 value = (value & 0xDF)|0x20;
1495 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1496 }
1497
1498 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1499 u8 spectral_invert, u32 mode)
1500 {
1501 u32 colibri_carrier_offset = 0;
1502 u32 func_mode = 0x01; /* Device has a DIF if this function is called */
1503 u32 standard = 0;
1504 u8 value[4] = { 0, 0, 0, 0 };
1505
1506 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1507 value[0] = (u8) 0x6F;
1508 value[1] = (u8) 0x6F;
1509 value[2] = (u8) 0x6F;
1510 value[3] = (u8) 0x6F;
1511 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1512 PWR_CTL_EN, value, 4);
1513
1514 /*Set colibri for low IF*/
1515 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1516
1517 /* Set C2HH for low IF operation.*/
1518 standard = dev->norm;
1519 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1520 func_mode, standard);
1521
1522 /* Get colibri offsets.*/
1523 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1524 standard);
1525
1526 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1527 colibri_carrier_offset, standard);
1528
1529 /* Set the band Pass filter for DIF*/
1530 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1531 spectral_invert, mode);
1532 }
1533
1534 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1535 {
1536 u32 colibri_carrier_offset = 0;
1537
1538 if (mode == TUNER_MODE_FM_RADIO) {
1539 colibri_carrier_offset = 1100000;
1540 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
1541 colibri_carrier_offset = 4832000; /*4.83MHz */
1542 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1543 colibri_carrier_offset = 2700000; /*2.70MHz */
1544 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1545 | V4L2_STD_SECAM)) {
1546 colibri_carrier_offset = 2100000; /*2.10MHz */
1547 }
1548
1549 return colibri_carrier_offset;
1550 }
1551
1552 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1553 u8 spectral_invert, u32 mode)
1554 {
1555 unsigned long pll_freq_word;
1556 u32 dif_misc_ctrl_value = 0;
1557 u64 pll_freq_u64 = 0;
1558 u32 i = 0;
1559
1560 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1561 if_freq, spectral_invert, mode);
1562
1563
1564 if (mode == TUNER_MODE_FM_RADIO) {
1565 pll_freq_word = 0x905A1CAC;
1566 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1567
1568 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1569 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1570 pll_freq_word = if_freq;
1571 pll_freq_u64 = (u64)pll_freq_word << 28L;
1572 do_div(pll_freq_u64, 50000000);
1573 pll_freq_word = (u32)pll_freq_u64;
1574 /*pll_freq_word = 0x3463497;*/
1575 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1576
1577 if (spectral_invert) {
1578 if_freq -= 400000;
1579 /* Enable Spectral Invert*/
1580 vid_blk_read_word(dev, DIF_MISC_CTRL,
1581 &dif_misc_ctrl_value);
1582 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1583 vid_blk_write_word(dev, DIF_MISC_CTRL,
1584 dif_misc_ctrl_value);
1585 } else {
1586 if_freq += 400000;
1587 /* Disable Spectral Invert*/
1588 vid_blk_read_word(dev, DIF_MISC_CTRL,
1589 &dif_misc_ctrl_value);
1590 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1591 vid_blk_write_word(dev, DIF_MISC_CTRL,
1592 dif_misc_ctrl_value);
1593 }
1594
1595 if_freq = (if_freq/100000)*100000;
1596
1597 if (if_freq < 3000000)
1598 if_freq = 3000000;
1599
1600 if (if_freq > 16000000)
1601 if_freq = 16000000;
1602 }
1603
1604 cx231xx_info("Enter IF=%zu\n",
1605 ARRAY_SIZE(Dif_set_array));
1606 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) {
1607 if (Dif_set_array[i].if_freq == if_freq) {
1608 vid_blk_write_word(dev,
1609 Dif_set_array[i].register_address, Dif_set_array[i].value);
1610 }
1611 }
1612 }
1613
1614 /******************************************************************************
1615 * D I F - B L O C K C O N T R O L functions *
1616 ******************************************************************************/
1617 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1618 u32 function_mode, u32 standard)
1619 {
1620 int status = 0;
1621
1622
1623 if (mode == V4L2_TUNER_RADIO) {
1624 /* C2HH */
1625 /* lo if big signal */
1626 status = cx231xx_reg_mask_write(dev,
1627 VID_BLK_I2C_ADDRESS, 32,
1628 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1629 /* FUNC_MODE = DIF */
1630 status = cx231xx_reg_mask_write(dev,
1631 VID_BLK_I2C_ADDRESS, 32,
1632 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1633 /* IF_MODE */
1634 status = cx231xx_reg_mask_write(dev,
1635 VID_BLK_I2C_ADDRESS, 32,
1636 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1637 /* no inv */
1638 status = cx231xx_reg_mask_write(dev,
1639 VID_BLK_I2C_ADDRESS, 32,
1640 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1641 } else if (standard != DIF_USE_BASEBAND) {
1642 if (standard & V4L2_STD_MN) {
1643 /* lo if big signal */
1644 status = cx231xx_reg_mask_write(dev,
1645 VID_BLK_I2C_ADDRESS, 32,
1646 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1647 /* FUNC_MODE = DIF */
1648 status = cx231xx_reg_mask_write(dev,
1649 VID_BLK_I2C_ADDRESS, 32,
1650 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1651 function_mode);
1652 /* IF_MODE */
1653 status = cx231xx_reg_mask_write(dev,
1654 VID_BLK_I2C_ADDRESS, 32,
1655 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1656 /* no inv */
1657 status = cx231xx_reg_mask_write(dev,
1658 VID_BLK_I2C_ADDRESS, 32,
1659 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1660 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1661 status = cx231xx_reg_mask_write(dev,
1662 VID_BLK_I2C_ADDRESS, 32,
1663 AUD_IO_CTRL, 0, 31, 0x00000003);
1664 } else if ((standard == V4L2_STD_PAL_I) |
1665 (standard & V4L2_STD_PAL_D) |
1666 (standard & V4L2_STD_SECAM)) {
1667 /* C2HH setup */
1668 /* lo if big signal */
1669 status = cx231xx_reg_mask_write(dev,
1670 VID_BLK_I2C_ADDRESS, 32,
1671 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1672 /* FUNC_MODE = DIF */
1673 status = cx231xx_reg_mask_write(dev,
1674 VID_BLK_I2C_ADDRESS, 32,
1675 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1676 function_mode);
1677 /* IF_MODE */
1678 status = cx231xx_reg_mask_write(dev,
1679 VID_BLK_I2C_ADDRESS, 32,
1680 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1681 /* no inv */
1682 status = cx231xx_reg_mask_write(dev,
1683 VID_BLK_I2C_ADDRESS, 32,
1684 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1685 } else {
1686 /* default PAL BG */
1687 /* C2HH setup */
1688 /* lo if big signal */
1689 status = cx231xx_reg_mask_write(dev,
1690 VID_BLK_I2C_ADDRESS, 32,
1691 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1692 /* FUNC_MODE = DIF */
1693 status = cx231xx_reg_mask_write(dev,
1694 VID_BLK_I2C_ADDRESS, 32,
1695 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1696 function_mode);
1697 /* IF_MODE */
1698 status = cx231xx_reg_mask_write(dev,
1699 VID_BLK_I2C_ADDRESS, 32,
1700 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1701 /* no inv */
1702 status = cx231xx_reg_mask_write(dev,
1703 VID_BLK_I2C_ADDRESS, 32,
1704 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1705 }
1706 }
1707
1708 return status;
1709 }
1710
1711 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1712 {
1713 int status = 0;
1714 u32 dif_misc_ctrl_value = 0;
1715 u32 func_mode = 0;
1716
1717 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1718
1719 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1720 if (standard != DIF_USE_BASEBAND)
1721 dev->norm = standard;
1722
1723 switch (dev->model) {
1724 case CX231XX_BOARD_CNXT_CARRAERA:
1725 case CX231XX_BOARD_CNXT_RDE_250:
1726 case CX231XX_BOARD_CNXT_SHELBY:
1727 case CX231XX_BOARD_CNXT_RDU_250:
1728 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1729 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1730 case CX231XX_BOARD_OTG102:
1731 func_mode = 0x03;
1732 break;
1733 case CX231XX_BOARD_CNXT_RDE_253S:
1734 case CX231XX_BOARD_CNXT_RDU_253S:
1735 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
1736 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
1737 func_mode = 0x01;
1738 break;
1739 default:
1740 func_mode = 0x01;
1741 }
1742
1743 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1744 func_mode, standard);
1745
1746 if (standard == DIF_USE_BASEBAND) { /* base band */
1747 /* There is a different SRC_PHASE_INC value
1748 for baseband vs. DIF */
1749 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1750 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1751 &dif_misc_ctrl_value);
1752 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1753 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1754 dif_misc_ctrl_value);
1755 } else if (standard & V4L2_STD_PAL_D) {
1756 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1757 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1758 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1759 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1760 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1761 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1762 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1763 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1764 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1765 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1766 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1767 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1768 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1769 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1770 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1771 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1772 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1773 DIF_AGC_IF_INT_CURRENT, 0, 31,
1774 0x26001700);
1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 DIF_AGC_RF_CURRENT, 0, 31,
1777 0x00002660);
1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1779 DIF_VIDEO_AGC_CTRL, 0, 31,
1780 0x72500800);
1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 DIF_VID_AUD_OVERRIDE, 0, 31,
1783 0x27000100);
1784 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1785 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1787 DIF_COMP_FLT_CTRL, 0, 31,
1788 0x00000000);
1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1790 DIF_SRC_PHASE_INC, 0, 31,
1791 0x1befbf06);
1792 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1793 DIF_SRC_GAIN_CONTROL, 0, 31,
1794 0x000035e8);
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1797 /* Save the Spec Inversion value */
1798 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1799 dif_misc_ctrl_value |= 0x3a023F11;
1800 } else if (standard & V4L2_STD_PAL_I) {
1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1804 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1805 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1806 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1808 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1810 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1811 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1812 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1813 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1814 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1816 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1817 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1818 DIF_AGC_IF_INT_CURRENT, 0, 31,
1819 0x26001700);
1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821 DIF_AGC_RF_CURRENT, 0, 31,
1822 0x00002660);
1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1824 DIF_VIDEO_AGC_CTRL, 0, 31,
1825 0x72500800);
1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827 DIF_VID_AUD_OVERRIDE, 0, 31,
1828 0x27000100);
1829 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1830 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1832 DIF_COMP_FLT_CTRL, 0, 31,
1833 0x00000000);
1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1835 DIF_SRC_PHASE_INC, 0, 31,
1836 0x1befbf06);
1837 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1838 DIF_SRC_GAIN_CONTROL, 0, 31,
1839 0x000035e8);
1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1842 /* Save the Spec Inversion value */
1843 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1844 dif_misc_ctrl_value |= 0x3a033F11;
1845 } else if (standard & V4L2_STD_PAL_M) {
1846 /* improved Low Frequency Phase Noise */
1847 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1848 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1849 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1850 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1851 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1852 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1853 0x26001700);
1854 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1855 0x00002660);
1856 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1857 0x72500800);
1858 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1859 0x27000100);
1860 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1861 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1862 0x009f50c1);
1863 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1864 0x1befbf06);
1865 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1866 0x000035e8);
1867 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1868 0x00000000);
1869 /* Save the Spec Inversion value */
1870 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1871 dif_misc_ctrl_value |= 0x3A0A3F10;
1872 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1873 /* improved Low Frequency Phase Noise */
1874 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1875 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1876 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1877 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1878 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1879 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1880 0x26001700);
1881 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1882 0x00002660);
1883 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1884 0x72500800);
1885 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1886 0x27000100);
1887 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1888 0x012c405d);
1889 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1890 0x009f50c1);
1891 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1892 0x1befbf06);
1893 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1894 0x000035e8);
1895 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1896 0x00000000);
1897 /* Save the Spec Inversion value */
1898 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1899 dif_misc_ctrl_value = 0x3A093F10;
1900 } else if (standard &
1901 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1902 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1903
1904 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1905 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1906 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1907 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1908 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1909 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1910 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1911 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1912 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1913 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1914 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1915 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1916 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1917 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1918 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1919 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1920 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1921 DIF_AGC_IF_INT_CURRENT, 0, 31,
1922 0x26001700);
1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924 DIF_AGC_RF_CURRENT, 0, 31,
1925 0x00002660);
1926 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1927 DIF_VID_AUD_OVERRIDE, 0, 31,
1928 0x27000100);
1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1932 DIF_COMP_FLT_CTRL, 0, 31,
1933 0x00000000);
1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1935 DIF_SRC_PHASE_INC, 0, 31,
1936 0x1befbf06);
1937 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1938 DIF_SRC_GAIN_CONTROL, 0, 31,
1939 0x000035e8);
1940 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1942 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1943 DIF_VIDEO_AGC_CTRL, 0, 31,
1944 0xf4000000);
1945
1946 /* Save the Spec Inversion value */
1947 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1948 dif_misc_ctrl_value |= 0x3a023F11;
1949 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1950 /* Is it SECAM_L1? */
1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1954 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1955 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1956 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1958 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1959 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1960 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1961 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1962 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1964 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1965 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1966 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1967 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1968 DIF_AGC_IF_INT_CURRENT, 0, 31,
1969 0x26001700);
1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971 DIF_AGC_RF_CURRENT, 0, 31,
1972 0x00002660);
1973 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1974 DIF_VID_AUD_OVERRIDE, 0, 31,
1975 0x27000100);
1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1979 DIF_COMP_FLT_CTRL, 0, 31,
1980 0x00000000);
1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1982 DIF_SRC_PHASE_INC, 0, 31,
1983 0x1befbf06);
1984 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1985 DIF_SRC_GAIN_CONTROL, 0, 31,
1986 0x000035e8);
1987 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1989 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1990 DIF_VIDEO_AGC_CTRL, 0, 31,
1991 0xf2560000);
1992
1993 /* Save the Spec Inversion value */
1994 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1995 dif_misc_ctrl_value |= 0x3a023F11;
1996
1997 } else if (standard & V4L2_STD_NTSC_M) {
1998 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1999 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
2000
2001 /* For NTSC the centre frequency of video coming out of
2002 sidewinder is around 7.1MHz or 3.6MHz depending on the
2003 spectral inversion. so for a non spectrally inverted channel
2004 the pll freq word is 0x03420c49
2005 */
2006
2007 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2008 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2009 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2010 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2011 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2012 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2013 0x26001700);
2014 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2015 0x00002660);
2016 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2017 0x04000800);
2018 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2019 0x27000100);
2020 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2021
2022 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2023 0x009f50c1);
2024 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2025 0x1befbf06);
2026 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2027 0x000035e8);
2028
2029 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2030 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2031 0xC2262600);
2032 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2033
2034 /* Save the Spec Inversion value */
2035 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2036 dif_misc_ctrl_value |= 0x3a003F10;
2037 } else {
2038 /* default PAL BG */
2039 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2040 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2041 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2042 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2043 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2044 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2045 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2046 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2047 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2048 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2049 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2050 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2051 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2052 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2053 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2054 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2055 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2056 DIF_AGC_IF_INT_CURRENT, 0, 31,
2057 0x26001700);
2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059 DIF_AGC_RF_CURRENT, 0, 31,
2060 0x00002660);
2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2062 DIF_VIDEO_AGC_CTRL, 0, 31,
2063 0x72500800);
2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065 DIF_VID_AUD_OVERRIDE, 0, 31,
2066 0x27000100);
2067 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2068 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2070 DIF_COMP_FLT_CTRL, 0, 31,
2071 0x00A653A8);
2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2073 DIF_SRC_PHASE_INC, 0, 31,
2074 0x1befbf06);
2075 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2076 DIF_SRC_GAIN_CONTROL, 0, 31,
2077 0x000035e8);
2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2080 /* Save the Spec Inversion value */
2081 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2082 dif_misc_ctrl_value |= 0x3a013F11;
2083 }
2084
2085 /* The AGC values should be the same for all standards,
2086 AUD_SRC_SEL[19] should always be disabled */
2087 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2088
2089 /* It is still possible to get Set Standard calls even when we
2090 are in FM mode.
2091 This is done to override the value for FM. */
2092 if (dev->active_mode == V4L2_TUNER_RADIO)
2093 dif_misc_ctrl_value = 0x7a080000;
2094
2095 /* Write the calculated value for misc ontrol register */
2096 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2097
2098 return status;
2099 }
2100
2101 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2102 {
2103 int status = 0;
2104 u32 dwval;
2105
2106 /* Set the RF and IF k_agc values to 3 */
2107 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2108 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2109 dwval |= 0x33000000;
2110
2111 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2112
2113 return status;
2114 }
2115
2116 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2117 {
2118 int status = 0;
2119 u32 dwval;
2120 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2121 dev->tuner_type);
2122 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2123 * SECAM L/B/D standards */
2124 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2125 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2126
2127 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2128 V4L2_STD_SECAM_D)) {
2129 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2130 dwval &= ~FLD_DIF_IF_REF;
2131 dwval |= 0x88000300;
2132 } else
2133 dwval |= 0x88000000;
2134 } else {
2135 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2136 dwval &= ~FLD_DIF_IF_REF;
2137 dwval |= 0xCC000300;
2138 } else
2139 dwval |= 0x44000000;
2140 }
2141
2142 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2143
2144 return status == sizeof(dwval) ? 0 : -EIO;
2145 }
2146
2147 /******************************************************************************
2148 * I 2 S - B L O C K C O N T R O L functions *
2149 ******************************************************************************/
2150 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2151 {
2152 int status = 0;
2153 u32 value;
2154
2155 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2156 CH_PWR_CTRL1, 1, &value, 1);
2157 /* enables clock to delta-sigma and decimation filter */
2158 value |= 0x80;
2159 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2160 CH_PWR_CTRL1, 1, value, 1);
2161 /* power up all channel */
2162 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2163 CH_PWR_CTRL2, 1, 0x00, 1);
2164
2165 return status;
2166 }
2167
2168 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2169 enum AV_MODE avmode)
2170 {
2171 int status = 0;
2172 u32 value = 0;
2173
2174 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2175 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2176 CH_PWR_CTRL2, 1, &value, 1);
2177 value |= 0xfe;
2178 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2179 CH_PWR_CTRL2, 1, value, 1);
2180 } else {
2181 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2182 CH_PWR_CTRL2, 1, 0x00, 1);
2183 }
2184
2185 return status;
2186 }
2187
2188 /* set i2s_blk for audio input types */
2189 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2190 {
2191 int status = 0;
2192
2193 switch (audio_input) {
2194 case CX231XX_AMUX_LINE_IN:
2195 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2196 CH_PWR_CTRL2, 1, 0x00, 1);
2197 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2198 CH_PWR_CTRL1, 1, 0x80, 1);
2199 break;
2200 case CX231XX_AMUX_VIDEO:
2201 default:
2202 break;
2203 }
2204
2205 dev->ctl_ainput = audio_input;
2206
2207 return status;
2208 }
2209
2210 /******************************************************************************
2211 * P O W E R C O N T R O L functions *
2212 ******************************************************************************/
2213 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2214 {
2215 u8 value[4] = { 0, 0, 0, 0 };
2216 u32 tmp = 0;
2217 int status = 0;
2218
2219 if (dev->power_mode != mode)
2220 dev->power_mode = mode;
2221 else {
2222 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2223 mode);
2224 return 0;
2225 }
2226
2227 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2228 4);
2229 if (status < 0)
2230 return status;
2231
2232 tmp = le32_to_cpu(*((__le32 *) value));
2233
2234 switch (mode) {
2235 case POLARIS_AVMODE_ENXTERNAL_AV:
2236
2237 tmp &= (~PWR_MODE_MASK);
2238
2239 tmp |= PWR_AV_EN;
2240 value[0] = (u8) tmp;
2241 value[1] = (u8) (tmp >> 8);
2242 value[2] = (u8) (tmp >> 16);
2243 value[3] = (u8) (tmp >> 24);
2244 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2245 PWR_CTL_EN, value, 4);
2246 msleep(PWR_SLEEP_INTERVAL);
2247
2248 tmp |= PWR_ISO_EN;
2249 value[0] = (u8) tmp;
2250 value[1] = (u8) (tmp >> 8);
2251 value[2] = (u8) (tmp >> 16);
2252 value[3] = (u8) (tmp >> 24);
2253 status =
2254 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2255 value, 4);
2256 msleep(PWR_SLEEP_INTERVAL);
2257
2258 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2259 value[0] = (u8) tmp;
2260 value[1] = (u8) (tmp >> 8);
2261 value[2] = (u8) (tmp >> 16);
2262 value[3] = (u8) (tmp >> 24);
2263 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2264 PWR_CTL_EN, value, 4);
2265
2266 /* reset state of xceive tuner */
2267 dev->xc_fw_load_done = 0;
2268 break;
2269
2270 case POLARIS_AVMODE_ANALOGT_TV:
2271
2272 tmp |= PWR_DEMOD_EN;
2273 value[0] = (u8) tmp;
2274 value[1] = (u8) (tmp >> 8);
2275 value[2] = (u8) (tmp >> 16);
2276 value[3] = (u8) (tmp >> 24);
2277 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2278 PWR_CTL_EN, value, 4);
2279 msleep(PWR_SLEEP_INTERVAL);
2280
2281 if (!(tmp & PWR_TUNER_EN)) {
2282 tmp |= (PWR_TUNER_EN);
2283 value[0] = (u8) tmp;
2284 value[1] = (u8) (tmp >> 8);
2285 value[2] = (u8) (tmp >> 16);
2286 value[3] = (u8) (tmp >> 24);
2287 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2288 PWR_CTL_EN, value, 4);
2289 msleep(PWR_SLEEP_INTERVAL);
2290 }
2291
2292 if (!(tmp & PWR_AV_EN)) {
2293 tmp |= PWR_AV_EN;
2294 value[0] = (u8) tmp;
2295 value[1] = (u8) (tmp >> 8);
2296 value[2] = (u8) (tmp >> 16);
2297 value[3] = (u8) (tmp >> 24);
2298 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2299 PWR_CTL_EN, value, 4);
2300 msleep(PWR_SLEEP_INTERVAL);
2301 }
2302 if (!(tmp & PWR_ISO_EN)) {
2303 tmp |= PWR_ISO_EN;
2304 value[0] = (u8) tmp;
2305 value[1] = (u8) (tmp >> 8);
2306 value[2] = (u8) (tmp >> 16);
2307 value[3] = (u8) (tmp >> 24);
2308 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2309 PWR_CTL_EN, value, 4);
2310 msleep(PWR_SLEEP_INTERVAL);
2311 }
2312
2313 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2314 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2315 value[0] = (u8) tmp;
2316 value[1] = (u8) (tmp >> 8);
2317 value[2] = (u8) (tmp >> 16);
2318 value[3] = (u8) (tmp >> 24);
2319 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2320 PWR_CTL_EN, value, 4);
2321 msleep(PWR_SLEEP_INTERVAL);
2322 }
2323
2324 if (dev->board.tuner_type != TUNER_ABSENT) {
2325 /* reset the Tuner */
2326 if (dev->board.tuner_gpio)
2327 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2328
2329 if (dev->cx231xx_reset_analog_tuner)
2330 dev->cx231xx_reset_analog_tuner(dev);
2331 }
2332
2333 break;
2334
2335 case POLARIS_AVMODE_DIGITAL:
2336 if (!(tmp & PWR_TUNER_EN)) {
2337 tmp |= (PWR_TUNER_EN);
2338 value[0] = (u8) tmp;
2339 value[1] = (u8) (tmp >> 8);
2340 value[2] = (u8) (tmp >> 16);
2341 value[3] = (u8) (tmp >> 24);
2342 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2343 PWR_CTL_EN, value, 4);
2344 msleep(PWR_SLEEP_INTERVAL);
2345 }
2346 if (!(tmp & PWR_AV_EN)) {
2347 tmp |= PWR_AV_EN;
2348 value[0] = (u8) tmp;
2349 value[1] = (u8) (tmp >> 8);
2350 value[2] = (u8) (tmp >> 16);
2351 value[3] = (u8) (tmp >> 24);
2352 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2353 PWR_CTL_EN, value, 4);
2354 msleep(PWR_SLEEP_INTERVAL);
2355 }
2356 if (!(tmp & PWR_ISO_EN)) {
2357 tmp |= PWR_ISO_EN;
2358 value[0] = (u8) tmp;
2359 value[1] = (u8) (tmp >> 8);
2360 value[2] = (u8) (tmp >> 16);
2361 value[3] = (u8) (tmp >> 24);
2362 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2363 PWR_CTL_EN, value, 4);
2364 msleep(PWR_SLEEP_INTERVAL);
2365 }
2366
2367 tmp &= (~PWR_AV_MODE);
2368 tmp |= POLARIS_AVMODE_DIGITAL;
2369 value[0] = (u8) tmp;
2370 value[1] = (u8) (tmp >> 8);
2371 value[2] = (u8) (tmp >> 16);
2372 value[3] = (u8) (tmp >> 24);
2373 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2374 PWR_CTL_EN, value, 4);
2375 msleep(PWR_SLEEP_INTERVAL);
2376
2377 if (!(tmp & PWR_DEMOD_EN)) {
2378 tmp |= PWR_DEMOD_EN;
2379 value[0] = (u8) tmp;
2380 value[1] = (u8) (tmp >> 8);
2381 value[2] = (u8) (tmp >> 16);
2382 value[3] = (u8) (tmp >> 24);
2383 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2384 PWR_CTL_EN, value, 4);
2385 msleep(PWR_SLEEP_INTERVAL);
2386 }
2387
2388 if (dev->board.tuner_type != TUNER_ABSENT) {
2389 /* reset the Tuner */
2390 if (dev->board.tuner_gpio)
2391 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2392
2393 if (dev->cx231xx_reset_analog_tuner)
2394 dev->cx231xx_reset_analog_tuner(dev);
2395 }
2396 break;
2397
2398 default:
2399 break;
2400 }
2401
2402 msleep(PWR_SLEEP_INTERVAL);
2403
2404 /* For power saving, only enable Pwr_resetout_n
2405 when digital TV is selected. */
2406 if (mode == POLARIS_AVMODE_DIGITAL) {
2407 tmp |= PWR_RESETOUT_EN;
2408 value[0] = (u8) tmp;
2409 value[1] = (u8) (tmp >> 8);
2410 value[2] = (u8) (tmp >> 16);
2411 value[3] = (u8) (tmp >> 24);
2412 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2413 PWR_CTL_EN, value, 4);
2414 msleep(PWR_SLEEP_INTERVAL);
2415 }
2416
2417 /* update power control for afe */
2418 status = cx231xx_afe_update_power_control(dev, mode);
2419
2420 /* update power control for i2s_blk */
2421 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2422
2423 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2424 4);
2425
2426 return status;
2427 }
2428
2429 int cx231xx_power_suspend(struct cx231xx *dev)
2430 {
2431 u8 value[4] = { 0, 0, 0, 0 };
2432 u32 tmp = 0;
2433 int status = 0;
2434
2435 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2436 value, 4);
2437 if (status > 0)
2438 return status;
2439
2440 tmp = le32_to_cpu(*((__le32 *) value));
2441 tmp &= (~PWR_MODE_MASK);
2442
2443 value[0] = (u8) tmp;
2444 value[1] = (u8) (tmp >> 8);
2445 value[2] = (u8) (tmp >> 16);
2446 value[3] = (u8) (tmp >> 24);
2447 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2448 value, 4);
2449
2450 return status;
2451 }
2452
2453 /******************************************************************************
2454 * S T R E A M C O N T R O L functions *
2455 ******************************************************************************/
2456 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2457 {
2458 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2459 u32 tmp = 0;
2460 int status = 0;
2461
2462 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2463 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2464 value, 4);
2465 if (status < 0)
2466 return status;
2467
2468 tmp = le32_to_cpu(*((__le32 *) value));
2469 tmp |= ep_mask;
2470 value[0] = (u8) tmp;
2471 value[1] = (u8) (tmp >> 8);
2472 value[2] = (u8) (tmp >> 16);
2473 value[3] = (u8) (tmp >> 24);
2474
2475 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2476 value, 4);
2477
2478 return status;
2479 }
2480
2481 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2482 {
2483 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2484 u32 tmp = 0;
2485 int status = 0;
2486
2487 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2488 status =
2489 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2490 if (status < 0)
2491 return status;
2492
2493 tmp = le32_to_cpu(*((__le32 *) value));
2494 tmp &= (~ep_mask);
2495 value[0] = (u8) tmp;
2496 value[1] = (u8) (tmp >> 8);
2497 value[2] = (u8) (tmp >> 16);
2498 value[3] = (u8) (tmp >> 24);
2499
2500 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2501 value, 4);
2502
2503 return status;
2504 }
2505
2506 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2507 {
2508 int status = 0;
2509 u32 value = 0;
2510 u8 val[4] = { 0, 0, 0, 0 };
2511
2512 if (dev->udev->speed == USB_SPEED_HIGH) {
2513 switch (media_type) {
2514 case Audio:
2515 cx231xx_info("%s: Audio enter HANC\n", __func__);
2516 status =
2517 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2518 break;
2519
2520 case Vbi:
2521 cx231xx_info("%s: set vanc registers\n", __func__);
2522 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2523 break;
2524
2525 case Sliced_cc:
2526 cx231xx_info("%s: set hanc registers\n", __func__);
2527 status =
2528 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2529 break;
2530
2531 case Raw_Video:
2532 cx231xx_info("%s: set video registers\n", __func__);
2533 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2534 break;
2535
2536 case TS1_serial_mode:
2537 cx231xx_info("%s: set ts1 registers", __func__);
2538
2539 if (dev->board.has_417) {
2540 cx231xx_info(" MPEG\n");
2541 value &= 0xFFFFFFFC;
2542 value |= 0x3;
2543
2544 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2545
2546 val[0] = 0x04;
2547 val[1] = 0xA3;
2548 val[2] = 0x3B;
2549 val[3] = 0x00;
2550 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2551 TS1_CFG_REG, val, 4);
2552
2553 val[0] = 0x00;
2554 val[1] = 0x08;
2555 val[2] = 0x00;
2556 val[3] = 0x08;
2557 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2558 TS1_LENGTH_REG, val, 4);
2559
2560 } else {
2561 cx231xx_info(" BDA\n");
2562 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2563 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2564 }
2565 break;
2566
2567 case TS1_parallel_mode:
2568 cx231xx_info("%s: set ts1 parallel mode registers\n",
2569 __func__);
2570 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2571 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2572 break;
2573 }
2574 } else {
2575 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2576 }
2577
2578 return status;
2579 }
2580
2581 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2582 {
2583 int rc = -1;
2584 u32 ep_mask = -1;
2585 struct pcb_config *pcb_config;
2586
2587 /* get EP for media type */
2588 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2589
2590 if (pcb_config->config_num) {
2591 switch (media_type) {
2592 case Raw_Video:
2593 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2594 break;
2595 case Audio:
2596 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2597 break;
2598 case Vbi:
2599 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2600 break;
2601 case Sliced_cc:
2602 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2603 break;
2604 case TS1_serial_mode:
2605 case TS1_parallel_mode:
2606 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2607 break;
2608 case TS2:
2609 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2610 break;
2611 }
2612 }
2613
2614 if (start) {
2615 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2616
2617 if (rc < 0)
2618 return rc;
2619
2620 /* enable video capture */
2621 if (ep_mask > 0)
2622 rc = cx231xx_start_stream(dev, ep_mask);
2623 } else {
2624 /* disable video capture */
2625 if (ep_mask > 0)
2626 rc = cx231xx_stop_stream(dev, ep_mask);
2627 }
2628
2629 return rc;
2630 }
2631 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2632
2633 /*****************************************************************************
2634 * G P I O B I T control functions *
2635 ******************************************************************************/
2636 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val)
2637 {
2638 int status = 0;
2639
2640 gpio_val = (__force u32)cpu_to_le32(gpio_val);
2641 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
2642
2643 return status;
2644 }
2645
2646 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val)
2647 {
2648 __le32 tmp;
2649 int status = 0;
2650
2651 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
2652 *gpio_val = le32_to_cpu(tmp);
2653
2654 return status;
2655 }
2656
2657 /*
2658 * cx231xx_set_gpio_direction
2659 * Sets the direction of the GPIO pin to input or output
2660 *
2661 * Parameters :
2662 * pin_number : The GPIO Pin number to program the direction for
2663 * from 0 to 31
2664 * pin_value : The Direction of the GPIO Pin under reference.
2665 * 0 = Input direction
2666 * 1 = Output direction
2667 */
2668 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2669 int pin_number, int pin_value)
2670 {
2671 int status = 0;
2672 u32 value = 0;
2673
2674 /* Check for valid pin_number - if 32 , bail out */
2675 if (pin_number >= 32)
2676 return -EINVAL;
2677
2678 /* input */
2679 if (pin_value == 0)
2680 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2681 else
2682 value = dev->gpio_dir | (1 << pin_number);
2683
2684 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
2685
2686 /* cache the value for future */
2687 dev->gpio_dir = value;
2688
2689 return status;
2690 }
2691
2692 /*
2693 * cx231xx_set_gpio_value
2694 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2695 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2696 *
2697 * Parameters :
2698 * pin_number : The GPIO Pin number to program the direction for
2699 * pin_value : The value of the GPIO Pin under reference.
2700 * 0 = set it to 0
2701 * 1 = set it to 1
2702 */
2703 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2704 {
2705 int status = 0;
2706 u32 value = 0;
2707
2708 /* Check for valid pin_number - if 0xFF , bail out */
2709 if (pin_number >= 32)
2710 return -EINVAL;
2711
2712 /* first do a sanity check - if the Pin is not output, make it output */
2713 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2714 /* It was in input mode */
2715 value = dev->gpio_dir | (1 << pin_number);
2716 dev->gpio_dir = value;
2717 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2718 dev->gpio_val);
2719 value = 0;
2720 }
2721
2722 if (pin_value == 0)
2723 value = dev->gpio_val & (~(1 << pin_number));
2724 else
2725 value = dev->gpio_val | (1 << pin_number);
2726
2727 /* store the value */
2728 dev->gpio_val = value;
2729
2730 /* toggle bit0 of GP_IO */
2731 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2732
2733 return status;
2734 }
2735
2736 /*****************************************************************************
2737 * G P I O I2C related functions *
2738 ******************************************************************************/
2739 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2740 {
2741 int status = 0;
2742
2743 /* set SCL to output 1 ; set SDA to output 1 */
2744 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2745 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2746 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2747 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2748
2749 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2750 if (status < 0)
2751 return -EINVAL;
2752
2753 /* set SCL to output 1; set SDA to output 0 */
2754 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2755 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2756
2757 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2758 if (status < 0)
2759 return -EINVAL;
2760
2761 /* set SCL to output 0; set SDA to output 0 */
2762 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2763 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2764
2765 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2766 if (status < 0)
2767 return -EINVAL;
2768
2769 return status;
2770 }
2771
2772 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2773 {
2774 int status = 0;
2775
2776 /* set SCL to output 0; set SDA to output 0 */
2777 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2778 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2779
2780 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2781 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2782
2783 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2784 if (status < 0)
2785 return -EINVAL;
2786
2787 /* set SCL to output 1; set SDA to output 0 */
2788 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2789 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2790
2791 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2792 if (status < 0)
2793 return -EINVAL;
2794
2795 /* set SCL to input ,release SCL cable control
2796 set SDA to input ,release SDA cable control */
2797 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2798 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2799
2800 status =
2801 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2802 if (status < 0)
2803 return -EINVAL;
2804
2805 return status;
2806 }
2807
2808 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2809 {
2810 int status = 0;
2811 u8 i;
2812
2813 /* set SCL to output ; set SDA to output */
2814 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2815 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2816
2817 for (i = 0; i < 8; i++) {
2818 if (((data << i) & 0x80) == 0) {
2819 /* set SCL to output 0; set SDA to output 0 */
2820 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2821 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2822 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2823 dev->gpio_val);
2824
2825 /* set SCL to output 1; set SDA to output 0 */
2826 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2827 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2828 dev->gpio_val);
2829
2830 /* set SCL to output 0; set SDA to output 0 */
2831 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2832 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2833 dev->gpio_val);
2834 } else {
2835 /* set SCL to output 0; set SDA to output 1 */
2836 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2837 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2838 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2839 dev->gpio_val);
2840
2841 /* set SCL to output 1; set SDA to output 1 */
2842 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2843 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2844 dev->gpio_val);
2845
2846 /* set SCL to output 0; set SDA to output 1 */
2847 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2848 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2849 dev->gpio_val);
2850 }
2851 }
2852 return status;
2853 }
2854
2855 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2856 {
2857 u8 value = 0;
2858 int status = 0;
2859 u32 gpio_logic_value = 0;
2860 u8 i;
2861
2862 /* read byte */
2863 for (i = 0; i < 8; i++) { /* send write I2c addr */
2864
2865 /* set SCL to output 0; set SDA to input */
2866 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2867 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2868 dev->gpio_val);
2869
2870 /* set SCL to output 1; set SDA to input */
2871 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2872 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2873 dev->gpio_val);
2874
2875 /* get SDA data bit */
2876 gpio_logic_value = dev->gpio_val;
2877 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2878 &dev->gpio_val);
2879 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2880 value |= (1 << (8 - i - 1));
2881
2882 dev->gpio_val = gpio_logic_value;
2883 }
2884
2885 /* set SCL to output 0,finish the read latest SCL signal.
2886 !!!set SDA to input, never to modify SDA direction at
2887 the same times */
2888 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2889 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2890
2891 /* store the value */
2892 *buf = value & 0xff;
2893
2894 return status;
2895 }
2896
2897 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2898 {
2899 int status = 0;
2900 u32 gpio_logic_value = 0;
2901 int nCnt = 10;
2902 int nInit = nCnt;
2903
2904 /* clock stretch; set SCL to input; set SDA to input;
2905 get SCL value till SCL = 1 */
2906 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2907 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2908
2909 gpio_logic_value = dev->gpio_val;
2910 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2911
2912 do {
2913 msleep(2);
2914 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2915 &dev->gpio_val);
2916 nCnt--;
2917 } while (((dev->gpio_val &
2918 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2919 (nCnt > 0));
2920
2921 if (nCnt == 0)
2922 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2923 nInit * 10);
2924
2925 /*
2926 * readAck
2927 * through clock stretch, slave has given a SCL signal,
2928 * so the SDA data can be directly read.
2929 */
2930 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
2931
2932 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2933 dev->gpio_val = gpio_logic_value;
2934 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2935 status = 0;
2936 } else {
2937 dev->gpio_val = gpio_logic_value;
2938 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2939 }
2940
2941 /* read SDA end, set the SCL to output 0, after this operation,
2942 SDA direction can be changed. */
2943 dev->gpio_val = gpio_logic_value;
2944 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2945 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2946 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2947
2948 return status;
2949 }
2950
2951 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2952 {
2953 int status = 0;
2954
2955 /* set SDA to ouput */
2956 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2957 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2958
2959 /* set SCL = 0 (output); set SDA = 0 (output) */
2960 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2961 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2962 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2963
2964 /* set SCL = 1 (output); set SDA = 0 (output) */
2965 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2966 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2967
2968 /* set SCL = 0 (output); set SDA = 0 (output) */
2969 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2970 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2971
2972 /* set SDA to input,and then the slave will read data from SDA. */
2973 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2974 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2975
2976 return status;
2977 }
2978
2979 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2980 {
2981 int status = 0;
2982
2983 /* set scl to output ; set sda to input */
2984 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2985 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2986 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2987
2988 /* set scl to output 0; set sda to input */
2989 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2990 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2991
2992 /* set scl to output 1; set sda to input */
2993 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2994 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2995
2996 return status;
2997 }
2998
2999 /*****************************************************************************
3000 * G P I O I2C related functions *
3001 ******************************************************************************/
3002 /* cx231xx_gpio_i2c_read
3003 * Function to read data from gpio based I2C interface
3004 */
3005 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3006 {
3007 int status = 0;
3008 int i = 0;
3009
3010 /* get the lock */
3011 mutex_lock(&dev->gpio_i2c_lock);
3012
3013 /* start */
3014 status = cx231xx_gpio_i2c_start(dev);
3015
3016 /* write dev_addr */
3017 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3018
3019 /* readAck */
3020 status = cx231xx_gpio_i2c_read_ack(dev);
3021
3022 /* read data */
3023 for (i = 0; i < len; i++) {
3024 /* read data */
3025 buf[i] = 0;
3026 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3027
3028 if ((i + 1) != len) {
3029 /* only do write ack if we more length */
3030 status = cx231xx_gpio_i2c_write_ack(dev);
3031 }
3032 }
3033
3034 /* write NAK - inform reads are complete */
3035 status = cx231xx_gpio_i2c_write_nak(dev);
3036
3037 /* write end */
3038 status = cx231xx_gpio_i2c_end(dev);
3039
3040 /* release the lock */
3041 mutex_unlock(&dev->gpio_i2c_lock);
3042
3043 return status;
3044 }
3045
3046 /* cx231xx_gpio_i2c_write
3047 * Function to write data to gpio based I2C interface
3048 */
3049 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3050 {
3051 int i = 0;
3052
3053 /* get the lock */
3054 mutex_lock(&dev->gpio_i2c_lock);
3055
3056 /* start */
3057 cx231xx_gpio_i2c_start(dev);
3058
3059 /* write dev_addr */
3060 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3061
3062 /* read Ack */
3063 cx231xx_gpio_i2c_read_ack(dev);
3064
3065 for (i = 0; i < len; i++) {
3066 /* Write data */
3067 cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3068
3069 /* read Ack */
3070 cx231xx_gpio_i2c_read_ack(dev);
3071 }
3072
3073 /* write End */
3074 cx231xx_gpio_i2c_end(dev);
3075
3076 /* release the lock */
3077 mutex_unlock(&dev->gpio_i2c_lock);
3078
3079 return 0;
3080 }
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