drivers/media/usb/dvb-usb/af9005-fe.c

   1 /* Frontend part of the Linux driver for the Afatech 9005
   2  * USB1.1 DVB-T receiver.
   3  *
   4  * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
   5  *
   6  * Thanks to Afatech who kindly provided information.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * see Documentation/dvb/README.dvb-usb for more information
  19  */
  20 #include "af9005.h"
  21 #include "af9005-script.h"
  22 #include "mt2060.h"
  23 #include "qt1010.h"
  24 #include <asm/div64.h>
  25
  26 struct af9005_fe_state {
  27         struct dvb_usb_device *d;
  28         enum fe_status stat;
  29
  30         /* retraining parameters */
  31         u32 original_fcw;
  32         u16 original_rf_top;
  33         u16 original_if_top;
  34         u16 original_if_min;
  35         u16 original_aci0_if_top;
  36         u16 original_aci1_if_top;
  37         u16 original_aci0_if_min;
  38         u8 original_if_unplug_th;
  39         u8 original_rf_unplug_th;
  40         u8 original_dtop_if_unplug_th;
  41         u8 original_dtop_rf_unplug_th;
  42
  43         /* statistics */
  44         u32 pre_vit_error_count;
  45         u32 pre_vit_bit_count;
  46         u32 ber;
  47         u32 post_vit_error_count;
  48         u32 post_vit_bit_count;
  49         u32 unc;
  50         u16 abort_count;
  51
  52         int opened;
  53         int strong;
  54         unsigned long next_status_check;
  55         struct dvb_frontend frontend;
  56 };
  57
  58 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
  59                                  u16 reglo, u8 pos, u8 len, u16 value)
  60 {
  61         int ret;
  62
  63         if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
  64                 return ret;
  65         return af9005_write_register_bits(d, reghi, pos, len,
  66                                           (u8) ((value & 0x300) >> 8));
  67 }
  68
  69 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
  70                                 u16 reglo, u8 pos, u8 len, u16 * value)
  71 {
  72         int ret;
  73         u8 temp0, temp1;
  74
  75         if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
  76                 return ret;
  77         if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
  78                 return ret;
  79         switch (pos) {
  80         case 0:
  81                 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
  82                 break;
  83         case 2:
  84                 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
  85                 break;
  86         case 4:
  87                 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
  88                 break;
  89         case 6:
  90                 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
  91                 break;
  92         default:
  93                 err("invalid pos in read word agc");
  94                 return -EINVAL;
  95         }
  96         return 0;
  97
  98 }
  99
 100 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
 101 {
 102         struct af9005_fe_state *state = fe->demodulator_priv;
 103         int ret;
 104         u8 temp;
 105
 106         *available = false;
 107
 108         ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
 109                                         fec_vtb_rsd_mon_en_pos,
 110                                         fec_vtb_rsd_mon_en_len, &temp);
 111         if (ret)
 112                 return ret;
 113         if (temp & 1) {
 114                 ret =
 115                     af9005_read_register_bits(state->d,
 116                                               xd_p_reg_ofsm_read_rbc_en,
 117                                               reg_ofsm_read_rbc_en_pos,
 118                                               reg_ofsm_read_rbc_en_len, &temp);
 119                 if (ret)
 120                         return ret;
 121                 if ((temp & 1) == 0)
 122                         *available = true;
 123
 124         }
 125         return 0;
 126 }
 127
 128 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
 129                                             u32 * post_err_count,
 130                                             u32 * post_cw_count,
 131                                             u16 * abort_count)
 132 {
 133         struct af9005_fe_state *state = fe->demodulator_priv;
 134         int ret;
 135         u32 err_count;
 136         u32 cw_count;
 137         u8 temp, temp0, temp1, temp2;
 138         u16 loc_abort_count;
 139
 140         *post_err_count = 0;
 141         *post_cw_count = 0;
 142
 143         /* check if error bit count is ready */
 144         ret =
 145             af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
 146                                       fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
 147                                       &temp);
 148         if (ret)
 149                 return ret;
 150         if (!temp) {
 151                 deb_info("rsd counter not ready\n");
 152                 return 100;
 153         }
 154         /* get abort count */
 155         ret =
 156             af9005_read_ofdm_register(state->d,
 157                                       xd_r_fec_rsd_abort_packet_cnt_7_0,
 158                                       &temp0);
 159         if (ret)
 160                 return ret;
 161         ret =
 162             af9005_read_ofdm_register(state->d,
 163                                       xd_r_fec_rsd_abort_packet_cnt_15_8,
 164                                       &temp1);
 165         if (ret)
 166                 return ret;
 167         loc_abort_count = ((u16) temp1 << 8) + temp0;
 168
 169         /* get error count */
 170         ret =
 171             af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
 172                                       &temp0);
 173         if (ret)
 174                 return ret;
 175         ret =
 176             af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
 177                                       &temp1);
 178         if (ret)
 179                 return ret;
 180         ret =
 181             af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
 182                                       &temp2);
 183         if (ret)
 184                 return ret;
 185         err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
 186         *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
 187
 188         /* get RSD packet number */
 189         ret =
 190             af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
 191                                       &temp0);
 192         if (ret)
 193                 return ret;
 194         ret =
 195             af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
 196                                       &temp1);
 197         if (ret)
 198                 return ret;
 199         cw_count = ((u32) temp1 << 8) + temp0;
 200         if (cw_count == 0) {
 201                 err("wrong RSD packet count");
 202                 return -EIO;
 203         }
 204         deb_info("POST abort count %d err count %d rsd packets %d\n",
 205                  loc_abort_count, err_count, cw_count);
 206         *post_cw_count = cw_count - (u32) loc_abort_count;
 207         *abort_count = loc_abort_count;
 208         return 0;
 209
 210 }
 211
 212 static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
 213                                    u32 * post_err_count, u32 * post_cw_count,
 214                                    u16 * abort_count)
 215 {
 216         u32 loc_cw_count = 0, loc_err_count;
 217         u16 loc_abort_count = 0;
 218         int ret;
 219
 220         ret =
 221             af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
 222                                              &loc_abort_count);
 223         if (ret)
 224                 return ret;
 225         *post_err_count = loc_err_count;
 226         *post_cw_count = loc_cw_count * 204 * 8;
 227         *abort_count = loc_abort_count;
 228
 229         return 0;
 230 }
 231
 232 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
 233                                             u32 * pre_err_count,
 234                                             u32 * pre_bit_count)
 235 {
 236         struct af9005_fe_state *state = fe->demodulator_priv;
 237         u8 temp, temp0, temp1, temp2;
 238         u32 super_frame_count, x, bits;
 239         int ret;
 240
 241         ret =
 242             af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
 243                                       fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
 244                                       &temp);
 245         if (ret)
 246                 return ret;
 247         if (!temp) {
 248                 deb_info("viterbi counter not ready\n");
 249                 return 101;     /* ERR_APO_VTB_COUNTER_NOT_READY; */
 250         }
 251         ret =
 252             af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
 253                                       &temp0);
 254         if (ret)
 255                 return ret;
 256         ret =
 257             af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
 258                                       &temp1);
 259         if (ret)
 260                 return ret;
 261         ret =
 262             af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
 263                                       &temp2);
 264         if (ret)
 265                 return ret;
 266         *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
 267
 268         ret =
 269             af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
 270                                       &temp0);
 271         if (ret)
 272                 return ret;
 273         ret =
 274             af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
 275                                       &temp1);
 276         if (ret)
 277                 return ret;
 278         super_frame_count = ((u32) temp1 << 8) + temp0;
 279         if (super_frame_count == 0) {
 280                 deb_info("super frame count 0\n");
 281                 return 102;
 282         }
 283
 284         /* read fft mode */
 285         ret =
 286             af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
 287                                       reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
 288                                       &temp);
 289         if (ret)
 290                 return ret;
 291         if (temp == 0) {
 292                 /* 2K */
 293                 x = 1512;
 294         } else if (temp == 1) {
 295                 /* 8k */
 296                 x = 6048;
 297         } else {
 298                 err("Invalid fft mode");
 299                 return -EINVAL;
 300         }
 301
 302         /* read modulation mode */
 303         ret =
 304             af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
 305                                       reg_tpsd_const_pos, reg_tpsd_const_len,
 306                                       &temp);
 307         if (ret)
 308                 return ret;
 309         switch (temp) {
 310         case 0:         /* QPSK */
 311                 bits = 2;
 312                 break;
 313         case 1:         /* QAM_16 */
 314                 bits = 4;
 315                 break;
 316         case 2:         /* QAM_64 */
 317                 bits = 6;
 318                 break;
 319         default:
 320                 err("invalid modulation mode");
 321                 return -EINVAL;
 322         }
 323         *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
 324         deb_info("PRE err count %d frame count %d bit count %d\n",
 325                  *pre_err_count, super_frame_count, *pre_bit_count);
 326         return 0;
 327 }
 328
 329 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
 330 {
 331         struct af9005_fe_state *state = fe->demodulator_priv;
 332         int ret;
 333
 334         /* set super frame count to 1 */
 335         ret =
 336             af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
 337                                        1 & 0xff);
 338         if (ret)
 339                 return ret;
 340         ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
 341                                          1 >> 8);
 342         if (ret)
 343                 return ret;
 344         /* reset pre viterbi error count */
 345         ret =
 346             af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
 347                                        fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
 348                                        1);
 349
 350         return ret;
 351 }
 352
 353 static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
 354 {
 355         struct af9005_fe_state *state = fe->demodulator_priv;
 356         int ret;
 357
 358         /* set packet unit */
 359         ret =
 360             af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
 361                                        10000 & 0xff);
 362         if (ret)
 363                 return ret;
 364         ret =
 365             af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
 366                                        10000 >> 8);
 367         if (ret)
 368                 return ret;
 369         /* reset post viterbi error count */
 370         ret =
 371             af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
 372                                        fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
 373                                        1);
 374
 375         return ret;
 376 }
 377
 378 static int af9005_get_statistic(struct dvb_frontend *fe)
 379 {
 380         struct af9005_fe_state *state = fe->demodulator_priv;
 381         int ret, fecavailable;
 382         u64 numerator, denominator;
 383
 384         deb_info("GET STATISTIC\n");
 385         ret = af9005_is_fecmon_available(fe, &fecavailable);
 386         if (ret)
 387                 return ret;
 388         if (!fecavailable) {
 389                 deb_info("fecmon not available\n");
 390                 return 0;
 391         }
 392
 393         ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
 394                                                &state->pre_vit_bit_count);
 395         if (ret == 0) {
 396                 af9005_reset_pre_viterbi(fe);
 397                 if (state->pre_vit_bit_count > 0) {
 398                         /* according to v 0.0.4 of the dvb api ber should be a multiple
 399                            of 10E-9 so we have to multiply the error count by
 400                            10E9=1000000000 */
 401                         numerator =
 402                             (u64) state->pre_vit_error_count * (u64) 1000000000;
 403                         denominator = (u64) state->pre_vit_bit_count;
 404                         state->ber = do_div(numerator, denominator);
 405                 } else {
 406                         state->ber = 0xffffffff;
 407                 }
 408         }
 409
 410         ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
 411                                       &state->post_vit_bit_count,
 412                                       &state->abort_count);
 413         if (ret == 0) {
 414                 ret = af9005_reset_post_viterbi(fe);
 415                 state->unc += state->abort_count;
 416                 if (ret)
 417                         return ret;
 418         }
 419         return 0;
 420 }
 421
 422 static int af9005_fe_refresh_state(struct dvb_frontend *fe)
 423 {
 424         struct af9005_fe_state *state = fe->demodulator_priv;
 425         if (time_after(jiffies, state->next_status_check)) {
 426                 deb_info("REFRESH STATE\n");
 427
 428                 /* statistics */
 429                 if (af9005_get_statistic(fe))
 430                         err("get_statistic_failed");
 431                 state->next_status_check = jiffies + 250 * HZ / 1000;
 432         }
 433         return 0;
 434 }
 435
 436 static int af9005_fe_read_status(struct dvb_frontend *fe,
 437                                  enum fe_status *stat)
 438 {
 439         struct af9005_fe_state *state = fe->demodulator_priv;
 440         u8 temp;
 441         int ret;
 442
 443         if (fe->ops.tuner_ops.release == NULL)
 444                 return -ENODEV;
 445
 446         *stat = 0;
 447         ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
 448                                         agc_lock_pos, agc_lock_len, &temp);
 449         if (ret)
 450                 return ret;
 451         if (temp)
 452                 *stat |= FE_HAS_SIGNAL;
 453
 454         ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
 455                                         fd_tpsd_lock_pos, fd_tpsd_lock_len,
 456                                         &temp);
 457         if (ret)
 458                 return ret;
 459         if (temp)
 460                 *stat |= FE_HAS_CARRIER;
 461
 462         ret = af9005_read_register_bits(state->d,
 463                                         xd_r_mp2if_sync_byte_locked,
 464                                         mp2if_sync_byte_locked_pos,
 465                                         mp2if_sync_byte_locked_pos, &temp);
 466         if (ret)
 467                 return ret;
 468         if (temp)
 469                 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
 470         if (state->opened)
 471                 af9005_led_control(state->d, *stat & FE_HAS_LOCK);
 472
 473         ret =
 474             af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
 475                                       reg_strong_sginal_detected_pos,
 476                                       reg_strong_sginal_detected_len, &temp);
 477         if (ret)
 478                 return ret;
 479         if (temp != state->strong) {
 480                 deb_info("adjust for strong signal %d\n", temp);
 481                 state->strong = temp;
 482         }
 483         return 0;
 484 }
 485
 486 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
 487 {
 488         struct af9005_fe_state *state = fe->demodulator_priv;
 489         if (fe->ops.tuner_ops.release  == NULL)
 490                 return -ENODEV;
 491         af9005_fe_refresh_state(fe);
 492         *ber = state->ber;
 493         return 0;
 494 }
 495
 496 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
 497 {
 498         struct af9005_fe_state *state = fe->demodulator_priv;
 499         if (fe->ops.tuner_ops.release == NULL)
 500                 return -ENODEV;
 501         af9005_fe_refresh_state(fe);
 502         *unc = state->unc;
 503         return 0;
 504 }
 505
 506 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
 507                                           u16 * strength)
 508 {
 509         struct af9005_fe_state *state = fe->demodulator_priv;
 510         int ret;
 511         u8 if_gain, rf_gain;
 512
 513         if (fe->ops.tuner_ops.release == NULL)
 514                 return -ENODEV;
 515         ret =
 516             af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
 517                                       &rf_gain);
 518         if (ret)
 519                 return ret;
 520         ret =
 521             af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
 522                                       &if_gain);
 523         if (ret)
 524                 return ret;
 525         /* this value has no real meaning, but i don't have the tables that relate
 526            the rf and if gain with the dbm, so I just scale the value */
 527         *strength = (512 - rf_gain - if_gain) << 7;
 528         return 0;
 529 }
 530
 531 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
 532 {
 533         /* the snr can be derived from the ber and the modulation
 534            but I don't think this kind of complex calculations belong
 535            in the driver. I may be wrong.... */
 536         return -ENOSYS;
 537 }
 538
 539 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw)
 540 {
 541         u8 temp0, temp1, temp2, temp3, buf[4];
 542         int ret;
 543         u32 NS_coeff1_2048Nu;
 544         u32 NS_coeff1_8191Nu;
 545         u32 NS_coeff1_8192Nu;
 546         u32 NS_coeff1_8193Nu;
 547         u32 NS_coeff2_2k;
 548         u32 NS_coeff2_8k;
 549
 550         switch (bw) {
 551         case 6000000:
 552                 NS_coeff1_2048Nu = 0x2ADB6DC;
 553                 NS_coeff1_8191Nu = 0xAB7313;
 554                 NS_coeff1_8192Nu = 0xAB6DB7;
 555                 NS_coeff1_8193Nu = 0xAB685C;
 556                 NS_coeff2_2k = 0x156DB6E;
 557                 NS_coeff2_8k = 0x55B6DC;
 558                 break;
 559
 560         case 7000000:
 561                 NS_coeff1_2048Nu = 0x3200001;
 562                 NS_coeff1_8191Nu = 0xC80640;
 563                 NS_coeff1_8192Nu = 0xC80000;
 564                 NS_coeff1_8193Nu = 0xC7F9C0;
 565                 NS_coeff2_2k = 0x1900000;
 566                 NS_coeff2_8k = 0x640000;
 567                 break;
 568
 569         case 8000000:
 570                 NS_coeff1_2048Nu = 0x3924926;
 571                 NS_coeff1_8191Nu = 0xE4996E;
 572                 NS_coeff1_8192Nu = 0xE49249;
 573                 NS_coeff1_8193Nu = 0xE48B25;
 574                 NS_coeff2_2k = 0x1C92493;
 575                 NS_coeff2_8k = 0x724925;
 576                 break;
 577         default:
 578                 err("Invalid bandwidth %d.", bw);
 579                 return -EINVAL;
 580         }
 581
 582         /*
 583          *  write NS_coeff1_2048Nu
 584          */
 585
 586         temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
 587         temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
 588         temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
 589         temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
 590
 591         /*  big endian to make 8051 happy */
 592         buf[0] = temp3;
 593         buf[1] = temp2;
 594         buf[2] = temp1;
 595         buf[3] = temp0;
 596
 597         /*  cfoe_NS_2k_coeff1_25_24 */
 598         ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
 599         if (ret)
 600                 return ret;
 601
 602         /*  cfoe_NS_2k_coeff1_23_16 */
 603         ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
 604         if (ret)
 605                 return ret;
 606
 607         /*  cfoe_NS_2k_coeff1_15_8 */
 608         ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
 609         if (ret)
 610                 return ret;
 611
 612         /*  cfoe_NS_2k_coeff1_7_0 */
 613         ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
 614         if (ret)
 615                 return ret;
 616
 617         /*
 618          *  write NS_coeff2_2k
 619          */
 620
 621         temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
 622         temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
 623         temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
 624         temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
 625
 626         /*  big endian to make 8051 happy */
 627         buf[0] = temp3;
 628         buf[1] = temp2;
 629         buf[2] = temp1;
 630         buf[3] = temp0;
 631
 632         ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
 633         if (ret)
 634                 return ret;
 635
 636         ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
 637         if (ret)
 638                 return ret;
 639
 640         ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
 641         if (ret)
 642                 return ret;
 643
 644         ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
 645         if (ret)
 646                 return ret;
 647
 648         /*
 649          *  write NS_coeff1_8191Nu
 650          */
 651
 652         temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
 653         temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
 654         temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
 655         temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
 656
 657         /*  big endian to make 8051 happy */
 658         buf[0] = temp3;
 659         buf[1] = temp2;
 660         buf[2] = temp1;
 661         buf[3] = temp0;
 662
 663         ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
 664         if (ret)
 665                 return ret;
 666
 667         ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
 668         if (ret)
 669                 return ret;
 670
 671         ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
 672         if (ret)
 673                 return ret;
 674
 675         ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
 676         if (ret)
 677                 return ret;
 678
 679         /*
 680          *  write NS_coeff1_8192Nu
 681          */
 682
 683         temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
 684         temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
 685         temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
 686         temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
 687
 688         /*  big endian to make 8051 happy */
 689         buf[0] = temp3;
 690         buf[1] = temp2;
 691         buf[2] = temp1;
 692         buf[3] = temp0;
 693
 694         ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
 695         if (ret)
 696                 return ret;
 697
 698         ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
 699         if (ret)
 700                 return ret;
 701
 702         ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
 703         if (ret)
 704                 return ret;
 705
 706         ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
 707         if (ret)
 708                 return ret;
 709
 710         /*
 711          *  write NS_coeff1_8193Nu
 712          */
 713
 714         temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
 715         temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
 716         temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
 717         temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
 718
 719         /*  big endian to make 8051 happy */
 720         buf[0] = temp3;
 721         buf[1] = temp2;
 722         buf[2] = temp1;
 723         buf[3] = temp0;
 724
 725         ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
 726         if (ret)
 727                 return ret;
 728
 729         ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
 730         if (ret)
 731                 return ret;
 732
 733         ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
 734         if (ret)
 735                 return ret;
 736
 737         ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
 738         if (ret)
 739                 return ret;
 740
 741         /*
 742          *  write NS_coeff2_8k
 743          */
 744
 745         temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
 746         temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
 747         temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
 748         temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
 749
 750         /*  big endian to make 8051 happy */
 751         buf[0] = temp3;
 752         buf[1] = temp2;
 753         buf[2] = temp1;
 754         buf[3] = temp0;
 755
 756         ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
 757         if (ret)
 758                 return ret;
 759
 760         ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
 761         if (ret)
 762                 return ret;
 763
 764         ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
 765         if (ret)
 766                 return ret;
 767
 768         ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
 769         return ret;
 770
 771 }
 772
 773 static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw)
 774 {
 775         u8 temp;
 776         switch (bw) {
 777         case 6000000:
 778                 temp = 0;
 779                 break;
 780         case 7000000:
 781                 temp = 1;
 782                 break;
 783         case 8000000:
 784                 temp = 2;
 785                 break;
 786         default:
 787                 err("Invalid bandwidth %d.", bw);
 788                 return -EINVAL;
 789         }
 790         return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
 791                                           reg_bw_len, temp);
 792 }
 793
 794 static int af9005_fe_power(struct dvb_frontend *fe, int on)
 795 {
 796         struct af9005_fe_state *state = fe->demodulator_priv;
 797         u8 temp = on;
 798         int ret;
 799         deb_info("power %s tuner\n", on ? "on" : "off");
 800         ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
 801         return ret;
 802 }
 803
 804 static struct mt2060_config af9005_mt2060_config = {
 805         0xC0
 806 };
 807
 808 static struct qt1010_config af9005_qt1010_config = {
 809         0xC4
 810 };
 811
 812 static int af9005_fe_init(struct dvb_frontend *fe)
 813 {
 814         struct af9005_fe_state *state = fe->demodulator_priv;
 815         struct dvb_usb_adapter *adap = fe->dvb->priv;
 816         int ret, i, scriptlen;
 817         u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
 818         u8 buf[2];
 819         u16 if1;
 820
 821         deb_info("in af9005_fe_init\n");
 822
 823         /* reset */
 824         deb_info("reset\n");
 825         if ((ret =
 826              af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
 827                                         4, 1, 0x01)))
 828                 return ret;
 829         if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
 830                 return ret;
 831         /* clear ofdm reset */
 832         deb_info("clear ofdm reset\n");
 833         for (i = 0; i < 150; i++) {
 834                 if ((ret =
 835                      af9005_read_ofdm_register(state->d,
 836                                                xd_I2C_reg_ofdm_rst, &temp)))
 837                         return ret;
 838                 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
 839                         break;
 840                 msleep(10);
 841         }
 842         if (i == 150)
 843                 return -ETIMEDOUT;
 844
 845         /*FIXME in the dump
 846            write B200 A9
 847            write xd_g_reg_ofsm_clk 7
 848            read eepr c6 (2)
 849            read eepr c7 (2)
 850            misc ctrl 3 -> 1
 851            read eepr ca (6)
 852            write xd_g_reg_ofsm_clk 0
 853            write B200 a1
 854          */
 855         ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
 856         if (ret)
 857                 return ret;
 858         ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
 859         if (ret)
 860                 return ret;
 861         temp = 0x01;
 862         ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
 863         if (ret)
 864                 return ret;
 865         ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
 866         if (ret)
 867                 return ret;
 868         ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
 869         if (ret)
 870                 return ret;
 871
 872         temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
 873         if ((ret =
 874              af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
 875                                         reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
 876                 return ret;
 877         ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
 878                                          reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
 879
 880         if (ret)
 881                 return ret;
 882         /* don't know what register aefc is, but this is what the windows driver does */
 883         ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
 884         if (ret)
 885                 return ret;
 886
 887         /* set stand alone chip */
 888         deb_info("set stand alone chip\n");
 889         if ((ret =
 890              af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
 891                                         reg_dca_stand_alone_pos,
 892                                         reg_dca_stand_alone_len, 1)))
 893                 return ret;
 894
 895         /* set dca upper & lower chip */
 896         deb_info("set dca upper & lower chip\n");
 897         if ((ret =
 898              af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
 899                                         reg_dca_upper_chip_pos,
 900                                         reg_dca_upper_chip_len, 0)))
 901                 return ret;
 902         if ((ret =
 903              af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
 904                                         reg_dca_lower_chip_pos,
 905                                         reg_dca_lower_chip_len, 0)))
 906                 return ret;
 907
 908         /* set 2wire master clock to 0x14 (for 60KHz) */
 909         deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
 910         if ((ret =
 911              af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
 912                 return ret;
 913
 914         /* clear dca enable chip */
 915         deb_info("clear dca enable chip\n");
 916         if ((ret =
 917              af9005_write_register_bits(state->d, xd_p_reg_dca_en,
 918                                         reg_dca_en_pos, reg_dca_en_len, 0)))
 919                 return ret;
 920         /* FIXME these are register bits, but I don't know which ones */
 921         ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
 922         if (ret)
 923                 return ret;
 924         ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
 925         if (ret)
 926                 return ret;
 927
 928         /* init other parameters: program cfoe and select bandwidth */
 929         deb_info("program cfoe\n");
 930         ret = af9005_fe_program_cfoe(state->d, 6000000);
 931         if (ret)
 932                 return ret;
 933         /* set read-update bit for modulation */
 934         deb_info("set read-update bit for modulation\n");
 935         if ((ret =
 936              af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
 937                                         reg_feq_read_update_pos,
 938                                         reg_feq_read_update_len, 1)))
 939                 return ret;
 940
 941         /* sample code has a set MPEG TS code here
 942            but sniffing reveals that it doesn't do it */
 943
 944         /* set read-update bit to 1 for DCA modulation */
 945         deb_info("set read-update bit 1 for DCA modulation\n");
 946         if ((ret =
 947              af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
 948                                         reg_dca_read_update_pos,
 949                                         reg_dca_read_update_len, 1)))
 950                 return ret;
 951
 952         /* enable fec monitor */
 953         deb_info("enable fec monitor\n");
 954         if ((ret =
 955              af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
 956                                         fec_vtb_rsd_mon_en_pos,
 957                                         fec_vtb_rsd_mon_en_len, 1)))
 958                 return ret;
 959
 960         /* FIXME should be register bits, I don't know which ones */
 961         ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
 962
 963         /* set api_retrain_never_freeze */
 964         deb_info("set api_retrain_never_freeze\n");
 965         if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
 966                 return ret;
 967
 968         /* load init script */
 969         deb_info("load init script\n");
 970         scriptlen = sizeof(script) / sizeof(RegDesc);
 971         for (i = 0; i < scriptlen; i++) {
 972                 if ((ret =
 973                      af9005_write_register_bits(state->d, script[i].reg,
 974                                                 script[i].pos,
 975                                                 script[i].len, script[i].val)))
 976                         return ret;
 977                 /* save 3 bytes of original fcw */
 978                 if (script[i].reg == 0xae18)
 979                         temp2 = script[i].val;
 980                 if (script[i].reg == 0xae19)
 981                         temp1 = script[i].val;
 982                 if (script[i].reg == 0xae1a)
 983                         temp0 = script[i].val;
 984
 985                 /* save original unplug threshold */
 986                 if (script[i].reg == xd_p_reg_unplug_th)
 987                         state->original_if_unplug_th = script[i].val;
 988                 if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
 989                         state->original_rf_unplug_th = script[i].val;
 990                 if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
 991                         state->original_dtop_if_unplug_th = script[i].val;
 992                 if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
 993                         state->original_dtop_rf_unplug_th = script[i].val;
 994
 995         }
 996         state->original_fcw =
 997             ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
 998
 999
1000         /* save original TOPs */
1001         deb_info("save original TOPs\n");
1002
1003         /*  RF TOP */
1004         ret =
1005             af9005_read_word_agc(state->d,
1006                                  xd_p_reg_aagc_rf_top_numerator_9_8,
1007                                  xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1008                                  &state->original_rf_top);
1009         if (ret)
1010                 return ret;
1011
1012         /*  IF TOP */
1013         ret =
1014             af9005_read_word_agc(state->d,
1015                                  xd_p_reg_aagc_if_top_numerator_9_8,
1016                                  xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1017                                  &state->original_if_top);
1018         if (ret)
1019                 return ret;
1020
1021         /*  ACI 0 IF TOP */
1022         ret =
1023             af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1024                                  &state->original_aci0_if_top);
1025         if (ret)
1026                 return ret;
1027
1028         /*  ACI 1 IF TOP */
1029         ret =
1030             af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1031                                  &state->original_aci1_if_top);
1032         if (ret)
1033                 return ret;
1034
1035         /* attach tuner and init */
1036         if (fe->ops.tuner_ops.release == NULL) {
1037                 /* read tuner and board id from eeprom */
1038                 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1039                 if (ret) {
1040                         err("Impossible to read EEPROM\n");
1041                         return ret;
1042                 }
1043                 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1044                 switch (buf[0]) {
1045                 case 2: /* MT2060 */
1046                         /* read if1 from eeprom */
1047                         ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1048                         if (ret) {
1049                                 err("Impossible to read EEPROM\n");
1050                                 return ret;
1051                         }
1052                         if1 = (u16) (buf[0] << 8) + buf[1];
1053                         if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1054                                          &af9005_mt2060_config, if1) == NULL) {
1055                                 deb_info("MT2060 attach failed\n");
1056                                 return -ENODEV;
1057                         }
1058                         break;
1059                 case 3: /* QT1010 */
1060                 case 9: /* QT1010B */
1061                         if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1062                                         &af9005_qt1010_config) ==NULL) {
1063                                 deb_info("QT1010 attach failed\n");
1064                                 return -ENODEV;
1065                         }
1066                         break;
1067                 default:
1068                         err("Unsupported tuner type %d", buf[0]);
1069                         return -ENODEV;
1070                 }
1071                 ret = fe->ops.tuner_ops.init(fe);
1072                 if (ret)
1073                         return ret;
1074         }
1075
1076         deb_info("profit!\n");
1077         return 0;
1078 }
1079
1080 static int af9005_fe_sleep(struct dvb_frontend *fe)
1081 {
1082         return af9005_fe_power(fe, 0);
1083 }
1084
1085 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1086 {
1087         struct af9005_fe_state *state = fe->demodulator_priv;
1088
1089         if (acquire) {
1090                 state->opened++;
1091         } else {
1092
1093                 state->opened--;
1094                 if (!state->opened)
1095                         af9005_led_control(state->d, 0);
1096         }
1097         return 0;
1098 }
1099
1100 static int af9005_fe_set_frontend(struct dvb_frontend *fe)
1101 {
1102         struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1103         struct af9005_fe_state *state = fe->demodulator_priv;
1104         int ret;
1105         u8 temp, temp0, temp1, temp2;
1106
1107         deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1108                  fep->bandwidth_hz);
1109         if (fe->ops.tuner_ops.release == NULL) {
1110                 err("Tuner not attached");
1111                 return -ENODEV;
1112         }
1113
1114         deb_info("turn off led\n");
1115         /* not in the log */
1116         ret = af9005_led_control(state->d, 0);
1117         if (ret)
1118                 return ret;
1119         /* not sure about the bits */
1120         ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1121         if (ret)
1122                 return ret;
1123
1124         /* set FCW to default value */
1125         deb_info("set FCW to default value\n");
1126         temp0 = (u8) (state->original_fcw & 0x000000ff);
1127         temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1128         temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1129         ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1130         if (ret)
1131                 return ret;
1132         ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1133         if (ret)
1134                 return ret;
1135         ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1136         if (ret)
1137                 return ret;
1138
1139         /* restore original TOPs */
1140         deb_info("restore original TOPs\n");
1141         ret =
1142             af9005_write_word_agc(state->d,
1143                                   xd_p_reg_aagc_rf_top_numerator_9_8,
1144                                   xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1145                                   state->original_rf_top);
1146         if (ret)
1147                 return ret;
1148         ret =
1149             af9005_write_word_agc(state->d,
1150                                   xd_p_reg_aagc_if_top_numerator_9_8,
1151                                   xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1152                                   state->original_if_top);
1153         if (ret)
1154                 return ret;
1155         ret =
1156             af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1157                                   state->original_aci0_if_top);
1158         if (ret)
1159                 return ret;
1160         ret =
1161             af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1162                                   state->original_aci1_if_top);
1163         if (ret)
1164                 return ret;
1165
1166         /* select bandwidth */
1167         deb_info("select bandwidth");
1168         ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz);
1169         if (ret)
1170                 return ret;
1171         ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz);
1172         if (ret)
1173                 return ret;
1174
1175         /* clear easy mode flag */
1176         deb_info("clear easy mode flag\n");
1177         ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1178         if (ret)
1179                 return ret;
1180
1181         /* set unplug threshold to original value */
1182         deb_info("set unplug threshold to original value\n");
1183         ret =
1184             af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1185                                        state->original_if_unplug_th);
1186         if (ret)
1187                 return ret;
1188         /* set tuner */
1189         deb_info("set tuner\n");
1190         ret = fe->ops.tuner_ops.set_params(fe);
1191         if (ret)
1192                 return ret;
1193
1194         /* trigger ofsm */
1195         deb_info("trigger ofsm\n");
1196         temp = 0;
1197         ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1198         if (ret)
1199                 return ret;
1200
1201         /* clear retrain and freeze flag */
1202         deb_info("clear retrain and freeze flag\n");
1203         ret =
1204             af9005_write_register_bits(state->d,
1205                                        xd_p_reg_api_retrain_request,
1206                                        reg_api_retrain_request_pos, 2, 0);
1207         if (ret)
1208                 return ret;
1209
1210         /* reset pre viterbi and post viterbi registers and statistics */
1211         af9005_reset_pre_viterbi(fe);
1212         af9005_reset_post_viterbi(fe);
1213         state->pre_vit_error_count = 0;
1214         state->pre_vit_bit_count = 0;
1215         state->ber = 0;
1216         state->post_vit_error_count = 0;
1217         /* state->unc = 0; commented out since it should be ever increasing */
1218         state->abort_count = 0;
1219
1220         state->next_status_check = jiffies;
1221         state->strong = -1;
1222
1223         return 0;
1224 }
1225
1226 static int af9005_fe_get_frontend(struct dvb_frontend *fe,
1227                                   struct dtv_frontend_properties *fep)
1228 {
1229         struct af9005_fe_state *state = fe->demodulator_priv;
1230         int ret;
1231         u8 temp;
1232
1233         /* mode */
1234         ret =
1235             af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1236                                       reg_tpsd_const_pos, reg_tpsd_const_len,
1237                                       &temp);
1238         if (ret)
1239                 return ret;
1240         deb_info("===== fe_get_frontend_legacy = =============\n");
1241         deb_info("CONSTELLATION ");
1242         switch (temp) {
1243         case 0:
1244                 fep->modulation = QPSK;
1245                 deb_info("QPSK\n");
1246                 break;
1247         case 1:
1248                 fep->modulation = QAM_16;
1249                 deb_info("QAM_16\n");
1250                 break;
1251         case 2:
1252                 fep->modulation = QAM_64;
1253                 deb_info("QAM_64\n");
1254                 break;
1255         }
1256
1257         /* tps hierarchy and alpha value */
1258         ret =
1259             af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1260                                       reg_tpsd_hier_pos, reg_tpsd_hier_len,
1261                                       &temp);
1262         if (ret)
1263                 return ret;
1264         deb_info("HIERARCHY ");
1265         switch (temp) {
1266         case 0:
1267                 fep->hierarchy = HIERARCHY_NONE;
1268                 deb_info("NONE\n");
1269                 break;
1270         case 1:
1271                 fep->hierarchy = HIERARCHY_1;
1272                 deb_info("1\n");
1273                 break;
1274         case 2:
1275                 fep->hierarchy = HIERARCHY_2;
1276                 deb_info("2\n");
1277                 break;
1278         case 3:
1279                 fep->hierarchy = HIERARCHY_4;
1280                 deb_info("4\n");
1281                 break;
1282         }
1283
1284         /*  high/low priority     */
1285         ret =
1286             af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1287                                       reg_dec_pri_pos, reg_dec_pri_len, &temp);
1288         if (ret)
1289                 return ret;
1290         /* if temp is set = high priority */
1291         deb_info("PRIORITY %s\n", temp ? "high" : "low");
1292
1293         /* high coderate */
1294         ret =
1295             af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1296                                       reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1297                                       &temp);
1298         if (ret)
1299                 return ret;
1300         deb_info("CODERATE HP ");
1301         switch (temp) {
1302         case 0:
1303                 fep->code_rate_HP = FEC_1_2;
1304                 deb_info("FEC_1_2\n");
1305                 break;
1306         case 1:
1307                 fep->code_rate_HP = FEC_2_3;
1308                 deb_info("FEC_2_3\n");
1309                 break;
1310         case 2:
1311                 fep->code_rate_HP = FEC_3_4;
1312                 deb_info("FEC_3_4\n");
1313                 break;
1314         case 3:
1315                 fep->code_rate_HP = FEC_5_6;
1316                 deb_info("FEC_5_6\n");
1317                 break;
1318         case 4:
1319                 fep->code_rate_HP = FEC_7_8;
1320                 deb_info("FEC_7_8\n");
1321                 break;
1322         }
1323
1324         /* low coderate */
1325         ret =
1326             af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1327                                       reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1328                                       &temp);
1329         if (ret)
1330                 return ret;
1331         deb_info("CODERATE LP ");
1332         switch (temp) {
1333         case 0:
1334                 fep->code_rate_LP = FEC_1_2;
1335                 deb_info("FEC_1_2\n");
1336                 break;
1337         case 1:
1338                 fep->code_rate_LP = FEC_2_3;
1339                 deb_info("FEC_2_3\n");
1340                 break;
1341         case 2:
1342                 fep->code_rate_LP = FEC_3_4;
1343                 deb_info("FEC_3_4\n");
1344                 break;
1345         case 3:
1346                 fep->code_rate_LP = FEC_5_6;
1347                 deb_info("FEC_5_6\n");
1348                 break;
1349         case 4:
1350                 fep->code_rate_LP = FEC_7_8;
1351                 deb_info("FEC_7_8\n");
1352                 break;
1353         }
1354
1355         /* guard interval */
1356         ret =
1357             af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1358                                       reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1359         if (ret)
1360                 return ret;
1361         deb_info("GUARD INTERVAL ");
1362         switch (temp) {
1363         case 0:
1364                 fep->guard_interval = GUARD_INTERVAL_1_32;
1365                 deb_info("1_32\n");
1366                 break;
1367         case 1:
1368                 fep->guard_interval = GUARD_INTERVAL_1_16;
1369                 deb_info("1_16\n");
1370                 break;
1371         case 2:
1372                 fep->guard_interval = GUARD_INTERVAL_1_8;
1373                 deb_info("1_8\n");
1374                 break;
1375         case 3:
1376                 fep->guard_interval = GUARD_INTERVAL_1_4;
1377                 deb_info("1_4\n");
1378                 break;
1379         }
1380
1381         /* fft */
1382         ret =
1383             af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1384                                       reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1385                                       &temp);
1386         if (ret)
1387                 return ret;
1388         deb_info("TRANSMISSION MODE ");
1389         switch (temp) {
1390         case 0:
1391                 fep->transmission_mode = TRANSMISSION_MODE_2K;
1392                 deb_info("2K\n");
1393                 break;
1394         case 1:
1395                 fep->transmission_mode = TRANSMISSION_MODE_8K;
1396                 deb_info("8K\n");
1397                 break;
1398         }
1399
1400         /* bandwidth      */
1401         ret =
1402             af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1403                                       reg_bw_len, &temp);
1404         deb_info("BANDWIDTH ");
1405         switch (temp) {
1406         case 0:
1407                 fep->bandwidth_hz = 6000000;
1408                 deb_info("6\n");
1409                 break;
1410         case 1:
1411                 fep->bandwidth_hz = 7000000;
1412                 deb_info("7\n");
1413                 break;
1414         case 2:
1415                 fep->bandwidth_hz = 8000000;
1416                 deb_info("8\n");
1417                 break;
1418         }
1419         return 0;
1420 }
1421
1422 static void af9005_fe_release(struct dvb_frontend *fe)
1423 {
1424         struct af9005_fe_state *state =
1425             (struct af9005_fe_state *)fe->demodulator_priv;
1426         kfree(state);
1427 }
1428
1429 static const struct dvb_frontend_ops af9005_fe_ops;
1430
1431 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1432 {
1433         struct af9005_fe_state *state = NULL;
1434
1435         /* allocate memory for the internal state */
1436         state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1437         if (state == NULL)
1438                 goto error;
1439
1440         deb_info("attaching frontend af9005\n");
1441
1442         state->d = d;
1443         state->opened = 0;
1444
1445         memcpy(&state->frontend.ops, &af9005_fe_ops,
1446                sizeof(struct dvb_frontend_ops));
1447         state->frontend.demodulator_priv = state;
1448
1449         return &state->frontend;
1450       error:
1451         return NULL;
1452 }
1453
1454 static const struct dvb_frontend_ops af9005_fe_ops = {
1455         .delsys = { SYS_DVBT },
1456         .info = {
1457                  .name = "AF9005 USB DVB-T",
1458                  .frequency_min = 44250000,
1459                  .frequency_max = 867250000,
1460                  .frequency_stepsize = 250000,
1461                  .caps = FE_CAN_INVERSION_AUTO |
1462                  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1463                  FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1464                  FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1465                  FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1466                  FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1467                  FE_CAN_HIERARCHY_AUTO,
1468                  },
1469
1470         .release = af9005_fe_release,
1471
1472         .init = af9005_fe_init,
1473         .sleep = af9005_fe_sleep,
1474         .ts_bus_ctrl = af9005_ts_bus_ctrl,
1475
1476         .set_frontend = af9005_fe_set_frontend,
1477         .get_frontend = af9005_fe_get_frontend,
1478
1479         .read_status = af9005_fe_read_status,
1480         .read_ber = af9005_fe_read_ber,
1481         .read_signal_strength = af9005_fe_read_signal_strength,
1482         .read_snr = af9005_fe_read_snr,
1483         .read_ucblocks = af9005_fe_read_unc_blocks,
1484 };