drivers/media/usb/em28xx/em28xx-reg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #define EM_GPIO_0  (1 << 0)
   3 #define EM_GPIO_1  (1 << 1)
   4 #define EM_GPIO_2  (1 << 2)
   5 #define EM_GPIO_3  (1 << 3)
   6 #define EM_GPIO_4  (1 << 4)
   7 #define EM_GPIO_5  (1 << 5)
   8 #define EM_GPIO_6  (1 << 6)
   9 #define EM_GPIO_7  (1 << 7)
  10
  11 #define EM_GPO_0   (1 << 0)
  12 #define EM_GPO_1   (1 << 1)
  13 #define EM_GPO_2   (1 << 2)
  14 #define EM_GPO_3   (1 << 3)
  15
  16 /* em28xx endpoints */
  17 /* 0x82:   (always ?) analog */
  18 #define EM28XX_EP_AUDIO         0x83
  19 /* 0x84:   digital or analog */
  20
  21 /* em2800 registers */
  22 #define EM2800_R08_AUDIOSRC 0x08
  23
  24 /* em28xx registers */
  25
  26 #define EM28XX_R00_CHIPCFG      0x00
  27
  28 /* em28xx Chip Configuration 0x00 */
  29 #define EM2860_CHIPCFG_VENDOR_AUDIO             0x80
  30 #define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE       0x40
  31 #define EM2820_CHIPCFG_I2S_3_SAMPRATES          0x30
  32 #define EM2860_CHIPCFG_I2S_5_SAMPRATES          0x30
  33 #define EM2820_CHIPCFG_I2S_1_SAMPRATE           0x20
  34 #define EM2860_CHIPCFG_I2S_3_SAMPRATES          0x20
  35 #define EM28XX_CHIPCFG_AC97                     0x10
  36 #define EM28XX_CHIPCFG_AUDIOMASK                0x30
  37
  38 #define EM28XX_R01_CHIPCFG2     0x01
  39
  40 /* em28xx Chip Configuration 2 0x01 */
  41 #define EM28XX_CHIPCFG2_TS_PRESENT              0x10
  42 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK    0x0c /* bits 3-2 */
  43 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF     0x00
  44 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF     0x04
  45 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF     0x08
  46 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF     0x0c
  47 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK      0x03 /* bits 0-1 */
  48 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188       0x00
  49 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376       0x01
  50 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564       0x02
  51 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752       0x03
  52
  53 /* GPIO/GPO registers */
  54 #define EM2880_R04_GPO          0x04    /* em2880-em2883 only */
  55 #define EM2820_R08_GPIO_CTRL    0x08    /* em2820-em2873/83 only */
  56 #define EM2820_R09_GPIO_STATE   0x09    /* em2820-em2873/83 only */
  57
  58 #define EM28XX_R06_I2C_CLK      0x06
  59
  60 /* em28xx I2C Clock Register (0x06) */
  61 #define EM28XX_I2C_CLK_ACK_LAST_READ    0x80
  62 #define EM28XX_I2C_CLK_WAIT_ENABLE      0x40
  63 #define EM28XX_I2C_EEPROM_ON_BOARD      0x08
  64 #define EM28XX_I2C_EEPROM_KEY_VALID     0x04
  65 #define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */
  66 #define EM28XX_I2C_FREQ_1_5_MHZ         0x03 /* bus frequency (bits [1-0]) */
  67 #define EM28XX_I2C_FREQ_25_KHZ          0x02
  68 #define EM28XX_I2C_FREQ_400_KHZ         0x01
  69 #define EM28XX_I2C_FREQ_100_KHZ         0x00
  70
  71 #define EM28XX_R0A_CHIPID       0x0a
  72 #define EM28XX_R0C_USBSUSP      0x0c
  73 #define   EM28XX_R0C_USBSUSP_SNAPSHOT   0x20 /* 1=button pressed, needs reset */
  74
  75 #define EM28XX_R0E_AUDIOSRC     0x0e
  76 #define EM28XX_R0F_XCLK 0x0f
  77
  78 /* em28xx XCLK Register (0x0f) */
  79 #define EM28XX_XCLK_AUDIO_UNMUTE        0x80 /* otherwise audio muted */
  80 #define EM28XX_XCLK_I2S_MSB_TIMING      0x40 /* otherwise standard timing */
  81 #define EM28XX_XCLK_IR_RC5_MODE         0x20 /* otherwise NEC mode */
  82 #define EM28XX_XCLK_IR_NEC_CHK_PARITY   0x10
  83 #define EM28XX_XCLK_FREQUENCY_30MHZ     0x00 /* Freq. select (bits [3-0]) */
  84 #define EM28XX_XCLK_FREQUENCY_15MHZ     0x01
  85 #define EM28XX_XCLK_FREQUENCY_10MHZ     0x02
  86 #define EM28XX_XCLK_FREQUENCY_7_5MHZ    0x03
  87 #define EM28XX_XCLK_FREQUENCY_6MHZ      0x04
  88 #define EM28XX_XCLK_FREQUENCY_5MHZ      0x05
  89 #define EM28XX_XCLK_FREQUENCY_4_3MHZ    0x06
  90 #define EM28XX_XCLK_FREQUENCY_12MHZ     0x07
  91 #define EM28XX_XCLK_FREQUENCY_20MHZ     0x08
  92 #define EM28XX_XCLK_FREQUENCY_20MHZ_2   0x09
  93 #define EM28XX_XCLK_FREQUENCY_48MHZ     0x0a
  94 #define EM28XX_XCLK_FREQUENCY_24MHZ     0x0b
  95
  96 #define EM28XX_R10_VINMODE      0x10
  97           /* used by all non-camera devices: */
  98 #define   EM28XX_VINMODE_YUV422_CbYCrY  0x10
  99           /* used by camera devices: */
 100 #define   EM28XX_VINMODE_YUV422_YUYV    0x08
 101 #define   EM28XX_VINMODE_YUV422_YVYU    0x09
 102 #define   EM28XX_VINMODE_YUV422_UYVY    0x0a
 103 #define   EM28XX_VINMODE_YUV422_VYUY    0x0b
 104 #define   EM28XX_VINMODE_RGB8_BGGR      0x0c
 105 #define   EM28XX_VINMODE_RGB8_GRBG      0x0d
 106 #define   EM28XX_VINMODE_RGB8_GBRG      0x0e
 107 #define   EM28XX_VINMODE_RGB8_RGGB      0x0f
 108           /*
 109            * apparently:
 110            *   bit 0: swap component 1+2 with 3+4
 111            *                 => e.g.: YUYV => YVYU, BGGR => GRBG
 112            *   bit 1: swap component 1 with 2 and 3 with 4
 113            *                 => e.g.: YUYV => UYVY, BGGR => GBRG
 114            */
 115
 116 #define EM28XX_R11_VINCTRL      0x11
 117
 118 /* em28xx Video Input Control Register 0x11 */
 119 #define EM28XX_VINCTRL_VBI_SLICED       0x80
 120 #define EM28XX_VINCTRL_VBI_RAW          0x40
 121 #define EM28XX_VINCTRL_VOUT_MODE_IN     0x20 /* HREF,VREF,VACT in output */
 122 #define EM28XX_VINCTRL_CCIR656_ENABLE   0x10
 123 #define EM28XX_VINCTRL_VBI_16BIT_RAW    0x08 /* otherwise 8-bit raw */
 124 #define EM28XX_VINCTRL_FID_ON_HREF      0x04
 125 #define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02
 126 #define EM28XX_VINCTRL_INTERLACED       0x01
 127
 128 #define EM28XX_R12_VINENABLE    0x12    /* */
 129
 130 #define EM28XX_R14_GAMMA        0x14
 131 #define EM28XX_R15_RGAIN        0x15
 132 #define EM28XX_R16_GGAIN        0x16
 133 #define EM28XX_R17_BGAIN        0x17
 134 #define EM28XX_R18_ROFFSET      0x18
 135 #define EM28XX_R19_GOFFSET      0x19
 136 #define EM28XX_R1A_BOFFSET      0x1a
 137
 138 #define EM28XX_R1B_OFLOW        0x1b
 139 #define EM28XX_R1C_HSTART       0x1c
 140 #define EM28XX_R1D_VSTART       0x1d
 141 #define EM28XX_R1E_CWIDTH       0x1e
 142 #define EM28XX_R1F_CHEIGHT      0x1f
 143
 144 #define EM28XX_R20_YGAIN        0x20 /* contrast [0:4]   */
 145 #define   CONTRAST_DEFAULT      0x10
 146
 147 #define EM28XX_R21_YOFFSET      0x21 /* brightness       */     /* signed */
 148 #define   BRIGHTNESS_DEFAULT    0x00
 149
 150 #define EM28XX_R22_UVGAIN       0x22 /* saturation [0:4] */
 151 #define   SATURATION_DEFAULT    0x10
 152
 153 #define EM28XX_R23_UOFFSET      0x23 /* blue balance     */     /* signed */
 154 #define   BLUE_BALANCE_DEFAULT  0x00
 155
 156 #define EM28XX_R24_VOFFSET      0x24 /* red balance      */     /* signed */
 157 #define   RED_BALANCE_DEFAULT   0x00
 158
 159 #define EM28XX_R25_SHARPNESS    0x25 /* sharpness [0:4]  */
 160 #define   SHARPNESS_DEFAULT     0x00
 161
 162 #define EM28XX_R26_COMPR        0x26
 163 #define EM28XX_R27_OUTFMT       0x27
 164
 165 /* em28xx Output Format Register (0x27) */
 166 #define EM28XX_OUTFMT_RGB_8_RGRG        0x00
 167 #define EM28XX_OUTFMT_RGB_8_GRGR        0x01
 168 #define EM28XX_OUTFMT_RGB_8_GBGB        0x02
 169 #define EM28XX_OUTFMT_RGB_8_BGBG        0x03
 170 #define EM28XX_OUTFMT_RGB_16_656        0x04
 171 #define EM28XX_OUTFMT_RGB_8_BAYER       0x08 /* Pattern in Reg 0x10[1-0] */
 172 #define EM28XX_OUTFMT_YUV211            0x10
 173 #define EM28XX_OUTFMT_YUV422_Y0UY1V     0x14
 174 #define EM28XX_OUTFMT_YUV422_Y1UY0V     0x15
 175 #define EM28XX_OUTFMT_YUV411            0x18
 176
 177 #define EM28XX_R28_XMIN 0x28
 178 #define EM28XX_R29_XMAX 0x29
 179 #define EM28XX_R2A_YMIN 0x2a
 180 #define EM28XX_R2B_YMAX 0x2b
 181
 182 #define EM28XX_R30_HSCALELOW    0x30
 183 #define EM28XX_R31_HSCALEHIGH   0x31
 184 #define EM28XX_R32_VSCALELOW    0x32
 185 #define EM28XX_R33_VSCALEHIGH   0x33
 186 #define   EM28XX_HVSCALE_MAX    0x3fff /* => 20% */
 187
 188 #define EM28XX_R34_VBI_START_H  0x34
 189 #define EM28XX_R35_VBI_START_V  0x35
 190 /*
 191  * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these
 192  * registers for a different unknown purpose.
 193  *   => register 0x34 is set to capture width / 16
 194  *   => register 0x35 is set to capture height / 16
 195  */
 196
 197 #define EM28XX_R36_VBI_WIDTH    0x36
 198 #define EM28XX_R37_VBI_HEIGHT   0x37
 199
 200 #define EM28XX_R40_AC97LSB      0x40
 201 #define EM28XX_R41_AC97MSB      0x41
 202 #define EM28XX_R42_AC97ADDR     0x42
 203 #define EM28XX_R43_AC97BUSY     0x43
 204
 205 #define EM28XX_R45_IR           0x45
 206         /* 0x45  bit 7    - parity bit
 207                  bits 6-0 - count
 208            0x46  IR brand
 209            0x47  IR data
 210          */
 211
 212 /* em2874 registers */
 213 #define EM2874_R50_IR_CONFIG    0x50
 214 #define EM2874_R51_IR           0x51
 215 #define EM2874_R5D_TS1_PKT_SIZE 0x5d
 216 #define EM2874_R5E_TS2_PKT_SIZE 0x5e
 217         /*
 218          * For both TS1 and TS2, In isochronous mode:
 219          *  0x01  188 bytes
 220          *  0x02  376 bytes
 221          *  0x03  564 bytes
 222          *  0x04  752 bytes
 223          *  0x05  940 bytes
 224          * In bulk mode:
 225          *  0x01..0xff  total packet count in 188-byte
 226          */
 227
 228 #define EM2874_R5F_TS_ENABLE    0x5f
 229
 230 /* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */
 231 /*
 232  * NOTE: not all ports are bonded out;
 233  * Some ports are multiplexed with special function I/O
 234  */
 235 #define EM2874_R80_GPIO_P0_CTRL    0x80
 236 #define EM2874_R81_GPIO_P1_CTRL    0x81
 237 #define EM2874_R82_GPIO_P2_CTRL    0x82
 238 #define EM2874_R83_GPIO_P3_CTRL    0x83
 239 #define EM2874_R84_GPIO_P0_STATE   0x84
 240 #define EM2874_R85_GPIO_P1_STATE   0x85
 241 #define EM2874_R86_GPIO_P2_STATE   0x86
 242 #define EM2874_R87_GPIO_P3_STATE   0x87
 243
 244 /* em2874 IR config register (0x50) */
 245 #define EM2874_IR_NEC           0x00
 246 #define EM2874_IR_NEC_NO_PARITY 0x01
 247 #define EM2874_IR_RC5           0x04
 248 #define EM2874_IR_RC6_MODE_0    0x08
 249 #define EM2874_IR_RC6_MODE_6A   0x0b
 250
 251 /* em2874 Transport Stream Enable Register (0x5f) */
 252 #define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
 253 #define EM2874_TS1_FILTER_ENABLE  (1 << 1)
 254 #define EM2874_TS1_NULL_DISCARD   (1 << 2)
 255 #define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
 256 #define EM2874_TS2_FILTER_ENABLE  (1 << 5)
 257 #define EM2874_TS2_NULL_DISCARD   (1 << 6)
 258
 259 /* register settings */
 260 #define EM2800_AUDIO_SRC_TUNER  0x0d
 261 #define EM2800_AUDIO_SRC_LINE   0x0c
 262 #define EM28XX_AUDIO_SRC_TUNER  0xc0
 263 #define EM28XX_AUDIO_SRC_LINE   0x80
 264
 265 /* FIXME: Need to be populated with the other chip ID's */
 266 enum em28xx_chip_id {
 267         CHIP_ID_EM2800 = 7,
 268         CHIP_ID_EM2710 = 17,
 269         CHIP_ID_EM2820 = 18,    /* Also used by some em2710 */
 270         CHIP_ID_EM2840 = 20,
 271         CHIP_ID_EM2750 = 33,
 272         CHIP_ID_EM2860 = 34,
 273         CHIP_ID_EM2870 = 35,
 274         CHIP_ID_EM2883 = 36,
 275         CHIP_ID_EM2765 = 54,
 276         CHIP_ID_EM2874 = 65,
 277         CHIP_ID_EM2884 = 68,
 278         CHIP_ID_EM28174 = 113,
 279         CHIP_ID_EM28178 = 114,
 280 };
 281
 282 /*
 283  * Registers used by em202
 284  */
 285
 286 /* EMP202 vendor registers */
 287 #define EM202_EXT_MODEM_CTRL     0x3e
 288 #define EM202_GPIO_CONF          0x4c
 289 #define EM202_GPIO_POLARITY      0x4e
 290 #define EM202_GPIO_STICKY        0x50
 291 #define EM202_GPIO_MASK          0x52
 292 #define EM202_GPIO_STATUS        0x54
 293 #define EM202_SPDIF_OUT_SEL      0x6a
 294 #define EM202_ANTIPOP            0x72
 295 #define EM202_EAPD_GPIO_ACCESS   0x74