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Merge branch 'thinkpad-2.6.32-part2' into release
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / cx23885 / cx23885-core.c
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
32
33 #include "cx23885.h"
34 #include "cimax2.h"
35
36 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
37 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
38 MODULE_LICENSE("GPL");
39
40 static unsigned int debug;
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "enable debug messages");
43
44 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
45 module_param_array(card, int, NULL, 0444);
46 MODULE_PARM_DESC(card, "card type");
47
48 #define dprintk(level, fmt, arg...)\
49 do { if (debug >= level)\
50 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
51 } while (0)
52
53 static unsigned int cx23885_devcount;
54
55 static DEFINE_MUTEX(devlist);
56 LIST_HEAD(cx23885_devlist);
57
58 #define NO_SYNC_LINE (-1U)
59
60 /* FIXME, these allocations will change when
61 * analog arrives. The be reviewed.
62 * CX23887 Assumptions
63 * 1 line = 16 bytes of CDT
64 * cmds size = 80
65 * cdt size = 16 * linesize
66 * iqsize = 64
67 * maxlines = 6
68 *
69 * Address Space:
70 * 0x00000000 0x00008fff FIFO clusters
71 * 0x00010000 0x000104af Channel Management Data Structures
72 * 0x000104b0 0x000104ff Free
73 * 0x00010500 0x000108bf 15 channels * iqsize
74 * 0x000108c0 0x000108ff Free
75 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
76 * 15 channels * (iqsize + (maxlines * linesize))
77 * 0x00010ea0 0x00010xxx Free
78 */
79
80 static struct sram_channel cx23885_sram_channels[] = {
81 [SRAM_CH01] = {
82 .name = "VID A",
83 .cmds_start = 0x10000,
84 .ctrl_start = 0x10380,
85 .cdt = 0x104c0,
86 .fifo_start = 0x40,
87 .fifo_size = 0x2800,
88 .ptr1_reg = DMA1_PTR1,
89 .ptr2_reg = DMA1_PTR2,
90 .cnt1_reg = DMA1_CNT1,
91 .cnt2_reg = DMA1_CNT2,
92 },
93 [SRAM_CH02] = {
94 .name = "ch2",
95 .cmds_start = 0x0,
96 .ctrl_start = 0x0,
97 .cdt = 0x0,
98 .fifo_start = 0x0,
99 .fifo_size = 0x0,
100 .ptr1_reg = DMA2_PTR1,
101 .ptr2_reg = DMA2_PTR2,
102 .cnt1_reg = DMA2_CNT1,
103 .cnt2_reg = DMA2_CNT2,
104 },
105 [SRAM_CH03] = {
106 .name = "TS1 B",
107 .cmds_start = 0x100A0,
108 .ctrl_start = 0x10400,
109 .cdt = 0x10580,
110 .fifo_start = 0x5000,
111 .fifo_size = 0x1000,
112 .ptr1_reg = DMA3_PTR1,
113 .ptr2_reg = DMA3_PTR2,
114 .cnt1_reg = DMA3_CNT1,
115 .cnt2_reg = DMA3_CNT2,
116 },
117 [SRAM_CH04] = {
118 .name = "ch4",
119 .cmds_start = 0x0,
120 .ctrl_start = 0x0,
121 .cdt = 0x0,
122 .fifo_start = 0x0,
123 .fifo_size = 0x0,
124 .ptr1_reg = DMA4_PTR1,
125 .ptr2_reg = DMA4_PTR2,
126 .cnt1_reg = DMA4_CNT1,
127 .cnt2_reg = DMA4_CNT2,
128 },
129 [SRAM_CH05] = {
130 .name = "ch5",
131 .cmds_start = 0x0,
132 .ctrl_start = 0x0,
133 .cdt = 0x0,
134 .fifo_start = 0x0,
135 .fifo_size = 0x0,
136 .ptr1_reg = DMA5_PTR1,
137 .ptr2_reg = DMA5_PTR2,
138 .cnt1_reg = DMA5_CNT1,
139 .cnt2_reg = DMA5_CNT2,
140 },
141 [SRAM_CH06] = {
142 .name = "TS2 C",
143 .cmds_start = 0x10140,
144 .ctrl_start = 0x10440,
145 .cdt = 0x105e0,
146 .fifo_start = 0x6000,
147 .fifo_size = 0x1000,
148 .ptr1_reg = DMA5_PTR1,
149 .ptr2_reg = DMA5_PTR2,
150 .cnt1_reg = DMA5_CNT1,
151 .cnt2_reg = DMA5_CNT2,
152 },
153 [SRAM_CH07] = {
154 .name = "ch7",
155 .cmds_start = 0x0,
156 .ctrl_start = 0x0,
157 .cdt = 0x0,
158 .fifo_start = 0x0,
159 .fifo_size = 0x0,
160 .ptr1_reg = DMA6_PTR1,
161 .ptr2_reg = DMA6_PTR2,
162 .cnt1_reg = DMA6_CNT1,
163 .cnt2_reg = DMA6_CNT2,
164 },
165 [SRAM_CH08] = {
166 .name = "ch8",
167 .cmds_start = 0x0,
168 .ctrl_start = 0x0,
169 .cdt = 0x0,
170 .fifo_start = 0x0,
171 .fifo_size = 0x0,
172 .ptr1_reg = DMA7_PTR1,
173 .ptr2_reg = DMA7_PTR2,
174 .cnt1_reg = DMA7_CNT1,
175 .cnt2_reg = DMA7_CNT2,
176 },
177 [SRAM_CH09] = {
178 .name = "ch9",
179 .cmds_start = 0x0,
180 .ctrl_start = 0x0,
181 .cdt = 0x0,
182 .fifo_start = 0x0,
183 .fifo_size = 0x0,
184 .ptr1_reg = DMA8_PTR1,
185 .ptr2_reg = DMA8_PTR2,
186 .cnt1_reg = DMA8_CNT1,
187 .cnt2_reg = DMA8_CNT2,
188 },
189 };
190
191 static struct sram_channel cx23887_sram_channels[] = {
192 [SRAM_CH01] = {
193 .name = "VID A",
194 .cmds_start = 0x10000,
195 .ctrl_start = 0x105b0,
196 .cdt = 0x107b0,
197 .fifo_start = 0x40,
198 .fifo_size = 0x2800,
199 .ptr1_reg = DMA1_PTR1,
200 .ptr2_reg = DMA1_PTR2,
201 .cnt1_reg = DMA1_CNT1,
202 .cnt2_reg = DMA1_CNT2,
203 },
204 [SRAM_CH02] = {
205 .name = "ch2",
206 .cmds_start = 0x0,
207 .ctrl_start = 0x0,
208 .cdt = 0x0,
209 .fifo_start = 0x0,
210 .fifo_size = 0x0,
211 .ptr1_reg = DMA2_PTR1,
212 .ptr2_reg = DMA2_PTR2,
213 .cnt1_reg = DMA2_CNT1,
214 .cnt2_reg = DMA2_CNT2,
215 },
216 [SRAM_CH03] = {
217 .name = "TS1 B",
218 .cmds_start = 0x100A0,
219 .ctrl_start = 0x10630,
220 .cdt = 0x10870,
221 .fifo_start = 0x5000,
222 .fifo_size = 0x1000,
223 .ptr1_reg = DMA3_PTR1,
224 .ptr2_reg = DMA3_PTR2,
225 .cnt1_reg = DMA3_CNT1,
226 .cnt2_reg = DMA3_CNT2,
227 },
228 [SRAM_CH04] = {
229 .name = "ch4",
230 .cmds_start = 0x0,
231 .ctrl_start = 0x0,
232 .cdt = 0x0,
233 .fifo_start = 0x0,
234 .fifo_size = 0x0,
235 .ptr1_reg = DMA4_PTR1,
236 .ptr2_reg = DMA4_PTR2,
237 .cnt1_reg = DMA4_CNT1,
238 .cnt2_reg = DMA4_CNT2,
239 },
240 [SRAM_CH05] = {
241 .name = "ch5",
242 .cmds_start = 0x0,
243 .ctrl_start = 0x0,
244 .cdt = 0x0,
245 .fifo_start = 0x0,
246 .fifo_size = 0x0,
247 .ptr1_reg = DMA5_PTR1,
248 .ptr2_reg = DMA5_PTR2,
249 .cnt1_reg = DMA5_CNT1,
250 .cnt2_reg = DMA5_CNT2,
251 },
252 [SRAM_CH06] = {
253 .name = "TS2 C",
254 .cmds_start = 0x10140,
255 .ctrl_start = 0x10670,
256 .cdt = 0x108d0,
257 .fifo_start = 0x6000,
258 .fifo_size = 0x1000,
259 .ptr1_reg = DMA5_PTR1,
260 .ptr2_reg = DMA5_PTR2,
261 .cnt1_reg = DMA5_CNT1,
262 .cnt2_reg = DMA5_CNT2,
263 },
264 [SRAM_CH07] = {
265 .name = "ch7",
266 .cmds_start = 0x0,
267 .ctrl_start = 0x0,
268 .cdt = 0x0,
269 .fifo_start = 0x0,
270 .fifo_size = 0x0,
271 .ptr1_reg = DMA6_PTR1,
272 .ptr2_reg = DMA6_PTR2,
273 .cnt1_reg = DMA6_CNT1,
274 .cnt2_reg = DMA6_CNT2,
275 },
276 [SRAM_CH08] = {
277 .name = "ch8",
278 .cmds_start = 0x0,
279 .ctrl_start = 0x0,
280 .cdt = 0x0,
281 .fifo_start = 0x0,
282 .fifo_size = 0x0,
283 .ptr1_reg = DMA7_PTR1,
284 .ptr2_reg = DMA7_PTR2,
285 .cnt1_reg = DMA7_CNT1,
286 .cnt2_reg = DMA7_CNT2,
287 },
288 [SRAM_CH09] = {
289 .name = "ch9",
290 .cmds_start = 0x0,
291 .ctrl_start = 0x0,
292 .cdt = 0x0,
293 .fifo_start = 0x0,
294 .fifo_size = 0x0,
295 .ptr1_reg = DMA8_PTR1,
296 .ptr2_reg = DMA8_PTR2,
297 .cnt1_reg = DMA8_CNT1,
298 .cnt2_reg = DMA8_CNT2,
299 },
300 };
301
302 static int cx23885_risc_decode(u32 risc)
303 {
304 static char *instr[16] = {
305 [RISC_SYNC >> 28] = "sync",
306 [RISC_WRITE >> 28] = "write",
307 [RISC_WRITEC >> 28] = "writec",
308 [RISC_READ >> 28] = "read",
309 [RISC_READC >> 28] = "readc",
310 [RISC_JUMP >> 28] = "jump",
311 [RISC_SKIP >> 28] = "skip",
312 [RISC_WRITERM >> 28] = "writerm",
313 [RISC_WRITECM >> 28] = "writecm",
314 [RISC_WRITECR >> 28] = "writecr",
315 };
316 static int incr[16] = {
317 [RISC_WRITE >> 28] = 3,
318 [RISC_JUMP >> 28] = 3,
319 [RISC_SKIP >> 28] = 1,
320 [RISC_SYNC >> 28] = 1,
321 [RISC_WRITERM >> 28] = 3,
322 [RISC_WRITECM >> 28] = 3,
323 [RISC_WRITECR >> 28] = 4,
324 };
325 static char *bits[] = {
326 "12", "13", "14", "resync",
327 "cnt0", "cnt1", "18", "19",
328 "20", "21", "22", "23",
329 "irq1", "irq2", "eol", "sol",
330 };
331 int i;
332
333 printk("0x%08x [ %s", risc,
334 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
335 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
336 if (risc & (1 << (i + 12)))
337 printk(" %s", bits[i]);
338 printk(" count=%d ]\n", risc & 0xfff);
339 return incr[risc >> 28] ? incr[risc >> 28] : 1;
340 }
341
342 void cx23885_wakeup(struct cx23885_tsport *port,
343 struct cx23885_dmaqueue *q, u32 count)
344 {
345 struct cx23885_dev *dev = port->dev;
346 struct cx23885_buffer *buf;
347 int bc;
348
349 for (bc = 0;; bc++) {
350 if (list_empty(&q->active))
351 break;
352 buf = list_entry(q->active.next,
353 struct cx23885_buffer, vb.queue);
354
355 /* count comes from the hw and is is 16bit wide --
356 * this trick handles wrap-arounds correctly for
357 * up to 32767 buffers in flight... */
358 if ((s16) (count - buf->count) < 0)
359 break;
360
361 do_gettimeofday(&buf->vb.ts);
362 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
363 count, buf->count);
364 buf->vb.state = VIDEOBUF_DONE;
365 list_del(&buf->vb.queue);
366 wake_up(&buf->vb.done);
367 }
368 if (list_empty(&q->active))
369 del_timer(&q->timeout);
370 else
371 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
372 if (bc != 1)
373 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
374 __func__, bc);
375 }
376
377 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
378 struct sram_channel *ch,
379 unsigned int bpl, u32 risc)
380 {
381 unsigned int i, lines;
382 u32 cdt;
383
384 if (ch->cmds_start == 0) {
385 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
386 ch->name);
387 cx_write(ch->ptr1_reg, 0);
388 cx_write(ch->ptr2_reg, 0);
389 cx_write(ch->cnt2_reg, 0);
390 cx_write(ch->cnt1_reg, 0);
391 return 0;
392 } else {
393 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
394 ch->name);
395 }
396
397 bpl = (bpl + 7) & ~7; /* alignment */
398 cdt = ch->cdt;
399 lines = ch->fifo_size / bpl;
400 if (lines > 6)
401 lines = 6;
402 BUG_ON(lines < 2);
403
404 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
405 cx_write(8 + 4, 8);
406 cx_write(8 + 8, 0);
407
408 /* write CDT */
409 for (i = 0; i < lines; i++) {
410 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
411 ch->fifo_start + bpl*i);
412 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
413 cx_write(cdt + 16*i + 4, 0);
414 cx_write(cdt + 16*i + 8, 0);
415 cx_write(cdt + 16*i + 12, 0);
416 }
417
418 /* write CMDS */
419 if (ch->jumponly)
420 cx_write(ch->cmds_start + 0, 8);
421 else
422 cx_write(ch->cmds_start + 0, risc);
423 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
424 cx_write(ch->cmds_start + 8, cdt);
425 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
426 cx_write(ch->cmds_start + 16, ch->ctrl_start);
427 if (ch->jumponly)
428 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
429 else
430 cx_write(ch->cmds_start + 20, 64 >> 2);
431 for (i = 24; i < 80; i += 4)
432 cx_write(ch->cmds_start + i, 0);
433
434 /* fill registers */
435 cx_write(ch->ptr1_reg, ch->fifo_start);
436 cx_write(ch->ptr2_reg, cdt);
437 cx_write(ch->cnt2_reg, (lines*16) >> 3);
438 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
439
440 dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
441 dev->bridge,
442 ch->name,
443 bpl,
444 lines);
445
446 return 0;
447 }
448
449 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
450 struct sram_channel *ch)
451 {
452 static char *name[] = {
453 "init risc lo",
454 "init risc hi",
455 "cdt base",
456 "cdt size",
457 "iq base",
458 "iq size",
459 "risc pc lo",
460 "risc pc hi",
461 "iq wr ptr",
462 "iq rd ptr",
463 "cdt current",
464 "pci target lo",
465 "pci target hi",
466 "line / byte",
467 };
468 u32 risc;
469 unsigned int i, j, n;
470
471 printk(KERN_WARNING "%s: %s - dma channel status dump\n",
472 dev->name, ch->name);
473 for (i = 0; i < ARRAY_SIZE(name); i++)
474 printk(KERN_WARNING "%s: cmds: %-15s: 0x%08x\n",
475 dev->name, name[i],
476 cx_read(ch->cmds_start + 4*i));
477
478 for (i = 0; i < 4; i++) {
479 risc = cx_read(ch->cmds_start + 4 * (i + 14));
480 printk(KERN_WARNING "%s: risc%d: ", dev->name, i);
481 cx23885_risc_decode(risc);
482 }
483 for (i = 0; i < (64 >> 2); i += n) {
484 risc = cx_read(ch->ctrl_start + 4 * i);
485 /* No consideration for bits 63-32 */
486
487 printk(KERN_WARNING "%s: (0x%08x) iq %x: ", dev->name,
488 ch->ctrl_start + 4 * i, i);
489 n = cx23885_risc_decode(risc);
490 for (j = 1; j < n; j++) {
491 risc = cx_read(ch->ctrl_start + 4 * (i + j));
492 printk(KERN_WARNING "%s: iq %x: 0x%08x [ arg #%d ]\n",
493 dev->name, i+j, risc, j);
494 }
495 }
496
497 printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
498 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
499 printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
500 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
501 printk(KERN_WARNING "%s: ptr1_reg: 0x%08x\n",
502 dev->name, cx_read(ch->ptr1_reg));
503 printk(KERN_WARNING "%s: ptr2_reg: 0x%08x\n",
504 dev->name, cx_read(ch->ptr2_reg));
505 printk(KERN_WARNING "%s: cnt1_reg: 0x%08x\n",
506 dev->name, cx_read(ch->cnt1_reg));
507 printk(KERN_WARNING "%s: cnt2_reg: 0x%08x\n",
508 dev->name, cx_read(ch->cnt2_reg));
509 }
510
511 static void cx23885_risc_disasm(struct cx23885_tsport *port,
512 struct btcx_riscmem *risc)
513 {
514 struct cx23885_dev *dev = port->dev;
515 unsigned int i, j, n;
516
517 printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
518 dev->name, risc->cpu, (unsigned long)risc->dma);
519 for (i = 0; i < (risc->size >> 2); i += n) {
520 printk(KERN_INFO "%s: %04d: ", dev->name, i);
521 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
522 for (j = 1; j < n; j++)
523 printk(KERN_INFO "%s: %04d: 0x%08x [ arg #%d ]\n",
524 dev->name, i + j, risc->cpu[i + j], j);
525 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
526 break;
527 }
528 }
529
530 static void cx23885_shutdown(struct cx23885_dev *dev)
531 {
532 /* disable RISC controller */
533 cx_write(DEV_CNTRL2, 0);
534
535 /* Disable all IR activity */
536 cx_write(IR_CNTRL_REG, 0);
537
538 /* Disable Video A/B activity */
539 cx_write(VID_A_DMA_CTL, 0);
540 cx_write(VID_B_DMA_CTL, 0);
541 cx_write(VID_C_DMA_CTL, 0);
542
543 /* Disable Audio activity */
544 cx_write(AUD_INT_DMA_CTL, 0);
545 cx_write(AUD_EXT_DMA_CTL, 0);
546
547 /* Disable Serial port */
548 cx_write(UART_CTL, 0);
549
550 /* Disable Interrupts */
551 cx_write(PCI_INT_MSK, 0);
552 cx_write(VID_A_INT_MSK, 0);
553 cx_write(VID_B_INT_MSK, 0);
554 cx_write(VID_C_INT_MSK, 0);
555 cx_write(AUDIO_INT_INT_MSK, 0);
556 cx_write(AUDIO_EXT_INT_MSK, 0);
557
558 }
559
560 static void cx23885_reset(struct cx23885_dev *dev)
561 {
562 dprintk(1, "%s()\n", __func__);
563
564 cx23885_shutdown(dev);
565
566 cx_write(PCI_INT_STAT, 0xffffffff);
567 cx_write(VID_A_INT_STAT, 0xffffffff);
568 cx_write(VID_B_INT_STAT, 0xffffffff);
569 cx_write(VID_C_INT_STAT, 0xffffffff);
570 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
571 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
572 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
573 cx_write(PAD_CTRL, 0x00500300);
574
575 mdelay(100);
576
577 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
578 720*4, 0);
579 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
580 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
581 188*4, 0);
582 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
583 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
584 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
585 188*4, 0);
586 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
587 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
588 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
589
590 cx23885_gpio_setup(dev);
591 }
592
593
594 static int cx23885_pci_quirks(struct cx23885_dev *dev)
595 {
596 dprintk(1, "%s()\n", __func__);
597
598 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
599 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
600 * occur on the cx23887 bridge.
601 */
602 if (dev->bridge == CX23885_BRIDGE_885)
603 cx_clear(RDR_TLCTL0, 1 << 4);
604
605 return 0;
606 }
607
608 static int get_resources(struct cx23885_dev *dev)
609 {
610 if (request_mem_region(pci_resource_start(dev->pci, 0),
611 pci_resource_len(dev->pci, 0),
612 dev->name))
613 return 0;
614
615 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
616 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
617
618 return -EBUSY;
619 }
620
621 static void cx23885_timeout(unsigned long data);
622 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
623 u32 reg, u32 mask, u32 value);
624
625 static int cx23885_init_tsport(struct cx23885_dev *dev,
626 struct cx23885_tsport *port, int portno)
627 {
628 dprintk(1, "%s(portno=%d)\n", __func__, portno);
629
630 /* Transport bus init dma queue - Common settings */
631 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
632 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
633 port->vld_misc_val = 0x0;
634 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
635
636 spin_lock_init(&port->slock);
637 port->dev = dev;
638 port->nr = portno;
639
640 INIT_LIST_HEAD(&port->mpegq.active);
641 INIT_LIST_HEAD(&port->mpegq.queued);
642 port->mpegq.timeout.function = cx23885_timeout;
643 port->mpegq.timeout.data = (unsigned long)port;
644 init_timer(&port->mpegq.timeout);
645
646 mutex_init(&port->frontends.lock);
647 INIT_LIST_HEAD(&port->frontends.felist);
648 port->frontends.active_fe_id = 0;
649
650 /* This should be hardcoded allow a single frontend
651 * attachment to this tsport, keeping the -dvb.c
652 * code clean and safe.
653 */
654 if (!port->num_frontends)
655 port->num_frontends = 1;
656
657 switch (portno) {
658 case 1:
659 port->reg_gpcnt = VID_B_GPCNT;
660 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
661 port->reg_dma_ctl = VID_B_DMA_CTL;
662 port->reg_lngth = VID_B_LNGTH;
663 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
664 port->reg_gen_ctrl = VID_B_GEN_CTL;
665 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
666 port->reg_sop_status = VID_B_SOP_STATUS;
667 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
668 port->reg_vld_misc = VID_B_VLD_MISC;
669 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
670 port->reg_src_sel = VID_B_SRC_SEL;
671 port->reg_ts_int_msk = VID_B_INT_MSK;
672 port->reg_ts_int_stat = VID_B_INT_STAT;
673 port->sram_chno = SRAM_CH03; /* VID_B */
674 port->pci_irqmask = 0x02; /* VID_B bit1 */
675 break;
676 case 2:
677 port->reg_gpcnt = VID_C_GPCNT;
678 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
679 port->reg_dma_ctl = VID_C_DMA_CTL;
680 port->reg_lngth = VID_C_LNGTH;
681 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
682 port->reg_gen_ctrl = VID_C_GEN_CTL;
683 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
684 port->reg_sop_status = VID_C_SOP_STATUS;
685 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
686 port->reg_vld_misc = VID_C_VLD_MISC;
687 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
688 port->reg_src_sel = 0;
689 port->reg_ts_int_msk = VID_C_INT_MSK;
690 port->reg_ts_int_stat = VID_C_INT_STAT;
691 port->sram_chno = SRAM_CH06; /* VID_C */
692 port->pci_irqmask = 0x04; /* VID_C bit2 */
693 break;
694 default:
695 BUG();
696 }
697
698 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
699 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
700
701 return 0;
702 }
703
704 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
705 {
706 switch (cx_read(RDR_CFG2) & 0xff) {
707 case 0x00:
708 /* cx23885 */
709 dev->hwrevision = 0xa0;
710 break;
711 case 0x01:
712 /* CX23885-12Z */
713 dev->hwrevision = 0xa1;
714 break;
715 case 0x02:
716 /* CX23885-13Z/14Z */
717 dev->hwrevision = 0xb0;
718 break;
719 case 0x03:
720 if (dev->pci->device == 0x8880) {
721 /* CX23888-21Z/22Z */
722 dev->hwrevision = 0xc0;
723 } else {
724 /* CX23885-14Z */
725 dev->hwrevision = 0xa4;
726 }
727 break;
728 case 0x04:
729 if (dev->pci->device == 0x8880) {
730 /* CX23888-31Z */
731 dev->hwrevision = 0xd0;
732 } else {
733 /* CX23885-15Z, CX23888-31Z */
734 dev->hwrevision = 0xa5;
735 }
736 break;
737 case 0x0e:
738 /* CX23887-15Z */
739 dev->hwrevision = 0xc0;
740 case 0x0f:
741 /* CX23887-14Z */
742 dev->hwrevision = 0xb1;
743 break;
744 default:
745 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
746 __func__, dev->hwrevision);
747 }
748 if (dev->hwrevision)
749 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
750 __func__, dev->hwrevision);
751 else
752 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
753 __func__, dev->hwrevision);
754 }
755
756 static int cx23885_dev_setup(struct cx23885_dev *dev)
757 {
758 int i;
759
760 mutex_init(&dev->lock);
761 mutex_init(&dev->gpio_lock);
762
763 atomic_inc(&dev->refcount);
764
765 dev->nr = cx23885_devcount++;
766 sprintf(dev->name, "cx23885[%d]", dev->nr);
767
768 mutex_lock(&devlist);
769 list_add_tail(&dev->devlist, &cx23885_devlist);
770 mutex_unlock(&devlist);
771
772 /* Configure the internal memory */
773 if (dev->pci->device == 0x8880) {
774 /* Could be 887 or 888, assume a default */
775 dev->bridge = CX23885_BRIDGE_887;
776 /* Apply a sensible clock frequency for the PCIe bridge */
777 dev->clk_freq = 25000000;
778 dev->sram_channels = cx23887_sram_channels;
779 } else
780 if (dev->pci->device == 0x8852) {
781 dev->bridge = CX23885_BRIDGE_885;
782 /* Apply a sensible clock frequency for the PCIe bridge */
783 dev->clk_freq = 28000000;
784 dev->sram_channels = cx23885_sram_channels;
785 } else
786 BUG();
787
788 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
789 __func__, dev->bridge);
790
791 /* board config */
792 dev->board = UNSET;
793 if (card[dev->nr] < cx23885_bcount)
794 dev->board = card[dev->nr];
795 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
796 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
797 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
798 dev->board = cx23885_subids[i].card;
799 if (UNSET == dev->board) {
800 dev->board = CX23885_BOARD_UNKNOWN;
801 cx23885_card_list(dev);
802 }
803
804 /* If the user specific a clk freq override, apply it */
805 if (cx23885_boards[dev->board].clk_freq > 0)
806 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
807
808 dev->pci_bus = dev->pci->bus->number;
809 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
810 dev->pci_irqmask = 0x001f00;
811 if (cx23885_boards[dev->board].cimax > 0)
812 dev->pci_irqmask |= 0x01800000; /* for CiMaxes */
813
814 /* External Master 1 Bus */
815 dev->i2c_bus[0].nr = 0;
816 dev->i2c_bus[0].dev = dev;
817 dev->i2c_bus[0].reg_stat = I2C1_STAT;
818 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
819 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
820 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
821 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
822 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
823
824 /* External Master 2 Bus */
825 dev->i2c_bus[1].nr = 1;
826 dev->i2c_bus[1].dev = dev;
827 dev->i2c_bus[1].reg_stat = I2C2_STAT;
828 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
829 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
830 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
831 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
832 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
833
834 /* Internal Master 3 Bus */
835 dev->i2c_bus[2].nr = 2;
836 dev->i2c_bus[2].dev = dev;
837 dev->i2c_bus[2].reg_stat = I2C3_STAT;
838 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
839 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
840 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
841 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
842 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
843
844 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
845 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
846 cx23885_init_tsport(dev, &dev->ts1, 1);
847
848 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
849 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
850 cx23885_init_tsport(dev, &dev->ts2, 2);
851
852 if (get_resources(dev) < 0) {
853 printk(KERN_ERR "CORE %s No more PCIe resources for "
854 "subsystem: %04x:%04x\n",
855 dev->name, dev->pci->subsystem_vendor,
856 dev->pci->subsystem_device);
857
858 cx23885_devcount--;
859 return -ENODEV;
860 }
861
862 /* PCIe stuff */
863 dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
864 pci_resource_len(dev->pci, 0));
865
866 dev->bmmio = (u8 __iomem *)dev->lmmio;
867
868 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
869 dev->name, dev->pci->subsystem_vendor,
870 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
871 dev->board, card[dev->nr] == dev->board ?
872 "insmod option" : "autodetected");
873
874 cx23885_pci_quirks(dev);
875
876 /* Assume some sensible defaults */
877 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
878 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
879 dev->radio_type = cx23885_boards[dev->board].radio_type;
880 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
881
882 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
883 __func__, dev->tuner_type, dev->tuner_addr);
884 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
885 __func__, dev->radio_type, dev->radio_addr);
886
887 /* The cx23417 encoder has GPIO's that need to be initialised
888 * before DVB, so that demodulators and tuners are out of
889 * reset before DVB uses them.
890 */
891 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
892 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
893 cx23885_mc417_init(dev);
894
895 /* init hardware */
896 cx23885_reset(dev);
897
898 cx23885_i2c_register(&dev->i2c_bus[0]);
899 cx23885_i2c_register(&dev->i2c_bus[1]);
900 cx23885_i2c_register(&dev->i2c_bus[2]);
901 cx23885_card_setup(dev);
902 call_all(dev, tuner, s_standby);
903 cx23885_ir_init(dev);
904
905 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
906 if (cx23885_video_register(dev) < 0) {
907 printk(KERN_ERR "%s() Failed to register analog "
908 "video adapters on VID_A\n", __func__);
909 }
910 }
911
912 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
913 if (cx23885_dvb_register(&dev->ts1) < 0) {
914 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
915 __func__);
916 }
917 } else
918 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
919 if (cx23885_417_register(dev) < 0) {
920 printk(KERN_ERR
921 "%s() Failed to register 417 on VID_B\n",
922 __func__);
923 }
924 }
925
926 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
927 if (cx23885_dvb_register(&dev->ts2) < 0) {
928 printk(KERN_ERR
929 "%s() Failed to register dvb on VID_C\n",
930 __func__);
931 }
932 } else
933 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
934 if (cx23885_417_register(dev) < 0) {
935 printk(KERN_ERR
936 "%s() Failed to register 417 on VID_C\n",
937 __func__);
938 }
939 }
940
941 cx23885_dev_checkrevision(dev);
942
943 return 0;
944 }
945
946 static void cx23885_dev_unregister(struct cx23885_dev *dev)
947 {
948 release_mem_region(pci_resource_start(dev->pci, 0),
949 pci_resource_len(dev->pci, 0));
950
951 if (!atomic_dec_and_test(&dev->refcount))
952 return;
953
954 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
955 cx23885_video_unregister(dev);
956
957 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
958 cx23885_dvb_unregister(&dev->ts1);
959
960 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
961 cx23885_417_unregister(dev);
962
963 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
964 cx23885_dvb_unregister(&dev->ts2);
965
966 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
967 cx23885_417_unregister(dev);
968
969 cx23885_i2c_unregister(&dev->i2c_bus[2]);
970 cx23885_i2c_unregister(&dev->i2c_bus[1]);
971 cx23885_i2c_unregister(&dev->i2c_bus[0]);
972
973 iounmap(dev->lmmio);
974 }
975
976 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
977 unsigned int offset, u32 sync_line,
978 unsigned int bpl, unsigned int padding,
979 unsigned int lines)
980 {
981 struct scatterlist *sg;
982 unsigned int line, todo;
983
984 /* sync instruction */
985 if (sync_line != NO_SYNC_LINE)
986 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
987
988 /* scan lines */
989 sg = sglist;
990 for (line = 0; line < lines; line++) {
991 while (offset && offset >= sg_dma_len(sg)) {
992 offset -= sg_dma_len(sg);
993 sg++;
994 }
995 if (bpl <= sg_dma_len(sg)-offset) {
996 /* fits into current chunk */
997 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
998 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
999 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1000 offset += bpl;
1001 } else {
1002 /* scanline needs to be split */
1003 todo = bpl;
1004 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
1005 (sg_dma_len(sg)-offset));
1006 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1007 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1008 todo -= (sg_dma_len(sg)-offset);
1009 offset = 0;
1010 sg++;
1011 while (todo > sg_dma_len(sg)) {
1012 *(rp++) = cpu_to_le32(RISC_WRITE|
1013 sg_dma_len(sg));
1014 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1015 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1016 todo -= sg_dma_len(sg);
1017 sg++;
1018 }
1019 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1020 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1021 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1022 offset += todo;
1023 }
1024 offset += padding;
1025 }
1026
1027 return rp;
1028 }
1029
1030 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1031 struct scatterlist *sglist, unsigned int top_offset,
1032 unsigned int bottom_offset, unsigned int bpl,
1033 unsigned int padding, unsigned int lines)
1034 {
1035 u32 instructions, fields;
1036 __le32 *rp;
1037 int rc;
1038
1039 fields = 0;
1040 if (UNSET != top_offset)
1041 fields++;
1042 if (UNSET != bottom_offset)
1043 fields++;
1044
1045 /* estimate risc mem: worst case is one write per page border +
1046 one write per scan line + syncs + jump (all 2 dwords). Padding
1047 can cause next bpl to start close to a page border. First DMA
1048 region may be smaller than PAGE_SIZE */
1049 /* write and jump need and extra dword */
1050 instructions = fields * (1 + ((bpl + padding) * lines)
1051 / PAGE_SIZE + lines);
1052 instructions += 2;
1053 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1054 if (rc < 0)
1055 return rc;
1056
1057 /* write risc instructions */
1058 rp = risc->cpu;
1059 if (UNSET != top_offset)
1060 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1061 bpl, padding, lines);
1062 if (UNSET != bottom_offset)
1063 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1064 bpl, padding, lines);
1065
1066 /* save pointer to jmp instruction address */
1067 risc->jmp = rp;
1068 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1069 return 0;
1070 }
1071
1072 static int cx23885_risc_databuffer(struct pci_dev *pci,
1073 struct btcx_riscmem *risc,
1074 struct scatterlist *sglist,
1075 unsigned int bpl,
1076 unsigned int lines)
1077 {
1078 u32 instructions;
1079 __le32 *rp;
1080 int rc;
1081
1082 /* estimate risc mem: worst case is one write per page border +
1083 one write per scan line + syncs + jump (all 2 dwords). Here
1084 there is no padding and no sync. First DMA region may be smaller
1085 than PAGE_SIZE */
1086 /* Jump and write need an extra dword */
1087 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1088 instructions += 1;
1089
1090 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1091 if (rc < 0)
1092 return rc;
1093
1094 /* write risc instructions */
1095 rp = risc->cpu;
1096 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1097
1098 /* save pointer to jmp instruction address */
1099 risc->jmp = rp;
1100 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1101 return 0;
1102 }
1103
1104 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1105 u32 reg, u32 mask, u32 value)
1106 {
1107 __le32 *rp;
1108 int rc;
1109
1110 rc = btcx_riscmem_alloc(pci, risc, 4*16);
1111 if (rc < 0)
1112 return rc;
1113
1114 /* write risc instructions */
1115 rp = risc->cpu;
1116 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
1117 *(rp++) = cpu_to_le32(reg);
1118 *(rp++) = cpu_to_le32(value);
1119 *(rp++) = cpu_to_le32(mask);
1120 *(rp++) = cpu_to_le32(RISC_JUMP);
1121 *(rp++) = cpu_to_le32(risc->dma);
1122 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1123 return 0;
1124 }
1125
1126 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1127 {
1128 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1129
1130 BUG_ON(in_interrupt());
1131 videobuf_waiton(&buf->vb, 0, 0);
1132 videobuf_dma_unmap(q, dma);
1133 videobuf_dma_free(dma);
1134 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1135 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1136 }
1137
1138 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1139 {
1140 struct cx23885_dev *dev = port->dev;
1141
1142 dprintk(1, "%s() Register Dump\n", __func__);
1143 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
1144 cx_read(DEV_CNTRL2));
1145 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
1146 cx_read(PCI_INT_MSK));
1147 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
1148 cx_read(AUDIO_INT_INT_MSK));
1149 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
1150 cx_read(AUD_INT_DMA_CTL));
1151 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
1152 cx_read(AUDIO_EXT_INT_MSK));
1153 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
1154 cx_read(AUD_EXT_DMA_CTL));
1155 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
1156 cx_read(PAD_CTRL));
1157 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
1158 cx_read(ALT_PIN_OUT_SEL));
1159 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
1160 cx_read(GPIO2));
1161 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
1162 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1163 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
1164 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1165 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1166 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1167 if (port->reg_src_sel)
1168 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1169 port->reg_src_sel, cx_read(port->reg_src_sel));
1170 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1171 port->reg_lngth, cx_read(port->reg_lngth));
1172 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
1173 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1174 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
1175 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1176 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
1177 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1178 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
1179 port->reg_sop_status, cx_read(port->reg_sop_status));
1180 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1181 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1182 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1183 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1184 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1185 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1186 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1187 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1188 }
1189
1190 static int cx23885_start_dma(struct cx23885_tsport *port,
1191 struct cx23885_dmaqueue *q,
1192 struct cx23885_buffer *buf)
1193 {
1194 struct cx23885_dev *dev = port->dev;
1195 u32 reg;
1196
1197 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1198 buf->vb.width, buf->vb.height, buf->vb.field);
1199
1200 /* Stop the fifo and risc engine for this port */
1201 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1202
1203 /* setup fifo + format */
1204 cx23885_sram_channel_setup(dev,
1205 &dev->sram_channels[port->sram_chno],
1206 port->ts_packet_size, buf->risc.dma);
1207 if (debug > 5) {
1208 cx23885_sram_channel_dump(dev,
1209 &dev->sram_channels[port->sram_chno]);
1210 cx23885_risc_disasm(port, &buf->risc);
1211 }
1212
1213 /* write TS length to chip */
1214 cx_write(port->reg_lngth, buf->vb.width);
1215
1216 if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1217 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1218 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1219 __func__,
1220 cx23885_boards[dev->board].portb,
1221 cx23885_boards[dev->board].portc);
1222 return -EINVAL;
1223 }
1224
1225 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1226 cx23885_av_clk(dev, 0);
1227
1228 udelay(100);
1229
1230 /* If the port supports SRC SELECT, configure it */
1231 if (port->reg_src_sel)
1232 cx_write(port->reg_src_sel, port->src_sel_val);
1233
1234 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1235 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1236 cx_write(port->reg_vld_misc, port->vld_misc_val);
1237 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1238 udelay(100);
1239
1240 /* NOTE: this is 2 (reserved) for portb, does it matter? */
1241 /* reset counter to zero */
1242 cx_write(port->reg_gpcnt_ctl, 3);
1243 q->count = 1;
1244
1245 /* Set VIDB pins to input */
1246 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1247 reg = cx_read(PAD_CTRL);
1248 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1249 cx_write(PAD_CTRL, reg);
1250 }
1251
1252 /* Set VIDC pins to input */
1253 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1254 reg = cx_read(PAD_CTRL);
1255 reg &= ~0x4; /* Clear TS2_SOP_OE */
1256 cx_write(PAD_CTRL, reg);
1257 }
1258
1259 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1260
1261 reg = cx_read(PAD_CTRL);
1262 reg = reg & ~0x1; /* Clear TS1_OE */
1263
1264 /* FIXME, bit 2 writing here is questionable */
1265 /* set TS1_SOP_OE and TS1_OE_HI */
1266 reg = reg | 0xa;
1267 cx_write(PAD_CTRL, reg);
1268
1269 /* FIXME and these two registers should be documented. */
1270 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1271 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1272 }
1273
1274 switch (dev->bridge) {
1275 case CX23885_BRIDGE_885:
1276 case CX23885_BRIDGE_887:
1277 case CX23885_BRIDGE_888:
1278 /* enable irqs */
1279 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1280 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1281 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1282 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1283 break;
1284 default:
1285 BUG();
1286 }
1287
1288 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1289
1290 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1291 cx23885_av_clk(dev, 1);
1292
1293 if (debug > 4)
1294 cx23885_tsport_reg_dump(port);
1295
1296 return 0;
1297 }
1298
1299 static int cx23885_stop_dma(struct cx23885_tsport *port)
1300 {
1301 struct cx23885_dev *dev = port->dev;
1302 u32 reg;
1303
1304 dprintk(1, "%s()\n", __func__);
1305
1306 /* Stop interrupts and DMA */
1307 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1308 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1309
1310 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1311
1312 reg = cx_read(PAD_CTRL);
1313
1314 /* Set TS1_OE */
1315 reg = reg | 0x1;
1316
1317 /* clear TS1_SOP_OE and TS1_OE_HI */
1318 reg = reg & ~0xa;
1319 cx_write(PAD_CTRL, reg);
1320 cx_write(port->reg_src_sel, 0);
1321 cx_write(port->reg_gen_ctrl, 8);
1322
1323 }
1324
1325 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1326 cx23885_av_clk(dev, 0);
1327
1328 return 0;
1329 }
1330
1331 int cx23885_restart_queue(struct cx23885_tsport *port,
1332 struct cx23885_dmaqueue *q)
1333 {
1334 struct cx23885_dev *dev = port->dev;
1335 struct cx23885_buffer *buf;
1336
1337 dprintk(5, "%s()\n", __func__);
1338 if (list_empty(&q->active)) {
1339 struct cx23885_buffer *prev;
1340 prev = NULL;
1341
1342 dprintk(5, "%s() queue is empty\n", __func__);
1343
1344 for (;;) {
1345 if (list_empty(&q->queued))
1346 return 0;
1347 buf = list_entry(q->queued.next, struct cx23885_buffer,
1348 vb.queue);
1349 if (NULL == prev) {
1350 list_del(&buf->vb.queue);
1351 list_add_tail(&buf->vb.queue, &q->active);
1352 cx23885_start_dma(port, q, buf);
1353 buf->vb.state = VIDEOBUF_ACTIVE;
1354 buf->count = q->count++;
1355 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1356 dprintk(5, "[%p/%d] restart_queue - f/active\n",
1357 buf, buf->vb.i);
1358
1359 } else if (prev->vb.width == buf->vb.width &&
1360 prev->vb.height == buf->vb.height &&
1361 prev->fmt == buf->fmt) {
1362 list_del(&buf->vb.queue);
1363 list_add_tail(&buf->vb.queue, &q->active);
1364 buf->vb.state = VIDEOBUF_ACTIVE;
1365 buf->count = q->count++;
1366 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1367 /* 64 bit bits 63-32 */
1368 prev->risc.jmp[2] = cpu_to_le32(0);
1369 dprintk(5, "[%p/%d] restart_queue - m/active\n",
1370 buf, buf->vb.i);
1371 } else {
1372 return 0;
1373 }
1374 prev = buf;
1375 }
1376 return 0;
1377 }
1378
1379 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1380 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1381 buf, buf->vb.i);
1382 cx23885_start_dma(port, q, buf);
1383 list_for_each_entry(buf, &q->active, vb.queue)
1384 buf->count = q->count++;
1385 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1386 return 0;
1387 }
1388
1389 /* ------------------------------------------------------------------ */
1390
1391 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1392 struct cx23885_buffer *buf, enum v4l2_field field)
1393 {
1394 struct cx23885_dev *dev = port->dev;
1395 int size = port->ts_packet_size * port->ts_packet_count;
1396 int rc;
1397
1398 dprintk(1, "%s: %p\n", __func__, buf);
1399 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1400 return -EINVAL;
1401
1402 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1403 buf->vb.width = port->ts_packet_size;
1404 buf->vb.height = port->ts_packet_count;
1405 buf->vb.size = size;
1406 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1407
1408 rc = videobuf_iolock(q, &buf->vb, NULL);
1409 if (0 != rc)
1410 goto fail;
1411 cx23885_risc_databuffer(dev->pci, &buf->risc,
1412 videobuf_to_dma(&buf->vb)->sglist,
1413 buf->vb.width, buf->vb.height);
1414 }
1415 buf->vb.state = VIDEOBUF_PREPARED;
1416 return 0;
1417
1418 fail:
1419 cx23885_free_buffer(q, buf);
1420 return rc;
1421 }
1422
1423 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1424 {
1425 struct cx23885_buffer *prev;
1426 struct cx23885_dev *dev = port->dev;
1427 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1428
1429 /* add jump to stopper */
1430 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1431 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1432 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1433
1434 if (list_empty(&cx88q->active)) {
1435 dprintk(1, "queue is empty - first active\n");
1436 list_add_tail(&buf->vb.queue, &cx88q->active);
1437 cx23885_start_dma(port, cx88q, buf);
1438 buf->vb.state = VIDEOBUF_ACTIVE;
1439 buf->count = cx88q->count++;
1440 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1441 dprintk(1, "[%p/%d] %s - first active\n",
1442 buf, buf->vb.i, __func__);
1443 } else {
1444 dprintk(1, "queue is not empty - append to active\n");
1445 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1446 vb.queue);
1447 list_add_tail(&buf->vb.queue, &cx88q->active);
1448 buf->vb.state = VIDEOBUF_ACTIVE;
1449 buf->count = cx88q->count++;
1450 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1451 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1452 dprintk(1, "[%p/%d] %s - append to active\n",
1453 buf, buf->vb.i, __func__);
1454 }
1455 }
1456
1457 /* ----------------------------------------------------------- */
1458
1459 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1460 int restart)
1461 {
1462 struct cx23885_dev *dev = port->dev;
1463 struct cx23885_dmaqueue *q = &port->mpegq;
1464 struct cx23885_buffer *buf;
1465 unsigned long flags;
1466
1467 spin_lock_irqsave(&port->slock, flags);
1468 while (!list_empty(&q->active)) {
1469 buf = list_entry(q->active.next, struct cx23885_buffer,
1470 vb.queue);
1471 list_del(&buf->vb.queue);
1472 buf->vb.state = VIDEOBUF_ERROR;
1473 wake_up(&buf->vb.done);
1474 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1475 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1476 }
1477 if (restart) {
1478 dprintk(1, "restarting queue\n");
1479 cx23885_restart_queue(port, q);
1480 }
1481 spin_unlock_irqrestore(&port->slock, flags);
1482 }
1483
1484 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1485 {
1486 struct cx23885_dev *dev = port->dev;
1487 struct cx23885_dmaqueue *q = &port->mpegq;
1488
1489 dprintk(1, "%s()\n", __func__);
1490 del_timer_sync(&q->timeout);
1491 cx23885_stop_dma(port);
1492 do_cancel_buffers(port, "cancel", 0);
1493 }
1494
1495 static void cx23885_timeout(unsigned long data)
1496 {
1497 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1498 struct cx23885_dev *dev = port->dev;
1499
1500 dprintk(1, "%s()\n", __func__);
1501
1502 if (debug > 5)
1503 cx23885_sram_channel_dump(dev,
1504 &dev->sram_channels[port->sram_chno]);
1505
1506 cx23885_stop_dma(port);
1507 do_cancel_buffers(port, "timeout", 1);
1508 }
1509
1510 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1511 {
1512 /* FIXME: port1 assumption here. */
1513 struct cx23885_tsport *port = &dev->ts1;
1514 int count = 0;
1515 int handled = 0;
1516
1517 if (status == 0)
1518 return handled;
1519
1520 count = cx_read(port->reg_gpcnt);
1521 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1522 status, cx_read(port->reg_ts_int_msk), count);
1523
1524 if ((status & VID_B_MSK_BAD_PKT) ||
1525 (status & VID_B_MSK_OPC_ERR) ||
1526 (status & VID_B_MSK_VBI_OPC_ERR) ||
1527 (status & VID_B_MSK_SYNC) ||
1528 (status & VID_B_MSK_VBI_SYNC) ||
1529 (status & VID_B_MSK_OF) ||
1530 (status & VID_B_MSK_VBI_OF)) {
1531 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1532 "= 0x%x\n", dev->name, status);
1533 if (status & VID_B_MSK_BAD_PKT)
1534 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1535 if (status & VID_B_MSK_OPC_ERR)
1536 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1537 if (status & VID_B_MSK_VBI_OPC_ERR)
1538 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1539 if (status & VID_B_MSK_SYNC)
1540 dprintk(1, " VID_B_MSK_SYNC\n");
1541 if (status & VID_B_MSK_VBI_SYNC)
1542 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1543 if (status & VID_B_MSK_OF)
1544 dprintk(1, " VID_B_MSK_OF\n");
1545 if (status & VID_B_MSK_VBI_OF)
1546 dprintk(1, " VID_B_MSK_VBI_OF\n");
1547
1548 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1549 cx23885_sram_channel_dump(dev,
1550 &dev->sram_channels[port->sram_chno]);
1551 cx23885_417_check_encoder(dev);
1552 } else if (status & VID_B_MSK_RISCI1) {
1553 dprintk(7, " VID_B_MSK_RISCI1\n");
1554 spin_lock(&port->slock);
1555 cx23885_wakeup(port, &port->mpegq, count);
1556 spin_unlock(&port->slock);
1557 } else if (status & VID_B_MSK_RISCI2) {
1558 dprintk(7, " VID_B_MSK_RISCI2\n");
1559 spin_lock(&port->slock);
1560 cx23885_restart_queue(port, &port->mpegq);
1561 spin_unlock(&port->slock);
1562 }
1563 if (status) {
1564 cx_write(port->reg_ts_int_stat, status);
1565 handled = 1;
1566 }
1567
1568 return handled;
1569 }
1570
1571 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1572 {
1573 struct cx23885_dev *dev = port->dev;
1574 int handled = 0;
1575 u32 count;
1576
1577 if ((status & VID_BC_MSK_OPC_ERR) ||
1578 (status & VID_BC_MSK_BAD_PKT) ||
1579 (status & VID_BC_MSK_SYNC) ||
1580 (status & VID_BC_MSK_OF)) {
1581
1582 if (status & VID_BC_MSK_OPC_ERR)
1583 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1584 VID_BC_MSK_OPC_ERR);
1585
1586 if (status & VID_BC_MSK_BAD_PKT)
1587 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1588 VID_BC_MSK_BAD_PKT);
1589
1590 if (status & VID_BC_MSK_SYNC)
1591 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n",
1592 VID_BC_MSK_SYNC);
1593
1594 if (status & VID_BC_MSK_OF)
1595 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n",
1596 VID_BC_MSK_OF);
1597
1598 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1599
1600 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1601 cx23885_sram_channel_dump(dev,
1602 &dev->sram_channels[port->sram_chno]);
1603
1604 } else if (status & VID_BC_MSK_RISCI1) {
1605
1606 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1607
1608 spin_lock(&port->slock);
1609 count = cx_read(port->reg_gpcnt);
1610 cx23885_wakeup(port, &port->mpegq, count);
1611 spin_unlock(&port->slock);
1612
1613 } else if (status & VID_BC_MSK_RISCI2) {
1614
1615 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1616
1617 spin_lock(&port->slock);
1618 cx23885_restart_queue(port, &port->mpegq);
1619 spin_unlock(&port->slock);
1620
1621 }
1622 if (status) {
1623 cx_write(port->reg_ts_int_stat, status);
1624 handled = 1;
1625 }
1626
1627 return handled;
1628 }
1629
1630 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1631 {
1632 struct cx23885_dev *dev = dev_id;
1633 struct cx23885_tsport *ts1 = &dev->ts1;
1634 struct cx23885_tsport *ts2 = &dev->ts2;
1635 u32 pci_status, pci_mask;
1636 u32 vida_status, vida_mask;
1637 u32 ts1_status, ts1_mask;
1638 u32 ts2_status, ts2_mask;
1639 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1640
1641 pci_status = cx_read(PCI_INT_STAT);
1642 pci_mask = cx_read(PCI_INT_MSK);
1643 vida_status = cx_read(VID_A_INT_STAT);
1644 vida_mask = cx_read(VID_A_INT_MSK);
1645 ts1_status = cx_read(VID_B_INT_STAT);
1646 ts1_mask = cx_read(VID_B_INT_MSK);
1647 ts2_status = cx_read(VID_C_INT_STAT);
1648 ts2_mask = cx_read(VID_C_INT_MSK);
1649
1650 if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1651 goto out;
1652
1653 vida_count = cx_read(VID_A_GPCNT);
1654 ts1_count = cx_read(ts1->reg_gpcnt);
1655 ts2_count = cx_read(ts2->reg_gpcnt);
1656 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1657 pci_status, pci_mask);
1658 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1659 vida_status, vida_mask, vida_count);
1660 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1661 ts1_status, ts1_mask, ts1_count);
1662 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1663 ts2_status, ts2_mask, ts2_count);
1664
1665 if ((pci_status & PCI_MSK_RISC_RD) ||
1666 (pci_status & PCI_MSK_RISC_WR) ||
1667 (pci_status & PCI_MSK_AL_RD) ||
1668 (pci_status & PCI_MSK_AL_WR) ||
1669 (pci_status & PCI_MSK_APB_DMA) ||
1670 (pci_status & PCI_MSK_VID_C) ||
1671 (pci_status & PCI_MSK_VID_B) ||
1672 (pci_status & PCI_MSK_VID_A) ||
1673 (pci_status & PCI_MSK_AUD_INT) ||
1674 (pci_status & PCI_MSK_AUD_EXT) ||
1675 (pci_status & PCI_MSK_GPIO0) ||
1676 (pci_status & PCI_MSK_GPIO1)) {
1677
1678 if (pci_status & PCI_MSK_RISC_RD)
1679 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n",
1680 PCI_MSK_RISC_RD);
1681
1682 if (pci_status & PCI_MSK_RISC_WR)
1683 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n",
1684 PCI_MSK_RISC_WR);
1685
1686 if (pci_status & PCI_MSK_AL_RD)
1687 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n",
1688 PCI_MSK_AL_RD);
1689
1690 if (pci_status & PCI_MSK_AL_WR)
1691 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n",
1692 PCI_MSK_AL_WR);
1693
1694 if (pci_status & PCI_MSK_APB_DMA)
1695 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n",
1696 PCI_MSK_APB_DMA);
1697
1698 if (pci_status & PCI_MSK_VID_C)
1699 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n",
1700 PCI_MSK_VID_C);
1701
1702 if (pci_status & PCI_MSK_VID_B)
1703 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n",
1704 PCI_MSK_VID_B);
1705
1706 if (pci_status & PCI_MSK_VID_A)
1707 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n",
1708 PCI_MSK_VID_A);
1709
1710 if (pci_status & PCI_MSK_AUD_INT)
1711 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n",
1712 PCI_MSK_AUD_INT);
1713
1714 if (pci_status & PCI_MSK_AUD_EXT)
1715 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n",
1716 PCI_MSK_AUD_EXT);
1717
1718 if (pci_status & PCI_MSK_GPIO0)
1719 dprintk(7, " (PCI_MSK_GPIO0 0x%08x)\n",
1720 PCI_MSK_GPIO0);
1721
1722 if (pci_status & PCI_MSK_GPIO1)
1723 dprintk(7, " (PCI_MSK_GPIO1 0x%08x)\n",
1724 PCI_MSK_GPIO1);
1725 }
1726
1727 if (cx23885_boards[dev->board].cimax > 0 &&
1728 ((pci_status & PCI_MSK_GPIO0) ||
1729 (pci_status & PCI_MSK_GPIO1))) {
1730
1731 if (cx23885_boards[dev->board].cimax > 0)
1732 handled += netup_ci_slot_status(dev, pci_status);
1733
1734 }
1735
1736 if (ts1_status) {
1737 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1738 handled += cx23885_irq_ts(ts1, ts1_status);
1739 else
1740 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1741 handled += cx23885_irq_417(dev, ts1_status);
1742 }
1743
1744 if (ts2_status) {
1745 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1746 handled += cx23885_irq_ts(ts2, ts2_status);
1747 else
1748 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1749 handled += cx23885_irq_417(dev, ts2_status);
1750 }
1751
1752 if (vida_status)
1753 handled += cx23885_video_irq(dev, vida_status);
1754
1755 if (handled)
1756 cx_write(PCI_INT_STAT, pci_status);
1757 out:
1758 return IRQ_RETVAL(handled);
1759 }
1760
1761 static inline int encoder_on_portb(struct cx23885_dev *dev)
1762 {
1763 return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1764 }
1765
1766 static inline int encoder_on_portc(struct cx23885_dev *dev)
1767 {
1768 return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1769 }
1770
1771 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1772 * registers depending on the board configuration (and whether the
1773 * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1774 * be pushed into the correct hardware register, regardless of the
1775 * physical location. Certain registers are shared so we sanity check
1776 * and report errors if we think we're tampering with a GPIo that might
1777 * be assigned to the encoder (and used for the host bus).
1778 *
1779 * GPIO 2 thru 0 - On the cx23885 bridge
1780 * GPIO 18 thru 3 - On the cx23417 host bus interface
1781 * GPIO 23 thru 19 - On the cx25840 a/v core
1782 */
1783 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1784 {
1785 if (mask & 0x7)
1786 cx_set(GP0_IO, mask & 0x7);
1787
1788 if (mask & 0x0007fff8) {
1789 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1790 printk(KERN_ERR
1791 "%s: Setting GPIO on encoder ports\n",
1792 dev->name);
1793 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1794 }
1795
1796 /* TODO: 23-19 */
1797 if (mask & 0x00f80000)
1798 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1799 }
1800
1801 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1802 {
1803 if (mask & 0x00000007)
1804 cx_clear(GP0_IO, mask & 0x7);
1805
1806 if (mask & 0x0007fff8) {
1807 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1808 printk(KERN_ERR
1809 "%s: Clearing GPIO moving on encoder ports\n",
1810 dev->name);
1811 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1812 }
1813
1814 /* TODO: 23-19 */
1815 if (mask & 0x00f80000)
1816 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1817 }
1818
1819 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1820 {
1821 if ((mask & 0x00000007) && asoutput)
1822 cx_set(GP0_IO, (mask & 0x7) << 16);
1823 else if ((mask & 0x00000007) && !asoutput)
1824 cx_clear(GP0_IO, (mask & 0x7) << 16);
1825
1826 if (mask & 0x0007fff8) {
1827 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1828 printk(KERN_ERR
1829 "%s: Enabling GPIO on encoder ports\n",
1830 dev->name);
1831 }
1832
1833 /* MC417_OEN is active low for output, write 1 for an input */
1834 if ((mask & 0x0007fff8) && asoutput)
1835 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1836
1837 else if ((mask & 0x0007fff8) && !asoutput)
1838 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1839
1840 /* TODO: 23-19 */
1841 }
1842
1843 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1844 const struct pci_device_id *pci_id)
1845 {
1846 struct cx23885_dev *dev;
1847 int err;
1848
1849 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1850 if (NULL == dev)
1851 return -ENOMEM;
1852
1853 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1854 if (err < 0)
1855 goto fail_free;
1856
1857 /* pci init */
1858 dev->pci = pci_dev;
1859 if (pci_enable_device(pci_dev)) {
1860 err = -EIO;
1861 goto fail_unreg;
1862 }
1863
1864 if (cx23885_dev_setup(dev) < 0) {
1865 err = -EINVAL;
1866 goto fail_unreg;
1867 }
1868
1869 /* print pci info */
1870 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1871 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1872 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1873 "latency: %d, mmio: 0x%llx\n", dev->name,
1874 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1875 dev->pci_lat,
1876 (unsigned long long)pci_resource_start(pci_dev, 0));
1877
1878 pci_set_master(pci_dev);
1879 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1880 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1881 err = -EIO;
1882 goto fail_irq;
1883 }
1884
1885 err = request_irq(pci_dev->irq, cx23885_irq,
1886 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1887 if (err < 0) {
1888 printk(KERN_ERR "%s: can't get IRQ %d\n",
1889 dev->name, pci_dev->irq);
1890 goto fail_irq;
1891 }
1892
1893 switch (dev->board) {
1894 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1895 cx_set(PCI_INT_MSK, 0x01800000); /* for NetUP */
1896 break;
1897 }
1898
1899 return 0;
1900
1901 fail_irq:
1902 cx23885_dev_unregister(dev);
1903 fail_unreg:
1904 v4l2_device_unregister(&dev->v4l2_dev);
1905 fail_free:
1906 kfree(dev);
1907 return err;
1908 }
1909
1910 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1911 {
1912 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1913 struct cx23885_dev *dev = to_cx23885(v4l2_dev);
1914
1915 cx23885_shutdown(dev);
1916
1917 pci_disable_device(pci_dev);
1918
1919 /* unregister stuff */
1920 free_irq(pci_dev->irq, dev);
1921
1922 mutex_lock(&devlist);
1923 list_del(&dev->devlist);
1924 mutex_unlock(&devlist);
1925
1926 cx23885_dev_unregister(dev);
1927 v4l2_device_unregister(v4l2_dev);
1928 kfree(dev);
1929 }
1930
1931 static struct pci_device_id cx23885_pci_tbl[] = {
1932 {
1933 /* CX23885 */
1934 .vendor = 0x14f1,
1935 .device = 0x8852,
1936 .subvendor = PCI_ANY_ID,
1937 .subdevice = PCI_ANY_ID,
1938 }, {
1939 /* CX23887 Rev 2 */
1940 .vendor = 0x14f1,
1941 .device = 0x8880,
1942 .subvendor = PCI_ANY_ID,
1943 .subdevice = PCI_ANY_ID,
1944 }, {
1945 /* --- end of list --- */
1946 }
1947 };
1948 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1949
1950 static struct pci_driver cx23885_pci_driver = {
1951 .name = "cx23885",
1952 .id_table = cx23885_pci_tbl,
1953 .probe = cx23885_initdev,
1954 .remove = __devexit_p(cx23885_finidev),
1955 /* TODO */
1956 .suspend = NULL,
1957 .resume = NULL,
1958 };
1959
1960 static int cx23885_init(void)
1961 {
1962 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1963 (CX23885_VERSION_CODE >> 16) & 0xff,
1964 (CX23885_VERSION_CODE >> 8) & 0xff,
1965 CX23885_VERSION_CODE & 0xff);
1966 #ifdef SNAPSHOT
1967 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1968 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1969 #endif
1970 return pci_register_driver(&cx23885_pci_driver);
1971 }
1972
1973 static void cx23885_fini(void)
1974 {
1975 pci_unregister_driver(&cx23885_pci_driver);
1976 }
1977
1978 module_init(cx23885_init);
1979 module_exit(cx23885_fini);
1980
1981 /* ----------------------------------------------------------- */
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