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Merge branch 'thinkpad' into release
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / cx23885 / cx23885-core.c
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
32
33 #include "cx23885.h"
34 #include "cimax2.h"
35
36 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
37 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
38 MODULE_LICENSE("GPL");
39
40 static unsigned int debug;
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "enable debug messages");
43
44 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
45 module_param_array(card, int, NULL, 0444);
46 MODULE_PARM_DESC(card, "card type");
47
48 #define dprintk(level, fmt, arg...)\
49 do { if (debug >= level)\
50 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
51 } while (0)
52
53 static unsigned int cx23885_devcount;
54
55 static DEFINE_MUTEX(devlist);
56 LIST_HEAD(cx23885_devlist);
57
58 #define NO_SYNC_LINE (-1U)
59
60 /* FIXME, these allocations will change when
61 * analog arrives. The be reviewed.
62 * CX23887 Assumptions
63 * 1 line = 16 bytes of CDT
64 * cmds size = 80
65 * cdt size = 16 * linesize
66 * iqsize = 64
67 * maxlines = 6
68 *
69 * Address Space:
70 * 0x00000000 0x00008fff FIFO clusters
71 * 0x00010000 0x000104af Channel Management Data Structures
72 * 0x000104b0 0x000104ff Free
73 * 0x00010500 0x000108bf 15 channels * iqsize
74 * 0x000108c0 0x000108ff Free
75 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
76 * 15 channels * (iqsize + (maxlines * linesize))
77 * 0x00010ea0 0x00010xxx Free
78 */
79
80 static struct sram_channel cx23885_sram_channels[] = {
81 [SRAM_CH01] = {
82 .name = "VID A",
83 .cmds_start = 0x10000,
84 .ctrl_start = 0x10380,
85 .cdt = 0x104c0,
86 .fifo_start = 0x40,
87 .fifo_size = 0x2800,
88 .ptr1_reg = DMA1_PTR1,
89 .ptr2_reg = DMA1_PTR2,
90 .cnt1_reg = DMA1_CNT1,
91 .cnt2_reg = DMA1_CNT2,
92 },
93 [SRAM_CH02] = {
94 .name = "ch2",
95 .cmds_start = 0x0,
96 .ctrl_start = 0x0,
97 .cdt = 0x0,
98 .fifo_start = 0x0,
99 .fifo_size = 0x0,
100 .ptr1_reg = DMA2_PTR1,
101 .ptr2_reg = DMA2_PTR2,
102 .cnt1_reg = DMA2_CNT1,
103 .cnt2_reg = DMA2_CNT2,
104 },
105 [SRAM_CH03] = {
106 .name = "TS1 B",
107 .cmds_start = 0x100A0,
108 .ctrl_start = 0x10400,
109 .cdt = 0x10580,
110 .fifo_start = 0x5000,
111 .fifo_size = 0x1000,
112 .ptr1_reg = DMA3_PTR1,
113 .ptr2_reg = DMA3_PTR2,
114 .cnt1_reg = DMA3_CNT1,
115 .cnt2_reg = DMA3_CNT2,
116 },
117 [SRAM_CH04] = {
118 .name = "ch4",
119 .cmds_start = 0x0,
120 .ctrl_start = 0x0,
121 .cdt = 0x0,
122 .fifo_start = 0x0,
123 .fifo_size = 0x0,
124 .ptr1_reg = DMA4_PTR1,
125 .ptr2_reg = DMA4_PTR2,
126 .cnt1_reg = DMA4_CNT1,
127 .cnt2_reg = DMA4_CNT2,
128 },
129 [SRAM_CH05] = {
130 .name = "ch5",
131 .cmds_start = 0x0,
132 .ctrl_start = 0x0,
133 .cdt = 0x0,
134 .fifo_start = 0x0,
135 .fifo_size = 0x0,
136 .ptr1_reg = DMA5_PTR1,
137 .ptr2_reg = DMA5_PTR2,
138 .cnt1_reg = DMA5_CNT1,
139 .cnt2_reg = DMA5_CNT2,
140 },
141 [SRAM_CH06] = {
142 .name = "TS2 C",
143 .cmds_start = 0x10140,
144 .ctrl_start = 0x10440,
145 .cdt = 0x105e0,
146 .fifo_start = 0x6000,
147 .fifo_size = 0x1000,
148 .ptr1_reg = DMA5_PTR1,
149 .ptr2_reg = DMA5_PTR2,
150 .cnt1_reg = DMA5_CNT1,
151 .cnt2_reg = DMA5_CNT2,
152 },
153 [SRAM_CH07] = {
154 .name = "ch7",
155 .cmds_start = 0x0,
156 .ctrl_start = 0x0,
157 .cdt = 0x0,
158 .fifo_start = 0x0,
159 .fifo_size = 0x0,
160 .ptr1_reg = DMA6_PTR1,
161 .ptr2_reg = DMA6_PTR2,
162 .cnt1_reg = DMA6_CNT1,
163 .cnt2_reg = DMA6_CNT2,
164 },
165 [SRAM_CH08] = {
166 .name = "ch8",
167 .cmds_start = 0x0,
168 .ctrl_start = 0x0,
169 .cdt = 0x0,
170 .fifo_start = 0x0,
171 .fifo_size = 0x0,
172 .ptr1_reg = DMA7_PTR1,
173 .ptr2_reg = DMA7_PTR2,
174 .cnt1_reg = DMA7_CNT1,
175 .cnt2_reg = DMA7_CNT2,
176 },
177 [SRAM_CH09] = {
178 .name = "ch9",
179 .cmds_start = 0x0,
180 .ctrl_start = 0x0,
181 .cdt = 0x0,
182 .fifo_start = 0x0,
183 .fifo_size = 0x0,
184 .ptr1_reg = DMA8_PTR1,
185 .ptr2_reg = DMA8_PTR2,
186 .cnt1_reg = DMA8_CNT1,
187 .cnt2_reg = DMA8_CNT2,
188 },
189 };
190
191 static struct sram_channel cx23887_sram_channels[] = {
192 [SRAM_CH01] = {
193 .name = "VID A",
194 .cmds_start = 0x10000,
195 .ctrl_start = 0x105b0,
196 .cdt = 0x107b0,
197 .fifo_start = 0x40,
198 .fifo_size = 0x2800,
199 .ptr1_reg = DMA1_PTR1,
200 .ptr2_reg = DMA1_PTR2,
201 .cnt1_reg = DMA1_CNT1,
202 .cnt2_reg = DMA1_CNT2,
203 },
204 [SRAM_CH02] = {
205 .name = "ch2",
206 .cmds_start = 0x0,
207 .ctrl_start = 0x0,
208 .cdt = 0x0,
209 .fifo_start = 0x0,
210 .fifo_size = 0x0,
211 .ptr1_reg = DMA2_PTR1,
212 .ptr2_reg = DMA2_PTR2,
213 .cnt1_reg = DMA2_CNT1,
214 .cnt2_reg = DMA2_CNT2,
215 },
216 [SRAM_CH03] = {
217 .name = "TS1 B",
218 .cmds_start = 0x100A0,
219 .ctrl_start = 0x10630,
220 .cdt = 0x10870,
221 .fifo_start = 0x5000,
222 .fifo_size = 0x1000,
223 .ptr1_reg = DMA3_PTR1,
224 .ptr2_reg = DMA3_PTR2,
225 .cnt1_reg = DMA3_CNT1,
226 .cnt2_reg = DMA3_CNT2,
227 },
228 [SRAM_CH04] = {
229 .name = "ch4",
230 .cmds_start = 0x0,
231 .ctrl_start = 0x0,
232 .cdt = 0x0,
233 .fifo_start = 0x0,
234 .fifo_size = 0x0,
235 .ptr1_reg = DMA4_PTR1,
236 .ptr2_reg = DMA4_PTR2,
237 .cnt1_reg = DMA4_CNT1,
238 .cnt2_reg = DMA4_CNT2,
239 },
240 [SRAM_CH05] = {
241 .name = "ch5",
242 .cmds_start = 0x0,
243 .ctrl_start = 0x0,
244 .cdt = 0x0,
245 .fifo_start = 0x0,
246 .fifo_size = 0x0,
247 .ptr1_reg = DMA5_PTR1,
248 .ptr2_reg = DMA5_PTR2,
249 .cnt1_reg = DMA5_CNT1,
250 .cnt2_reg = DMA5_CNT2,
251 },
252 [SRAM_CH06] = {
253 .name = "TS2 C",
254 .cmds_start = 0x10140,
255 .ctrl_start = 0x10670,
256 .cdt = 0x108d0,
257 .fifo_start = 0x6000,
258 .fifo_size = 0x1000,
259 .ptr1_reg = DMA5_PTR1,
260 .ptr2_reg = DMA5_PTR2,
261 .cnt1_reg = DMA5_CNT1,
262 .cnt2_reg = DMA5_CNT2,
263 },
264 [SRAM_CH07] = {
265 .name = "ch7",
266 .cmds_start = 0x0,
267 .ctrl_start = 0x0,
268 .cdt = 0x0,
269 .fifo_start = 0x0,
270 .fifo_size = 0x0,
271 .ptr1_reg = DMA6_PTR1,
272 .ptr2_reg = DMA6_PTR2,
273 .cnt1_reg = DMA6_CNT1,
274 .cnt2_reg = DMA6_CNT2,
275 },
276 [SRAM_CH08] = {
277 .name = "ch8",
278 .cmds_start = 0x0,
279 .ctrl_start = 0x0,
280 .cdt = 0x0,
281 .fifo_start = 0x0,
282 .fifo_size = 0x0,
283 .ptr1_reg = DMA7_PTR1,
284 .ptr2_reg = DMA7_PTR2,
285 .cnt1_reg = DMA7_CNT1,
286 .cnt2_reg = DMA7_CNT2,
287 },
288 [SRAM_CH09] = {
289 .name = "ch9",
290 .cmds_start = 0x0,
291 .ctrl_start = 0x0,
292 .cdt = 0x0,
293 .fifo_start = 0x0,
294 .fifo_size = 0x0,
295 .ptr1_reg = DMA8_PTR1,
296 .ptr2_reg = DMA8_PTR2,
297 .cnt1_reg = DMA8_CNT1,
298 .cnt2_reg = DMA8_CNT2,
299 },
300 };
301
302 static int cx23885_risc_decode(u32 risc)
303 {
304 static char *instr[16] = {
305 [RISC_SYNC >> 28] = "sync",
306 [RISC_WRITE >> 28] = "write",
307 [RISC_WRITEC >> 28] = "writec",
308 [RISC_READ >> 28] = "read",
309 [RISC_READC >> 28] = "readc",
310 [RISC_JUMP >> 28] = "jump",
311 [RISC_SKIP >> 28] = "skip",
312 [RISC_WRITERM >> 28] = "writerm",
313 [RISC_WRITECM >> 28] = "writecm",
314 [RISC_WRITECR >> 28] = "writecr",
315 };
316 static int incr[16] = {
317 [RISC_WRITE >> 28] = 3,
318 [RISC_JUMP >> 28] = 3,
319 [RISC_SKIP >> 28] = 1,
320 [RISC_SYNC >> 28] = 1,
321 [RISC_WRITERM >> 28] = 3,
322 [RISC_WRITECM >> 28] = 3,
323 [RISC_WRITECR >> 28] = 4,
324 };
325 static char *bits[] = {
326 "12", "13", "14", "resync",
327 "cnt0", "cnt1", "18", "19",
328 "20", "21", "22", "23",
329 "irq1", "irq2", "eol", "sol",
330 };
331 int i;
332
333 printk("0x%08x [ %s", risc,
334 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
335 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
336 if (risc & (1 << (i + 12)))
337 printk(" %s", bits[i]);
338 printk(" count=%d ]\n", risc & 0xfff);
339 return incr[risc >> 28] ? incr[risc >> 28] : 1;
340 }
341
342 void cx23885_wakeup(struct cx23885_tsport *port,
343 struct cx23885_dmaqueue *q, u32 count)
344 {
345 struct cx23885_dev *dev = port->dev;
346 struct cx23885_buffer *buf;
347 int bc;
348
349 for (bc = 0;; bc++) {
350 if (list_empty(&q->active))
351 break;
352 buf = list_entry(q->active.next,
353 struct cx23885_buffer, vb.queue);
354
355 /* count comes from the hw and is is 16bit wide --
356 * this trick handles wrap-arounds correctly for
357 * up to 32767 buffers in flight... */
358 if ((s16) (count - buf->count) < 0)
359 break;
360
361 do_gettimeofday(&buf->vb.ts);
362 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
363 count, buf->count);
364 buf->vb.state = VIDEOBUF_DONE;
365 list_del(&buf->vb.queue);
366 wake_up(&buf->vb.done);
367 }
368 if (list_empty(&q->active))
369 del_timer(&q->timeout);
370 else
371 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
372 if (bc != 1)
373 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
374 __func__, bc);
375 }
376
377 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
378 struct sram_channel *ch,
379 unsigned int bpl, u32 risc)
380 {
381 unsigned int i, lines;
382 u32 cdt;
383
384 if (ch->cmds_start == 0) {
385 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
386 ch->name);
387 cx_write(ch->ptr1_reg, 0);
388 cx_write(ch->ptr2_reg, 0);
389 cx_write(ch->cnt2_reg, 0);
390 cx_write(ch->cnt1_reg, 0);
391 return 0;
392 } else {
393 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
394 ch->name);
395 }
396
397 bpl = (bpl + 7) & ~7; /* alignment */
398 cdt = ch->cdt;
399 lines = ch->fifo_size / bpl;
400 if (lines > 6)
401 lines = 6;
402 BUG_ON(lines < 2);
403
404 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
405 cx_write(8 + 4, 8);
406 cx_write(8 + 8, 0);
407
408 /* write CDT */
409 for (i = 0; i < lines; i++) {
410 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
411 ch->fifo_start + bpl*i);
412 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
413 cx_write(cdt + 16*i + 4, 0);
414 cx_write(cdt + 16*i + 8, 0);
415 cx_write(cdt + 16*i + 12, 0);
416 }
417
418 /* write CMDS */
419 if (ch->jumponly)
420 cx_write(ch->cmds_start + 0, 8);
421 else
422 cx_write(ch->cmds_start + 0, risc);
423 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
424 cx_write(ch->cmds_start + 8, cdt);
425 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
426 cx_write(ch->cmds_start + 16, ch->ctrl_start);
427 if (ch->jumponly)
428 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
429 else
430 cx_write(ch->cmds_start + 20, 64 >> 2);
431 for (i = 24; i < 80; i += 4)
432 cx_write(ch->cmds_start + i, 0);
433
434 /* fill registers */
435 cx_write(ch->ptr1_reg, ch->fifo_start);
436 cx_write(ch->ptr2_reg, cdt);
437 cx_write(ch->cnt2_reg, (lines*16) >> 3);
438 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
439
440 dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
441 dev->bridge,
442 ch->name,
443 bpl,
444 lines);
445
446 return 0;
447 }
448
449 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
450 struct sram_channel *ch)
451 {
452 static char *name[] = {
453 "init risc lo",
454 "init risc hi",
455 "cdt base",
456 "cdt size",
457 "iq base",
458 "iq size",
459 "risc pc lo",
460 "risc pc hi",
461 "iq wr ptr",
462 "iq rd ptr",
463 "cdt current",
464 "pci target lo",
465 "pci target hi",
466 "line / byte",
467 };
468 u32 risc;
469 unsigned int i, j, n;
470
471 printk(KERN_WARNING "%s: %s - dma channel status dump\n",
472 dev->name, ch->name);
473 for (i = 0; i < ARRAY_SIZE(name); i++)
474 printk(KERN_WARNING "%s: cmds: %-15s: 0x%08x\n",
475 dev->name, name[i],
476 cx_read(ch->cmds_start + 4*i));
477
478 for (i = 0; i < 4; i++) {
479 risc = cx_read(ch->cmds_start + 4 * (i + 14));
480 printk(KERN_WARNING "%s: risc%d: ", dev->name, i);
481 cx23885_risc_decode(risc);
482 }
483 for (i = 0; i < (64 >> 2); i += n) {
484 risc = cx_read(ch->ctrl_start + 4 * i);
485 /* No consideration for bits 63-32 */
486
487 printk(KERN_WARNING "%s: (0x%08x) iq %x: ", dev->name,
488 ch->ctrl_start + 4 * i, i);
489 n = cx23885_risc_decode(risc);
490 for (j = 1; j < n; j++) {
491 risc = cx_read(ch->ctrl_start + 4 * (i + j));
492 printk(KERN_WARNING "%s: iq %x: 0x%08x [ arg #%d ]\n",
493 dev->name, i+j, risc, j);
494 }
495 }
496
497 printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
498 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
499 printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
500 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
501 printk(KERN_WARNING "%s: ptr1_reg: 0x%08x\n",
502 dev->name, cx_read(ch->ptr1_reg));
503 printk(KERN_WARNING "%s: ptr2_reg: 0x%08x\n",
504 dev->name, cx_read(ch->ptr2_reg));
505 printk(KERN_WARNING "%s: cnt1_reg: 0x%08x\n",
506 dev->name, cx_read(ch->cnt1_reg));
507 printk(KERN_WARNING "%s: cnt2_reg: 0x%08x\n",
508 dev->name, cx_read(ch->cnt2_reg));
509 }
510
511 static void cx23885_risc_disasm(struct cx23885_tsport *port,
512 struct btcx_riscmem *risc)
513 {
514 struct cx23885_dev *dev = port->dev;
515 unsigned int i, j, n;
516
517 printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
518 dev->name, risc->cpu, (unsigned long)risc->dma);
519 for (i = 0; i < (risc->size >> 2); i += n) {
520 printk(KERN_INFO "%s: %04d: ", dev->name, i);
521 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
522 for (j = 1; j < n; j++)
523 printk(KERN_INFO "%s: %04d: 0x%08x [ arg #%d ]\n",
524 dev->name, i + j, risc->cpu[i + j], j);
525 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
526 break;
527 }
528 }
529
530 static void cx23885_shutdown(struct cx23885_dev *dev)
531 {
532 /* disable RISC controller */
533 cx_write(DEV_CNTRL2, 0);
534
535 /* Disable all IR activity */
536 cx_write(IR_CNTRL_REG, 0);
537
538 /* Disable Video A/B activity */
539 cx_write(VID_A_DMA_CTL, 0);
540 cx_write(VID_B_DMA_CTL, 0);
541 cx_write(VID_C_DMA_CTL, 0);
542
543 /* Disable Audio activity */
544 cx_write(AUD_INT_DMA_CTL, 0);
545 cx_write(AUD_EXT_DMA_CTL, 0);
546
547 /* Disable Serial port */
548 cx_write(UART_CTL, 0);
549
550 /* Disable Interrupts */
551 cx_write(PCI_INT_MSK, 0);
552 cx_write(VID_A_INT_MSK, 0);
553 cx_write(VID_B_INT_MSK, 0);
554 cx_write(VID_C_INT_MSK, 0);
555 cx_write(AUDIO_INT_INT_MSK, 0);
556 cx_write(AUDIO_EXT_INT_MSK, 0);
557
558 }
559
560 static void cx23885_reset(struct cx23885_dev *dev)
561 {
562 dprintk(1, "%s()\n", __func__);
563
564 cx23885_shutdown(dev);
565
566 cx_write(PCI_INT_STAT, 0xffffffff);
567 cx_write(VID_A_INT_STAT, 0xffffffff);
568 cx_write(VID_B_INT_STAT, 0xffffffff);
569 cx_write(VID_C_INT_STAT, 0xffffffff);
570 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
571 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
572 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
573 cx_write(PAD_CTRL, 0x00500300);
574
575 mdelay(100);
576
577 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
578 720*4, 0);
579 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
580 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
581 188*4, 0);
582 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
583 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
584 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
585 188*4, 0);
586 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
587 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
588 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
589
590 cx23885_gpio_setup(dev);
591 }
592
593
594 static int cx23885_pci_quirks(struct cx23885_dev *dev)
595 {
596 dprintk(1, "%s()\n", __func__);
597
598 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
599 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
600 * occur on the cx23887 bridge.
601 */
602 if (dev->bridge == CX23885_BRIDGE_885)
603 cx_clear(RDR_TLCTL0, 1 << 4);
604
605 return 0;
606 }
607
608 static int get_resources(struct cx23885_dev *dev)
609 {
610 if (request_mem_region(pci_resource_start(dev->pci, 0),
611 pci_resource_len(dev->pci, 0),
612 dev->name))
613 return 0;
614
615 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
616 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
617
618 return -EBUSY;
619 }
620
621 static void cx23885_timeout(unsigned long data);
622 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
623 u32 reg, u32 mask, u32 value);
624
625 static int cx23885_init_tsport(struct cx23885_dev *dev,
626 struct cx23885_tsport *port, int portno)
627 {
628 dprintk(1, "%s(portno=%d)\n", __func__, portno);
629
630 /* Transport bus init dma queue - Common settings */
631 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
632 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
633 port->vld_misc_val = 0x0;
634 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
635
636 spin_lock_init(&port->slock);
637 port->dev = dev;
638 port->nr = portno;
639
640 INIT_LIST_HEAD(&port->mpegq.active);
641 INIT_LIST_HEAD(&port->mpegq.queued);
642 port->mpegq.timeout.function = cx23885_timeout;
643 port->mpegq.timeout.data = (unsigned long)port;
644 init_timer(&port->mpegq.timeout);
645
646 mutex_init(&port->frontends.lock);
647 INIT_LIST_HEAD(&port->frontends.felist);
648 port->frontends.active_fe_id = 0;
649
650 /* This should be hardcoded allow a single frontend
651 * attachment to this tsport, keeping the -dvb.c
652 * code clean and safe.
653 */
654 if (!port->num_frontends)
655 port->num_frontends = 1;
656
657 switch (portno) {
658 case 1:
659 port->reg_gpcnt = VID_B_GPCNT;
660 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
661 port->reg_dma_ctl = VID_B_DMA_CTL;
662 port->reg_lngth = VID_B_LNGTH;
663 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
664 port->reg_gen_ctrl = VID_B_GEN_CTL;
665 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
666 port->reg_sop_status = VID_B_SOP_STATUS;
667 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
668 port->reg_vld_misc = VID_B_VLD_MISC;
669 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
670 port->reg_src_sel = VID_B_SRC_SEL;
671 port->reg_ts_int_msk = VID_B_INT_MSK;
672 port->reg_ts_int_stat = VID_B_INT_STAT;
673 port->sram_chno = SRAM_CH03; /* VID_B */
674 port->pci_irqmask = 0x02; /* VID_B bit1 */
675 break;
676 case 2:
677 port->reg_gpcnt = VID_C_GPCNT;
678 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
679 port->reg_dma_ctl = VID_C_DMA_CTL;
680 port->reg_lngth = VID_C_LNGTH;
681 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
682 port->reg_gen_ctrl = VID_C_GEN_CTL;
683 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
684 port->reg_sop_status = VID_C_SOP_STATUS;
685 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
686 port->reg_vld_misc = VID_C_VLD_MISC;
687 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
688 port->reg_src_sel = 0;
689 port->reg_ts_int_msk = VID_C_INT_MSK;
690 port->reg_ts_int_stat = VID_C_INT_STAT;
691 port->sram_chno = SRAM_CH06; /* VID_C */
692 port->pci_irqmask = 0x04; /* VID_C bit2 */
693 break;
694 default:
695 BUG();
696 }
697
698 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
699 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
700
701 return 0;
702 }
703
704 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
705 {
706 switch (cx_read(RDR_CFG2) & 0xff) {
707 case 0x00:
708 /* cx23885 */
709 dev->hwrevision = 0xa0;
710 break;
711 case 0x01:
712 /* CX23885-12Z */
713 dev->hwrevision = 0xa1;
714 break;
715 case 0x02:
716 /* CX23885-13Z/14Z */
717 dev->hwrevision = 0xb0;
718 break;
719 case 0x03:
720 if (dev->pci->device == 0x8880) {
721 /* CX23888-21Z/22Z */
722 dev->hwrevision = 0xc0;
723 } else {
724 /* CX23885-14Z */
725 dev->hwrevision = 0xa4;
726 }
727 break;
728 case 0x04:
729 if (dev->pci->device == 0x8880) {
730 /* CX23888-31Z */
731 dev->hwrevision = 0xd0;
732 } else {
733 /* CX23885-15Z, CX23888-31Z */
734 dev->hwrevision = 0xa5;
735 }
736 break;
737 case 0x0e:
738 /* CX23887-15Z */
739 dev->hwrevision = 0xc0;
740 case 0x0f:
741 /* CX23887-14Z */
742 dev->hwrevision = 0xb1;
743 break;
744 default:
745 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
746 __func__, dev->hwrevision);
747 }
748 if (dev->hwrevision)
749 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
750 __func__, dev->hwrevision);
751 else
752 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
753 __func__, dev->hwrevision);
754 }
755
756 static int cx23885_dev_setup(struct cx23885_dev *dev)
757 {
758 int i;
759
760 mutex_init(&dev->lock);
761
762 atomic_inc(&dev->refcount);
763
764 dev->nr = cx23885_devcount++;
765 sprintf(dev->name, "cx23885[%d]", dev->nr);
766
767 mutex_lock(&devlist);
768 list_add_tail(&dev->devlist, &cx23885_devlist);
769 mutex_unlock(&devlist);
770
771 /* Configure the internal memory */
772 if (dev->pci->device == 0x8880) {
773 /* Could be 887 or 888, assume a default */
774 dev->bridge = CX23885_BRIDGE_887;
775 /* Apply a sensible clock frequency for the PCIe bridge */
776 dev->clk_freq = 25000000;
777 dev->sram_channels = cx23887_sram_channels;
778 } else
779 if (dev->pci->device == 0x8852) {
780 dev->bridge = CX23885_BRIDGE_885;
781 /* Apply a sensible clock frequency for the PCIe bridge */
782 dev->clk_freq = 28000000;
783 dev->sram_channels = cx23885_sram_channels;
784 } else
785 BUG();
786
787 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
788 __func__, dev->bridge);
789
790 /* board config */
791 dev->board = UNSET;
792 if (card[dev->nr] < cx23885_bcount)
793 dev->board = card[dev->nr];
794 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
795 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
796 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
797 dev->board = cx23885_subids[i].card;
798 if (UNSET == dev->board) {
799 dev->board = CX23885_BOARD_UNKNOWN;
800 cx23885_card_list(dev);
801 }
802
803 /* If the user specific a clk freq override, apply it */
804 if (cx23885_boards[dev->board].clk_freq > 0)
805 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
806
807 dev->pci_bus = dev->pci->bus->number;
808 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
809 dev->pci_irqmask = 0x001f00;
810 if (cx23885_boards[dev->board].cimax > 0)
811 dev->pci_irqmask |= 0x01800000; /* for CiMaxes */
812
813 /* External Master 1 Bus */
814 dev->i2c_bus[0].nr = 0;
815 dev->i2c_bus[0].dev = dev;
816 dev->i2c_bus[0].reg_stat = I2C1_STAT;
817 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
818 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
819 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
820 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
821 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
822
823 /* External Master 2 Bus */
824 dev->i2c_bus[1].nr = 1;
825 dev->i2c_bus[1].dev = dev;
826 dev->i2c_bus[1].reg_stat = I2C2_STAT;
827 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
828 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
829 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
830 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
831 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
832
833 /* Internal Master 3 Bus */
834 dev->i2c_bus[2].nr = 2;
835 dev->i2c_bus[2].dev = dev;
836 dev->i2c_bus[2].reg_stat = I2C3_STAT;
837 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
838 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
839 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
840 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
841 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
842
843 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
844 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
845 cx23885_init_tsport(dev, &dev->ts1, 1);
846
847 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
848 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
849 cx23885_init_tsport(dev, &dev->ts2, 2);
850
851 if (get_resources(dev) < 0) {
852 printk(KERN_ERR "CORE %s No more PCIe resources for "
853 "subsystem: %04x:%04x\n",
854 dev->name, dev->pci->subsystem_vendor,
855 dev->pci->subsystem_device);
856
857 cx23885_devcount--;
858 return -ENODEV;
859 }
860
861 /* PCIe stuff */
862 dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
863 pci_resource_len(dev->pci, 0));
864
865 dev->bmmio = (u8 __iomem *)dev->lmmio;
866
867 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
868 dev->name, dev->pci->subsystem_vendor,
869 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
870 dev->board, card[dev->nr] == dev->board ?
871 "insmod option" : "autodetected");
872
873 cx23885_pci_quirks(dev);
874
875 /* Assume some sensible defaults */
876 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
877 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
878 dev->radio_type = cx23885_boards[dev->board].radio_type;
879 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
880
881 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
882 __func__, dev->tuner_type, dev->tuner_addr);
883 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
884 __func__, dev->radio_type, dev->radio_addr);
885
886 /* The cx23417 encoder has GPIO's that need to be initialised
887 * before DVB, so that demodulators and tuners are out of
888 * reset before DVB uses them.
889 */
890 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
891 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
892 cx23885_mc417_init(dev);
893
894 /* init hardware */
895 cx23885_reset(dev);
896
897 cx23885_i2c_register(&dev->i2c_bus[0]);
898 cx23885_i2c_register(&dev->i2c_bus[1]);
899 cx23885_i2c_register(&dev->i2c_bus[2]);
900 cx23885_card_setup(dev);
901 call_all(dev, tuner, s_standby);
902 cx23885_ir_init(dev);
903
904 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
905 if (cx23885_video_register(dev) < 0) {
906 printk(KERN_ERR "%s() Failed to register analog "
907 "video adapters on VID_A\n", __func__);
908 }
909 }
910
911 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
912 if (cx23885_dvb_register(&dev->ts1) < 0) {
913 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
914 __func__);
915 }
916 } else
917 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
918 if (cx23885_417_register(dev) < 0) {
919 printk(KERN_ERR
920 "%s() Failed to register 417 on VID_B\n",
921 __func__);
922 }
923 }
924
925 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
926 if (cx23885_dvb_register(&dev->ts2) < 0) {
927 printk(KERN_ERR
928 "%s() Failed to register dvb on VID_C\n",
929 __func__);
930 }
931 } else
932 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
933 if (cx23885_417_register(dev) < 0) {
934 printk(KERN_ERR
935 "%s() Failed to register 417 on VID_C\n",
936 __func__);
937 }
938 }
939
940 cx23885_dev_checkrevision(dev);
941
942 return 0;
943 }
944
945 static void cx23885_dev_unregister(struct cx23885_dev *dev)
946 {
947 release_mem_region(pci_resource_start(dev->pci, 0),
948 pci_resource_len(dev->pci, 0));
949
950 if (!atomic_dec_and_test(&dev->refcount))
951 return;
952
953 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
954 cx23885_video_unregister(dev);
955
956 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
957 cx23885_dvb_unregister(&dev->ts1);
958
959 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
960 cx23885_417_unregister(dev);
961
962 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
963 cx23885_dvb_unregister(&dev->ts2);
964
965 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
966 cx23885_417_unregister(dev);
967
968 cx23885_i2c_unregister(&dev->i2c_bus[2]);
969 cx23885_i2c_unregister(&dev->i2c_bus[1]);
970 cx23885_i2c_unregister(&dev->i2c_bus[0]);
971
972 iounmap(dev->lmmio);
973 }
974
975 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
976 unsigned int offset, u32 sync_line,
977 unsigned int bpl, unsigned int padding,
978 unsigned int lines)
979 {
980 struct scatterlist *sg;
981 unsigned int line, todo;
982
983 /* sync instruction */
984 if (sync_line != NO_SYNC_LINE)
985 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
986
987 /* scan lines */
988 sg = sglist;
989 for (line = 0; line < lines; line++) {
990 while (offset && offset >= sg_dma_len(sg)) {
991 offset -= sg_dma_len(sg);
992 sg++;
993 }
994 if (bpl <= sg_dma_len(sg)-offset) {
995 /* fits into current chunk */
996 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
997 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
998 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
999 offset += bpl;
1000 } else {
1001 /* scanline needs to be split */
1002 todo = bpl;
1003 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
1004 (sg_dma_len(sg)-offset));
1005 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1006 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1007 todo -= (sg_dma_len(sg)-offset);
1008 offset = 0;
1009 sg++;
1010 while (todo > sg_dma_len(sg)) {
1011 *(rp++) = cpu_to_le32(RISC_WRITE|
1012 sg_dma_len(sg));
1013 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1014 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1015 todo -= sg_dma_len(sg);
1016 sg++;
1017 }
1018 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1019 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1020 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1021 offset += todo;
1022 }
1023 offset += padding;
1024 }
1025
1026 return rp;
1027 }
1028
1029 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1030 struct scatterlist *sglist, unsigned int top_offset,
1031 unsigned int bottom_offset, unsigned int bpl,
1032 unsigned int padding, unsigned int lines)
1033 {
1034 u32 instructions, fields;
1035 __le32 *rp;
1036 int rc;
1037
1038 fields = 0;
1039 if (UNSET != top_offset)
1040 fields++;
1041 if (UNSET != bottom_offset)
1042 fields++;
1043
1044 /* estimate risc mem: worst case is one write per page border +
1045 one write per scan line + syncs + jump (all 2 dwords). Padding
1046 can cause next bpl to start close to a page border. First DMA
1047 region may be smaller than PAGE_SIZE */
1048 /* write and jump need and extra dword */
1049 instructions = fields * (1 + ((bpl + padding) * lines)
1050 / PAGE_SIZE + lines);
1051 instructions += 2;
1052 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1053 if (rc < 0)
1054 return rc;
1055
1056 /* write risc instructions */
1057 rp = risc->cpu;
1058 if (UNSET != top_offset)
1059 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1060 bpl, padding, lines);
1061 if (UNSET != bottom_offset)
1062 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1063 bpl, padding, lines);
1064
1065 /* save pointer to jmp instruction address */
1066 risc->jmp = rp;
1067 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1068 return 0;
1069 }
1070
1071 static int cx23885_risc_databuffer(struct pci_dev *pci,
1072 struct btcx_riscmem *risc,
1073 struct scatterlist *sglist,
1074 unsigned int bpl,
1075 unsigned int lines)
1076 {
1077 u32 instructions;
1078 __le32 *rp;
1079 int rc;
1080
1081 /* estimate risc mem: worst case is one write per page border +
1082 one write per scan line + syncs + jump (all 2 dwords). Here
1083 there is no padding and no sync. First DMA region may be smaller
1084 than PAGE_SIZE */
1085 /* Jump and write need an extra dword */
1086 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1087 instructions += 1;
1088
1089 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1090 if (rc < 0)
1091 return rc;
1092
1093 /* write risc instructions */
1094 rp = risc->cpu;
1095 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1096
1097 /* save pointer to jmp instruction address */
1098 risc->jmp = rp;
1099 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1100 return 0;
1101 }
1102
1103 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1104 u32 reg, u32 mask, u32 value)
1105 {
1106 __le32 *rp;
1107 int rc;
1108
1109 rc = btcx_riscmem_alloc(pci, risc, 4*16);
1110 if (rc < 0)
1111 return rc;
1112
1113 /* write risc instructions */
1114 rp = risc->cpu;
1115 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
1116 *(rp++) = cpu_to_le32(reg);
1117 *(rp++) = cpu_to_le32(value);
1118 *(rp++) = cpu_to_le32(mask);
1119 *(rp++) = cpu_to_le32(RISC_JUMP);
1120 *(rp++) = cpu_to_le32(risc->dma);
1121 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1122 return 0;
1123 }
1124
1125 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1126 {
1127 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1128
1129 BUG_ON(in_interrupt());
1130 videobuf_waiton(&buf->vb, 0, 0);
1131 videobuf_dma_unmap(q, dma);
1132 videobuf_dma_free(dma);
1133 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1134 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1135 }
1136
1137 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1138 {
1139 struct cx23885_dev *dev = port->dev;
1140
1141 dprintk(1, "%s() Register Dump\n", __func__);
1142 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
1143 cx_read(DEV_CNTRL2));
1144 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
1145 cx_read(PCI_INT_MSK));
1146 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
1147 cx_read(AUDIO_INT_INT_MSK));
1148 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
1149 cx_read(AUD_INT_DMA_CTL));
1150 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
1151 cx_read(AUDIO_EXT_INT_MSK));
1152 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
1153 cx_read(AUD_EXT_DMA_CTL));
1154 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
1155 cx_read(PAD_CTRL));
1156 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
1157 cx_read(ALT_PIN_OUT_SEL));
1158 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
1159 cx_read(GPIO2));
1160 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
1161 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1162 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
1163 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1164 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1165 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1166 if (port->reg_src_sel)
1167 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1168 port->reg_src_sel, cx_read(port->reg_src_sel));
1169 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1170 port->reg_lngth, cx_read(port->reg_lngth));
1171 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
1172 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1173 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
1174 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1175 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
1176 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1177 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
1178 port->reg_sop_status, cx_read(port->reg_sop_status));
1179 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1180 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1181 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1182 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1183 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1184 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1185 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1186 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1187 }
1188
1189 static int cx23885_start_dma(struct cx23885_tsport *port,
1190 struct cx23885_dmaqueue *q,
1191 struct cx23885_buffer *buf)
1192 {
1193 struct cx23885_dev *dev = port->dev;
1194 u32 reg;
1195
1196 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1197 buf->vb.width, buf->vb.height, buf->vb.field);
1198
1199 /* Stop the fifo and risc engine for this port */
1200 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1201
1202 /* setup fifo + format */
1203 cx23885_sram_channel_setup(dev,
1204 &dev->sram_channels[port->sram_chno],
1205 port->ts_packet_size, buf->risc.dma);
1206 if (debug > 5) {
1207 cx23885_sram_channel_dump(dev,
1208 &dev->sram_channels[port->sram_chno]);
1209 cx23885_risc_disasm(port, &buf->risc);
1210 }
1211
1212 /* write TS length to chip */
1213 cx_write(port->reg_lngth, buf->vb.width);
1214
1215 if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1216 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1217 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1218 __func__,
1219 cx23885_boards[dev->board].portb,
1220 cx23885_boards[dev->board].portc);
1221 return -EINVAL;
1222 }
1223
1224 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1225 cx23885_av_clk(dev, 0);
1226
1227 udelay(100);
1228
1229 /* If the port supports SRC SELECT, configure it */
1230 if (port->reg_src_sel)
1231 cx_write(port->reg_src_sel, port->src_sel_val);
1232
1233 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1234 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1235 cx_write(port->reg_vld_misc, port->vld_misc_val);
1236 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1237 udelay(100);
1238
1239 /* NOTE: this is 2 (reserved) for portb, does it matter? */
1240 /* reset counter to zero */
1241 cx_write(port->reg_gpcnt_ctl, 3);
1242 q->count = 1;
1243
1244 /* Set VIDB pins to input */
1245 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1246 reg = cx_read(PAD_CTRL);
1247 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1248 cx_write(PAD_CTRL, reg);
1249 }
1250
1251 /* Set VIDC pins to input */
1252 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1253 reg = cx_read(PAD_CTRL);
1254 reg &= ~0x4; /* Clear TS2_SOP_OE */
1255 cx_write(PAD_CTRL, reg);
1256 }
1257
1258 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1259
1260 reg = cx_read(PAD_CTRL);
1261 reg = reg & ~0x1; /* Clear TS1_OE */
1262
1263 /* FIXME, bit 2 writing here is questionable */
1264 /* set TS1_SOP_OE and TS1_OE_HI */
1265 reg = reg | 0xa;
1266 cx_write(PAD_CTRL, reg);
1267
1268 /* FIXME and these two registers should be documented. */
1269 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1270 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1271 }
1272
1273 switch (dev->bridge) {
1274 case CX23885_BRIDGE_885:
1275 case CX23885_BRIDGE_887:
1276 case CX23885_BRIDGE_888:
1277 /* enable irqs */
1278 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1279 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1280 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1281 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1282 break;
1283 default:
1284 BUG();
1285 }
1286
1287 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1288
1289 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1290 cx23885_av_clk(dev, 1);
1291
1292 if (debug > 4)
1293 cx23885_tsport_reg_dump(port);
1294
1295 return 0;
1296 }
1297
1298 static int cx23885_stop_dma(struct cx23885_tsport *port)
1299 {
1300 struct cx23885_dev *dev = port->dev;
1301 u32 reg;
1302
1303 dprintk(1, "%s()\n", __func__);
1304
1305 /* Stop interrupts and DMA */
1306 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1307 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1308
1309 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1310
1311 reg = cx_read(PAD_CTRL);
1312
1313 /* Set TS1_OE */
1314 reg = reg | 0x1;
1315
1316 /* clear TS1_SOP_OE and TS1_OE_HI */
1317 reg = reg & ~0xa;
1318 cx_write(PAD_CTRL, reg);
1319 cx_write(port->reg_src_sel, 0);
1320 cx_write(port->reg_gen_ctrl, 8);
1321
1322 }
1323
1324 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1325 cx23885_av_clk(dev, 0);
1326
1327 return 0;
1328 }
1329
1330 int cx23885_restart_queue(struct cx23885_tsport *port,
1331 struct cx23885_dmaqueue *q)
1332 {
1333 struct cx23885_dev *dev = port->dev;
1334 struct cx23885_buffer *buf;
1335
1336 dprintk(5, "%s()\n", __func__);
1337 if (list_empty(&q->active)) {
1338 struct cx23885_buffer *prev;
1339 prev = NULL;
1340
1341 dprintk(5, "%s() queue is empty\n", __func__);
1342
1343 for (;;) {
1344 if (list_empty(&q->queued))
1345 return 0;
1346 buf = list_entry(q->queued.next, struct cx23885_buffer,
1347 vb.queue);
1348 if (NULL == prev) {
1349 list_del(&buf->vb.queue);
1350 list_add_tail(&buf->vb.queue, &q->active);
1351 cx23885_start_dma(port, q, buf);
1352 buf->vb.state = VIDEOBUF_ACTIVE;
1353 buf->count = q->count++;
1354 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1355 dprintk(5, "[%p/%d] restart_queue - f/active\n",
1356 buf, buf->vb.i);
1357
1358 } else if (prev->vb.width == buf->vb.width &&
1359 prev->vb.height == buf->vb.height &&
1360 prev->fmt == buf->fmt) {
1361 list_del(&buf->vb.queue);
1362 list_add_tail(&buf->vb.queue, &q->active);
1363 buf->vb.state = VIDEOBUF_ACTIVE;
1364 buf->count = q->count++;
1365 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1366 /* 64 bit bits 63-32 */
1367 prev->risc.jmp[2] = cpu_to_le32(0);
1368 dprintk(5, "[%p/%d] restart_queue - m/active\n",
1369 buf, buf->vb.i);
1370 } else {
1371 return 0;
1372 }
1373 prev = buf;
1374 }
1375 return 0;
1376 }
1377
1378 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1379 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1380 buf, buf->vb.i);
1381 cx23885_start_dma(port, q, buf);
1382 list_for_each_entry(buf, &q->active, vb.queue)
1383 buf->count = q->count++;
1384 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1385 return 0;
1386 }
1387
1388 /* ------------------------------------------------------------------ */
1389
1390 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1391 struct cx23885_buffer *buf, enum v4l2_field field)
1392 {
1393 struct cx23885_dev *dev = port->dev;
1394 int size = port->ts_packet_size * port->ts_packet_count;
1395 int rc;
1396
1397 dprintk(1, "%s: %p\n", __func__, buf);
1398 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1399 return -EINVAL;
1400
1401 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1402 buf->vb.width = port->ts_packet_size;
1403 buf->vb.height = port->ts_packet_count;
1404 buf->vb.size = size;
1405 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1406
1407 rc = videobuf_iolock(q, &buf->vb, NULL);
1408 if (0 != rc)
1409 goto fail;
1410 cx23885_risc_databuffer(dev->pci, &buf->risc,
1411 videobuf_to_dma(&buf->vb)->sglist,
1412 buf->vb.width, buf->vb.height);
1413 }
1414 buf->vb.state = VIDEOBUF_PREPARED;
1415 return 0;
1416
1417 fail:
1418 cx23885_free_buffer(q, buf);
1419 return rc;
1420 }
1421
1422 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1423 {
1424 struct cx23885_buffer *prev;
1425 struct cx23885_dev *dev = port->dev;
1426 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1427
1428 /* add jump to stopper */
1429 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1430 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1431 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1432
1433 if (list_empty(&cx88q->active)) {
1434 dprintk(1, "queue is empty - first active\n");
1435 list_add_tail(&buf->vb.queue, &cx88q->active);
1436 cx23885_start_dma(port, cx88q, buf);
1437 buf->vb.state = VIDEOBUF_ACTIVE;
1438 buf->count = cx88q->count++;
1439 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1440 dprintk(1, "[%p/%d] %s - first active\n",
1441 buf, buf->vb.i, __func__);
1442 } else {
1443 dprintk(1, "queue is not empty - append to active\n");
1444 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1445 vb.queue);
1446 list_add_tail(&buf->vb.queue, &cx88q->active);
1447 buf->vb.state = VIDEOBUF_ACTIVE;
1448 buf->count = cx88q->count++;
1449 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1450 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1451 dprintk(1, "[%p/%d] %s - append to active\n",
1452 buf, buf->vb.i, __func__);
1453 }
1454 }
1455
1456 /* ----------------------------------------------------------- */
1457
1458 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1459 int restart)
1460 {
1461 struct cx23885_dev *dev = port->dev;
1462 struct cx23885_dmaqueue *q = &port->mpegq;
1463 struct cx23885_buffer *buf;
1464 unsigned long flags;
1465
1466 spin_lock_irqsave(&port->slock, flags);
1467 while (!list_empty(&q->active)) {
1468 buf = list_entry(q->active.next, struct cx23885_buffer,
1469 vb.queue);
1470 list_del(&buf->vb.queue);
1471 buf->vb.state = VIDEOBUF_ERROR;
1472 wake_up(&buf->vb.done);
1473 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1474 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1475 }
1476 if (restart) {
1477 dprintk(1, "restarting queue\n");
1478 cx23885_restart_queue(port, q);
1479 }
1480 spin_unlock_irqrestore(&port->slock, flags);
1481 }
1482
1483 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1484 {
1485 struct cx23885_dev *dev = port->dev;
1486 struct cx23885_dmaqueue *q = &port->mpegq;
1487
1488 dprintk(1, "%s()\n", __func__);
1489 del_timer_sync(&q->timeout);
1490 cx23885_stop_dma(port);
1491 do_cancel_buffers(port, "cancel", 0);
1492 }
1493
1494 static void cx23885_timeout(unsigned long data)
1495 {
1496 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1497 struct cx23885_dev *dev = port->dev;
1498
1499 dprintk(1, "%s()\n", __func__);
1500
1501 if (debug > 5)
1502 cx23885_sram_channel_dump(dev,
1503 &dev->sram_channels[port->sram_chno]);
1504
1505 cx23885_stop_dma(port);
1506 do_cancel_buffers(port, "timeout", 1);
1507 }
1508
1509 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1510 {
1511 /* FIXME: port1 assumption here. */
1512 struct cx23885_tsport *port = &dev->ts1;
1513 int count = 0;
1514 int handled = 0;
1515
1516 if (status == 0)
1517 return handled;
1518
1519 count = cx_read(port->reg_gpcnt);
1520 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1521 status, cx_read(port->reg_ts_int_msk), count);
1522
1523 if ((status & VID_B_MSK_BAD_PKT) ||
1524 (status & VID_B_MSK_OPC_ERR) ||
1525 (status & VID_B_MSK_VBI_OPC_ERR) ||
1526 (status & VID_B_MSK_SYNC) ||
1527 (status & VID_B_MSK_VBI_SYNC) ||
1528 (status & VID_B_MSK_OF) ||
1529 (status & VID_B_MSK_VBI_OF)) {
1530 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1531 "= 0x%x\n", dev->name, status);
1532 if (status & VID_B_MSK_BAD_PKT)
1533 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1534 if (status & VID_B_MSK_OPC_ERR)
1535 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1536 if (status & VID_B_MSK_VBI_OPC_ERR)
1537 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1538 if (status & VID_B_MSK_SYNC)
1539 dprintk(1, " VID_B_MSK_SYNC\n");
1540 if (status & VID_B_MSK_VBI_SYNC)
1541 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1542 if (status & VID_B_MSK_OF)
1543 dprintk(1, " VID_B_MSK_OF\n");
1544 if (status & VID_B_MSK_VBI_OF)
1545 dprintk(1, " VID_B_MSK_VBI_OF\n");
1546
1547 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1548 cx23885_sram_channel_dump(dev,
1549 &dev->sram_channels[port->sram_chno]);
1550 cx23885_417_check_encoder(dev);
1551 } else if (status & VID_B_MSK_RISCI1) {
1552 dprintk(7, " VID_B_MSK_RISCI1\n");
1553 spin_lock(&port->slock);
1554 cx23885_wakeup(port, &port->mpegq, count);
1555 spin_unlock(&port->slock);
1556 } else if (status & VID_B_MSK_RISCI2) {
1557 dprintk(7, " VID_B_MSK_RISCI2\n");
1558 spin_lock(&port->slock);
1559 cx23885_restart_queue(port, &port->mpegq);
1560 spin_unlock(&port->slock);
1561 }
1562 if (status) {
1563 cx_write(port->reg_ts_int_stat, status);
1564 handled = 1;
1565 }
1566
1567 return handled;
1568 }
1569
1570 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1571 {
1572 struct cx23885_dev *dev = port->dev;
1573 int handled = 0;
1574 u32 count;
1575
1576 if ((status & VID_BC_MSK_OPC_ERR) ||
1577 (status & VID_BC_MSK_BAD_PKT) ||
1578 (status & VID_BC_MSK_SYNC) ||
1579 (status & VID_BC_MSK_OF)) {
1580
1581 if (status & VID_BC_MSK_OPC_ERR)
1582 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1583 VID_BC_MSK_OPC_ERR);
1584
1585 if (status & VID_BC_MSK_BAD_PKT)
1586 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1587 VID_BC_MSK_BAD_PKT);
1588
1589 if (status & VID_BC_MSK_SYNC)
1590 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n",
1591 VID_BC_MSK_SYNC);
1592
1593 if (status & VID_BC_MSK_OF)
1594 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n",
1595 VID_BC_MSK_OF);
1596
1597 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1598
1599 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1600 cx23885_sram_channel_dump(dev,
1601 &dev->sram_channels[port->sram_chno]);
1602
1603 } else if (status & VID_BC_MSK_RISCI1) {
1604
1605 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1606
1607 spin_lock(&port->slock);
1608 count = cx_read(port->reg_gpcnt);
1609 cx23885_wakeup(port, &port->mpegq, count);
1610 spin_unlock(&port->slock);
1611
1612 } else if (status & VID_BC_MSK_RISCI2) {
1613
1614 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1615
1616 spin_lock(&port->slock);
1617 cx23885_restart_queue(port, &port->mpegq);
1618 spin_unlock(&port->slock);
1619
1620 }
1621 if (status) {
1622 cx_write(port->reg_ts_int_stat, status);
1623 handled = 1;
1624 }
1625
1626 return handled;
1627 }
1628
1629 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1630 {
1631 struct cx23885_dev *dev = dev_id;
1632 struct cx23885_tsport *ts1 = &dev->ts1;
1633 struct cx23885_tsport *ts2 = &dev->ts2;
1634 u32 pci_status, pci_mask;
1635 u32 vida_status, vida_mask;
1636 u32 ts1_status, ts1_mask;
1637 u32 ts2_status, ts2_mask;
1638 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1639
1640 pci_status = cx_read(PCI_INT_STAT);
1641 pci_mask = cx_read(PCI_INT_MSK);
1642 vida_status = cx_read(VID_A_INT_STAT);
1643 vida_mask = cx_read(VID_A_INT_MSK);
1644 ts1_status = cx_read(VID_B_INT_STAT);
1645 ts1_mask = cx_read(VID_B_INT_MSK);
1646 ts2_status = cx_read(VID_C_INT_STAT);
1647 ts2_mask = cx_read(VID_C_INT_MSK);
1648
1649 if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1650 goto out;
1651
1652 vida_count = cx_read(VID_A_GPCNT);
1653 ts1_count = cx_read(ts1->reg_gpcnt);
1654 ts2_count = cx_read(ts2->reg_gpcnt);
1655 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1656 pci_status, pci_mask);
1657 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1658 vida_status, vida_mask, vida_count);
1659 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1660 ts1_status, ts1_mask, ts1_count);
1661 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1662 ts2_status, ts2_mask, ts2_count);
1663
1664 if ((pci_status & PCI_MSK_RISC_RD) ||
1665 (pci_status & PCI_MSK_RISC_WR) ||
1666 (pci_status & PCI_MSK_AL_RD) ||
1667 (pci_status & PCI_MSK_AL_WR) ||
1668 (pci_status & PCI_MSK_APB_DMA) ||
1669 (pci_status & PCI_MSK_VID_C) ||
1670 (pci_status & PCI_MSK_VID_B) ||
1671 (pci_status & PCI_MSK_VID_A) ||
1672 (pci_status & PCI_MSK_AUD_INT) ||
1673 (pci_status & PCI_MSK_AUD_EXT) ||
1674 (pci_status & PCI_MSK_GPIO0) ||
1675 (pci_status & PCI_MSK_GPIO1)) {
1676
1677 if (pci_status & PCI_MSK_RISC_RD)
1678 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n",
1679 PCI_MSK_RISC_RD);
1680
1681 if (pci_status & PCI_MSK_RISC_WR)
1682 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n",
1683 PCI_MSK_RISC_WR);
1684
1685 if (pci_status & PCI_MSK_AL_RD)
1686 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n",
1687 PCI_MSK_AL_RD);
1688
1689 if (pci_status & PCI_MSK_AL_WR)
1690 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n",
1691 PCI_MSK_AL_WR);
1692
1693 if (pci_status & PCI_MSK_APB_DMA)
1694 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n",
1695 PCI_MSK_APB_DMA);
1696
1697 if (pci_status & PCI_MSK_VID_C)
1698 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n",
1699 PCI_MSK_VID_C);
1700
1701 if (pci_status & PCI_MSK_VID_B)
1702 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n",
1703 PCI_MSK_VID_B);
1704
1705 if (pci_status & PCI_MSK_VID_A)
1706 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n",
1707 PCI_MSK_VID_A);
1708
1709 if (pci_status & PCI_MSK_AUD_INT)
1710 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n",
1711 PCI_MSK_AUD_INT);
1712
1713 if (pci_status & PCI_MSK_AUD_EXT)
1714 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n",
1715 PCI_MSK_AUD_EXT);
1716
1717 if (pci_status & PCI_MSK_GPIO0)
1718 dprintk(7, " (PCI_MSK_GPIO0 0x%08x)\n",
1719 PCI_MSK_GPIO0);
1720
1721 if (pci_status & PCI_MSK_GPIO1)
1722 dprintk(7, " (PCI_MSK_GPIO1 0x%08x)\n",
1723 PCI_MSK_GPIO1);
1724 }
1725
1726 if (cx23885_boards[dev->board].cimax > 0 &&
1727 ((pci_status & PCI_MSK_GPIO0) ||
1728 (pci_status & PCI_MSK_GPIO1))) {
1729
1730 if (cx23885_boards[dev->board].cimax > 0)
1731 handled += netup_ci_slot_status(dev, pci_status);
1732
1733 }
1734
1735 if (ts1_status) {
1736 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1737 handled += cx23885_irq_ts(ts1, ts1_status);
1738 else
1739 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1740 handled += cx23885_irq_417(dev, ts1_status);
1741 }
1742
1743 if (ts2_status) {
1744 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1745 handled += cx23885_irq_ts(ts2, ts2_status);
1746 else
1747 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1748 handled += cx23885_irq_417(dev, ts2_status);
1749 }
1750
1751 if (vida_status)
1752 handled += cx23885_video_irq(dev, vida_status);
1753
1754 if (handled)
1755 cx_write(PCI_INT_STAT, pci_status);
1756 out:
1757 return IRQ_RETVAL(handled);
1758 }
1759
1760 static inline int encoder_on_portb(struct cx23885_dev *dev)
1761 {
1762 return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1763 }
1764
1765 static inline int encoder_on_portc(struct cx23885_dev *dev)
1766 {
1767 return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1768 }
1769
1770 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1771 * registers depending on the board configuration (and whether the
1772 * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1773 * be pushed into the correct hardware register, regardless of the
1774 * physical location. Certain registers are shared so we sanity check
1775 * and report errors if we think we're tampering with a GPIo that might
1776 * be assigned to the encoder (and used for the host bus).
1777 *
1778 * GPIO 2 thru 0 - On the cx23885 bridge
1779 * GPIO 18 thru 3 - On the cx23417 host bus interface
1780 * GPIO 23 thru 19 - On the cx25840 a/v core
1781 */
1782 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1783 {
1784 if (mask & 0x7)
1785 cx_set(GP0_IO, mask & 0x7);
1786
1787 if (mask & 0x0007fff8) {
1788 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1789 printk(KERN_ERR
1790 "%s: Setting GPIO on encoder ports\n",
1791 dev->name);
1792 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1793 }
1794
1795 /* TODO: 23-19 */
1796 if (mask & 0x00f80000)
1797 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1798 }
1799
1800 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1801 {
1802 if (mask & 0x00000007)
1803 cx_clear(GP0_IO, mask & 0x7);
1804
1805 if (mask & 0x0007fff8) {
1806 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1807 printk(KERN_ERR
1808 "%s: Clearing GPIO moving on encoder ports\n",
1809 dev->name);
1810 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1811 }
1812
1813 /* TODO: 23-19 */
1814 if (mask & 0x00f80000)
1815 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1816 }
1817
1818 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1819 {
1820 if ((mask & 0x00000007) && asoutput)
1821 cx_set(GP0_IO, (mask & 0x7) << 16);
1822 else if ((mask & 0x00000007) && !asoutput)
1823 cx_clear(GP0_IO, (mask & 0x7) << 16);
1824
1825 if (mask & 0x0007fff8) {
1826 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1827 printk(KERN_ERR
1828 "%s: Enabling GPIO on encoder ports\n",
1829 dev->name);
1830 }
1831
1832 /* MC417_OEN is active low for output, write 1 for an input */
1833 if ((mask & 0x0007fff8) && asoutput)
1834 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1835
1836 else if ((mask & 0x0007fff8) && !asoutput)
1837 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1838
1839 /* TODO: 23-19 */
1840 }
1841
1842 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1843 const struct pci_device_id *pci_id)
1844 {
1845 struct cx23885_dev *dev;
1846 int err;
1847
1848 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1849 if (NULL == dev)
1850 return -ENOMEM;
1851
1852 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1853 if (err < 0)
1854 goto fail_free;
1855
1856 /* pci init */
1857 dev->pci = pci_dev;
1858 if (pci_enable_device(pci_dev)) {
1859 err = -EIO;
1860 goto fail_unreg;
1861 }
1862
1863 if (cx23885_dev_setup(dev) < 0) {
1864 err = -EINVAL;
1865 goto fail_unreg;
1866 }
1867
1868 /* print pci info */
1869 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1870 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1871 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1872 "latency: %d, mmio: 0x%llx\n", dev->name,
1873 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1874 dev->pci_lat,
1875 (unsigned long long)pci_resource_start(pci_dev, 0));
1876
1877 pci_set_master(pci_dev);
1878 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1879 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1880 err = -EIO;
1881 goto fail_irq;
1882 }
1883
1884 err = request_irq(pci_dev->irq, cx23885_irq,
1885 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1886 if (err < 0) {
1887 printk(KERN_ERR "%s: can't get IRQ %d\n",
1888 dev->name, pci_dev->irq);
1889 goto fail_irq;
1890 }
1891
1892 switch (dev->board) {
1893 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1894 cx_set(PCI_INT_MSK, 0x01800000); /* for NetUP */
1895 break;
1896 }
1897
1898 return 0;
1899
1900 fail_irq:
1901 cx23885_dev_unregister(dev);
1902 fail_unreg:
1903 v4l2_device_unregister(&dev->v4l2_dev);
1904 fail_free:
1905 kfree(dev);
1906 return err;
1907 }
1908
1909 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1910 {
1911 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1912 struct cx23885_dev *dev = to_cx23885(v4l2_dev);
1913
1914 cx23885_shutdown(dev);
1915
1916 pci_disable_device(pci_dev);
1917
1918 /* unregister stuff */
1919 free_irq(pci_dev->irq, dev);
1920
1921 mutex_lock(&devlist);
1922 list_del(&dev->devlist);
1923 mutex_unlock(&devlist);
1924
1925 cx23885_dev_unregister(dev);
1926 v4l2_device_unregister(v4l2_dev);
1927 kfree(dev);
1928 }
1929
1930 static struct pci_device_id cx23885_pci_tbl[] = {
1931 {
1932 /* CX23885 */
1933 .vendor = 0x14f1,
1934 .device = 0x8852,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 }, {
1938 /* CX23887 Rev 2 */
1939 .vendor = 0x14f1,
1940 .device = 0x8880,
1941 .subvendor = PCI_ANY_ID,
1942 .subdevice = PCI_ANY_ID,
1943 }, {
1944 /* --- end of list --- */
1945 }
1946 };
1947 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1948
1949 static struct pci_driver cx23885_pci_driver = {
1950 .name = "cx23885",
1951 .id_table = cx23885_pci_tbl,
1952 .probe = cx23885_initdev,
1953 .remove = __devexit_p(cx23885_finidev),
1954 /* TODO */
1955 .suspend = NULL,
1956 .resume = NULL,
1957 };
1958
1959 static int cx23885_init(void)
1960 {
1961 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1962 (CX23885_VERSION_CODE >> 16) & 0xff,
1963 (CX23885_VERSION_CODE >> 8) & 0xff,
1964 CX23885_VERSION_CODE & 0xff);
1965 #ifdef SNAPSHOT
1966 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1967 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1968 #endif
1969 return pci_register_driver(&cx23885_pci_driver);
1970 }
1971
1972 static void cx23885_fini(void)
1973 {
1974 pci_unregister_driver(&cx23885_pci_driver);
1975 }
1976
1977 module_init(cx23885_init);
1978 module_exit(cx23885_fini);
1979
1980 /* ----------------------------------------------------------- */
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