drivers/media/video/cx23885/cx23885.h

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/pci.h>
  23 #include <linux/i2c.h>
  24 #include <linux/i2c-algo-bit.h>
  25 #include <linux/kdev_t.h>
  26
  27 #include <media/v4l2-device.h>
  28 #include <media/tuner.h>
  29 #include <media/tveeprom.h>
  30 #include <media/videobuf-dma-sg.h>
  31 #include <media/videobuf-dvb.h>
  32
  33 #include "btcx-risc.h"
  34 #include "cx23885-reg.h"
  35 #include "media/cx2341x.h"
  36
  37 #include <linux/version.h>
  38 #include <linux/mutex.h>
  39
  40 #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
  41
  42 #define UNSET (-1U)
  43
  44 #define CX23885_MAXBOARDS 8
  45
  46 /* Max number of inputs by card */
  47 #define MAX_CX23885_INPUT 8
  48 #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
  49 #define RESOURCE_OVERLAY       1
  50 #define RESOURCE_VIDEO         2
  51 #define RESOURCE_VBI           4
  52
  53 #define BUFFER_TIMEOUT     (HZ)  /* 0.5 seconds */
  54
  55 #define CX23885_BOARD_NOAUTO               UNSET
  56 #define CX23885_BOARD_UNKNOWN                  0
  57 #define CX23885_BOARD_HAUPPAUGE_HVR1800lp      1
  58 #define CX23885_BOARD_HAUPPAUGE_HVR1800        2
  59 #define CX23885_BOARD_HAUPPAUGE_HVR1250        3
  60 #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP   4
  61 #define CX23885_BOARD_HAUPPAUGE_HVR1500Q       5
  62 #define CX23885_BOARD_HAUPPAUGE_HVR1500        6
  63 #define CX23885_BOARD_HAUPPAUGE_HVR1200        7
  64 #define CX23885_BOARD_HAUPPAUGE_HVR1700        8
  65 #define CX23885_BOARD_HAUPPAUGE_HVR1400        9
  66 #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
  67 #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
  68 #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
  69 #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F   13
  70 #define CX23885_BOARD_TBS_6920                 14
  71 #define CX23885_BOARD_TEVII_S470               15
  72 #define CX23885_BOARD_DVBWORLD_2005            16
  73 #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI      17
  74 #define CX23885_BOARD_HAUPPAUGE_HVR1270        18
  75 #define CX23885_BOARD_HAUPPAUGE_HVR1275        19
  76 #define CX23885_BOARD_HAUPPAUGE_HVR1255        20
  77 #define CX23885_BOARD_HAUPPAUGE_HVR1210        21
  78 #define CX23885_BOARD_MYGICA_X8506             22
  79 #define CX23885_BOARD_MAGICPRO_PROHDTVE2       23
  80 #define CX23885_BOARD_HAUPPAUGE_HVR1850        24
  81 #define CX23885_BOARD_COMPRO_VIDEOMATE_E800    25
  82 #define CX23885_BOARD_HAUPPAUGE_HVR1290        26
  83 #define CX23885_BOARD_MYGICA_X8558PRO          27
  84 #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
  85
  86 #define GPIO_0 0x00000001
  87 #define GPIO_1 0x00000002
  88 #define GPIO_2 0x00000004
  89 #define GPIO_3 0x00000008
  90 #define GPIO_4 0x00000010
  91 #define GPIO_5 0x00000020
  92 #define GPIO_6 0x00000040
  93 #define GPIO_7 0x00000080
  94 #define GPIO_8 0x00000100
  95 #define GPIO_9 0x00000200
  96 #define GPIO_10 0x00000400
  97 #define GPIO_11 0x00000800
  98 #define GPIO_12 0x00001000
  99 #define GPIO_13 0x00002000
 100 #define GPIO_14 0x00004000
 101 #define GPIO_15 0x00008000
 102
 103 /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
 104 #define CX23885_NORMS (\
 105         V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP |  V4L2_STD_NTSC_443 | \
 106         V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
 107         V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_Nc   | \
 108         V4L2_STD_PAL_60 |  V4L2_STD_SECAM_L   |  V4L2_STD_SECAM_DK)
 109
 110 struct cx23885_fmt {
 111         char  *name;
 112         u32   fourcc;          /* v4l2 format id */
 113         int   depth;
 114         int   flags;
 115         u32   cxformat;
 116 };
 117
 118 struct cx23885_ctrl {
 119         struct v4l2_queryctrl v;
 120         u32                   off;
 121         u32                   reg;
 122         u32                   mask;
 123         u32                   shift;
 124 };
 125
 126 struct cx23885_tvnorm {
 127         char            *name;
 128         v4l2_std_id     id;
 129         u32             cxiformat;
 130         u32             cxoformat;
 131 };
 132
 133 struct cx23885_fh {
 134         struct cx23885_dev         *dev;
 135         enum v4l2_buf_type         type;
 136         int                        radio;
 137         u32                        resources;
 138
 139         /* video overlay */
 140         struct v4l2_window         win;
 141         struct v4l2_clip           *clips;
 142         unsigned int               nclips;
 143
 144         /* video capture */
 145         struct cx23885_fmt         *fmt;
 146         unsigned int               width, height;
 147
 148         /* vbi capture */
 149         struct videobuf_queue      vidq;
 150         struct videobuf_queue      vbiq;
 151
 152         /* MPEG Encoder specifics ONLY */
 153         struct videobuf_queue      mpegq;
 154         atomic_t                   v4l_reading;
 155 };
 156
 157 enum cx23885_itype {
 158         CX23885_VMUX_COMPOSITE1 = 1,
 159         CX23885_VMUX_COMPOSITE2,
 160         CX23885_VMUX_COMPOSITE3,
 161         CX23885_VMUX_COMPOSITE4,
 162         CX23885_VMUX_SVIDEO,
 163         CX23885_VMUX_COMPONENT,
 164         CX23885_VMUX_TELEVISION,
 165         CX23885_VMUX_CABLE,
 166         CX23885_VMUX_DVB,
 167         CX23885_VMUX_DEBUG,
 168         CX23885_RADIO,
 169 };
 170
 171 enum cx23885_src_sel_type {
 172         CX23885_SRC_SEL_EXT_656_VIDEO = 0,
 173         CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
 174 };
 175
 176 /* buffer for one video frame */
 177 struct cx23885_buffer {
 178         /* common v4l buffer stuff -- must be first */
 179         struct videobuf_buffer vb;
 180
 181         /* cx23885 specific */
 182         unsigned int           bpl;
 183         struct btcx_riscmem    risc;
 184         struct cx23885_fmt     *fmt;
 185         u32                    count;
 186 };
 187
 188 struct cx23885_input {
 189         enum cx23885_itype type;
 190         unsigned int    vmux;
 191         u32             gpio0, gpio1, gpio2, gpio3;
 192 };
 193
 194 typedef enum {
 195         CX23885_MPEG_UNDEFINED = 0,
 196         CX23885_MPEG_DVB,
 197         CX23885_ANALOG_VIDEO,
 198         CX23885_MPEG_ENCODER,
 199 } port_t;
 200
 201 struct cx23885_board {
 202         char                    *name;
 203         port_t                  porta, portb, portc;
 204         unsigned int            tuner_type;
 205         unsigned int            radio_type;
 206         unsigned char           tuner_addr;
 207         unsigned char           radio_addr;
 208
 209         /* Vendors can and do run the PCIe bridge at different
 210          * clock rates, driven physically by crystals on the PCBs.
 211          * The core has to accomodate this. This allows the user
 212          * to add new boards with new frequencys. The value is
 213          * expressed in Hz.
 214          *
 215          * The core framework will default this value based on
 216          * current designs, but it can vary.
 217          */
 218         u32                     clk_freq;
 219         struct cx23885_input    input[MAX_CX23885_INPUT];
 220         int                     cimax; /* for NetUP */
 221 };
 222
 223 struct cx23885_subid {
 224         u16     subvendor;
 225         u16     subdevice;
 226         u32     card;
 227 };
 228
 229 struct cx23885_i2c {
 230         struct cx23885_dev *dev;
 231
 232         int                        nr;
 233
 234         /* i2c i/o */
 235         struct i2c_adapter         i2c_adap;
 236         struct i2c_algo_bit_data   i2c_algo;
 237         struct i2c_client          i2c_client;
 238         u32                        i2c_rc;
 239
 240         /* 885 registers used for raw addess */
 241         u32                        i2c_period;
 242         u32                        reg_ctrl;
 243         u32                        reg_stat;
 244         u32                        reg_addr;
 245         u32                        reg_rdata;
 246         u32                        reg_wdata;
 247 };
 248
 249 struct cx23885_dmaqueue {
 250         struct list_head       active;
 251         struct list_head       queued;
 252         struct timer_list      timeout;
 253         struct btcx_riscmem    stopper;
 254         u32                    count;
 255 };
 256
 257 struct cx23885_tsport {
 258         struct cx23885_dev *dev;
 259
 260         int                        nr;
 261         int                        sram_chno;
 262
 263         struct videobuf_dvb_frontends frontends;
 264
 265         /* dma queues */
 266         struct cx23885_dmaqueue    mpegq;
 267         u32                        ts_packet_size;
 268         u32                        ts_packet_count;
 269
 270         int                        width;
 271         int                        height;
 272
 273         spinlock_t                 slock;
 274
 275         /* registers */
 276         u32                        reg_gpcnt;
 277         u32                        reg_gpcnt_ctl;
 278         u32                        reg_dma_ctl;
 279         u32                        reg_lngth;
 280         u32                        reg_hw_sop_ctrl;
 281         u32                        reg_gen_ctrl;
 282         u32                        reg_bd_pkt_status;
 283         u32                        reg_sop_status;
 284         u32                        reg_fifo_ovfl_stat;
 285         u32                        reg_vld_misc;
 286         u32                        reg_ts_clk_en;
 287         u32                        reg_ts_int_msk;
 288         u32                        reg_ts_int_stat;
 289         u32                        reg_src_sel;
 290
 291         /* Default register vals */
 292         int                        pci_irqmask;
 293         u32                        dma_ctl_val;
 294         u32                        ts_int_msk_val;
 295         u32                        gen_ctrl_val;
 296         u32                        ts_clk_en_val;
 297         u32                        src_sel_val;
 298         u32                        vld_misc_val;
 299         u32                        hw_sop_ctrl_val;
 300
 301         /* Allow a single tsport to have multiple frontends */
 302         u32                        num_frontends;
 303         void                       *port_priv;
 304 };
 305
 306 struct cx23885_dev {
 307         atomic_t                   refcount;
 308         struct v4l2_device         v4l2_dev;
 309
 310         /* pci stuff */
 311         struct pci_dev             *pci;
 312         unsigned char              pci_rev, pci_lat;
 313         int                        pci_bus, pci_slot;
 314         u32                        __iomem *lmmio;
 315         u8                         __iomem *bmmio;
 316         int                        pci_irqmask;
 317         int                        hwrevision;
 318
 319         /* This valud is board specific and is used to configure the
 320          * AV core so we see nice clean and stable video and audio. */
 321         u32                        clk_freq;
 322
 323         /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
 324         struct cx23885_i2c         i2c_bus[3];
 325
 326         int                        nr;
 327         struct mutex               lock;
 328         struct mutex               gpio_lock;
 329
 330         /* board details */
 331         unsigned int               board;
 332         char                       name[32];
 333
 334         struct cx23885_tsport      ts1, ts2;
 335
 336         /* sram configuration */
 337         struct sram_channel        *sram_channels;
 338
 339         enum {
 340                 CX23885_BRIDGE_UNDEFINED = 0,
 341                 CX23885_BRIDGE_885 = 885,
 342                 CX23885_BRIDGE_887 = 887,
 343                 CX23885_BRIDGE_888 = 888,
 344         } bridge;
 345
 346         /* Analog video */
 347         u32                        resources;
 348         unsigned int               input;
 349         u32                        tvaudio;
 350         v4l2_std_id                tvnorm;
 351         unsigned int               tuner_type;
 352         unsigned char              tuner_addr;
 353         unsigned int               radio_type;
 354         unsigned char              radio_addr;
 355         unsigned int               has_radio;
 356         struct v4l2_subdev         *sd_cx25840;
 357
 358         /* Infrared */
 359         struct v4l2_subdev         *sd_ir;
 360         struct work_struct         ir_rx_work;
 361         unsigned long              ir_rx_notifications;
 362         struct work_struct         ir_tx_work;
 363         unsigned long              ir_tx_notifications;
 364
 365         struct card_ir             *ir_input;
 366         atomic_t                   ir_input_stopping;
 367
 368         /* V4l */
 369         u32                        freq;
 370         struct video_device        *video_dev;
 371         struct video_device        *vbi_dev;
 372         struct video_device        *radio_dev;
 373
 374         struct cx23885_dmaqueue    vidq;
 375         struct cx23885_dmaqueue    vbiq;
 376         spinlock_t                 slock;
 377
 378         /* MPEG Encoder ONLY settings */
 379         u32                        cx23417_mailbox;
 380         struct cx2341x_mpeg_params mpeg_params;
 381         struct video_device        *v4l_device;
 382         atomic_t                   v4l_reader_count;
 383         struct cx23885_tvnorm      encodernorm;
 384
 385 };
 386
 387 static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
 388 {
 389         return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
 390 }
 391
 392 #define call_all(dev, o, f, args...) \
 393         v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
 394
 395 #define CX23885_HW_888_IR (1 << 0)
 396
 397 #define call_hw(dev, grpid, o, f, args...) \
 398         v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
 399
 400 extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
 401
 402 #define SRAM_CH01  0 /* Video A */
 403 #define SRAM_CH02  1 /* VBI A */
 404 #define SRAM_CH03  2 /* Video B */
 405 #define SRAM_CH04  3 /* Transport via B */
 406 #define SRAM_CH05  4 /* VBI B */
 407 #define SRAM_CH06  5 /* Video C */
 408 #define SRAM_CH07  6 /* Transport via C */
 409 #define SRAM_CH08  7 /* Audio Internal A */
 410 #define SRAM_CH09  8 /* Audio Internal B */
 411 #define SRAM_CH10  9 /* Audio External */
 412 #define SRAM_CH11 10 /* COMB_3D_N */
 413 #define SRAM_CH12 11 /* Comb 3D N1 */
 414 #define SRAM_CH13 12 /* Comb 3D N2 */
 415 #define SRAM_CH14 13 /* MOE Vid */
 416 #define SRAM_CH15 14 /* MOE RSLT */
 417
 418 struct sram_channel {
 419         char *name;
 420         u32  cmds_start;
 421         u32  ctrl_start;
 422         u32  cdt;
 423         u32  fifo_start;
 424         u32  fifo_size;
 425         u32  ptr1_reg;
 426         u32  ptr2_reg;
 427         u32  cnt1_reg;
 428         u32  cnt2_reg;
 429         u32  jumponly;
 430 };
 431
 432 /* ----------------------------------------------------------- */
 433
 434 #define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
 435 #define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))
 436
 437 #define cx_andor(reg, mask, value) \
 438   writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
 439   ((value) & (mask)), dev->lmmio+((reg)>>2))
 440
 441 #define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
 442 #define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)
 443
 444 /* ----------------------------------------------------------- */
 445 /* cx23885-core.c                                              */
 446
 447 extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 448         struct sram_channel *ch,
 449         unsigned int bpl, u32 risc);
 450
 451 extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 452         struct sram_channel *ch);
 453
 454 extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 455         u32 reg, u32 mask, u32 value);
 456
 457 extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 458         struct scatterlist *sglist,
 459         unsigned int top_offset, unsigned int bottom_offset,
 460         unsigned int bpl, unsigned int padding, unsigned int lines);
 461
 462 void cx23885_cancel_buffers(struct cx23885_tsport *port);
 463
 464 extern int cx23885_restart_queue(struct cx23885_tsport *port,
 465                                 struct cx23885_dmaqueue *q);
 466
 467 extern void cx23885_wakeup(struct cx23885_tsport *port,
 468                            struct cx23885_dmaqueue *q, u32 count);
 469
 470 extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
 471 extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
 472 extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
 473 extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
 474         int asoutput);
 475
 476
 477 /* ----------------------------------------------------------- */
 478 /* cx23885-cards.c                                             */
 479 extern struct cx23885_board cx23885_boards[];
 480 extern const unsigned int cx23885_bcount;
 481
 482 extern struct cx23885_subid cx23885_subids[];
 483 extern const unsigned int cx23885_idcount;
 484
 485 extern int cx23885_tuner_callback(void *priv, int component,
 486         int command, int arg);
 487 extern void cx23885_card_list(struct cx23885_dev *dev);
 488 extern int  cx23885_ir_init(struct cx23885_dev *dev);
 489 extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
 490 extern void cx23885_ir_fini(struct cx23885_dev *dev);
 491 extern void cx23885_gpio_setup(struct cx23885_dev *dev);
 492 extern void cx23885_card_setup(struct cx23885_dev *dev);
 493 extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
 494
 495 extern int cx23885_dvb_register(struct cx23885_tsport *port);
 496 extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
 497
 498 extern int cx23885_buf_prepare(struct videobuf_queue *q,
 499                                struct cx23885_tsport *port,
 500                                struct cx23885_buffer *buf,
 501                                enum v4l2_field field);
 502 extern void cx23885_buf_queue(struct cx23885_tsport *port,
 503                               struct cx23885_buffer *buf);
 504 extern void cx23885_free_buffer(struct videobuf_queue *q,
 505                                 struct cx23885_buffer *buf);
 506
 507 /* ----------------------------------------------------------- */
 508 /* cx23885-video.c                                             */
 509 /* Video */
 510 extern int cx23885_video_register(struct cx23885_dev *dev);
 511 extern void cx23885_video_unregister(struct cx23885_dev *dev);
 512 extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
 513
 514 /* ----------------------------------------------------------- */
 515 /* cx23885-vbi.c                                               */
 516 extern int cx23885_vbi_fmt(struct file *file, void *priv,
 517         struct v4l2_format *f);
 518 extern void cx23885_vbi_timeout(unsigned long data);
 519 extern struct videobuf_queue_ops cx23885_vbi_qops;
 520
 521 /* cx23885-i2c.c                                                */
 522 extern int cx23885_i2c_register(struct cx23885_i2c *bus);
 523 extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
 524 extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
 525
 526 /* ----------------------------------------------------------- */
 527 /* cx23885-417.c                                               */
 528 extern int cx23885_417_register(struct cx23885_dev *dev);
 529 extern void cx23885_417_unregister(struct cx23885_dev *dev);
 530 extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
 531 extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
 532 extern void cx23885_mc417_init(struct cx23885_dev *dev);
 533 extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
 534 extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
 535 extern int mc417_register_read(struct cx23885_dev *dev,
 536                                 u16 address, u32 *value);
 537 extern int mc417_register_write(struct cx23885_dev *dev,
 538                                 u16 address, u32 value);
 539 extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
 540 extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
 541 extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
 542
 543
 544 /* ----------------------------------------------------------- */
 545 /* tv norms                                                    */
 546
 547 static inline unsigned int norm_maxw(v4l2_std_id norm)
 548 {
 549         return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
 550 }
 551
 552 static inline unsigned int norm_maxh(v4l2_std_id norm)
 553 {
 554         return (norm & V4L2_STD_625_50) ? 576 : 480;
 555 }
 556
 557 static inline unsigned int norm_swidth(v4l2_std_id norm)
 558 {
 559         return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
 560 }