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[media] omap3isp: preview: Add crop support on the sink pad
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1 /*
2 * isppreview.c
3 *
4 * TI OMAP3 ISP driver - Preview module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #include <linux/device.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/mutex.h>
31 #include <linux/uaccess.h>
32
33 #include "isp.h"
34 #include "ispreg.h"
35 #include "isppreview.h"
36
37 /* Default values in Office Fluorescent Light for RGBtoRGB Blending */
38 static struct omap3isp_prev_rgbtorgb flr_rgb2rgb = {
39 { /* RGB-RGB Matrix */
40 {0x01E2, 0x0F30, 0x0FEE},
41 {0x0F9B, 0x01AC, 0x0FB9},
42 {0x0FE0, 0x0EC0, 0x0260}
43 }, /* RGB Offset */
44 {0x0000, 0x0000, 0x0000}
45 };
46
47 /* Default values in Office Fluorescent Light for RGB to YUV Conversion*/
48 static struct omap3isp_prev_csc flr_prev_csc = {
49 { /* CSC Coef Matrix */
50 {66, 129, 25},
51 {-38, -75, 112},
52 {112, -94 , -18}
53 }, /* CSC Offset */
54 {0x0, 0x0, 0x0}
55 };
56
57 /* Default values in Office Fluorescent Light for CFA Gradient*/
58 #define FLR_CFA_GRADTHRS_HORZ 0x28
59 #define FLR_CFA_GRADTHRS_VERT 0x28
60
61 /* Default values in Office Fluorescent Light for Chroma Suppression*/
62 #define FLR_CSUP_GAIN 0x0D
63 #define FLR_CSUP_THRES 0xEB
64
65 /* Default values in Office Fluorescent Light for Noise Filter*/
66 #define FLR_NF_STRGTH 0x03
67
68 /* Default values for White Balance */
69 #define FLR_WBAL_DGAIN 0x100
70 #define FLR_WBAL_COEF 0x20
71
72 /* Default values in Office Fluorescent Light for Black Adjustment*/
73 #define FLR_BLKADJ_BLUE 0x0
74 #define FLR_BLKADJ_GREEN 0x0
75 #define FLR_BLKADJ_RED 0x0
76
77 #define DEF_DETECT_CORRECT_VAL 0xe
78
79 /*
80 * Margins and image size limits.
81 *
82 * The preview engine crops several rows and columns internally depending on
83 * which filters are enabled. To avoid format changes when the filters are
84 * enabled or disabled (which would prevent them from being turned on or off
85 * during streaming), the driver assumes all the filters are enabled when
86 * computing sink crop and source format limits.
87 *
88 * If a filter is disabled, additional cropping is automatically added at the
89 * preview engine input by the driver to avoid overflow at line and frame end.
90 * This is completely transparent for applications.
91 *
92 * Median filter 4 pixels
93 * Noise filter,
94 * Faulty pixels correction 4 pixels, 4 lines
95 * CFA filter 4 pixels, 4 lines in Bayer mode
96 * 2 lines in other modes
97 * Color suppression 2 pixels
98 * or luma enhancement
99 * -------------------------------------------------------------
100 * Maximum total 14 pixels, 8 lines
101 *
102 * The color suppression and luma enhancement filters are applied after bayer to
103 * YUV conversion. They thus can crop one pixel on the left and one pixel on the
104 * right side of the image without changing the color pattern. When both those
105 * filters are disabled, the driver must crop the two pixels on the same side of
106 * the image to avoid changing the bayer pattern. The left margin is thus set to
107 * 8 pixels and the right margin to 6 pixels.
108 */
109
110 #define PREV_MARGIN_LEFT 8
111 #define PREV_MARGIN_RIGHT 6
112 #define PREV_MARGIN_TOP 4
113 #define PREV_MARGIN_BOTTOM 4
114
115 #define PREV_MIN_IN_WIDTH 64
116 #define PREV_MIN_IN_HEIGHT 8
117 #define PREV_MAX_IN_HEIGHT 16384
118
119 #define PREV_MIN_OUT_WIDTH 0
120 #define PREV_MIN_OUT_HEIGHT 0
121 #define PREV_MAX_OUT_WIDTH 1280
122 #define PREV_MAX_OUT_WIDTH_ES2 3300
123 #define PREV_MAX_OUT_WIDTH_3630 4096
124
125 /*
126 * Coeficient Tables for the submodules in Preview.
127 * Array is initialised with the values from.the tables text file.
128 */
129
130 /*
131 * CFA Filter Coefficient Table
132 *
133 */
134 static u32 cfa_coef_table[] = {
135 #include "cfa_coef_table.h"
136 };
137
138 /*
139 * Default Gamma Correction Table - All components
140 */
141 static u32 gamma_table[] = {
142 #include "gamma_table.h"
143 };
144
145 /*
146 * Noise Filter Threshold table
147 */
148 static u32 noise_filter_table[] = {
149 #include "noise_filter_table.h"
150 };
151
152 /*
153 * Luminance Enhancement Table
154 */
155 static u32 luma_enhance_table[] = {
156 #include "luma_enhance_table.h"
157 };
158
159 /*
160 * preview_enable_invalaw - Enable/Disable Inverse A-Law module in Preview.
161 * @enable: 1 - Reverse the A-Law done in CCDC.
162 */
163 static void
164 preview_enable_invalaw(struct isp_prev_device *prev, u8 enable)
165 {
166 struct isp_device *isp = to_isp_device(prev);
167
168 if (enable)
169 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
170 ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW);
171 else
172 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
173 ISPPRV_PCR_WIDTH | ISPPRV_PCR_INVALAW);
174 }
175
176 /*
177 * preview_enable_drkframe_capture - Enable/Disable of the darkframe capture.
178 * @prev -
179 * @enable: 1 - Enable, 0 - Disable
180 *
181 * NOTE: PRV_WSDR_ADDR and PRV_WADD_OFFSET must be set also
182 * The process is applied for each captured frame.
183 */
184 static void
185 preview_enable_drkframe_capture(struct isp_prev_device *prev, u8 enable)
186 {
187 struct isp_device *isp = to_isp_device(prev);
188
189 if (enable)
190 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
191 ISPPRV_PCR_DRKFCAP);
192 else
193 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
194 ISPPRV_PCR_DRKFCAP);
195 }
196
197 /*
198 * preview_enable_drkframe - Enable/Disable of the darkframe subtract.
199 * @enable: 1 - Acquires memory bandwidth since the pixels in each frame is
200 * subtracted with the pixels in the current frame.
201 *
202 * The process is applied for each captured frame.
203 */
204 static void
205 preview_enable_drkframe(struct isp_prev_device *prev, u8 enable)
206 {
207 struct isp_device *isp = to_isp_device(prev);
208
209 if (enable)
210 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
211 ISPPRV_PCR_DRKFEN);
212 else
213 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
214 ISPPRV_PCR_DRKFEN);
215 }
216
217 /*
218 * preview_config_drkf_shadcomp - Configures shift value in shading comp.
219 * @scomp_shtval: 3bit value of shift used in shading compensation.
220 */
221 static void
222 preview_config_drkf_shadcomp(struct isp_prev_device *prev,
223 const void *scomp_shtval)
224 {
225 struct isp_device *isp = to_isp_device(prev);
226 const u32 *shtval = scomp_shtval;
227
228 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
229 ISPPRV_PCR_SCOMP_SFT_MASK,
230 *shtval << ISPPRV_PCR_SCOMP_SFT_SHIFT);
231 }
232
233 /*
234 * preview_enable_hmed - Enables/Disables of the Horizontal Median Filter.
235 * @enable: 1 - Enables Horizontal Median Filter.
236 */
237 static void
238 preview_enable_hmed(struct isp_prev_device *prev, u8 enable)
239 {
240 struct isp_device *isp = to_isp_device(prev);
241
242 if (enable)
243 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
244 ISPPRV_PCR_HMEDEN);
245 else
246 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
247 ISPPRV_PCR_HMEDEN);
248 }
249
250 /*
251 * preview_config_hmed - Configures the Horizontal Median Filter.
252 * @prev_hmed: Structure containing the odd and even distance between the
253 * pixels in the image along with the filter threshold.
254 */
255 static void
256 preview_config_hmed(struct isp_prev_device *prev, const void *prev_hmed)
257 {
258 struct isp_device *isp = to_isp_device(prev);
259 const struct omap3isp_prev_hmed *hmed = prev_hmed;
260
261 isp_reg_writel(isp, (hmed->odddist == 1 ? 0 : ISPPRV_HMED_ODDDIST) |
262 (hmed->evendist == 1 ? 0 : ISPPRV_HMED_EVENDIST) |
263 (hmed->thres << ISPPRV_HMED_THRESHOLD_SHIFT),
264 OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED);
265 }
266
267 /*
268 * preview_config_noisefilter - Configures the Noise Filter.
269 * @prev_nf: Structure containing the noisefilter table, strength to be used
270 * for the noise filter and the defect correction enable flag.
271 */
272 static void
273 preview_config_noisefilter(struct isp_prev_device *prev, const void *prev_nf)
274 {
275 struct isp_device *isp = to_isp_device(prev);
276 const struct omap3isp_prev_nf *nf = prev_nf;
277 unsigned int i;
278
279 isp_reg_writel(isp, nf->spread, OMAP3_ISP_IOMEM_PREV, ISPPRV_NF);
280 isp_reg_writel(isp, ISPPRV_NF_TABLE_ADDR,
281 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
282 for (i = 0; i < OMAP3ISP_PREV_NF_TBL_SIZE; i++) {
283 isp_reg_writel(isp, nf->table[i],
284 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
285 }
286 }
287
288 /*
289 * preview_config_dcor - Configures the defect correction
290 * @prev_dcor: Structure containing the defect correct thresholds
291 */
292 static void
293 preview_config_dcor(struct isp_prev_device *prev, const void *prev_dcor)
294 {
295 struct isp_device *isp = to_isp_device(prev);
296 const struct omap3isp_prev_dcor *dcor = prev_dcor;
297
298 isp_reg_writel(isp, dcor->detect_correct[0],
299 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR0);
300 isp_reg_writel(isp, dcor->detect_correct[1],
301 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR1);
302 isp_reg_writel(isp, dcor->detect_correct[2],
303 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR2);
304 isp_reg_writel(isp, dcor->detect_correct[3],
305 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR3);
306 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
307 ISPPRV_PCR_DCCOUP,
308 dcor->couplet_mode_en ? ISPPRV_PCR_DCCOUP : 0);
309 }
310
311 /*
312 * preview_config_cfa - Configures the CFA Interpolation parameters.
313 * @prev_cfa: Structure containing the CFA interpolation table, CFA format
314 * in the image, vertical and horizontal gradient threshold.
315 */
316 static void
317 preview_config_cfa(struct isp_prev_device *prev, const void *prev_cfa)
318 {
319 struct isp_device *isp = to_isp_device(prev);
320 const struct omap3isp_prev_cfa *cfa = prev_cfa;
321 unsigned int i;
322
323 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
324 ISPPRV_PCR_CFAFMT_MASK,
325 cfa->format << ISPPRV_PCR_CFAFMT_SHIFT);
326
327 isp_reg_writel(isp,
328 (cfa->gradthrs_vert << ISPPRV_CFA_GRADTH_VER_SHIFT) |
329 (cfa->gradthrs_horz << ISPPRV_CFA_GRADTH_HOR_SHIFT),
330 OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA);
331
332 isp_reg_writel(isp, ISPPRV_CFA_TABLE_ADDR,
333 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
334
335 for (i = 0; i < OMAP3ISP_PREV_CFA_TBL_SIZE; i++) {
336 isp_reg_writel(isp, cfa->table[i],
337 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
338 }
339 }
340
341 /*
342 * preview_config_gammacorrn - Configures the Gamma Correction table values
343 * @gtable: Structure containing the table for red, blue, green gamma table.
344 */
345 static void
346 preview_config_gammacorrn(struct isp_prev_device *prev, const void *gtable)
347 {
348 struct isp_device *isp = to_isp_device(prev);
349 const struct omap3isp_prev_gtables *gt = gtable;
350 unsigned int i;
351
352 isp_reg_writel(isp, ISPPRV_REDGAMMA_TABLE_ADDR,
353 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
354 for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
355 isp_reg_writel(isp, gt->red[i], OMAP3_ISP_IOMEM_PREV,
356 ISPPRV_SET_TBL_DATA);
357
358 isp_reg_writel(isp, ISPPRV_GREENGAMMA_TABLE_ADDR,
359 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
360 for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
361 isp_reg_writel(isp, gt->green[i], OMAP3_ISP_IOMEM_PREV,
362 ISPPRV_SET_TBL_DATA);
363
364 isp_reg_writel(isp, ISPPRV_BLUEGAMMA_TABLE_ADDR,
365 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
366 for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
367 isp_reg_writel(isp, gt->blue[i], OMAP3_ISP_IOMEM_PREV,
368 ISPPRV_SET_TBL_DATA);
369 }
370
371 /*
372 * preview_config_luma_enhancement - Sets the Luminance Enhancement table.
373 * @ytable: Structure containing the table for Luminance Enhancement table.
374 */
375 static void
376 preview_config_luma_enhancement(struct isp_prev_device *prev,
377 const void *ytable)
378 {
379 struct isp_device *isp = to_isp_device(prev);
380 const struct omap3isp_prev_luma *yt = ytable;
381 unsigned int i;
382
383 isp_reg_writel(isp, ISPPRV_YENH_TABLE_ADDR,
384 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
385 for (i = 0; i < OMAP3ISP_PREV_YENH_TBL_SIZE; i++) {
386 isp_reg_writel(isp, yt->table[i],
387 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
388 }
389 }
390
391 /*
392 * preview_config_chroma_suppression - Configures the Chroma Suppression.
393 * @csup: Structure containing the threshold value for suppression
394 * and the hypass filter enable flag.
395 */
396 static void
397 preview_config_chroma_suppression(struct isp_prev_device *prev,
398 const void *csup)
399 {
400 struct isp_device *isp = to_isp_device(prev);
401 const struct omap3isp_prev_csup *cs = csup;
402
403 isp_reg_writel(isp,
404 cs->gain | (cs->thres << ISPPRV_CSUP_THRES_SHIFT) |
405 (cs->hypf_en << ISPPRV_CSUP_HPYF_SHIFT),
406 OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP);
407 }
408
409 /*
410 * preview_enable_noisefilter - Enables/Disables the Noise Filter.
411 * @enable: 1 - Enables the Noise Filter.
412 */
413 static void
414 preview_enable_noisefilter(struct isp_prev_device *prev, u8 enable)
415 {
416 struct isp_device *isp = to_isp_device(prev);
417
418 if (enable)
419 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
420 ISPPRV_PCR_NFEN);
421 else
422 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
423 ISPPRV_PCR_NFEN);
424 }
425
426 /*
427 * preview_enable_dcor - Enables/Disables the defect correction.
428 * @enable: 1 - Enables the defect correction.
429 */
430 static void
431 preview_enable_dcor(struct isp_prev_device *prev, u8 enable)
432 {
433 struct isp_device *isp = to_isp_device(prev);
434
435 if (enable)
436 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
437 ISPPRV_PCR_DCOREN);
438 else
439 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
440 ISPPRV_PCR_DCOREN);
441 }
442
443 /*
444 * preview_enable_cfa - Enable/Disable the CFA Interpolation.
445 * @enable: 1 - Enables the CFA.
446 */
447 static void
448 preview_enable_cfa(struct isp_prev_device *prev, u8 enable)
449 {
450 struct isp_device *isp = to_isp_device(prev);
451
452 if (enable)
453 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
454 ISPPRV_PCR_CFAEN);
455 else
456 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
457 ISPPRV_PCR_CFAEN);
458 }
459
460 /*
461 * preview_enable_gammabypass - Enables/Disables the GammaByPass
462 * @enable: 1 - Bypasses Gamma - 10bit input is cropped to 8MSB.
463 * 0 - Goes through Gamma Correction. input and output is 10bit.
464 */
465 static void
466 preview_enable_gammabypass(struct isp_prev_device *prev, u8 enable)
467 {
468 struct isp_device *isp = to_isp_device(prev);
469
470 if (enable)
471 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
472 ISPPRV_PCR_GAMMA_BYPASS);
473 else
474 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
475 ISPPRV_PCR_GAMMA_BYPASS);
476 }
477
478 /*
479 * preview_enable_luma_enhancement - Enables/Disables Luminance Enhancement
480 * @enable: 1 - Enable the Luminance Enhancement.
481 */
482 static void
483 preview_enable_luma_enhancement(struct isp_prev_device *prev, u8 enable)
484 {
485 struct isp_device *isp = to_isp_device(prev);
486
487 if (enable)
488 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
489 ISPPRV_PCR_YNENHEN);
490 else
491 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
492 ISPPRV_PCR_YNENHEN);
493 }
494
495 /*
496 * preview_enable_chroma_suppression - Enables/Disables Chrominance Suppr.
497 * @enable: 1 - Enable the Chrominance Suppression.
498 */
499 static void
500 preview_enable_chroma_suppression(struct isp_prev_device *prev, u8 enable)
501 {
502 struct isp_device *isp = to_isp_device(prev);
503
504 if (enable)
505 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
506 ISPPRV_PCR_SUPEN);
507 else
508 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
509 ISPPRV_PCR_SUPEN);
510 }
511
512 /*
513 * preview_config_whitebalance - Configures the White Balance parameters.
514 * @prev_wbal: Structure containing the digital gain and white balance
515 * coefficient.
516 *
517 * Coefficient matrix always with default values.
518 */
519 static void
520 preview_config_whitebalance(struct isp_prev_device *prev, const void *prev_wbal)
521 {
522 struct isp_device *isp = to_isp_device(prev);
523 const struct omap3isp_prev_wbal *wbal = prev_wbal;
524 u32 val;
525
526 isp_reg_writel(isp, wbal->dgain, OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN);
527
528 val = wbal->coef0 << ISPPRV_WBGAIN_COEF0_SHIFT;
529 val |= wbal->coef1 << ISPPRV_WBGAIN_COEF1_SHIFT;
530 val |= wbal->coef2 << ISPPRV_WBGAIN_COEF2_SHIFT;
531 val |= wbal->coef3 << ISPPRV_WBGAIN_COEF3_SHIFT;
532 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN);
533
534 isp_reg_writel(isp,
535 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_0_SHIFT |
536 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_1_SHIFT |
537 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_2_SHIFT |
538 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_3_SHIFT |
539 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_0_SHIFT |
540 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_1_SHIFT |
541 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_2_SHIFT |
542 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_3_SHIFT |
543 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_0_SHIFT |
544 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_1_SHIFT |
545 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_2_SHIFT |
546 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_3_SHIFT |
547 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_0_SHIFT |
548 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_1_SHIFT |
549 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_2_SHIFT |
550 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_3_SHIFT,
551 OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL);
552 }
553
554 /*
555 * preview_config_blkadj - Configures the Black Adjustment parameters.
556 * @prev_blkadj: Structure containing the black adjustment towards red, green,
557 * blue.
558 */
559 static void
560 preview_config_blkadj(struct isp_prev_device *prev, const void *prev_blkadj)
561 {
562 struct isp_device *isp = to_isp_device(prev);
563 const struct omap3isp_prev_blkadj *blkadj = prev_blkadj;
564
565 isp_reg_writel(isp, (blkadj->blue << ISPPRV_BLKADJOFF_B_SHIFT) |
566 (blkadj->green << ISPPRV_BLKADJOFF_G_SHIFT) |
567 (blkadj->red << ISPPRV_BLKADJOFF_R_SHIFT),
568 OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF);
569 }
570
571 /*
572 * preview_config_rgb_blending - Configures the RGB-RGB Blending matrix.
573 * @rgb2rgb: Structure containing the rgb to rgb blending matrix and the rgb
574 * offset.
575 */
576 static void
577 preview_config_rgb_blending(struct isp_prev_device *prev, const void *rgb2rgb)
578 {
579 struct isp_device *isp = to_isp_device(prev);
580 const struct omap3isp_prev_rgbtorgb *rgbrgb = rgb2rgb;
581 u32 val;
582
583 val = (rgbrgb->matrix[0][0] & 0xfff) << ISPPRV_RGB_MAT1_MTX_RR_SHIFT;
584 val |= (rgbrgb->matrix[0][1] & 0xfff) << ISPPRV_RGB_MAT1_MTX_GR_SHIFT;
585 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1);
586
587 val = (rgbrgb->matrix[0][2] & 0xfff) << ISPPRV_RGB_MAT2_MTX_BR_SHIFT;
588 val |= (rgbrgb->matrix[1][0] & 0xfff) << ISPPRV_RGB_MAT2_MTX_RG_SHIFT;
589 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2);
590
591 val = (rgbrgb->matrix[1][1] & 0xfff) << ISPPRV_RGB_MAT3_MTX_GG_SHIFT;
592 val |= (rgbrgb->matrix[1][2] & 0xfff) << ISPPRV_RGB_MAT3_MTX_BG_SHIFT;
593 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3);
594
595 val = (rgbrgb->matrix[2][0] & 0xfff) << ISPPRV_RGB_MAT4_MTX_RB_SHIFT;
596 val |= (rgbrgb->matrix[2][1] & 0xfff) << ISPPRV_RGB_MAT4_MTX_GB_SHIFT;
597 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4);
598
599 val = (rgbrgb->matrix[2][2] & 0xfff) << ISPPRV_RGB_MAT5_MTX_BB_SHIFT;
600 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5);
601
602 val = (rgbrgb->offset[0] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT;
603 val |= (rgbrgb->offset[1] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT;
604 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1);
605
606 val = (rgbrgb->offset[2] & 0x3ff) << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT;
607 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2);
608 }
609
610 /*
611 * Configures the RGB-YCbYCr conversion matrix
612 * @prev_csc: Structure containing the RGB to YCbYCr matrix and the
613 * YCbCr offset.
614 */
615 static void
616 preview_config_rgb_to_ycbcr(struct isp_prev_device *prev, const void *prev_csc)
617 {
618 struct isp_device *isp = to_isp_device(prev);
619 const struct omap3isp_prev_csc *csc = prev_csc;
620 u32 val;
621
622 val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT;
623 val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT;
624 val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT;
625 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0);
626
627 val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT;
628 val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT;
629 val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT;
630 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1);
631
632 val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT;
633 val |= (csc->matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT;
634 val |= (csc->matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT;
635 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2);
636
637 val = (csc->offset[0] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT;
638 val |= (csc->offset[1] & 0xff) << ISPPRV_CSC_OFFSET_CB_SHIFT;
639 val |= (csc->offset[2] & 0xff) << ISPPRV_CSC_OFFSET_CR_SHIFT;
640 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET);
641 }
642
643 /*
644 * preview_update_contrast - Updates the contrast.
645 * @contrast: Pointer to hold the current programmed contrast value.
646 *
647 * Value should be programmed before enabling the module.
648 */
649 static void
650 preview_update_contrast(struct isp_prev_device *prev, u8 contrast)
651 {
652 struct prev_params *params = &prev->params;
653
654 if (params->contrast != (contrast * ISPPRV_CONTRAST_UNITS)) {
655 params->contrast = contrast * ISPPRV_CONTRAST_UNITS;
656 prev->update |= PREV_CONTRAST;
657 }
658 }
659
660 /*
661 * preview_config_contrast - Configures the Contrast.
662 * @params: Contrast value (u8 pointer, U8Q0 format).
663 *
664 * Value should be programmed before enabling the module.
665 */
666 static void
667 preview_config_contrast(struct isp_prev_device *prev, const void *params)
668 {
669 struct isp_device *isp = to_isp_device(prev);
670
671 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT,
672 0xff << ISPPRV_CNT_BRT_CNT_SHIFT,
673 *(u8 *)params << ISPPRV_CNT_BRT_CNT_SHIFT);
674 }
675
676 /*
677 * preview_update_brightness - Updates the brightness in preview module.
678 * @brightness: Pointer to hold the current programmed brightness value.
679 *
680 */
681 static void
682 preview_update_brightness(struct isp_prev_device *prev, u8 brightness)
683 {
684 struct prev_params *params = &prev->params;
685
686 if (params->brightness != (brightness * ISPPRV_BRIGHT_UNITS)) {
687 params->brightness = brightness * ISPPRV_BRIGHT_UNITS;
688 prev->update |= PREV_BRIGHTNESS;
689 }
690 }
691
692 /*
693 * preview_config_brightness - Configures the brightness.
694 * @params: Brightness value (u8 pointer, U8Q0 format).
695 */
696 static void
697 preview_config_brightness(struct isp_prev_device *prev, const void *params)
698 {
699 struct isp_device *isp = to_isp_device(prev);
700
701 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT,
702 0xff << ISPPRV_CNT_BRT_BRT_SHIFT,
703 *(u8 *)params << ISPPRV_CNT_BRT_BRT_SHIFT);
704 }
705
706 /*
707 * preview_config_yc_range - Configures the max and min Y and C values.
708 * @yclimit: Structure containing the range of Y and C values.
709 */
710 static void
711 preview_config_yc_range(struct isp_prev_device *prev, const void *yclimit)
712 {
713 struct isp_device *isp = to_isp_device(prev);
714 const struct omap3isp_prev_yclimit *yc = yclimit;
715
716 isp_reg_writel(isp,
717 yc->maxC << ISPPRV_SETUP_YC_MAXC_SHIFT |
718 yc->maxY << ISPPRV_SETUP_YC_MAXY_SHIFT |
719 yc->minC << ISPPRV_SETUP_YC_MINC_SHIFT |
720 yc->minY << ISPPRV_SETUP_YC_MINY_SHIFT,
721 OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC);
722 }
723
724 /* preview parameters update structure */
725 struct preview_update {
726 int cfg_bit;
727 int feature_bit;
728 void (*config)(struct isp_prev_device *, const void *);
729 void (*enable)(struct isp_prev_device *, u8);
730 };
731
732 static struct preview_update update_attrs[] = {
733 {OMAP3ISP_PREV_LUMAENH, PREV_LUMA_ENHANCE,
734 preview_config_luma_enhancement,
735 preview_enable_luma_enhancement},
736 {OMAP3ISP_PREV_INVALAW, PREV_INVERSE_ALAW,
737 NULL,
738 preview_enable_invalaw},
739 {OMAP3ISP_PREV_HRZ_MED, PREV_HORZ_MEDIAN_FILTER,
740 preview_config_hmed,
741 preview_enable_hmed},
742 {OMAP3ISP_PREV_CFA, PREV_CFA,
743 preview_config_cfa,
744 preview_enable_cfa},
745 {OMAP3ISP_PREV_CHROMA_SUPP, PREV_CHROMA_SUPPRESS,
746 preview_config_chroma_suppression,
747 preview_enable_chroma_suppression},
748 {OMAP3ISP_PREV_WB, PREV_WB,
749 preview_config_whitebalance,
750 NULL},
751 {OMAP3ISP_PREV_BLKADJ, PREV_BLKADJ,
752 preview_config_blkadj,
753 NULL},
754 {OMAP3ISP_PREV_RGB2RGB, PREV_RGB2RGB,
755 preview_config_rgb_blending,
756 NULL},
757 {OMAP3ISP_PREV_COLOR_CONV, PREV_COLOR_CONV,
758 preview_config_rgb_to_ycbcr,
759 NULL},
760 {OMAP3ISP_PREV_YC_LIMIT, PREV_YCLIMITS,
761 preview_config_yc_range,
762 NULL},
763 {OMAP3ISP_PREV_DEFECT_COR, PREV_DEFECT_COR,
764 preview_config_dcor,
765 preview_enable_dcor},
766 {OMAP3ISP_PREV_GAMMABYPASS, PREV_GAMMA_BYPASS,
767 NULL,
768 preview_enable_gammabypass},
769 {OMAP3ISP_PREV_DRK_FRM_CAPTURE, PREV_DARK_FRAME_CAPTURE,
770 NULL,
771 preview_enable_drkframe_capture},
772 {OMAP3ISP_PREV_DRK_FRM_SUBTRACT, PREV_DARK_FRAME_SUBTRACT,
773 NULL,
774 preview_enable_drkframe},
775 {OMAP3ISP_PREV_LENS_SHADING, PREV_LENS_SHADING,
776 preview_config_drkf_shadcomp,
777 preview_enable_drkframe},
778 {OMAP3ISP_PREV_NF, PREV_NOISE_FILTER,
779 preview_config_noisefilter,
780 preview_enable_noisefilter},
781 {OMAP3ISP_PREV_GAMMA, PREV_GAMMA,
782 preview_config_gammacorrn,
783 NULL},
784 {-1, PREV_CONTRAST,
785 preview_config_contrast,
786 NULL},
787 {-1, PREV_BRIGHTNESS,
788 preview_config_brightness,
789 NULL},
790 };
791
792 /*
793 * __preview_get_ptrs - helper function which return pointers to members
794 * of params and config structures.
795 * @params - pointer to preview_params structure.
796 * @param - return pointer to appropriate structure field.
797 * @configs - pointer to update config structure.
798 * @config - return pointer to appropriate structure field.
799 * @bit - for which feature to return pointers.
800 * Return size of corresponding prev_params member
801 */
802 static u32
803 __preview_get_ptrs(struct prev_params *params, void **param,
804 struct omap3isp_prev_update_config *configs,
805 void __user **config, u32 bit)
806 {
807 #define CHKARG(cfgs, cfg, field) \
808 if (cfgs && cfg) { \
809 *(cfg) = (cfgs)->field; \
810 }
811
812 switch (bit) {
813 case PREV_HORZ_MEDIAN_FILTER:
814 *param = &params->hmed;
815 CHKARG(configs, config, hmed)
816 return sizeof(params->hmed);
817 case PREV_NOISE_FILTER:
818 *param = &params->nf;
819 CHKARG(configs, config, nf)
820 return sizeof(params->nf);
821 break;
822 case PREV_CFA:
823 *param = &params->cfa;
824 CHKARG(configs, config, cfa)
825 return sizeof(params->cfa);
826 case PREV_LUMA_ENHANCE:
827 *param = &params->luma;
828 CHKARG(configs, config, luma)
829 return sizeof(params->luma);
830 case PREV_CHROMA_SUPPRESS:
831 *param = &params->csup;
832 CHKARG(configs, config, csup)
833 return sizeof(params->csup);
834 case PREV_DEFECT_COR:
835 *param = &params->dcor;
836 CHKARG(configs, config, dcor)
837 return sizeof(params->dcor);
838 case PREV_BLKADJ:
839 *param = &params->blk_adj;
840 CHKARG(configs, config, blkadj)
841 return sizeof(params->blk_adj);
842 case PREV_YCLIMITS:
843 *param = &params->yclimit;
844 CHKARG(configs, config, yclimit)
845 return sizeof(params->yclimit);
846 case PREV_RGB2RGB:
847 *param = &params->rgb2rgb;
848 CHKARG(configs, config, rgb2rgb)
849 return sizeof(params->rgb2rgb);
850 case PREV_COLOR_CONV:
851 *param = &params->rgb2ycbcr;
852 CHKARG(configs, config, csc)
853 return sizeof(params->rgb2ycbcr);
854 case PREV_WB:
855 *param = &params->wbal;
856 CHKARG(configs, config, wbal)
857 return sizeof(params->wbal);
858 case PREV_GAMMA:
859 *param = &params->gamma;
860 CHKARG(configs, config, gamma)
861 return sizeof(params->gamma);
862 case PREV_CONTRAST:
863 *param = &params->contrast;
864 return 0;
865 case PREV_BRIGHTNESS:
866 *param = &params->brightness;
867 return 0;
868 default:
869 *param = NULL;
870 *config = NULL;
871 break;
872 }
873 return 0;
874 }
875
876 /*
877 * preview_config - Copy and update local structure with userspace preview
878 * configuration.
879 * @prev: ISP preview engine
880 * @cfg: Configuration
881 *
882 * Return zero if success or -EFAULT if the configuration can't be copied from
883 * userspace.
884 */
885 static int preview_config(struct isp_prev_device *prev,
886 struct omap3isp_prev_update_config *cfg)
887 {
888 struct prev_params *params;
889 struct preview_update *attr;
890 int i, bit, rval = 0;
891
892 params = &prev->params;
893
894 if (prev->state != ISP_PIPELINE_STREAM_STOPPED) {
895 unsigned long flags;
896
897 spin_lock_irqsave(&prev->lock, flags);
898 prev->shadow_update = 1;
899 spin_unlock_irqrestore(&prev->lock, flags);
900 }
901
902 for (i = 0; i < ARRAY_SIZE(update_attrs); i++) {
903 attr = &update_attrs[i];
904 bit = 0;
905
906 if (!(cfg->update & attr->cfg_bit))
907 continue;
908
909 bit = cfg->flag & attr->cfg_bit;
910 if (bit) {
911 void *to = NULL, __user *from = NULL;
912 unsigned long sz = 0;
913
914 sz = __preview_get_ptrs(params, &to, cfg, &from,
915 bit);
916 if (to && from && sz) {
917 if (copy_from_user(to, from, sz)) {
918 rval = -EFAULT;
919 break;
920 }
921 }
922 params->features |= attr->feature_bit;
923 } else {
924 params->features &= ~attr->feature_bit;
925 }
926
927 prev->update |= attr->feature_bit;
928 }
929
930 prev->shadow_update = 0;
931 return rval;
932 }
933
934 /*
935 * preview_setup_hw - Setup preview registers and/or internal memory
936 * @prev: pointer to preview private structure
937 * Note: can be called from interrupt context
938 * Return none
939 */
940 static void preview_setup_hw(struct isp_prev_device *prev)
941 {
942 struct prev_params *params = &prev->params;
943 struct preview_update *attr;
944 int i, bit;
945 void *param_ptr;
946
947 for (i = 0; i < ARRAY_SIZE(update_attrs); i++) {
948 attr = &update_attrs[i];
949
950 if (!(prev->update & attr->feature_bit))
951 continue;
952 bit = params->features & attr->feature_bit;
953 if (bit) {
954 if (attr->config) {
955 __preview_get_ptrs(params, &param_ptr, NULL,
956 NULL, bit);
957 attr->config(prev, param_ptr);
958 }
959 if (attr->enable)
960 attr->enable(prev, 1);
961 } else
962 if (attr->enable)
963 attr->enable(prev, 0);
964
965 prev->update &= ~attr->feature_bit;
966 }
967 }
968
969 /*
970 * preview_config_ycpos - Configure byte layout of YUV image.
971 * @mode: Indicates the required byte layout.
972 */
973 static void
974 preview_config_ycpos(struct isp_prev_device *prev,
975 enum v4l2_mbus_pixelcode pixelcode)
976 {
977 struct isp_device *isp = to_isp_device(prev);
978 enum preview_ycpos_mode mode;
979
980 switch (pixelcode) {
981 case V4L2_MBUS_FMT_YUYV8_1X16:
982 mode = YCPOS_CrYCbY;
983 break;
984 case V4L2_MBUS_FMT_UYVY8_1X16:
985 mode = YCPOS_YCrYCb;
986 break;
987 default:
988 return;
989 }
990
991 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
992 ISPPRV_PCR_YCPOS_CrYCbY,
993 mode << ISPPRV_PCR_YCPOS_SHIFT);
994 }
995
996 /*
997 * preview_config_averager - Enable / disable / configure averager
998 * @average: Average value to be configured.
999 */
1000 static void preview_config_averager(struct isp_prev_device *prev, u8 average)
1001 {
1002 struct isp_device *isp = to_isp_device(prev);
1003 int reg = 0;
1004
1005 if (prev->params.cfa.format == OMAP3ISP_CFAFMT_BAYER)
1006 reg = ISPPRV_AVE_EVENDIST_2 << ISPPRV_AVE_EVENDIST_SHIFT |
1007 ISPPRV_AVE_ODDDIST_2 << ISPPRV_AVE_ODDDIST_SHIFT |
1008 average;
1009 else if (prev->params.cfa.format == OMAP3ISP_CFAFMT_RGBFOVEON)
1010 reg = ISPPRV_AVE_EVENDIST_3 << ISPPRV_AVE_EVENDIST_SHIFT |
1011 ISPPRV_AVE_ODDDIST_3 << ISPPRV_AVE_ODDDIST_SHIFT |
1012 average;
1013 isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE);
1014 }
1015
1016 /*
1017 * preview_config_input_size - Configure the input frame size
1018 *
1019 * The preview engine crops several rows and columns internally depending on
1020 * which processing blocks are enabled. The driver assumes all those blocks are
1021 * enabled when reporting source pad formats to userspace. If this assumption is
1022 * not true, rows and columns must be manually cropped at the preview engine
1023 * input to avoid overflows at the end of lines and frames.
1024 *
1025 * See the explanation at the PREV_MARGIN_* definitions for more details.
1026 */
1027 static void preview_config_input_size(struct isp_prev_device *prev)
1028 {
1029 struct isp_device *isp = to_isp_device(prev);
1030 struct prev_params *params = &prev->params;
1031 unsigned int sph = prev->crop.left;
1032 unsigned int eph = prev->crop.left + prev->crop.width - 1;
1033 unsigned int slv = prev->crop.top;
1034 unsigned int elv = prev->crop.top + prev->crop.height - 1;
1035
1036 if (params->features & PREV_CFA) {
1037 sph -= 2;
1038 eph += 2;
1039 slv -= 2;
1040 elv += 2;
1041 }
1042 if (params->features & (PREV_DEFECT_COR | PREV_NOISE_FILTER)) {
1043 sph -= 2;
1044 eph += 2;
1045 slv -= 2;
1046 elv += 2;
1047 }
1048 if (params->features & PREV_HORZ_MEDIAN_FILTER) {
1049 sph -= 2;
1050 eph += 2;
1051 }
1052 if (params->features & (PREV_CHROMA_SUPPRESS | PREV_LUMA_ENHANCE))
1053 sph -= 2;
1054
1055 isp_reg_writel(isp, (sph << ISPPRV_HORZ_INFO_SPH_SHIFT) | eph,
1056 OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO);
1057 isp_reg_writel(isp, (slv << ISPPRV_VERT_INFO_SLV_SHIFT) | elv,
1058 OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO);
1059 }
1060
1061 /*
1062 * preview_config_inlineoffset - Configures the Read address line offset.
1063 * @prev: Preview module
1064 * @offset: Line offset
1065 *
1066 * According to the TRM, the line offset must be aligned on a 32 bytes boundary.
1067 * However, a hardware bug requires the memory start address to be aligned on a
1068 * 64 bytes boundary, so the offset probably should be aligned on 64 bytes as
1069 * well.
1070 */
1071 static void
1072 preview_config_inlineoffset(struct isp_prev_device *prev, u32 offset)
1073 {
1074 struct isp_device *isp = to_isp_device(prev);
1075
1076 isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
1077 ISPPRV_RADR_OFFSET);
1078 }
1079
1080 /*
1081 * preview_set_inaddr - Sets memory address of input frame.
1082 * @addr: 32bit memory address aligned on 32byte boundary.
1083 *
1084 * Configures the memory address from which the input frame is to be read.
1085 */
1086 static void preview_set_inaddr(struct isp_prev_device *prev, u32 addr)
1087 {
1088 struct isp_device *isp = to_isp_device(prev);
1089
1090 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_RSDR_ADDR);
1091 }
1092
1093 /*
1094 * preview_config_outlineoffset - Configures the Write address line offset.
1095 * @offset: Line Offset for the preview output.
1096 *
1097 * The offset must be a multiple of 32 bytes.
1098 */
1099 static void preview_config_outlineoffset(struct isp_prev_device *prev,
1100 u32 offset)
1101 {
1102 struct isp_device *isp = to_isp_device(prev);
1103
1104 isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
1105 ISPPRV_WADD_OFFSET);
1106 }
1107
1108 /*
1109 * preview_set_outaddr - Sets the memory address to store output frame
1110 * @addr: 32bit memory address aligned on 32byte boundary.
1111 *
1112 * Configures the memory address to which the output frame is written.
1113 */
1114 static void preview_set_outaddr(struct isp_prev_device *prev, u32 addr)
1115 {
1116 struct isp_device *isp = to_isp_device(prev);
1117
1118 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR);
1119 }
1120
1121 static void preview_adjust_bandwidth(struct isp_prev_device *prev)
1122 {
1123 struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity);
1124 struct isp_device *isp = to_isp_device(prev);
1125 const struct v4l2_mbus_framefmt *ifmt = &prev->formats[PREV_PAD_SINK];
1126 unsigned long l3_ick = pipe->l3_ick;
1127 struct v4l2_fract *timeperframe;
1128 unsigned int cycles_per_frame;
1129 unsigned int requests_per_frame;
1130 unsigned int cycles_per_request;
1131 unsigned int minimum;
1132 unsigned int maximum;
1133 unsigned int value;
1134
1135 if (prev->input != PREVIEW_INPUT_MEMORY) {
1136 isp_reg_clr(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP,
1137 ISPSBL_SDR_REQ_PRV_EXP_MASK);
1138 return;
1139 }
1140
1141 /* Compute the minimum number of cycles per request, based on the
1142 * pipeline maximum data rate. This is an absolute lower bound if we
1143 * don't want SBL overflows, so round the value up.
1144 */
1145 cycles_per_request = div_u64((u64)l3_ick / 2 * 256 + pipe->max_rate - 1,
1146 pipe->max_rate);
1147 minimum = DIV_ROUND_UP(cycles_per_request, 32);
1148
1149 /* Compute the maximum number of cycles per request, based on the
1150 * requested frame rate. This is a soft upper bound to achieve a frame
1151 * rate equal or higher than the requested value, so round the value
1152 * down.
1153 */
1154 timeperframe = &pipe->max_timeperframe;
1155
1156 requests_per_frame = DIV_ROUND_UP(ifmt->width * 2, 256) * ifmt->height;
1157 cycles_per_frame = div_u64((u64)l3_ick * timeperframe->numerator,
1158 timeperframe->denominator);
1159 cycles_per_request = cycles_per_frame / requests_per_frame;
1160
1161 maximum = cycles_per_request / 32;
1162
1163 value = max(minimum, maximum);
1164
1165 dev_dbg(isp->dev, "%s: cycles per request = %u\n", __func__, value);
1166 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP,
1167 ISPSBL_SDR_REQ_PRV_EXP_MASK,
1168 value << ISPSBL_SDR_REQ_PRV_EXP_SHIFT);
1169 }
1170
1171 /*
1172 * omap3isp_preview_busy - Gets busy state of preview module.
1173 */
1174 int omap3isp_preview_busy(struct isp_prev_device *prev)
1175 {
1176 struct isp_device *isp = to_isp_device(prev);
1177
1178 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR)
1179 & ISPPRV_PCR_BUSY;
1180 }
1181
1182 /*
1183 * omap3isp_preview_restore_context - Restores the values of preview registers
1184 */
1185 void omap3isp_preview_restore_context(struct isp_device *isp)
1186 {
1187 isp->isp_prev.update = PREV_FEATURES_END - 1;
1188 preview_setup_hw(&isp->isp_prev);
1189 }
1190
1191 /*
1192 * preview_print_status - Dump preview module registers to the kernel log
1193 */
1194 #define PREV_PRINT_REGISTER(isp, name)\
1195 dev_dbg(isp->dev, "###PRV " #name "=0x%08x\n", \
1196 isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_##name))
1197
1198 static void preview_print_status(struct isp_prev_device *prev)
1199 {
1200 struct isp_device *isp = to_isp_device(prev);
1201
1202 dev_dbg(isp->dev, "-------------Preview Register dump----------\n");
1203
1204 PREV_PRINT_REGISTER(isp, PCR);
1205 PREV_PRINT_REGISTER(isp, HORZ_INFO);
1206 PREV_PRINT_REGISTER(isp, VERT_INFO);
1207 PREV_PRINT_REGISTER(isp, RSDR_ADDR);
1208 PREV_PRINT_REGISTER(isp, RADR_OFFSET);
1209 PREV_PRINT_REGISTER(isp, DSDR_ADDR);
1210 PREV_PRINT_REGISTER(isp, DRKF_OFFSET);
1211 PREV_PRINT_REGISTER(isp, WSDR_ADDR);
1212 PREV_PRINT_REGISTER(isp, WADD_OFFSET);
1213 PREV_PRINT_REGISTER(isp, AVE);
1214 PREV_PRINT_REGISTER(isp, HMED);
1215 PREV_PRINT_REGISTER(isp, NF);
1216 PREV_PRINT_REGISTER(isp, WB_DGAIN);
1217 PREV_PRINT_REGISTER(isp, WBGAIN);
1218 PREV_PRINT_REGISTER(isp, WBSEL);
1219 PREV_PRINT_REGISTER(isp, CFA);
1220 PREV_PRINT_REGISTER(isp, BLKADJOFF);
1221 PREV_PRINT_REGISTER(isp, RGB_MAT1);
1222 PREV_PRINT_REGISTER(isp, RGB_MAT2);
1223 PREV_PRINT_REGISTER(isp, RGB_MAT3);
1224 PREV_PRINT_REGISTER(isp, RGB_MAT4);
1225 PREV_PRINT_REGISTER(isp, RGB_MAT5);
1226 PREV_PRINT_REGISTER(isp, RGB_OFF1);
1227 PREV_PRINT_REGISTER(isp, RGB_OFF2);
1228 PREV_PRINT_REGISTER(isp, CSC0);
1229 PREV_PRINT_REGISTER(isp, CSC1);
1230 PREV_PRINT_REGISTER(isp, CSC2);
1231 PREV_PRINT_REGISTER(isp, CSC_OFFSET);
1232 PREV_PRINT_REGISTER(isp, CNT_BRT);
1233 PREV_PRINT_REGISTER(isp, CSUP);
1234 PREV_PRINT_REGISTER(isp, SETUP_YC);
1235 PREV_PRINT_REGISTER(isp, SET_TBL_ADDR);
1236 PREV_PRINT_REGISTER(isp, CDC_THR0);
1237 PREV_PRINT_REGISTER(isp, CDC_THR1);
1238 PREV_PRINT_REGISTER(isp, CDC_THR2);
1239 PREV_PRINT_REGISTER(isp, CDC_THR3);
1240
1241 dev_dbg(isp->dev, "--------------------------------------------\n");
1242 }
1243
1244 /*
1245 * preview_init_params - init image processing parameters.
1246 * @prev: pointer to previewer private structure
1247 * return none
1248 */
1249 static void preview_init_params(struct isp_prev_device *prev)
1250 {
1251 struct prev_params *params = &prev->params;
1252 int i = 0;
1253
1254 /* Init values */
1255 params->contrast = ISPPRV_CONTRAST_DEF * ISPPRV_CONTRAST_UNITS;
1256 params->brightness = ISPPRV_BRIGHT_DEF * ISPPRV_BRIGHT_UNITS;
1257 params->cfa.format = OMAP3ISP_CFAFMT_BAYER;
1258 memcpy(params->cfa.table, cfa_coef_table,
1259 sizeof(params->cfa.table));
1260 params->cfa.gradthrs_horz = FLR_CFA_GRADTHRS_HORZ;
1261 params->cfa.gradthrs_vert = FLR_CFA_GRADTHRS_VERT;
1262 params->csup.gain = FLR_CSUP_GAIN;
1263 params->csup.thres = FLR_CSUP_THRES;
1264 params->csup.hypf_en = 0;
1265 memcpy(params->luma.table, luma_enhance_table,
1266 sizeof(params->luma.table));
1267 params->nf.spread = FLR_NF_STRGTH;
1268 memcpy(params->nf.table, noise_filter_table, sizeof(params->nf.table));
1269 params->dcor.couplet_mode_en = 1;
1270 for (i = 0; i < OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS; i++)
1271 params->dcor.detect_correct[i] = DEF_DETECT_CORRECT_VAL;
1272 memcpy(params->gamma.blue, gamma_table, sizeof(params->gamma.blue));
1273 memcpy(params->gamma.green, gamma_table, sizeof(params->gamma.green));
1274 memcpy(params->gamma.red, gamma_table, sizeof(params->gamma.red));
1275 params->wbal.dgain = FLR_WBAL_DGAIN;
1276 params->wbal.coef0 = FLR_WBAL_COEF;
1277 params->wbal.coef1 = FLR_WBAL_COEF;
1278 params->wbal.coef2 = FLR_WBAL_COEF;
1279 params->wbal.coef3 = FLR_WBAL_COEF;
1280 params->blk_adj.red = FLR_BLKADJ_RED;
1281 params->blk_adj.green = FLR_BLKADJ_GREEN;
1282 params->blk_adj.blue = FLR_BLKADJ_BLUE;
1283 params->rgb2rgb = flr_rgb2rgb;
1284 params->rgb2ycbcr = flr_prev_csc;
1285 params->yclimit.minC = ISPPRV_YC_MIN;
1286 params->yclimit.maxC = ISPPRV_YC_MAX;
1287 params->yclimit.minY = ISPPRV_YC_MIN;
1288 params->yclimit.maxY = ISPPRV_YC_MAX;
1289
1290 params->features = PREV_CFA | PREV_DEFECT_COR | PREV_NOISE_FILTER
1291 | PREV_GAMMA | PREV_BLKADJ | PREV_YCLIMITS
1292 | PREV_RGB2RGB | PREV_COLOR_CONV | PREV_WB
1293 | PREV_BRIGHTNESS | PREV_CONTRAST;
1294
1295 prev->update = PREV_FEATURES_END - 1;
1296 }
1297
1298 /*
1299 * preview_max_out_width - Handle previewer hardware ouput limitations
1300 * @isp_revision : ISP revision
1301 * returns maximum width output for current isp revision
1302 */
1303 static unsigned int preview_max_out_width(struct isp_prev_device *prev)
1304 {
1305 struct isp_device *isp = to_isp_device(prev);
1306
1307 switch (isp->revision) {
1308 case ISP_REVISION_1_0:
1309 return PREV_MAX_OUT_WIDTH;
1310
1311 case ISP_REVISION_2_0:
1312 default:
1313 return PREV_MAX_OUT_WIDTH_ES2;
1314
1315 case ISP_REVISION_15_0:
1316 return PREV_MAX_OUT_WIDTH_3630;
1317 }
1318 }
1319
1320 static void preview_configure(struct isp_prev_device *prev)
1321 {
1322 struct isp_device *isp = to_isp_device(prev);
1323 struct v4l2_mbus_framefmt *format;
1324
1325 preview_setup_hw(prev);
1326
1327 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1328 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1329 ISPPRV_PCR_SDRPORT);
1330 else
1331 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1332 ISPPRV_PCR_SDRPORT);
1333
1334 if (prev->output & PREVIEW_OUTPUT_RESIZER)
1335 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1336 ISPPRV_PCR_RSZPORT);
1337 else
1338 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1339 ISPPRV_PCR_RSZPORT);
1340
1341 /* PREV_PAD_SINK */
1342 format = &prev->formats[PREV_PAD_SINK];
1343
1344 preview_adjust_bandwidth(prev);
1345
1346 preview_config_input_size(prev);
1347
1348 if (prev->input == PREVIEW_INPUT_CCDC)
1349 preview_config_inlineoffset(prev, 0);
1350 else
1351 preview_config_inlineoffset(prev,
1352 ALIGN(format->width, 0x20) * 2);
1353
1354 /* PREV_PAD_SOURCE */
1355 format = &prev->formats[PREV_PAD_SOURCE];
1356
1357 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1358 preview_config_outlineoffset(prev,
1359 ALIGN(format->width, 0x10) * 2);
1360
1361 preview_config_averager(prev, 0);
1362 preview_config_ycpos(prev, format->code);
1363 }
1364
1365 /* -----------------------------------------------------------------------------
1366 * Interrupt handling
1367 */
1368
1369 static void preview_enable_oneshot(struct isp_prev_device *prev)
1370 {
1371 struct isp_device *isp = to_isp_device(prev);
1372
1373 /* The PCR.SOURCE bit is automatically reset to 0 when the PCR.ENABLE
1374 * bit is set. As the preview engine is used in single-shot mode, we
1375 * need to set PCR.SOURCE before enabling the preview engine.
1376 */
1377 if (prev->input == PREVIEW_INPUT_MEMORY)
1378 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1379 ISPPRV_PCR_SOURCE);
1380
1381 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1382 ISPPRV_PCR_EN | ISPPRV_PCR_ONESHOT);
1383 }
1384
1385 void omap3isp_preview_isr_frame_sync(struct isp_prev_device *prev)
1386 {
1387 /*
1388 * If ISP_VIDEO_DMAQUEUE_QUEUED is set, DMA queue had an underrun
1389 * condition, the module was paused and now we have a buffer queued
1390 * on the output again. Restart the pipeline if running in continuous
1391 * mode.
1392 */
1393 if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS &&
1394 prev->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED) {
1395 preview_enable_oneshot(prev);
1396 isp_video_dmaqueue_flags_clr(&prev->video_out);
1397 }
1398 }
1399
1400 static void preview_isr_buffer(struct isp_prev_device *prev)
1401 {
1402 struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity);
1403 struct isp_buffer *buffer;
1404 int restart = 0;
1405
1406 if (prev->input == PREVIEW_INPUT_MEMORY) {
1407 buffer = omap3isp_video_buffer_next(&prev->video_in,
1408 prev->error);
1409 if (buffer != NULL)
1410 preview_set_inaddr(prev, buffer->isp_addr);
1411 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
1412 }
1413
1414 if (prev->output & PREVIEW_OUTPUT_MEMORY) {
1415 buffer = omap3isp_video_buffer_next(&prev->video_out,
1416 prev->error);
1417 if (buffer != NULL) {
1418 preview_set_outaddr(prev, buffer->isp_addr);
1419 restart = 1;
1420 }
1421 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1422 }
1423
1424 switch (prev->state) {
1425 case ISP_PIPELINE_STREAM_SINGLESHOT:
1426 if (isp_pipeline_ready(pipe))
1427 omap3isp_pipeline_set_stream(pipe,
1428 ISP_PIPELINE_STREAM_SINGLESHOT);
1429 break;
1430
1431 case ISP_PIPELINE_STREAM_CONTINUOUS:
1432 /* If an underrun occurs, the video queue operation handler will
1433 * restart the preview engine. Otherwise restart it immediately.
1434 */
1435 if (restart)
1436 preview_enable_oneshot(prev);
1437 break;
1438
1439 case ISP_PIPELINE_STREAM_STOPPED:
1440 default:
1441 return;
1442 }
1443
1444 prev->error = 0;
1445 }
1446
1447 /*
1448 * omap3isp_preview_isr - ISP preview engine interrupt handler
1449 *
1450 * Manage the preview engine video buffers and configure shadowed registers.
1451 */
1452 void omap3isp_preview_isr(struct isp_prev_device *prev)
1453 {
1454 unsigned long flags;
1455
1456 if (omap3isp_module_sync_is_stopping(&prev->wait, &prev->stopping))
1457 return;
1458
1459 spin_lock_irqsave(&prev->lock, flags);
1460 if (prev->shadow_update)
1461 goto done;
1462
1463 preview_setup_hw(prev);
1464 preview_config_input_size(prev);
1465
1466 done:
1467 spin_unlock_irqrestore(&prev->lock, flags);
1468
1469 if (prev->input == PREVIEW_INPUT_MEMORY ||
1470 prev->output & PREVIEW_OUTPUT_MEMORY)
1471 preview_isr_buffer(prev);
1472 else if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1473 preview_enable_oneshot(prev);
1474 }
1475
1476 /* -----------------------------------------------------------------------------
1477 * ISP video operations
1478 */
1479
1480 static int preview_video_queue(struct isp_video *video,
1481 struct isp_buffer *buffer)
1482 {
1483 struct isp_prev_device *prev = &video->isp->isp_prev;
1484
1485 if (video->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1486 preview_set_inaddr(prev, buffer->isp_addr);
1487
1488 if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1489 preview_set_outaddr(prev, buffer->isp_addr);
1490
1491 return 0;
1492 }
1493
1494 static const struct isp_video_operations preview_video_ops = {
1495 .queue = preview_video_queue,
1496 };
1497
1498 /* -----------------------------------------------------------------------------
1499 * V4L2 subdev operations
1500 */
1501
1502 /*
1503 * preview_s_ctrl - Handle set control subdev method
1504 * @ctrl: pointer to v4l2 control structure
1505 */
1506 static int preview_s_ctrl(struct v4l2_ctrl *ctrl)
1507 {
1508 struct isp_prev_device *prev =
1509 container_of(ctrl->handler, struct isp_prev_device, ctrls);
1510
1511 switch (ctrl->id) {
1512 case V4L2_CID_BRIGHTNESS:
1513 preview_update_brightness(prev, ctrl->val);
1514 break;
1515 case V4L2_CID_CONTRAST:
1516 preview_update_contrast(prev, ctrl->val);
1517 break;
1518 }
1519
1520 return 0;
1521 }
1522
1523 static const struct v4l2_ctrl_ops preview_ctrl_ops = {
1524 .s_ctrl = preview_s_ctrl,
1525 };
1526
1527 /*
1528 * preview_ioctl - Handle preview module private ioctl's
1529 * @prev: pointer to preview context structure
1530 * @cmd: configuration command
1531 * @arg: configuration argument
1532 * return -EINVAL or zero on success
1533 */
1534 static long preview_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1535 {
1536 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1537
1538 switch (cmd) {
1539 case VIDIOC_OMAP3ISP_PRV_CFG:
1540 return preview_config(prev, arg);
1541
1542 default:
1543 return -ENOIOCTLCMD;
1544 }
1545 }
1546
1547 /*
1548 * preview_set_stream - Enable/Disable streaming on preview subdev
1549 * @sd : pointer to v4l2 subdev structure
1550 * @enable: 1 == Enable, 0 == Disable
1551 * return -EINVAL or zero on success
1552 */
1553 static int preview_set_stream(struct v4l2_subdev *sd, int enable)
1554 {
1555 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1556 struct isp_video *video_out = &prev->video_out;
1557 struct isp_device *isp = to_isp_device(prev);
1558 struct device *dev = to_device(prev);
1559 unsigned long flags;
1560
1561 if (prev->state == ISP_PIPELINE_STREAM_STOPPED) {
1562 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1563 return 0;
1564
1565 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_PREVIEW);
1566 preview_configure(prev);
1567 atomic_set(&prev->stopping, 0);
1568 prev->error = 0;
1569 preview_print_status(prev);
1570 }
1571
1572 switch (enable) {
1573 case ISP_PIPELINE_STREAM_CONTINUOUS:
1574 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1575 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
1576
1577 if (video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED ||
1578 !(prev->output & PREVIEW_OUTPUT_MEMORY))
1579 preview_enable_oneshot(prev);
1580
1581 isp_video_dmaqueue_flags_clr(video_out);
1582 break;
1583
1584 case ISP_PIPELINE_STREAM_SINGLESHOT:
1585 if (prev->input == PREVIEW_INPUT_MEMORY)
1586 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_READ);
1587 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1588 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
1589
1590 preview_enable_oneshot(prev);
1591 break;
1592
1593 case ISP_PIPELINE_STREAM_STOPPED:
1594 if (omap3isp_module_sync_idle(&sd->entity, &prev->wait,
1595 &prev->stopping))
1596 dev_dbg(dev, "%s: stop timeout.\n", sd->name);
1597 spin_lock_irqsave(&prev->lock, flags);
1598 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_READ);
1599 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
1600 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_PREVIEW);
1601 spin_unlock_irqrestore(&prev->lock, flags);
1602 isp_video_dmaqueue_flags_clr(video_out);
1603 break;
1604 }
1605
1606 prev->state = enable;
1607 return 0;
1608 }
1609
1610 static struct v4l2_mbus_framefmt *
1611 __preview_get_format(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh,
1612 unsigned int pad, enum v4l2_subdev_format_whence which)
1613 {
1614 if (which == V4L2_SUBDEV_FORMAT_TRY)
1615 return v4l2_subdev_get_try_format(fh, pad);
1616 else
1617 return &prev->formats[pad];
1618 }
1619
1620 static struct v4l2_rect *
1621 __preview_get_crop(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh,
1622 enum v4l2_subdev_format_whence which)
1623 {
1624 if (which == V4L2_SUBDEV_FORMAT_TRY)
1625 return v4l2_subdev_get_try_crop(fh, PREV_PAD_SINK);
1626 else
1627 return &prev->crop;
1628 }
1629
1630 /* previewer format descriptions */
1631 static const unsigned int preview_input_fmts[] = {
1632 V4L2_MBUS_FMT_SGRBG10_1X10,
1633 V4L2_MBUS_FMT_SRGGB10_1X10,
1634 V4L2_MBUS_FMT_SBGGR10_1X10,
1635 V4L2_MBUS_FMT_SGBRG10_1X10,
1636 };
1637
1638 static const unsigned int preview_output_fmts[] = {
1639 V4L2_MBUS_FMT_UYVY8_1X16,
1640 V4L2_MBUS_FMT_YUYV8_1X16,
1641 };
1642
1643 /*
1644 * preview_try_format - Validate a format
1645 * @prev: ISP preview engine
1646 * @fh: V4L2 subdev file handle
1647 * @pad: pad number
1648 * @fmt: format to be validated
1649 * @which: try/active format selector
1650 *
1651 * Validate and adjust the given format for the given pad based on the preview
1652 * engine limits and the format and crop rectangles on other pads.
1653 */
1654 static void preview_try_format(struct isp_prev_device *prev,
1655 struct v4l2_subdev_fh *fh, unsigned int pad,
1656 struct v4l2_mbus_framefmt *fmt,
1657 enum v4l2_subdev_format_whence which)
1658 {
1659 enum v4l2_mbus_pixelcode pixelcode;
1660 struct v4l2_rect *crop;
1661 unsigned int i;
1662
1663 switch (pad) {
1664 case PREV_PAD_SINK:
1665 /* When reading data from the CCDC, the input size has already
1666 * been mangled by the CCDC output pad so it can be accepted
1667 * as-is.
1668 *
1669 * When reading data from memory, clamp the requested width and
1670 * height. The TRM doesn't specify a minimum input height, make
1671 * sure we got enough lines to enable the noise filter and color
1672 * filter array interpolation.
1673 */
1674 if (prev->input == PREVIEW_INPUT_MEMORY) {
1675 fmt->width = clamp_t(u32, fmt->width, PREV_MIN_IN_WIDTH,
1676 preview_max_out_width(prev));
1677 fmt->height = clamp_t(u32, fmt->height,
1678 PREV_MIN_IN_HEIGHT,
1679 PREV_MAX_IN_HEIGHT);
1680 }
1681
1682 fmt->colorspace = V4L2_COLORSPACE_SRGB;
1683
1684 for (i = 0; i < ARRAY_SIZE(preview_input_fmts); i++) {
1685 if (fmt->code == preview_input_fmts[i])
1686 break;
1687 }
1688
1689 /* If not found, use SGRBG10 as default */
1690 if (i >= ARRAY_SIZE(preview_input_fmts))
1691 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
1692 break;
1693
1694 case PREV_PAD_SOURCE:
1695 pixelcode = fmt->code;
1696 *fmt = *__preview_get_format(prev, fh, PREV_PAD_SINK, which);
1697
1698 switch (pixelcode) {
1699 case V4L2_MBUS_FMT_YUYV8_1X16:
1700 case V4L2_MBUS_FMT_UYVY8_1X16:
1701 fmt->code = pixelcode;
1702 break;
1703
1704 default:
1705 fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
1706 break;
1707 }
1708
1709 /* The preview module output size is configurable through the
1710 * averager (horizontal scaling by 1/1, 1/2, 1/4 or 1/8). This
1711 * is not supported yet, hardcode the output size to the crop
1712 * rectangle size.
1713 */
1714 crop = __preview_get_crop(prev, fh, which);
1715 fmt->width = crop->width;
1716 fmt->height = crop->height;
1717
1718 fmt->colorspace = V4L2_COLORSPACE_JPEG;
1719 break;
1720 }
1721
1722 fmt->field = V4L2_FIELD_NONE;
1723 }
1724
1725 /*
1726 * preview_try_crop - Validate a crop rectangle
1727 * @prev: ISP preview engine
1728 * @sink: format on the sink pad
1729 * @crop: crop rectangle to be validated
1730 *
1731 * The preview engine crops lines and columns for its internal operation,
1732 * depending on which filters are enabled. Enforce minimum crop margins to
1733 * handle that transparently for userspace.
1734 *
1735 * See the explanation at the PREV_MARGIN_* definitions for more details.
1736 */
1737 static void preview_try_crop(struct isp_prev_device *prev,
1738 const struct v4l2_mbus_framefmt *sink,
1739 struct v4l2_rect *crop)
1740 {
1741 unsigned int left = PREV_MARGIN_LEFT;
1742 unsigned int right = sink->width - PREV_MARGIN_RIGHT;
1743 unsigned int top = PREV_MARGIN_TOP;
1744 unsigned int bottom = sink->height - PREV_MARGIN_BOTTOM;
1745
1746 /* When processing data on-the-fly from the CCDC, at least 2 pixels must
1747 * be cropped from the left and right sides of the image. As we don't
1748 * know which filters will be enabled, increase the left and right
1749 * margins by two.
1750 */
1751 if (prev->input == PREVIEW_INPUT_CCDC) {
1752 left += 2;
1753 right -= 2;
1754 }
1755
1756 /* Restrict left/top to even values to keep the Bayer pattern. */
1757 crop->left &= ~1;
1758 crop->top &= ~1;
1759
1760 crop->left = clamp_t(u32, crop->left, left, right - PREV_MIN_OUT_WIDTH);
1761 crop->top = clamp_t(u32, crop->top, top, bottom - PREV_MIN_OUT_HEIGHT);
1762 crop->width = clamp_t(u32, crop->width, PREV_MIN_OUT_WIDTH,
1763 right - crop->left);
1764 crop->height = clamp_t(u32, crop->height, PREV_MIN_OUT_HEIGHT,
1765 bottom - crop->top);
1766 }
1767
1768 /*
1769 * preview_enum_mbus_code - Handle pixel format enumeration
1770 * @sd : pointer to v4l2 subdev structure
1771 * @fh : V4L2 subdev file handle
1772 * @code : pointer to v4l2_subdev_mbus_code_enum structure
1773 * return -EINVAL or zero on success
1774 */
1775 static int preview_enum_mbus_code(struct v4l2_subdev *sd,
1776 struct v4l2_subdev_fh *fh,
1777 struct v4l2_subdev_mbus_code_enum *code)
1778 {
1779 switch (code->pad) {
1780 case PREV_PAD_SINK:
1781 if (code->index >= ARRAY_SIZE(preview_input_fmts))
1782 return -EINVAL;
1783
1784 code->code = preview_input_fmts[code->index];
1785 break;
1786 case PREV_PAD_SOURCE:
1787 if (code->index >= ARRAY_SIZE(preview_output_fmts))
1788 return -EINVAL;
1789
1790 code->code = preview_output_fmts[code->index];
1791 break;
1792 default:
1793 return -EINVAL;
1794 }
1795
1796 return 0;
1797 }
1798
1799 static int preview_enum_frame_size(struct v4l2_subdev *sd,
1800 struct v4l2_subdev_fh *fh,
1801 struct v4l2_subdev_frame_size_enum *fse)
1802 {
1803 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1804 struct v4l2_mbus_framefmt format;
1805
1806 if (fse->index != 0)
1807 return -EINVAL;
1808
1809 format.code = fse->code;
1810 format.width = 1;
1811 format.height = 1;
1812 preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
1813 fse->min_width = format.width;
1814 fse->min_height = format.height;
1815
1816 if (format.code != fse->code)
1817 return -EINVAL;
1818
1819 format.code = fse->code;
1820 format.width = -1;
1821 format.height = -1;
1822 preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
1823 fse->max_width = format.width;
1824 fse->max_height = format.height;
1825
1826 return 0;
1827 }
1828
1829 /*
1830 * preview_get_crop - Retrieve the crop rectangle on a pad
1831 * @sd: ISP preview V4L2 subdevice
1832 * @fh: V4L2 subdev file handle
1833 * @crop: crop rectangle
1834 *
1835 * Return 0 on success or a negative error code otherwise.
1836 */
1837 static int preview_get_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1838 struct v4l2_subdev_crop *crop)
1839 {
1840 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1841
1842 /* Cropping is only supported on the sink pad. */
1843 if (crop->pad != PREV_PAD_SINK)
1844 return -EINVAL;
1845
1846 crop->rect = *__preview_get_crop(prev, fh, crop->which);
1847 return 0;
1848 }
1849
1850 /*
1851 * preview_set_crop - Retrieve the crop rectangle on a pad
1852 * @sd: ISP preview V4L2 subdevice
1853 * @fh: V4L2 subdev file handle
1854 * @crop: crop rectangle
1855 *
1856 * Return 0 on success or a negative error code otherwise.
1857 */
1858 static int preview_set_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1859 struct v4l2_subdev_crop *crop)
1860 {
1861 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1862 struct v4l2_mbus_framefmt *format;
1863
1864 /* Cropping is only supported on the sink pad. */
1865 if (crop->pad != PREV_PAD_SINK)
1866 return -EINVAL;
1867
1868 /* The crop rectangle can't be changed while streaming. */
1869 if (prev->state != ISP_PIPELINE_STREAM_STOPPED)
1870 return -EBUSY;
1871
1872 format = __preview_get_format(prev, fh, PREV_PAD_SINK, crop->which);
1873 preview_try_crop(prev, format, &crop->rect);
1874 *__preview_get_crop(prev, fh, crop->which) = crop->rect;
1875
1876 /* Update the source format. */
1877 format = __preview_get_format(prev, fh, PREV_PAD_SOURCE, crop->which);
1878 preview_try_format(prev, fh, PREV_PAD_SOURCE, format, crop->which);
1879
1880 return 0;
1881 }
1882
1883 /*
1884 * preview_get_format - Handle get format by pads subdev method
1885 * @sd : pointer to v4l2 subdev structure
1886 * @fh : V4L2 subdev file handle
1887 * @fmt: pointer to v4l2 subdev format structure
1888 * return -EINVAL or zero on success
1889 */
1890 static int preview_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1891 struct v4l2_subdev_format *fmt)
1892 {
1893 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1894 struct v4l2_mbus_framefmt *format;
1895
1896 format = __preview_get_format(prev, fh, fmt->pad, fmt->which);
1897 if (format == NULL)
1898 return -EINVAL;
1899
1900 fmt->format = *format;
1901 return 0;
1902 }
1903
1904 /*
1905 * preview_set_format - Handle set format by pads subdev method
1906 * @sd : pointer to v4l2 subdev structure
1907 * @fh : V4L2 subdev file handle
1908 * @fmt: pointer to v4l2 subdev format structure
1909 * return -EINVAL or zero on success
1910 */
1911 static int preview_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1912 struct v4l2_subdev_format *fmt)
1913 {
1914 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1915 struct v4l2_mbus_framefmt *format;
1916 struct v4l2_rect *crop;
1917
1918 format = __preview_get_format(prev, fh, fmt->pad, fmt->which);
1919 if (format == NULL)
1920 return -EINVAL;
1921
1922 preview_try_format(prev, fh, fmt->pad, &fmt->format, fmt->which);
1923 *format = fmt->format;
1924
1925 /* Propagate the format from sink to source */
1926 if (fmt->pad == PREV_PAD_SINK) {
1927 /* Reset the crop rectangle. */
1928 crop = __preview_get_crop(prev, fh, fmt->which);
1929 crop->left = 0;
1930 crop->top = 0;
1931 crop->width = fmt->format.width;
1932 crop->height = fmt->format.height;
1933
1934 preview_try_crop(prev, &fmt->format, crop);
1935
1936 /* Update the source format. */
1937 format = __preview_get_format(prev, fh, PREV_PAD_SOURCE,
1938 fmt->which);
1939 preview_try_format(prev, fh, PREV_PAD_SOURCE, format,
1940 fmt->which);
1941 }
1942
1943 return 0;
1944 }
1945
1946 /*
1947 * preview_init_formats - Initialize formats on all pads
1948 * @sd: ISP preview V4L2 subdevice
1949 * @fh: V4L2 subdev file handle
1950 *
1951 * Initialize all pad formats with default values. If fh is not NULL, try
1952 * formats are initialized on the file handle. Otherwise active formats are
1953 * initialized on the device.
1954 */
1955 static int preview_init_formats(struct v4l2_subdev *sd,
1956 struct v4l2_subdev_fh *fh)
1957 {
1958 struct v4l2_subdev_format format;
1959
1960 memset(&format, 0, sizeof(format));
1961 format.pad = PREV_PAD_SINK;
1962 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1963 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
1964 format.format.width = 4096;
1965 format.format.height = 4096;
1966 preview_set_format(sd, fh, &format);
1967
1968 return 0;
1969 }
1970
1971 /* subdev core operations */
1972 static const struct v4l2_subdev_core_ops preview_v4l2_core_ops = {
1973 .ioctl = preview_ioctl,
1974 };
1975
1976 /* subdev video operations */
1977 static const struct v4l2_subdev_video_ops preview_v4l2_video_ops = {
1978 .s_stream = preview_set_stream,
1979 };
1980
1981 /* subdev pad operations */
1982 static const struct v4l2_subdev_pad_ops preview_v4l2_pad_ops = {
1983 .enum_mbus_code = preview_enum_mbus_code,
1984 .enum_frame_size = preview_enum_frame_size,
1985 .get_fmt = preview_get_format,
1986 .set_fmt = preview_set_format,
1987 .get_crop = preview_get_crop,
1988 .set_crop = preview_set_crop,
1989 };
1990
1991 /* subdev operations */
1992 static const struct v4l2_subdev_ops preview_v4l2_ops = {
1993 .core = &preview_v4l2_core_ops,
1994 .video = &preview_v4l2_video_ops,
1995 .pad = &preview_v4l2_pad_ops,
1996 };
1997
1998 /* subdev internal operations */
1999 static const struct v4l2_subdev_internal_ops preview_v4l2_internal_ops = {
2000 .open = preview_init_formats,
2001 };
2002
2003 /* -----------------------------------------------------------------------------
2004 * Media entity operations
2005 */
2006
2007 /*
2008 * preview_link_setup - Setup previewer connections.
2009 * @entity : Pointer to media entity structure
2010 * @local : Pointer to local pad array
2011 * @remote : Pointer to remote pad array
2012 * @flags : Link flags
2013 * return -EINVAL or zero on success
2014 */
2015 static int preview_link_setup(struct media_entity *entity,
2016 const struct media_pad *local,
2017 const struct media_pad *remote, u32 flags)
2018 {
2019 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2020 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
2021
2022 switch (local->index | media_entity_type(remote->entity)) {
2023 case PREV_PAD_SINK | MEDIA_ENT_T_DEVNODE:
2024 /* read from memory */
2025 if (flags & MEDIA_LNK_FL_ENABLED) {
2026 if (prev->input == PREVIEW_INPUT_CCDC)
2027 return -EBUSY;
2028 prev->input = PREVIEW_INPUT_MEMORY;
2029 } else {
2030 if (prev->input == PREVIEW_INPUT_MEMORY)
2031 prev->input = PREVIEW_INPUT_NONE;
2032 }
2033 break;
2034
2035 case PREV_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2036 /* read from ccdc */
2037 if (flags & MEDIA_LNK_FL_ENABLED) {
2038 if (prev->input == PREVIEW_INPUT_MEMORY)
2039 return -EBUSY;
2040 prev->input = PREVIEW_INPUT_CCDC;
2041 } else {
2042 if (prev->input == PREVIEW_INPUT_CCDC)
2043 prev->input = PREVIEW_INPUT_NONE;
2044 }
2045 break;
2046
2047 /*
2048 * The ISP core doesn't support pipelines with multiple video outputs.
2049 * Revisit this when it will be implemented, and return -EBUSY for now.
2050 */
2051
2052 case PREV_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
2053 /* write to memory */
2054 if (flags & MEDIA_LNK_FL_ENABLED) {
2055 if (prev->output & ~PREVIEW_OUTPUT_MEMORY)
2056 return -EBUSY;
2057 prev->output |= PREVIEW_OUTPUT_MEMORY;
2058 } else {
2059 prev->output &= ~PREVIEW_OUTPUT_MEMORY;
2060 }
2061 break;
2062
2063 case PREV_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
2064 /* write to resizer */
2065 if (flags & MEDIA_LNK_FL_ENABLED) {
2066 if (prev->output & ~PREVIEW_OUTPUT_RESIZER)
2067 return -EBUSY;
2068 prev->output |= PREVIEW_OUTPUT_RESIZER;
2069 } else {
2070 prev->output &= ~PREVIEW_OUTPUT_RESIZER;
2071 }
2072 break;
2073
2074 default:
2075 return -EINVAL;
2076 }
2077
2078 return 0;
2079 }
2080
2081 /* media operations */
2082 static const struct media_entity_operations preview_media_ops = {
2083 .link_setup = preview_link_setup,
2084 };
2085
2086 void omap3isp_preview_unregister_entities(struct isp_prev_device *prev)
2087 {
2088 v4l2_device_unregister_subdev(&prev->subdev);
2089 omap3isp_video_unregister(&prev->video_in);
2090 omap3isp_video_unregister(&prev->video_out);
2091 }
2092
2093 int omap3isp_preview_register_entities(struct isp_prev_device *prev,
2094 struct v4l2_device *vdev)
2095 {
2096 int ret;
2097
2098 /* Register the subdev and video nodes. */
2099 ret = v4l2_device_register_subdev(vdev, &prev->subdev);
2100 if (ret < 0)
2101 goto error;
2102
2103 ret = omap3isp_video_register(&prev->video_in, vdev);
2104 if (ret < 0)
2105 goto error;
2106
2107 ret = omap3isp_video_register(&prev->video_out, vdev);
2108 if (ret < 0)
2109 goto error;
2110
2111 return 0;
2112
2113 error:
2114 omap3isp_preview_unregister_entities(prev);
2115 return ret;
2116 }
2117
2118 /* -----------------------------------------------------------------------------
2119 * ISP previewer initialisation and cleanup
2120 */
2121
2122 /*
2123 * preview_init_entities - Initialize subdev and media entity.
2124 * @prev : Pointer to preview structure
2125 * return -ENOMEM or zero on success
2126 */
2127 static int preview_init_entities(struct isp_prev_device *prev)
2128 {
2129 struct v4l2_subdev *sd = &prev->subdev;
2130 struct media_pad *pads = prev->pads;
2131 struct media_entity *me = &sd->entity;
2132 int ret;
2133
2134 prev->input = PREVIEW_INPUT_NONE;
2135
2136 v4l2_subdev_init(sd, &preview_v4l2_ops);
2137 sd->internal_ops = &preview_v4l2_internal_ops;
2138 strlcpy(sd->name, "OMAP3 ISP preview", sizeof(sd->name));
2139 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2140 v4l2_set_subdevdata(sd, prev);
2141 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2142
2143 v4l2_ctrl_handler_init(&prev->ctrls, 2);
2144 v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_BRIGHTNESS,
2145 ISPPRV_BRIGHT_LOW, ISPPRV_BRIGHT_HIGH,
2146 ISPPRV_BRIGHT_STEP, ISPPRV_BRIGHT_DEF);
2147 v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_CONTRAST,
2148 ISPPRV_CONTRAST_LOW, ISPPRV_CONTRAST_HIGH,
2149 ISPPRV_CONTRAST_STEP, ISPPRV_CONTRAST_DEF);
2150 v4l2_ctrl_handler_setup(&prev->ctrls);
2151 sd->ctrl_handler = &prev->ctrls;
2152
2153 pads[PREV_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
2154 pads[PREV_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
2155
2156 me->ops = &preview_media_ops;
2157 ret = media_entity_init(me, PREV_PADS_NUM, pads, 0);
2158 if (ret < 0)
2159 return ret;
2160
2161 preview_init_formats(sd, NULL);
2162
2163 /* According to the OMAP34xx TRM, video buffers need to be aligned on a
2164 * 32 bytes boundary. However, an undocumented hardware bug requires a
2165 * 64 bytes boundary at the preview engine input.
2166 */
2167 prev->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2168 prev->video_in.ops = &preview_video_ops;
2169 prev->video_in.isp = to_isp_device(prev);
2170 prev->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3;
2171 prev->video_in.bpl_alignment = 64;
2172 prev->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2173 prev->video_out.ops = &preview_video_ops;
2174 prev->video_out.isp = to_isp_device(prev);
2175 prev->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3;
2176 prev->video_out.bpl_alignment = 32;
2177
2178 ret = omap3isp_video_init(&prev->video_in, "preview");
2179 if (ret < 0)
2180 goto error_video_in;
2181
2182 ret = omap3isp_video_init(&prev->video_out, "preview");
2183 if (ret < 0)
2184 goto error_video_out;
2185
2186 /* Connect the video nodes to the previewer subdev. */
2187 ret = media_entity_create_link(&prev->video_in.video.entity, 0,
2188 &prev->subdev.entity, PREV_PAD_SINK, 0);
2189 if (ret < 0)
2190 goto error_link;
2191
2192 ret = media_entity_create_link(&prev->subdev.entity, PREV_PAD_SOURCE,
2193 &prev->video_out.video.entity, 0, 0);
2194 if (ret < 0)
2195 goto error_link;
2196
2197 return 0;
2198
2199 error_link:
2200 omap3isp_video_cleanup(&prev->video_out);
2201 error_video_out:
2202 omap3isp_video_cleanup(&prev->video_in);
2203 error_video_in:
2204 media_entity_cleanup(&prev->subdev.entity);
2205 return ret;
2206 }
2207
2208 /*
2209 * isp_preview_init - Previewer initialization.
2210 * @dev : Pointer to ISP device
2211 * return -ENOMEM or zero on success
2212 */
2213 int omap3isp_preview_init(struct isp_device *isp)
2214 {
2215 struct isp_prev_device *prev = &isp->isp_prev;
2216
2217 spin_lock_init(&prev->lock);
2218 init_waitqueue_head(&prev->wait);
2219 preview_init_params(prev);
2220
2221 return preview_init_entities(prev);
2222 }
2223
2224 void omap3isp_preview_cleanup(struct isp_device *isp)
2225 {
2226 struct isp_prev_device *prev = &isp->isp_prev;
2227
2228 v4l2_ctrl_handler_free(&prev->ctrls);
2229 omap3isp_video_cleanup(&prev->video_in);
2230 omap3isp_video_cleanup(&prev->video_out);
2231 media_entity_cleanup(&prev->subdev.entity);
2232 }