]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/media/video/ov6650.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'writeback-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / ov6650.c
1 /*
2 * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/v4l2-mediabus.h>
32
33 #include <media/soc_camera.h>
34 #include <media/v4l2-chip-ident.h>
35 #include <media/v4l2-ctrls.h>
36
37 /* Register definitions */
38 #define REG_GAIN 0x00 /* range 00 - 3F */
39 #define REG_BLUE 0x01
40 #define REG_RED 0x02
41 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
42 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
43
44 #define REG_BRT 0x06
45
46 #define REG_PIDH 0x0a
47 #define REG_PIDL 0x0b
48
49 #define REG_AECH 0x10
50 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
51 /* [7:6] Input system clock (MHz)*/
52 /* 00=8, 01=12, 10=16, 11=24 */
53 /* [5:0]: Internal Clock Pre-Scaler */
54 #define REG_COMA 0x12 /* [7] Reset */
55 #define REG_COMB 0x13
56 #define REG_COMC 0x14
57 #define REG_COMD 0x15
58 #define REG_COML 0x16
59 #define REG_HSTRT 0x17
60 #define REG_HSTOP 0x18
61 #define REG_VSTRT 0x19
62 #define REG_VSTOP 0x1a
63 #define REG_PSHFT 0x1b
64 #define REG_MIDH 0x1c
65 #define REG_MIDL 0x1d
66 #define REG_HSYNS 0x1e
67 #define REG_HSYNE 0x1f
68 #define REG_COME 0x20
69 #define REG_YOFF 0x21
70 #define REG_UOFF 0x22
71 #define REG_VOFF 0x23
72 #define REG_AEW 0x24
73 #define REG_AEB 0x25
74 #define REG_COMF 0x26
75 #define REG_COMG 0x27
76 #define REG_COMH 0x28
77 #define REG_COMI 0x29
78
79 #define REG_FRARL 0x2b
80 #define REG_COMJ 0x2c
81 #define REG_COMK 0x2d
82 #define REG_AVGY 0x2e
83 #define REG_REF0 0x2f
84 #define REG_REF1 0x30
85 #define REG_REF2 0x31
86 #define REG_FRAJH 0x32
87 #define REG_FRAJL 0x33
88 #define REG_FACT 0x34
89 #define REG_L1AEC 0x35
90 #define REG_AVGU 0x36
91 #define REG_AVGV 0x37
92
93 #define REG_SPCB 0x60
94 #define REG_SPCC 0x61
95 #define REG_GAM1 0x62
96 #define REG_GAM2 0x63
97 #define REG_GAM3 0x64
98 #define REG_SPCD 0x65
99
100 #define REG_SPCE 0x68
101 #define REG_ADCL 0x69
102
103 #define REG_RMCO 0x6c
104 #define REG_GMCO 0x6d
105 #define REG_BMCO 0x6e
106
107
108 /* Register bits, values, etc. */
109 #define OV6650_PIDH 0x66 /* high byte of product ID number */
110 #define OV6650_PIDL 0x50 /* low byte of product ID number */
111 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
112 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
113
114 #define DEF_GAIN 0x00
115 #define DEF_BLUE 0x80
116 #define DEF_RED 0x80
117
118 #define SAT_SHIFT 4
119 #define SAT_MASK (0xf << SAT_SHIFT)
120 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
121
122 #define HUE_EN BIT(5)
123 #define HUE_MASK 0x1f
124 #define DEF_HUE 0x10
125 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
126
127 #define DEF_AECH 0x4D
128
129 #define CLKRC_6MHz 0x00
130 #define CLKRC_12MHz 0x40
131 #define CLKRC_16MHz 0x80
132 #define CLKRC_24MHz 0xc0
133 #define CLKRC_DIV_MASK 0x3f
134 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
135
136 #define COMA_RESET BIT(7)
137 #define COMA_QCIF BIT(5)
138 #define COMA_RAW_RGB BIT(4)
139 #define COMA_RGB BIT(3)
140 #define COMA_BW BIT(2)
141 #define COMA_WORD_SWAP BIT(1)
142 #define COMA_BYTE_SWAP BIT(0)
143 #define DEF_COMA 0x00
144
145 #define COMB_FLIP_V BIT(7)
146 #define COMB_FLIP_H BIT(5)
147 #define COMB_BAND_FILTER BIT(4)
148 #define COMB_AWB BIT(2)
149 #define COMB_AGC BIT(1)
150 #define COMB_AEC BIT(0)
151 #define DEF_COMB 0x5f
152
153 #define COML_ONE_CHANNEL BIT(7)
154
155 #define DEF_HSTRT 0x24
156 #define DEF_HSTOP 0xd4
157 #define DEF_VSTRT 0x04
158 #define DEF_VSTOP 0x94
159
160 #define COMF_HREF_LOW BIT(4)
161
162 #define COMJ_PCLK_RISING BIT(4)
163 #define COMJ_VSYNC_HIGH BIT(0)
164
165 /* supported resolutions */
166 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
167 #define W_CIF (W_QCIF << 1)
168 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
169 #define H_CIF (H_QCIF << 1)
170
171 #define FRAME_RATE_MAX 30
172
173
174 struct ov6650_reg {
175 u8 reg;
176 u8 val;
177 };
178
179 struct ov6650 {
180 struct v4l2_subdev subdev;
181 struct v4l2_ctrl_handler hdl;
182 struct {
183 /* exposure/autoexposure cluster */
184 struct v4l2_ctrl *autoexposure;
185 struct v4l2_ctrl *exposure;
186 };
187 struct {
188 /* gain/autogain cluster */
189 struct v4l2_ctrl *autogain;
190 struct v4l2_ctrl *gain;
191 };
192 struct {
193 /* blue/red/autowhitebalance cluster */
194 struct v4l2_ctrl *autowb;
195 struct v4l2_ctrl *blue;
196 struct v4l2_ctrl *red;
197 };
198 bool half_scale; /* scale down output by 2 */
199 struct v4l2_rect rect; /* sensor cropping window */
200 unsigned long pclk_limit; /* from host */
201 unsigned long pclk_max; /* from resolution and format */
202 struct v4l2_fract tpf; /* as requested with s_parm */
203 enum v4l2_mbus_pixelcode code;
204 enum v4l2_colorspace colorspace;
205 };
206
207
208 static enum v4l2_mbus_pixelcode ov6650_codes[] = {
209 V4L2_MBUS_FMT_YUYV8_2X8,
210 V4L2_MBUS_FMT_UYVY8_2X8,
211 V4L2_MBUS_FMT_YVYU8_2X8,
212 V4L2_MBUS_FMT_VYUY8_2X8,
213 V4L2_MBUS_FMT_SBGGR8_1X8,
214 V4L2_MBUS_FMT_Y8_1X8,
215 };
216
217 /* read a register */
218 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
219 {
220 int ret;
221 u8 data = reg;
222 struct i2c_msg msg = {
223 .addr = client->addr,
224 .flags = 0,
225 .len = 1,
226 .buf = &data,
227 };
228
229 ret = i2c_transfer(client->adapter, &msg, 1);
230 if (ret < 0)
231 goto err;
232
233 msg.flags = I2C_M_RD;
234 ret = i2c_transfer(client->adapter, &msg, 1);
235 if (ret < 0)
236 goto err;
237
238 *val = data;
239 return 0;
240
241 err:
242 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
243 return ret;
244 }
245
246 /* write a register */
247 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
248 {
249 int ret;
250 unsigned char data[2] = { reg, val };
251 struct i2c_msg msg = {
252 .addr = client->addr,
253 .flags = 0,
254 .len = 2,
255 .buf = data,
256 };
257
258 ret = i2c_transfer(client->adapter, &msg, 1);
259 udelay(100);
260
261 if (ret < 0) {
262 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
263 return ret;
264 }
265 return 0;
266 }
267
268
269 /* Read a register, alter its bits, write it back */
270 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
271 {
272 u8 val;
273 int ret;
274
275 ret = ov6650_reg_read(client, reg, &val);
276 if (ret) {
277 dev_err(&client->dev,
278 "[Read]-Modify-Write of register 0x%02x failed!\n",
279 reg);
280 return ret;
281 }
282
283 val &= ~mask;
284 val |= set;
285
286 ret = ov6650_reg_write(client, reg, val);
287 if (ret)
288 dev_err(&client->dev,
289 "Read-Modify-[Write] of register 0x%02x failed!\n",
290 reg);
291
292 return ret;
293 }
294
295 static struct ov6650 *to_ov6650(const struct i2c_client *client)
296 {
297 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
298 }
299
300 /* Start/Stop streaming from the device */
301 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
302 {
303 return 0;
304 }
305
306 /* Get status of additional camera capabilities */
307 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
308 {
309 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
310 struct v4l2_subdev *sd = &priv->subdev;
311 struct i2c_client *client = v4l2_get_subdevdata(sd);
312 uint8_t reg, reg2;
313 int ret;
314
315 switch (ctrl->id) {
316 case V4L2_CID_AUTOGAIN:
317 ret = ov6650_reg_read(client, REG_GAIN, &reg);
318 if (!ret)
319 priv->gain->val = reg;
320 return ret;
321 case V4L2_CID_AUTO_WHITE_BALANCE:
322 ret = ov6650_reg_read(client, REG_BLUE, &reg);
323 if (!ret)
324 ret = ov6650_reg_read(client, REG_RED, &reg2);
325 if (!ret) {
326 priv->blue->val = reg;
327 priv->red->val = reg2;
328 }
329 return ret;
330 case V4L2_CID_EXPOSURE_AUTO:
331 ret = ov6650_reg_read(client, REG_AECH, &reg);
332 if (!ret)
333 priv->exposure->val = reg;
334 return ret;
335 }
336 return -EINVAL;
337 }
338
339 /* Set status of additional camera capabilities */
340 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
341 {
342 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
343 struct v4l2_subdev *sd = &priv->subdev;
344 struct i2c_client *client = v4l2_get_subdevdata(sd);
345 int ret;
346
347 switch (ctrl->id) {
348 case V4L2_CID_AUTOGAIN:
349 ret = ov6650_reg_rmw(client, REG_COMB,
350 ctrl->val ? COMB_AGC : 0, COMB_AGC);
351 if (!ret && !ctrl->val)
352 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
353 return ret;
354 case V4L2_CID_AUTO_WHITE_BALANCE:
355 ret = ov6650_reg_rmw(client, REG_COMB,
356 ctrl->val ? COMB_AWB : 0, COMB_AWB);
357 if (!ret && !ctrl->val) {
358 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
359 if (!ret)
360 ret = ov6650_reg_write(client, REG_RED,
361 priv->red->val);
362 }
363 return ret;
364 case V4L2_CID_SATURATION:
365 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
366 SAT_MASK);
367 case V4L2_CID_HUE:
368 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
369 HUE_MASK);
370 case V4L2_CID_BRIGHTNESS:
371 return ov6650_reg_write(client, REG_BRT, ctrl->val);
372 case V4L2_CID_EXPOSURE_AUTO:
373 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
374 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
375 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
376 ret = ov6650_reg_write(client, REG_AECH,
377 priv->exposure->val);
378 return ret;
379 case V4L2_CID_GAMMA:
380 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
381 case V4L2_CID_VFLIP:
382 return ov6650_reg_rmw(client, REG_COMB,
383 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
384 case V4L2_CID_HFLIP:
385 return ov6650_reg_rmw(client, REG_COMB,
386 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
387 }
388
389 return -EINVAL;
390 }
391
392 /* Get chip identification */
393 static int ov6650_g_chip_ident(struct v4l2_subdev *sd,
394 struct v4l2_dbg_chip_ident *id)
395 {
396 id->ident = V4L2_IDENT_OV6650;
397 id->revision = 0;
398
399 return 0;
400 }
401
402 #ifdef CONFIG_VIDEO_ADV_DEBUG
403 static int ov6650_get_register(struct v4l2_subdev *sd,
404 struct v4l2_dbg_register *reg)
405 {
406 struct i2c_client *client = v4l2_get_subdevdata(sd);
407 int ret;
408 u8 val;
409
410 if (reg->reg & ~0xff)
411 return -EINVAL;
412
413 reg->size = 1;
414
415 ret = ov6650_reg_read(client, reg->reg, &val);
416 if (!ret)
417 reg->val = (__u64)val;
418
419 return ret;
420 }
421
422 static int ov6650_set_register(struct v4l2_subdev *sd,
423 struct v4l2_dbg_register *reg)
424 {
425 struct i2c_client *client = v4l2_get_subdevdata(sd);
426
427 if (reg->reg & ~0xff || reg->val & ~0xff)
428 return -EINVAL;
429
430 return ov6650_reg_write(client, reg->reg, reg->val);
431 }
432 #endif
433
434 static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
435 {
436 struct i2c_client *client = v4l2_get_subdevdata(sd);
437 struct ov6650 *priv = to_ov6650(client);
438
439 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
440 a->c = priv->rect;
441
442 return 0;
443 }
444
445 static int ov6650_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
446 {
447 struct i2c_client *client = v4l2_get_subdevdata(sd);
448 struct ov6650 *priv = to_ov6650(client);
449 struct v4l2_rect *rect = &a->c;
450 int ret;
451
452 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
453 return -EINVAL;
454
455 rect->left = ALIGN(rect->left, 2);
456 rect->width = ALIGN(rect->width, 2);
457 rect->top = ALIGN(rect->top, 2);
458 rect->height = ALIGN(rect->height, 2);
459 soc_camera_limit_side(&rect->left, &rect->width,
460 DEF_HSTRT << 1, 2, W_CIF);
461 soc_camera_limit_side(&rect->top, &rect->height,
462 DEF_VSTRT << 1, 2, H_CIF);
463
464 ret = ov6650_reg_write(client, REG_HSTRT, rect->left >> 1);
465 if (!ret) {
466 priv->rect.left = rect->left;
467 ret = ov6650_reg_write(client, REG_HSTOP,
468 (rect->left + rect->width) >> 1);
469 }
470 if (!ret) {
471 priv->rect.width = rect->width;
472 ret = ov6650_reg_write(client, REG_VSTRT, rect->top >> 1);
473 }
474 if (!ret) {
475 priv->rect.top = rect->top;
476 ret = ov6650_reg_write(client, REG_VSTOP,
477 (rect->top + rect->height) >> 1);
478 }
479 if (!ret)
480 priv->rect.height = rect->height;
481
482 return ret;
483 }
484
485 static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
486 {
487 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
488 return -EINVAL;
489
490 a->bounds.left = DEF_HSTRT << 1;
491 a->bounds.top = DEF_VSTRT << 1;
492 a->bounds.width = W_CIF;
493 a->bounds.height = H_CIF;
494 a->defrect = a->bounds;
495 a->pixelaspect.numerator = 1;
496 a->pixelaspect.denominator = 1;
497
498 return 0;
499 }
500
501 static int ov6650_g_fmt(struct v4l2_subdev *sd,
502 struct v4l2_mbus_framefmt *mf)
503 {
504 struct i2c_client *client = v4l2_get_subdevdata(sd);
505 struct ov6650 *priv = to_ov6650(client);
506
507 mf->width = priv->rect.width >> priv->half_scale;
508 mf->height = priv->rect.height >> priv->half_scale;
509 mf->code = priv->code;
510 mf->colorspace = priv->colorspace;
511 mf->field = V4L2_FIELD_NONE;
512
513 return 0;
514 }
515
516 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
517 {
518 return width > rect->width >> 1 || height > rect->height >> 1;
519 }
520
521 static u8 to_clkrc(struct v4l2_fract *timeperframe,
522 unsigned long pclk_limit, unsigned long pclk_max)
523 {
524 unsigned long pclk;
525
526 if (timeperframe->numerator && timeperframe->denominator)
527 pclk = pclk_max * timeperframe->denominator /
528 (FRAME_RATE_MAX * timeperframe->numerator);
529 else
530 pclk = pclk_max;
531
532 if (pclk_limit && pclk_limit < pclk)
533 pclk = pclk_limit;
534
535 return (pclk_max - 1) / pclk;
536 }
537
538 /* set the format we will capture in */
539 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
540 {
541 struct i2c_client *client = v4l2_get_subdevdata(sd);
542 struct soc_camera_device *icd = (struct soc_camera_device *)sd->grp_id;
543 struct soc_camera_sense *sense = icd->sense;
544 struct ov6650 *priv = to_ov6650(client);
545 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
546 struct v4l2_crop a = {
547 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
548 .c = {
549 .left = priv->rect.left + (priv->rect.width >> 1) -
550 (mf->width >> (1 - half_scale)),
551 .top = priv->rect.top + (priv->rect.height >> 1) -
552 (mf->height >> (1 - half_scale)),
553 .width = mf->width << half_scale,
554 .height = mf->height << half_scale,
555 },
556 };
557 enum v4l2_mbus_pixelcode code = mf->code;
558 unsigned long mclk, pclk;
559 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
560 int ret;
561
562 /* select color matrix configuration for given color encoding */
563 switch (code) {
564 case V4L2_MBUS_FMT_Y8_1X8:
565 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
566 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
567 coma_set |= COMA_BW;
568 break;
569 case V4L2_MBUS_FMT_YUYV8_2X8:
570 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
571 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
572 coma_set |= COMA_WORD_SWAP;
573 break;
574 case V4L2_MBUS_FMT_YVYU8_2X8:
575 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
576 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
577 COMA_BYTE_SWAP;
578 break;
579 case V4L2_MBUS_FMT_UYVY8_2X8:
580 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
581 if (half_scale) {
582 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
583 coma_set |= COMA_BYTE_SWAP;
584 } else {
585 coma_mask |= COMA_RGB | COMA_BW;
586 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
587 }
588 break;
589 case V4L2_MBUS_FMT_VYUY8_2X8:
590 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
591 if (half_scale) {
592 coma_mask |= COMA_RGB | COMA_BW;
593 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
594 } else {
595 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
596 coma_set |= COMA_BYTE_SWAP;
597 }
598 break;
599 case V4L2_MBUS_FMT_SBGGR8_1X8:
600 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
601 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
602 coma_set |= COMA_RAW_RGB | COMA_RGB;
603 break;
604 default:
605 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
606 return -EINVAL;
607 }
608 priv->code = code;
609
610 if (code == V4L2_MBUS_FMT_Y8_1X8 ||
611 code == V4L2_MBUS_FMT_SBGGR8_1X8) {
612 coml_mask = COML_ONE_CHANNEL;
613 coml_set = 0;
614 priv->pclk_max = 4000000;
615 } else {
616 coml_mask = 0;
617 coml_set = COML_ONE_CHANNEL;
618 priv->pclk_max = 8000000;
619 }
620
621 if (code == V4L2_MBUS_FMT_SBGGR8_1X8)
622 priv->colorspace = V4L2_COLORSPACE_SRGB;
623 else if (code != 0)
624 priv->colorspace = V4L2_COLORSPACE_JPEG;
625
626 if (half_scale) {
627 dev_dbg(&client->dev, "max resolution: QCIF\n");
628 coma_set |= COMA_QCIF;
629 priv->pclk_max /= 2;
630 } else {
631 dev_dbg(&client->dev, "max resolution: CIF\n");
632 coma_mask |= COMA_QCIF;
633 }
634 priv->half_scale = half_scale;
635
636 if (sense) {
637 if (sense->master_clock == 8000000) {
638 dev_dbg(&client->dev, "8MHz input clock\n");
639 clkrc = CLKRC_6MHz;
640 } else if (sense->master_clock == 12000000) {
641 dev_dbg(&client->dev, "12MHz input clock\n");
642 clkrc = CLKRC_12MHz;
643 } else if (sense->master_clock == 16000000) {
644 dev_dbg(&client->dev, "16MHz input clock\n");
645 clkrc = CLKRC_16MHz;
646 } else if (sense->master_clock == 24000000) {
647 dev_dbg(&client->dev, "24MHz input clock\n");
648 clkrc = CLKRC_24MHz;
649 } else {
650 dev_err(&client->dev,
651 "unspported input clock, check platform data\n");
652 return -EINVAL;
653 }
654 mclk = sense->master_clock;
655 priv->pclk_limit = sense->pixel_clock_max;
656 } else {
657 clkrc = CLKRC_24MHz;
658 mclk = 24000000;
659 priv->pclk_limit = 0;
660 dev_dbg(&client->dev, "using default 24MHz input clock\n");
661 }
662
663 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
664
665 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
666 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
667 mclk / pclk, 10 * mclk % pclk / pclk);
668
669 ret = ov6650_s_crop(sd, &a);
670 if (!ret)
671 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
672 if (!ret)
673 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
674 if (!ret)
675 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
676
677 if (!ret) {
678 mf->colorspace = priv->colorspace;
679 mf->width = priv->rect.width >> half_scale;
680 mf->height = priv->rect.height >> half_scale;
681 }
682
683 return ret;
684 }
685
686 static int ov6650_try_fmt(struct v4l2_subdev *sd,
687 struct v4l2_mbus_framefmt *mf)
688 {
689 struct i2c_client *client = v4l2_get_subdevdata(sd);
690 struct ov6650 *priv = to_ov6650(client);
691
692 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
693 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
694 &mf->height, 2, H_CIF, 1, 0);
695
696 mf->field = V4L2_FIELD_NONE;
697
698 switch (mf->code) {
699 case V4L2_MBUS_FMT_Y10_1X10:
700 mf->code = V4L2_MBUS_FMT_Y8_1X8;
701 case V4L2_MBUS_FMT_Y8_1X8:
702 case V4L2_MBUS_FMT_YVYU8_2X8:
703 case V4L2_MBUS_FMT_YUYV8_2X8:
704 case V4L2_MBUS_FMT_VYUY8_2X8:
705 case V4L2_MBUS_FMT_UYVY8_2X8:
706 mf->colorspace = V4L2_COLORSPACE_JPEG;
707 break;
708 default:
709 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
710 case V4L2_MBUS_FMT_SBGGR8_1X8:
711 mf->colorspace = V4L2_COLORSPACE_SRGB;
712 break;
713 }
714
715 return 0;
716 }
717
718 static int ov6650_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
719 enum v4l2_mbus_pixelcode *code)
720 {
721 if (index >= ARRAY_SIZE(ov6650_codes))
722 return -EINVAL;
723
724 *code = ov6650_codes[index];
725 return 0;
726 }
727
728 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
729 {
730 struct i2c_client *client = v4l2_get_subdevdata(sd);
731 struct ov6650 *priv = to_ov6650(client);
732 struct v4l2_captureparm *cp = &parms->parm.capture;
733
734 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
735 return -EINVAL;
736
737 memset(cp, 0, sizeof(*cp));
738 cp->capability = V4L2_CAP_TIMEPERFRAME;
739 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
740 priv->pclk_limit, priv->pclk_max));
741 cp->timeperframe.denominator = FRAME_RATE_MAX;
742
743 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
744 cp->timeperframe.numerator, cp->timeperframe.denominator);
745
746 return 0;
747 }
748
749 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
750 {
751 struct i2c_client *client = v4l2_get_subdevdata(sd);
752 struct ov6650 *priv = to_ov6650(client);
753 struct v4l2_captureparm *cp = &parms->parm.capture;
754 struct v4l2_fract *tpf = &cp->timeperframe;
755 int div, ret;
756 u8 clkrc;
757
758 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
759 return -EINVAL;
760
761 if (cp->extendedmode != 0)
762 return -EINVAL;
763
764 if (tpf->numerator == 0 || tpf->denominator == 0)
765 div = 1; /* Reset to full rate */
766 else
767 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
768
769 if (div == 0)
770 div = 1;
771 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
772 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
773
774 /*
775 * Keep result to be used as tpf limit
776 * for subseqent clock divider calculations
777 */
778 priv->tpf.numerator = div;
779 priv->tpf.denominator = FRAME_RATE_MAX;
780
781 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
782
783 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
784 if (!ret) {
785 tpf->numerator = GET_CLKRC_DIV(clkrc);
786 tpf->denominator = FRAME_RATE_MAX;
787 }
788
789 return ret;
790 }
791
792 /* Soft reset the camera. This has nothing to do with the RESET pin! */
793 static int ov6650_reset(struct i2c_client *client)
794 {
795 int ret;
796
797 dev_dbg(&client->dev, "reset\n");
798
799 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
800 if (ret)
801 dev_err(&client->dev,
802 "An error occurred while entering soft reset!\n");
803
804 return ret;
805 }
806
807 /* program default register values */
808 static int ov6650_prog_dflt(struct i2c_client *client)
809 {
810 int ret;
811
812 dev_dbg(&client->dev, "initializing\n");
813
814 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
815 if (!ret)
816 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
817
818 return ret;
819 }
820
821 static int ov6650_video_probe(struct i2c_client *client)
822 {
823 u8 pidh, pidl, midh, midl;
824 int ret = 0;
825
826 /*
827 * check and show product ID and manufacturer ID
828 */
829 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
830 if (!ret)
831 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
832 if (!ret)
833 ret = ov6650_reg_read(client, REG_MIDH, &midh);
834 if (!ret)
835 ret = ov6650_reg_read(client, REG_MIDL, &midl);
836
837 if (ret)
838 return ret;
839
840 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
841 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
842 pidh, pidl);
843 return -ENODEV;
844 }
845
846 dev_info(&client->dev,
847 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
848 pidh, pidl, midh, midl);
849
850 ret = ov6650_reset(client);
851 if (!ret)
852 ret = ov6650_prog_dflt(client);
853
854 return ret;
855 }
856
857 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
858 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
859 .s_ctrl = ov6550_s_ctrl,
860 };
861
862 static struct v4l2_subdev_core_ops ov6650_core_ops = {
863 .g_chip_ident = ov6650_g_chip_ident,
864 #ifdef CONFIG_VIDEO_ADV_DEBUG
865 .g_register = ov6650_get_register,
866 .s_register = ov6650_set_register,
867 #endif
868 };
869
870 /* Request bus settings on camera side */
871 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
872 struct v4l2_mbus_config *cfg)
873 {
874 struct i2c_client *client = v4l2_get_subdevdata(sd);
875 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
876
877 cfg->flags = V4L2_MBUS_MASTER |
878 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
879 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
880 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
881 V4L2_MBUS_DATA_ACTIVE_HIGH;
882 cfg->type = V4L2_MBUS_PARALLEL;
883 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
884
885 return 0;
886 }
887
888 /* Alter bus settings on camera side */
889 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
890 const struct v4l2_mbus_config *cfg)
891 {
892 struct i2c_client *client = v4l2_get_subdevdata(sd);
893 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
894 unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
895 int ret;
896
897 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
898 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
899 else
900 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
901 if (ret)
902 return ret;
903
904 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
905 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
906 else
907 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
908 if (ret)
909 return ret;
910
911 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
912 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
913 else
914 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
915
916 return ret;
917 }
918
919 static struct v4l2_subdev_video_ops ov6650_video_ops = {
920 .s_stream = ov6650_s_stream,
921 .g_mbus_fmt = ov6650_g_fmt,
922 .s_mbus_fmt = ov6650_s_fmt,
923 .try_mbus_fmt = ov6650_try_fmt,
924 .enum_mbus_fmt = ov6650_enum_fmt,
925 .cropcap = ov6650_cropcap,
926 .g_crop = ov6650_g_crop,
927 .s_crop = ov6650_s_crop,
928 .g_parm = ov6650_g_parm,
929 .s_parm = ov6650_s_parm,
930 .g_mbus_config = ov6650_g_mbus_config,
931 .s_mbus_config = ov6650_s_mbus_config,
932 };
933
934 static struct v4l2_subdev_ops ov6650_subdev_ops = {
935 .core = &ov6650_core_ops,
936 .video = &ov6650_video_ops,
937 };
938
939 /*
940 * i2c_driver function
941 */
942 static int ov6650_probe(struct i2c_client *client,
943 const struct i2c_device_id *did)
944 {
945 struct ov6650 *priv;
946 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
947 int ret;
948
949 if (!icl) {
950 dev_err(&client->dev, "Missing platform_data for driver\n");
951 return -EINVAL;
952 }
953
954 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
955 if (!priv) {
956 dev_err(&client->dev,
957 "Failed to allocate memory for private data!\n");
958 return -ENOMEM;
959 }
960
961 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
962 v4l2_ctrl_handler_init(&priv->hdl, 13);
963 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
964 V4L2_CID_VFLIP, 0, 1, 1, 0);
965 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
966 V4L2_CID_HFLIP, 0, 1, 1, 0);
967 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
968 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
969 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
970 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
971 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
972 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
973 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
974 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
975 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
976 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
977 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
978 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
979 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
980 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
981 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
982 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
983 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
984 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
985 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
986 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
987 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
988 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
989 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
990
991 priv->subdev.ctrl_handler = &priv->hdl;
992 if (priv->hdl.error) {
993 int err = priv->hdl.error;
994
995 kfree(priv);
996 return err;
997 }
998 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
999 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1000 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1001 V4L2_EXPOSURE_MANUAL, true);
1002
1003 priv->rect.left = DEF_HSTRT << 1;
1004 priv->rect.top = DEF_VSTRT << 1;
1005 priv->rect.width = W_CIF;
1006 priv->rect.height = H_CIF;
1007 priv->half_scale = false;
1008 priv->code = V4L2_MBUS_FMT_YUYV8_2X8;
1009 priv->colorspace = V4L2_COLORSPACE_JPEG;
1010
1011 ret = ov6650_video_probe(client);
1012 if (!ret)
1013 ret = v4l2_ctrl_handler_setup(&priv->hdl);
1014
1015 if (ret) {
1016 v4l2_ctrl_handler_free(&priv->hdl);
1017 kfree(priv);
1018 }
1019
1020 return ret;
1021 }
1022
1023 static int ov6650_remove(struct i2c_client *client)
1024 {
1025 struct ov6650 *priv = to_ov6650(client);
1026
1027 v4l2_device_unregister_subdev(&priv->subdev);
1028 v4l2_ctrl_handler_free(&priv->hdl);
1029 kfree(priv);
1030 return 0;
1031 }
1032
1033 static const struct i2c_device_id ov6650_id[] = {
1034 { "ov6650", 0 },
1035 { }
1036 };
1037 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1038
1039 static struct i2c_driver ov6650_i2c_driver = {
1040 .driver = {
1041 .name = "ov6650",
1042 },
1043 .probe = ov6650_probe,
1044 .remove = ov6650_remove,
1045 .id_table = ov6650_id,
1046 };
1047
1048 static int __init ov6650_module_init(void)
1049 {
1050 return i2c_add_driver(&ov6650_i2c_driver);
1051 }
1052
1053 static void __exit ov6650_module_exit(void)
1054 {
1055 i2c_del_driver(&ov6650_i2c_driver);
1056 }
1057
1058 module_init(ov6650_module_init);
1059 module_exit(ov6650_module_exit);
1060
1061 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1062 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1063 MODULE_LICENSE("GPL v2");
Ubuntu Artful kernel mirror