2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/pxa-regs.h>
39 #include <mach/camera.h>
41 #include "pxa_camera.h"
43 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
44 #define PXA_CAM_DRV_NAME "pxa27x-camera"
46 /* Camera Interface */
59 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
60 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
61 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
62 #define CICR0_ENB (1 << 28) /* Camera interface enable */
63 #define CICR0_DIS (1 << 27) /* Camera interface disable */
64 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
65 #define CICR0_TOM (1 << 9) /* Time-out mask */
66 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
67 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
68 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
69 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
70 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
71 #define CICR0_CDM (1 << 3) /* Disable-done mask */
72 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
73 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
74 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
76 #define CICR1_TBIT (1 << 31) /* Transparency bit */
77 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
78 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
79 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
80 #define CICR1_RGB_F (1 << 11) /* RGB format */
81 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
82 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
83 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
84 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
85 #define CICR1_DW (0x7 << 0) /* Data width mask */
87 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
89 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
91 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
92 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
94 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
97 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
99 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
101 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
102 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
104 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
106 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
107 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
108 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
109 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
110 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
111 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
112 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
113 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
115 #define CISR_FTO (1 << 15) /* FIFO time-out */
116 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
117 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
118 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
119 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
120 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
121 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
122 #define CISR_EOL (1 << 8) /* End of line */
123 #define CISR_PAR_ERR (1 << 7) /* Parity error */
124 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
125 #define CISR_CDD (1 << 5) /* Camera interface disable done */
126 #define CISR_SOF (1 << 4) /* Start of frame */
127 #define CISR_EOF (1 << 3) /* End of frame */
128 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
129 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
130 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
132 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
133 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
134 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
135 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
136 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
137 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
138 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
139 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
141 #define CICR0_SIM_MP (0 << 24)
142 #define CICR0_SIM_SP (1 << 24)
143 #define CICR0_SIM_MS (2 << 24)
144 #define CICR0_SIM_EP (3 << 24)
145 #define CICR0_SIM_ES (4 << 24)
147 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
148 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
149 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
150 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
151 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
153 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
154 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
155 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
156 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
157 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
159 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
160 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
161 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
162 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
164 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
165 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
166 CICR0_EOFM | CICR0_FOM)
171 enum pxa_camera_active_dma
{
177 /* descriptor needed for the PXA DMA engine */
180 struct pxa_dma_desc
*sg_cpu
;
185 /* buffer for one video frame */
187 /* common v4l buffer stuff -- must be first */
188 struct videobuf_buffer vb
;
190 const struct soc_camera_data_format
*fmt
;
192 /* our descriptor lists for Y, U and V channels */
193 struct pxa_cam_dma dmas
[3];
197 enum pxa_camera_active_dma active_dma
;
200 struct pxa_camera_dev
{
202 /* PXA27x is only supposed to handle one camera on its Quick Capture
203 * interface. If anyone ever builds hardware to enable more than
204 * one camera, they will have to modify this driver too */
205 struct soc_camera_device
*icd
;
212 unsigned int dma_chans
[3];
214 struct pxacamera_platform_data
*pdata
;
215 struct resource
*res
;
216 unsigned long platform_flags
;
221 struct list_head capture
;
225 struct pxa_buffer
*active
;
226 struct pxa_dma_desc
*sg_tail
[3];
231 static const char *pxa_cam_driver_description
= "PXA_Camera";
233 static unsigned int vid_limit
= 16; /* Video memory limit, in Mb */
236 * Videobuf operations
238 static int pxa_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
241 struct soc_camera_device
*icd
= vq
->priv_data
;
242 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
243 struct pxa_camera_dev
*pcdev
= ici
->priv
;
245 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
247 /* planar capture requires Y, U and V buffers to be page aligned */
248 if (pcdev
->channels
== 3) {
249 *size
= PAGE_ALIGN(icd
->width
* icd
->height
); /* Y pages */
250 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* U pages */
251 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* V pages */
253 *size
= icd
->width
* icd
->height
*
254 ((icd
->current_fmt
->depth
+ 7) >> 3);
259 while (*size
* *count
> vid_limit
* 1024 * 1024)
265 static void free_buffer(struct videobuf_queue
*vq
, struct pxa_buffer
*buf
)
267 struct soc_camera_device
*icd
= vq
->priv_data
;
268 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
269 struct pxa_camera_dev
*pcdev
= ici
->priv
;
270 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
273 BUG_ON(in_interrupt());
275 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
276 &buf
->vb
, buf
->vb
.baddr
, buf
->vb
.bsize
);
278 /* This waits until this buffer is out of danger, i.e., until it is no
279 * longer in STATE_QUEUED or STATE_ACTIVE */
280 videobuf_waiton(&buf
->vb
, 0, 0);
281 videobuf_dma_unmap(vq
, dma
);
282 videobuf_dma_free(dma
);
284 for (i
= 0; i
< ARRAY_SIZE(buf
->dmas
); i
++) {
285 if (buf
->dmas
[i
].sg_cpu
)
286 dma_free_coherent(pcdev
->dev
, buf
->dmas
[i
].sg_size
,
288 buf
->dmas
[i
].sg_dma
);
289 buf
->dmas
[i
].sg_cpu
= NULL
;
292 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
295 static int pxa_init_dma_channel(struct pxa_camera_dev
*pcdev
,
296 struct pxa_buffer
*buf
,
297 struct videobuf_dmabuf
*dma
, int channel
,
298 int sglen
, int sg_start
, int cibr
,
301 struct pxa_cam_dma
*pxa_dma
= &buf
->dmas
[channel
];
305 dma_free_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
306 pxa_dma
->sg_cpu
, pxa_dma
->sg_dma
);
308 pxa_dma
->sg_size
= (sglen
+ 1) * sizeof(struct pxa_dma_desc
);
309 pxa_dma
->sg_cpu
= dma_alloc_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
310 &pxa_dma
->sg_dma
, GFP_KERNEL
);
311 if (!pxa_dma
->sg_cpu
)
314 pxa_dma
->sglen
= sglen
;
316 for (i
= 0; i
< sglen
; i
++) {
317 int sg_i
= sg_start
+ i
;
318 struct scatterlist
*sg
= dma
->sglist
;
319 unsigned int dma_len
= sg_dma_len(&sg
[sg_i
]), xfer_len
;
321 pxa_dma
->sg_cpu
[i
].dsadr
= pcdev
->res
->start
+ cibr
;
322 pxa_dma
->sg_cpu
[i
].dtadr
= sg_dma_address(&sg
[sg_i
]);
324 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
325 xfer_len
= (min(dma_len
, size
) + 7) & ~7;
327 pxa_dma
->sg_cpu
[i
].dcmd
=
328 DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_INCTRGADDR
| xfer_len
;
330 pxa_dma
->sg_cpu
[i
].ddadr
=
331 pxa_dma
->sg_dma
+ (i
+ 1) * sizeof(struct pxa_dma_desc
);
334 pxa_dma
->sg_cpu
[sglen
- 1].ddadr
= DDADR_STOP
;
335 pxa_dma
->sg_cpu
[sglen
- 1].dcmd
|= DCMD_ENDIRQEN
;
340 static int pxa_videobuf_prepare(struct videobuf_queue
*vq
,
341 struct videobuf_buffer
*vb
, enum v4l2_field field
)
343 struct soc_camera_device
*icd
= vq
->priv_data
;
344 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
345 struct pxa_camera_dev
*pcdev
= ici
->priv
;
346 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
348 int sglen_y
, sglen_yu
= 0, sglen_u
= 0, sglen_v
= 0;
349 int size_y
, size_u
= 0, size_v
= 0;
351 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
352 vb
, vb
->baddr
, vb
->bsize
);
354 /* Added list head initialization on alloc */
355 WARN_ON(!list_empty(&vb
->queue
));
358 /* This can be useful if you want to see if we actually fill
359 * the buffer with something */
360 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
363 BUG_ON(NULL
== icd
->current_fmt
);
365 /* I think, in buf_prepare you only have to protect global data,
366 * the actual buffer is yours */
369 if (buf
->fmt
!= icd
->current_fmt
||
370 vb
->width
!= icd
->width
||
371 vb
->height
!= icd
->height
||
372 vb
->field
!= field
) {
373 buf
->fmt
= icd
->current_fmt
;
374 vb
->width
= icd
->width
;
375 vb
->height
= icd
->height
;
377 vb
->state
= VIDEOBUF_NEEDS_INIT
;
380 vb
->size
= vb
->width
* vb
->height
* ((buf
->fmt
->depth
+ 7) >> 3);
381 if (0 != vb
->baddr
&& vb
->bsize
< vb
->size
) {
386 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
387 unsigned int size
= vb
->size
;
388 struct videobuf_dmabuf
*dma
= videobuf_to_dma(vb
);
390 ret
= videobuf_iolock(vq
, vb
, NULL
);
394 if (pcdev
->channels
== 3) {
395 /* FIXME the calculations should be more precise */
396 sglen_y
= dma
->sglen
/ 2;
397 sglen_u
= sglen_v
= dma
->sglen
/ 4 + 1;
398 sglen_yu
= sglen_y
+ sglen_u
;
400 size_u
= size_v
= size
/ 4;
402 sglen_y
= dma
->sglen
;
406 /* init DMA for Y channel */
407 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 0, sglen_y
,
412 "DMA initialization for Y/RGB failed\n");
416 if (pcdev
->channels
== 3) {
417 /* init DMA for U channel */
418 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 1, sglen_u
,
419 sglen_y
, 0x30, size_u
);
422 "DMA initialization for U failed\n");
426 /* init DMA for V channel */
427 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 2, sglen_v
,
428 sglen_yu
, 0x38, size_v
);
431 "DMA initialization for V failed\n");
436 vb
->state
= VIDEOBUF_PREPARED
;
440 buf
->active_dma
= DMA_Y
;
441 if (pcdev
->channels
== 3)
442 buf
->active_dma
|= DMA_U
| DMA_V
;
447 dma_free_coherent(pcdev
->dev
, buf
->dmas
[1].sg_size
,
448 buf
->dmas
[1].sg_cpu
, buf
->dmas
[1].sg_dma
);
450 dma_free_coherent(pcdev
->dev
, buf
->dmas
[0].sg_size
,
451 buf
->dmas
[0].sg_cpu
, buf
->dmas
[0].sg_dma
);
453 free_buffer(vq
, buf
);
459 static void pxa_videobuf_queue(struct videobuf_queue
*vq
,
460 struct videobuf_buffer
*vb
)
462 struct soc_camera_device
*icd
= vq
->priv_data
;
463 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
464 struct pxa_camera_dev
*pcdev
= ici
->priv
;
465 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
466 struct pxa_buffer
*active
;
470 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
471 vb
, vb
->baddr
, vb
->bsize
);
472 spin_lock_irqsave(&pcdev
->lock
, flags
);
474 list_add_tail(&vb
->queue
, &pcdev
->capture
);
476 vb
->state
= VIDEOBUF_ACTIVE
;
477 active
= pcdev
->active
;
480 unsigned long cifr
, cicr0
;
482 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
483 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
485 for (i
= 0; i
< pcdev
->channels
; i
++) {
486 DDADR(pcdev
->dma_chans
[i
]) = buf
->dmas
[i
].sg_dma
;
487 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
488 pcdev
->sg_tail
[i
] = buf
->dmas
[i
].sg_cpu
+ buf
->dmas
[i
].sglen
- 1;
493 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) | CICR0_ENB
;
494 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
496 struct pxa_cam_dma
*buf_dma
;
497 struct pxa_cam_dma
*act_dma
;
500 for (i
= 0; i
< pcdev
->channels
; i
++) {
501 buf_dma
= &buf
->dmas
[i
];
502 act_dma
= &active
->dmas
[i
];
503 nents
= buf_dma
->sglen
;
505 /* Stop DMA engine */
506 DCSR(pcdev
->dma_chans
[i
]) = 0;
508 /* Add the descriptors we just initialized to
509 the currently running chain */
510 pcdev
->sg_tail
[i
]->ddadr
= buf_dma
->sg_dma
;
511 pcdev
->sg_tail
[i
] = buf_dma
->sg_cpu
+ buf_dma
->sglen
- 1;
513 /* Setup a dummy descriptor with the DMA engines current
516 buf_dma
->sg_cpu
[nents
].dsadr
=
517 pcdev
->res
->start
+ 0x28 + i
*8; /* CIBRx */
518 buf_dma
->sg_cpu
[nents
].dtadr
=
519 DTADR(pcdev
->dma_chans
[i
]);
520 buf_dma
->sg_cpu
[nents
].dcmd
=
521 DCMD(pcdev
->dma_chans
[i
]);
523 if (DDADR(pcdev
->dma_chans
[i
]) == DDADR_STOP
) {
524 /* The DMA engine is on the last
525 descriptor, set the next descriptors
526 address to the descriptors we just
528 buf_dma
->sg_cpu
[nents
].ddadr
= buf_dma
->sg_dma
;
530 buf_dma
->sg_cpu
[nents
].ddadr
=
531 DDADR(pcdev
->dma_chans
[i
]);
534 /* The next descriptor is the dummy descriptor */
535 DDADR(pcdev
->dma_chans
[i
]) = buf_dma
->sg_dma
+ nents
*
536 sizeof(struct pxa_dma_desc
);
538 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
542 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
545 static void pxa_videobuf_release(struct videobuf_queue
*vq
,
546 struct videobuf_buffer
*vb
)
548 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
550 struct soc_camera_device
*icd
= vq
->priv_data
;
552 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
553 vb
, vb
->baddr
, vb
->bsize
);
556 case VIDEOBUF_ACTIVE
:
557 dev_dbg(&icd
->dev
, "%s (active)\n", __func__
);
559 case VIDEOBUF_QUEUED
:
560 dev_dbg(&icd
->dev
, "%s (queued)\n", __func__
);
562 case VIDEOBUF_PREPARED
:
563 dev_dbg(&icd
->dev
, "%s (prepared)\n", __func__
);
566 dev_dbg(&icd
->dev
, "%s (unknown)\n", __func__
);
571 free_buffer(vq
, buf
);
574 static void pxa_camera_wakeup(struct pxa_camera_dev
*pcdev
,
575 struct videobuf_buffer
*vb
,
576 struct pxa_buffer
*buf
)
580 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
581 list_del_init(&vb
->queue
);
582 vb
->state
= VIDEOBUF_DONE
;
583 do_gettimeofday(&vb
->ts
);
587 if (list_empty(&pcdev
->capture
)) {
588 pcdev
->active
= NULL
;
589 DCSR(pcdev
->dma_chans
[0]) = 0;
590 DCSR(pcdev
->dma_chans
[1]) = 0;
591 DCSR(pcdev
->dma_chans
[2]) = 0;
593 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) & ~CICR0_ENB
;
594 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
598 pcdev
->active
= list_entry(pcdev
->capture
.next
,
599 struct pxa_buffer
, vb
.queue
);
602 static void pxa_camera_dma_irq(int channel
, struct pxa_camera_dev
*pcdev
,
603 enum pxa_camera_active_dma act_dma
)
605 struct pxa_buffer
*buf
;
607 u32 status
, camera_status
, overrun
;
608 struct videobuf_buffer
*vb
;
609 unsigned long cifr
, cicr0
;
611 spin_lock_irqsave(&pcdev
->lock
, flags
);
613 status
= DCSR(channel
);
614 DCSR(channel
) = status
| DCSR_ENDINTR
;
616 if (status
& DCSR_BUSERR
) {
617 dev_err(pcdev
->dev
, "DMA Bus Error IRQ!\n");
621 if (!(status
& DCSR_ENDINTR
)) {
622 dev_err(pcdev
->dev
, "Unknown DMA IRQ source, "
623 "status: 0x%08x\n", status
);
627 if (!pcdev
->active
) {
628 dev_err(pcdev
->dev
, "DMA End IRQ with no active buffer!\n");
632 camera_status
= __raw_readl(pcdev
->base
+ CISR
);
633 overrun
= CISR_IFO_0
;
634 if (pcdev
->channels
== 3)
635 overrun
|= CISR_IFO_1
| CISR_IFO_2
;
636 if (camera_status
& overrun
) {
637 dev_dbg(pcdev
->dev
, "FIFO overrun! CISR: %x\n", camera_status
);
638 /* Stop the Capture Interface */
639 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) & ~CICR0_ENB
;
640 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
644 /* Reset the FIFOs */
645 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
646 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
647 /* Enable End-Of-Frame Interrupt */
648 cicr0
&= ~CICR0_EOFM
;
649 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
650 /* Restart the Capture Interface */
651 __raw_writel(cicr0
| CICR0_ENB
, pcdev
->base
+ CICR0
);
655 vb
= &pcdev
->active
->vb
;
656 buf
= container_of(vb
, struct pxa_buffer
, vb
);
657 WARN_ON(buf
->inwork
|| list_empty(&vb
->queue
));
658 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
659 vb
, vb
->baddr
, vb
->bsize
);
661 buf
->active_dma
&= ~act_dma
;
662 if (!buf
->active_dma
)
663 pxa_camera_wakeup(pcdev
, vb
, buf
);
666 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
669 static void pxa_camera_dma_irq_y(int channel
, void *data
)
671 struct pxa_camera_dev
*pcdev
= data
;
672 pxa_camera_dma_irq(channel
, pcdev
, DMA_Y
);
675 static void pxa_camera_dma_irq_u(int channel
, void *data
)
677 struct pxa_camera_dev
*pcdev
= data
;
678 pxa_camera_dma_irq(channel
, pcdev
, DMA_U
);
681 static void pxa_camera_dma_irq_v(int channel
, void *data
)
683 struct pxa_camera_dev
*pcdev
= data
;
684 pxa_camera_dma_irq(channel
, pcdev
, DMA_V
);
687 static struct videobuf_queue_ops pxa_videobuf_ops
= {
688 .buf_setup
= pxa_videobuf_setup
,
689 .buf_prepare
= pxa_videobuf_prepare
,
690 .buf_queue
= pxa_videobuf_queue
,
691 .buf_release
= pxa_videobuf_release
,
694 static void pxa_camera_init_videobuf(struct videobuf_queue
*q
,
695 struct soc_camera_device
*icd
)
697 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
698 struct pxa_camera_dev
*pcdev
= ici
->priv
;
700 /* We must pass NULL as dev pointer, then all pci_* dma operations
701 * transform to normal dma_* ones. */
702 videobuf_queue_sg_init(q
, &pxa_videobuf_ops
, NULL
, &pcdev
->lock
,
703 V4L2_BUF_TYPE_VIDEO_CAPTURE
, V4L2_FIELD_NONE
,
704 sizeof(struct pxa_buffer
), icd
);
707 static u32
mclk_get_divisor(struct pxa_camera_dev
*pcdev
)
709 unsigned long mclk
= pcdev
->mclk
;
711 unsigned long lcdclk
;
713 lcdclk
= clk_get_rate(pcdev
->clk
);
714 pcdev
->ciclk
= lcdclk
;
716 /* mclk <= ciclk / 4 (27.4.2) */
717 if (mclk
> lcdclk
/ 4) {
719 dev_warn(pcdev
->dev
, "Limiting master clock to %lu\n", mclk
);
722 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
723 div
= (lcdclk
+ 2 * mclk
- 1) / (2 * mclk
) - 1;
725 /* If we're not supplying MCLK, leave it at 0 */
726 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
727 pcdev
->mclk
= lcdclk
/ (2 * (div
+ 1));
729 dev_dbg(pcdev
->dev
, "LCD clock %luHz, target freq %luHz, "
730 "divisor %u\n", lcdclk
, mclk
, div
);
735 static void recalculate_fifo_timeout(struct pxa_camera_dev
*pcdev
,
738 /* We want a timeout > 1 pixel time, not ">=" */
739 u32 ciclk_per_pixel
= pcdev
->ciclk
/ pclk
+ 1;
741 __raw_writel(ciclk_per_pixel
, pcdev
->base
+ CITOR
);
744 static void pxa_camera_activate(struct pxa_camera_dev
*pcdev
)
746 struct pxacamera_platform_data
*pdata
= pcdev
->pdata
;
749 dev_dbg(pcdev
->dev
, "Registered platform device at %p data %p\n",
752 if (pdata
&& pdata
->init
) {
753 dev_dbg(pcdev
->dev
, "%s: Init gpios\n", __func__
);
754 pdata
->init(pcdev
->dev
);
757 /* disable all interrupts */
758 __raw_writel(0x3ff, pcdev
->base
+ CICR0
);
760 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
761 cicr4
|= CICR4_PCLK_EN
;
762 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
763 cicr4
|= CICR4_MCLK_EN
;
764 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
766 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
768 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
771 __raw_writel(pcdev
->mclk_divisor
| cicr4
, pcdev
->base
+ CICR4
);
773 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
774 /* Initialise the timeout under the assumption pclk = mclk */
775 recalculate_fifo_timeout(pcdev
, pcdev
->mclk
);
777 /* "Safe default" - 13MHz */
778 recalculate_fifo_timeout(pcdev
, 13000000);
780 clk_enable(pcdev
->clk
);
783 static void pxa_camera_deactivate(struct pxa_camera_dev
*pcdev
)
785 clk_disable(pcdev
->clk
);
788 static irqreturn_t
pxa_camera_irq(int irq
, void *data
)
790 struct pxa_camera_dev
*pcdev
= data
;
791 unsigned long status
, cicr0
;
793 status
= __raw_readl(pcdev
->base
+ CISR
);
794 dev_dbg(pcdev
->dev
, "Camera interrupt status 0x%lx\n", status
);
799 __raw_writel(status
, pcdev
->base
+ CISR
);
801 if (status
& CISR_EOF
) {
803 for (i
= 0; i
< pcdev
->channels
; i
++) {
804 DDADR(pcdev
->dma_chans
[i
]) =
805 pcdev
->active
->dmas
[i
].sg_dma
;
806 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
808 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) | CICR0_EOFM
;
809 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
816 * The following two functions absolutely depend on the fact, that
817 * there can be only one camera on PXA quick capture interface
818 * Called with .video_lock held
820 static int pxa_camera_add_device(struct soc_camera_device
*icd
)
822 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
823 struct pxa_camera_dev
*pcdev
= ici
->priv
;
831 dev_info(&icd
->dev
, "PXA Camera driver attached to camera %d\n",
834 pxa_camera_activate(pcdev
);
835 ret
= icd
->ops
->init(icd
);
844 /* Called with .video_lock held */
845 static void pxa_camera_remove_device(struct soc_camera_device
*icd
)
847 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
848 struct pxa_camera_dev
*pcdev
= ici
->priv
;
850 BUG_ON(icd
!= pcdev
->icd
);
852 dev_info(&icd
->dev
, "PXA Camera driver detached from camera %d\n",
855 /* disable capture, disable interrupts */
856 __raw_writel(0x3ff, pcdev
->base
+ CICR0
);
858 /* Stop DMA engine */
859 DCSR(pcdev
->dma_chans
[0]) = 0;
860 DCSR(pcdev
->dma_chans
[1]) = 0;
861 DCSR(pcdev
->dma_chans
[2]) = 0;
863 icd
->ops
->release(icd
);
865 pxa_camera_deactivate(pcdev
);
870 static int test_platform_param(struct pxa_camera_dev
*pcdev
,
871 unsigned char buswidth
, unsigned long *flags
)
874 * Platform specified synchronization and pixel clock polarities are
875 * only a recommendation and are only used during probing. The PXA270
876 * quick capture interface supports both.
878 *flags
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
879 SOCAM_MASTER
: SOCAM_SLAVE
) |
880 SOCAM_HSYNC_ACTIVE_HIGH
|
881 SOCAM_HSYNC_ACTIVE_LOW
|
882 SOCAM_VSYNC_ACTIVE_HIGH
|
883 SOCAM_VSYNC_ACTIVE_LOW
|
884 SOCAM_PCLK_SAMPLE_RISING
|
885 SOCAM_PCLK_SAMPLE_FALLING
;
887 /* If requested data width is supported by the platform, use it */
890 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
))
892 *flags
|= SOCAM_DATAWIDTH_10
;
895 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
))
897 *flags
|= SOCAM_DATAWIDTH_9
;
900 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
))
902 *flags
|= SOCAM_DATAWIDTH_8
;
911 static int pxa_camera_set_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
913 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
914 struct pxa_camera_dev
*pcdev
= ici
->priv
;
915 unsigned long dw
, bpp
, bus_flags
, camera_flags
, common_flags
;
916 u32 cicr0
, cicr1
, cicr2
, cicr3
, cicr4
= 0;
917 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
922 camera_flags
= icd
->ops
->query_bus_param(icd
);
924 common_flags
= soc_camera_bus_param_compatible(camera_flags
, bus_flags
);
930 /* Make choises, based on platform preferences */
931 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
932 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
933 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
934 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
936 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
939 if ((common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
) &&
940 (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)) {
941 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
942 common_flags
&= ~SOCAM_VSYNC_ACTIVE_HIGH
;
944 common_flags
&= ~SOCAM_VSYNC_ACTIVE_LOW
;
947 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
948 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
949 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
950 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
952 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
955 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
959 /* Datawidth is now guaranteed to be equal to one of the three values.
960 * We fix bit-per-pixel equal to data-width... */
961 switch (common_flags
& SOCAM_DATAWIDTH_MASK
) {
962 case SOCAM_DATAWIDTH_10
:
966 case SOCAM_DATAWIDTH_9
:
971 /* Actually it can only be 8 now,
972 * default is just to silence compiler warnings */
973 case SOCAM_DATAWIDTH_8
:
978 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
979 cicr4
|= CICR4_PCLK_EN
;
980 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
981 cicr4
|= CICR4_MCLK_EN
;
982 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
984 if (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)
986 if (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)
989 cicr0
= __raw_readl(pcdev
->base
+ CICR0
);
990 if (cicr0
& CICR0_ENB
)
991 __raw_writel(cicr0
& ~CICR0_ENB
, pcdev
->base
+ CICR0
);
993 cicr1
= CICR1_PPL_VAL(icd
->width
- 1) | bpp
| dw
;
996 case V4L2_PIX_FMT_YUV422P
:
998 cicr1
|= CICR1_YCBCR_F
;
1000 * Normally, pxa bus wants as input UYVY format. We allow all
1001 * reorderings of the YUV422 format, as no processing is done,
1002 * and the YUV stream is just passed through without any
1003 * transformation. Note that UYVY is the only format that
1004 * should be used if pxa framebuffer Overlay2 is used.
1006 case V4L2_PIX_FMT_UYVY
:
1007 case V4L2_PIX_FMT_VYUY
:
1008 case V4L2_PIX_FMT_YUYV
:
1009 case V4L2_PIX_FMT_YVYU
:
1010 cicr1
|= CICR1_COLOR_SP_VAL(2);
1012 case V4L2_PIX_FMT_RGB555
:
1013 cicr1
|= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1014 CICR1_TBIT
| CICR1_COLOR_SP_VAL(1);
1016 case V4L2_PIX_FMT_RGB565
:
1017 cicr1
|= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1022 cicr3
= CICR3_LPF_VAL(icd
->height
- 1) |
1023 CICR3_BFW_VAL(min((unsigned short)255, icd
->y_skip_top
));
1024 cicr4
|= pcdev
->mclk_divisor
;
1026 __raw_writel(cicr1
, pcdev
->base
+ CICR1
);
1027 __raw_writel(cicr2
, pcdev
->base
+ CICR2
);
1028 __raw_writel(cicr3
, pcdev
->base
+ CICR3
);
1029 __raw_writel(cicr4
, pcdev
->base
+ CICR4
);
1031 /* CIF interrupts are not used, only DMA */
1032 cicr0
= (cicr0
& CICR0_ENB
) | (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
1033 CICR0_SIM_MP
: (CICR0_SL_CAP_EN
| CICR0_SIM_SP
));
1034 cicr0
|= CICR0_DMAEN
| CICR0_IRQ_MASK
;
1035 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
1040 static int pxa_camera_try_bus_param(struct soc_camera_device
*icd
,
1041 unsigned char buswidth
)
1043 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1044 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1045 unsigned long bus_flags
, camera_flags
;
1046 int ret
= test_platform_param(pcdev
, buswidth
, &bus_flags
);
1051 camera_flags
= icd
->ops
->query_bus_param(icd
);
1053 return soc_camera_bus_param_compatible(camera_flags
, bus_flags
) ? 0 : -EINVAL
;
1056 static const struct soc_camera_data_format pxa_camera_formats
[] = {
1058 .name
= "Planar YUV422 16 bit",
1060 .fourcc
= V4L2_PIX_FMT_YUV422P
,
1061 .colorspace
= V4L2_COLORSPACE_JPEG
,
1065 static bool buswidth_supported(struct soc_camera_device
*icd
, int depth
)
1067 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1068 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1072 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
);
1074 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
);
1076 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
);
1081 static int required_buswidth(const struct soc_camera_data_format
*fmt
)
1083 switch (fmt
->fourcc
) {
1084 case V4L2_PIX_FMT_UYVY
:
1085 case V4L2_PIX_FMT_VYUY
:
1086 case V4L2_PIX_FMT_YUYV
:
1087 case V4L2_PIX_FMT_YVYU
:
1088 case V4L2_PIX_FMT_RGB565
:
1089 case V4L2_PIX_FMT_RGB555
:
1096 static int pxa_camera_get_formats(struct soc_camera_device
*icd
, int idx
,
1097 struct soc_camera_format_xlate
*xlate
)
1099 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1100 int formats
= 0, buswidth
, ret
;
1102 buswidth
= required_buswidth(icd
->formats
+ idx
);
1104 if (!buswidth_supported(icd
, buswidth
))
1107 ret
= pxa_camera_try_bus_param(icd
, buswidth
);
1111 switch (icd
->formats
[idx
].fourcc
) {
1112 case V4L2_PIX_FMT_UYVY
:
1115 xlate
->host_fmt
= &pxa_camera_formats
[0];
1116 xlate
->cam_fmt
= icd
->formats
+ idx
;
1117 xlate
->buswidth
= buswidth
;
1119 dev_dbg(&ici
->dev
, "Providing format %s using %s\n",
1120 pxa_camera_formats
[0].name
,
1121 icd
->formats
[idx
].name
);
1123 case V4L2_PIX_FMT_VYUY
:
1124 case V4L2_PIX_FMT_YUYV
:
1125 case V4L2_PIX_FMT_YVYU
:
1126 case V4L2_PIX_FMT_RGB565
:
1127 case V4L2_PIX_FMT_RGB555
:
1130 xlate
->host_fmt
= icd
->formats
+ idx
;
1131 xlate
->cam_fmt
= icd
->formats
+ idx
;
1132 xlate
->buswidth
= buswidth
;
1134 dev_dbg(&ici
->dev
, "Providing format %s packed\n",
1135 icd
->formats
[idx
].name
);
1139 /* Generic pass-through */
1142 xlate
->host_fmt
= icd
->formats
+ idx
;
1143 xlate
->cam_fmt
= icd
->formats
+ idx
;
1144 xlate
->buswidth
= icd
->formats
[idx
].depth
;
1147 "Providing format %s in pass-through mode\n",
1148 icd
->formats
[idx
].name
);
1155 static int pxa_camera_set_fmt(struct soc_camera_device
*icd
,
1156 __u32 pixfmt
, struct v4l2_rect
*rect
)
1158 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1159 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1160 const struct soc_camera_data_format
*host_fmt
, *cam_fmt
= NULL
;
1161 const struct soc_camera_format_xlate
*xlate
;
1162 struct soc_camera_sense sense
= {
1163 .master_clock
= pcdev
->mclk
,
1164 .pixel_clock_max
= pcdev
->ciclk
/ 4,
1168 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1170 dev_warn(&ici
->dev
, "Format %x not found\n", pixfmt
);
1174 buswidth
= xlate
->buswidth
;
1175 host_fmt
= xlate
->host_fmt
;
1176 cam_fmt
= xlate
->cam_fmt
;
1178 /* If PCLK is used to latch data from the sensor, check sense */
1179 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
1180 icd
->sense
= &sense
;
1183 case 0: /* Only geometry change */
1184 ret
= icd
->ops
->set_fmt(icd
, pixfmt
, rect
);
1187 ret
= icd
->ops
->set_fmt(icd
, cam_fmt
->fourcc
, rect
);
1193 dev_warn(&ici
->dev
, "Failed to configure for format %x\n",
1195 } else if (sense
.flags
& SOCAM_SENSE_PCLK_CHANGED
) {
1196 if (sense
.pixel_clock
> sense
.pixel_clock_max
) {
1198 "pixel clock %lu set by the camera too high!",
1202 recalculate_fifo_timeout(pcdev
, sense
.pixel_clock
);
1205 if (pixfmt
&& !ret
) {
1206 icd
->buswidth
= buswidth
;
1207 icd
->current_fmt
= host_fmt
;
1213 static int pxa_camera_try_fmt(struct soc_camera_device
*icd
,
1214 struct v4l2_format
*f
)
1216 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1217 const struct soc_camera_format_xlate
*xlate
;
1218 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1219 __u32 pixfmt
= pix
->pixelformat
;
1220 enum v4l2_field field
;
1223 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1225 dev_warn(&ici
->dev
, "Format %x not found\n", pixfmt
);
1229 /* limit to pxa hardware capabilities */
1230 if (pix
->height
< 32)
1232 if (pix
->height
> 2048)
1234 if (pix
->width
< 48)
1236 if (pix
->width
> 2048)
1238 pix
->width
&= ~0x01;
1240 pix
->bytesperline
= pix
->width
*
1241 DIV_ROUND_UP(xlate
->host_fmt
->depth
, 8);
1242 pix
->sizeimage
= pix
->height
* pix
->bytesperline
;
1244 /* camera has to see its format, but the user the original one */
1245 pix
->pixelformat
= xlate
->cam_fmt
->fourcc
;
1246 /* limit to sensor capabilities */
1247 ret
= icd
->ops
->try_fmt(icd
, f
);
1248 pix
->pixelformat
= xlate
->host_fmt
->fourcc
;
1252 if (field
== V4L2_FIELD_ANY
) {
1253 pix
->field
= V4L2_FIELD_NONE
;
1254 } else if (field
!= V4L2_FIELD_NONE
) {
1255 dev_err(&icd
->dev
, "Field type %d unsupported.\n", field
);
1262 static int pxa_camera_reqbufs(struct soc_camera_file
*icf
,
1263 struct v4l2_requestbuffers
*p
)
1267 /* This is for locking debugging only. I removed spinlocks and now I
1268 * check whether .prepare is ever called on a linked buffer, or whether
1269 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1270 * it hadn't triggered */
1271 for (i
= 0; i
< p
->count
; i
++) {
1272 struct pxa_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
1273 struct pxa_buffer
, vb
);
1275 INIT_LIST_HEAD(&buf
->vb
.queue
);
1281 static unsigned int pxa_camera_poll(struct file
*file
, poll_table
*pt
)
1283 struct soc_camera_file
*icf
= file
->private_data
;
1284 struct pxa_buffer
*buf
;
1286 buf
= list_entry(icf
->vb_vidq
.stream
.next
, struct pxa_buffer
,
1289 poll_wait(file
, &buf
->vb
.done
, pt
);
1291 if (buf
->vb
.state
== VIDEOBUF_DONE
||
1292 buf
->vb
.state
== VIDEOBUF_ERROR
)
1293 return POLLIN
|POLLRDNORM
;
1298 static int pxa_camera_querycap(struct soc_camera_host
*ici
,
1299 struct v4l2_capability
*cap
)
1301 /* cap->name is set by the firendly caller:-> */
1302 strlcpy(cap
->card
, pxa_cam_driver_description
, sizeof(cap
->card
));
1303 cap
->version
= PXA_CAM_VERSION_CODE
;
1304 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
1309 static int pxa_camera_suspend(struct soc_camera_device
*icd
, pm_message_t state
)
1311 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1312 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1315 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR0
);
1316 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR1
);
1317 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR2
);
1318 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR3
);
1319 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR4
);
1321 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->suspend
))
1322 ret
= pcdev
->icd
->ops
->suspend(pcdev
->icd
, state
);
1327 static int pxa_camera_resume(struct soc_camera_device
*icd
)
1329 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1330 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1333 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1334 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1335 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1337 __raw_writel(pcdev
->save_cicr
[i
++] & ~CICR0_ENB
, pcdev
->base
+ CICR0
);
1338 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR1
);
1339 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR2
);
1340 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR3
);
1341 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR4
);
1343 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->resume
))
1344 ret
= pcdev
->icd
->ops
->resume(pcdev
->icd
);
1346 /* Restart frame capture if active buffer exists */
1347 if (!ret
&& pcdev
->active
) {
1348 unsigned long cifr
, cicr0
;
1350 /* Reset the FIFOs */
1351 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
1352 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
1354 cicr0
= __raw_readl(pcdev
->base
+ CICR0
);
1355 cicr0
&= ~CICR0_EOFM
; /* Enable End-Of-Frame Interrupt */
1356 cicr0
|= CICR0_ENB
; /* Restart the Capture Interface */
1357 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
1363 static struct soc_camera_host_ops pxa_soc_camera_host_ops
= {
1364 .owner
= THIS_MODULE
,
1365 .add
= pxa_camera_add_device
,
1366 .remove
= pxa_camera_remove_device
,
1367 .suspend
= pxa_camera_suspend
,
1368 .resume
= pxa_camera_resume
,
1369 .get_formats
= pxa_camera_get_formats
,
1370 .set_fmt
= pxa_camera_set_fmt
,
1371 .try_fmt
= pxa_camera_try_fmt
,
1372 .init_videobuf
= pxa_camera_init_videobuf
,
1373 .reqbufs
= pxa_camera_reqbufs
,
1374 .poll
= pxa_camera_poll
,
1375 .querycap
= pxa_camera_querycap
,
1376 .set_bus_param
= pxa_camera_set_bus_param
,
1379 /* Should be allocated dynamically too, but we have only one. */
1380 static struct soc_camera_host pxa_soc_camera_host
= {
1381 .drv_name
= PXA_CAM_DRV_NAME
,
1382 .ops
= &pxa_soc_camera_host_ops
,
1385 static int pxa_camera_probe(struct platform_device
*pdev
)
1387 struct pxa_camera_dev
*pcdev
;
1388 struct resource
*res
;
1393 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1394 irq
= platform_get_irq(pdev
, 0);
1395 if (!res
|| irq
< 0) {
1400 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1402 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1407 pcdev
->clk
= clk_get(&pdev
->dev
, NULL
);
1408 if (IS_ERR(pcdev
->clk
)) {
1409 err
= PTR_ERR(pcdev
->clk
);
1413 dev_set_drvdata(&pdev
->dev
, pcdev
);
1416 pcdev
->pdata
= pdev
->dev
.platform_data
;
1417 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1418 if (!(pcdev
->platform_flags
& (PXA_CAMERA_DATAWIDTH_8
|
1419 PXA_CAMERA_DATAWIDTH_9
| PXA_CAMERA_DATAWIDTH_10
))) {
1420 /* Platform hasn't set available data widths. This is bad.
1421 * Warn and use a default. */
1422 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1423 "data widths, using default 10 bit\n");
1424 pcdev
->platform_flags
|= PXA_CAMERA_DATAWIDTH_10
;
1426 pcdev
->mclk
= pcdev
->pdata
->mclk_10khz
* 10000;
1428 dev_warn(&pdev
->dev
,
1429 "mclk == 0! Please, fix your platform data. "
1430 "Using default 20MHz\n");
1431 pcdev
->mclk
= 20000000;
1434 pcdev
->dev
= &pdev
->dev
;
1435 pcdev
->mclk_divisor
= mclk_get_divisor(pcdev
);
1437 INIT_LIST_HEAD(&pcdev
->capture
);
1438 spin_lock_init(&pcdev
->lock
);
1441 * Request the regions.
1443 if (!request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
1444 PXA_CAM_DRV_NAME
)) {
1449 base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1458 err
= pxa_request_dma("CI_Y", DMA_PRIO_HIGH
,
1459 pxa_camera_dma_irq_y
, pcdev
);
1461 dev_err(pcdev
->dev
, "Can't request DMA for Y\n");
1464 pcdev
->dma_chans
[0] = err
;
1465 dev_dbg(pcdev
->dev
, "got DMA channel %d\n", pcdev
->dma_chans
[0]);
1467 err
= pxa_request_dma("CI_U", DMA_PRIO_HIGH
,
1468 pxa_camera_dma_irq_u
, pcdev
);
1470 dev_err(pcdev
->dev
, "Can't request DMA for U\n");
1471 goto exit_free_dma_y
;
1473 pcdev
->dma_chans
[1] = err
;
1474 dev_dbg(pcdev
->dev
, "got DMA channel (U) %d\n", pcdev
->dma_chans
[1]);
1476 err
= pxa_request_dma("CI_V", DMA_PRIO_HIGH
,
1477 pxa_camera_dma_irq_v
, pcdev
);
1479 dev_err(pcdev
->dev
, "Can't request DMA for V\n");
1480 goto exit_free_dma_u
;
1482 pcdev
->dma_chans
[2] = err
;
1483 dev_dbg(pcdev
->dev
, "got DMA channel (V) %d\n", pcdev
->dma_chans
[2]);
1485 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1486 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1487 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1490 err
= request_irq(pcdev
->irq
, pxa_camera_irq
, 0, PXA_CAM_DRV_NAME
,
1493 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1497 pxa_soc_camera_host
.priv
= pcdev
;
1498 pxa_soc_camera_host
.dev
.parent
= &pdev
->dev
;
1499 pxa_soc_camera_host
.nr
= pdev
->id
;
1500 err
= soc_camera_host_register(&pxa_soc_camera_host
);
1507 free_irq(pcdev
->irq
, pcdev
);
1509 pxa_free_dma(pcdev
->dma_chans
[2]);
1511 pxa_free_dma(pcdev
->dma_chans
[1]);
1513 pxa_free_dma(pcdev
->dma_chans
[0]);
1517 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1519 clk_put(pcdev
->clk
);
1526 static int __devexit
pxa_camera_remove(struct platform_device
*pdev
)
1528 struct pxa_camera_dev
*pcdev
= platform_get_drvdata(pdev
);
1529 struct resource
*res
;
1531 clk_put(pcdev
->clk
);
1533 pxa_free_dma(pcdev
->dma_chans
[0]);
1534 pxa_free_dma(pcdev
->dma_chans
[1]);
1535 pxa_free_dma(pcdev
->dma_chans
[2]);
1536 free_irq(pcdev
->irq
, pcdev
);
1538 soc_camera_host_unregister(&pxa_soc_camera_host
);
1540 iounmap(pcdev
->base
);
1543 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1547 dev_info(&pdev
->dev
, "PXA Camera driver unloaded\n");
1552 static struct platform_driver pxa_camera_driver
= {
1554 .name
= PXA_CAM_DRV_NAME
,
1556 .probe
= pxa_camera_probe
,
1557 .remove
= __exit_p(pxa_camera_remove
),
1561 static int __devinit
pxa_camera_init(void)
1563 return platform_driver_register(&pxa_camera_driver
);
1566 static void __exit
pxa_camera_exit(void)
1568 platform_driver_unregister(&pxa_camera_driver
);
1571 module_init(pxa_camera_init
);
1572 module_exit(pxa_camera_exit
);
1574 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1575 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1576 MODULE_LICENSE("GPL");