drivers/memory/brcmstb_dpfe.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
   4  *
   5  * Copyright (c) 2017 Broadcom
   6  */
   7
   8 /*
   9  * This driver provides access to the DPFE interface of Broadcom STB SoCs.
  10  * The firmware running on the DCPU inside the DDR PHY can provide current
  11  * information about the system's RAM, for instance the DRAM refresh rate.
  12  * This can be used as an indirect indicator for the DRAM's temperature.
  13  * Slower refresh rate means cooler RAM, higher refresh rate means hotter
  14  * RAM.
  15  *
  16  * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
  17  * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
  18  *
  19  * Note regarding the loading of the firmware image: we use be32_to_cpu()
  20  * and le_32_to_cpu(), so we can support the following four cases:
  21  *     - LE kernel + LE firmware image (the most common case)
  22  *     - LE kernel + BE firmware image
  23  *     - BE kernel + LE firmware image
  24  *     - BE kernel + BE firmware image
  25  *
  26  * The DPCU always runs in big endian mode. The firmware image, however, can
  27  * be in either format. Also, communication between host CPU and DCPU is
  28  * always in little endian.
  29  */
  30
  31 #include <linux/delay.h>
  32 #include <linux/firmware.h>
  33 #include <linux/io.h>
  34 #include <linux/module.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_device.h>
  37 #include <linux/platform_device.h>
  38
  39 #define DRVNAME                 "brcmstb-dpfe"
  40
  41 /* DCPU register offsets */
  42 #define REG_DCPU_RESET          0x0
  43 #define REG_TO_DCPU_MBOX        0x10
  44 #define REG_TO_HOST_MBOX        0x14
  45
  46 /* Macros to process offsets returned by the DCPU */
  47 #define DRAM_MSG_ADDR_OFFSET    0x0
  48 #define DRAM_MSG_TYPE_OFFSET    0x1c
  49 #define DRAM_MSG_ADDR_MASK      ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
  50 #define DRAM_MSG_TYPE_MASK      ((1UL << \
  51                                  (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
  52
  53 /* Message RAM */
  54 #define DCPU_MSG_RAM_START      0x100
  55 #define DCPU_MSG_RAM(x)         (DCPU_MSG_RAM_START + (x) * sizeof(u32))
  56
  57 /* DRAM Info Offsets & Masks */
  58 #define DRAM_INFO_INTERVAL      0x0
  59 #define DRAM_INFO_MR4           0x4
  60 #define DRAM_INFO_ERROR         0x8
  61 #define DRAM_INFO_MR4_MASK      0xff
  62 #define DRAM_INFO_MR4_SHIFT     24      /* We need to look at byte 3 */
  63
  64 /* DRAM MR4 Offsets & Masks */
  65 #define DRAM_MR4_REFRESH        0x0     /* Refresh rate */
  66 #define DRAM_MR4_SR_ABORT       0x3     /* Self Refresh Abort */
  67 #define DRAM_MR4_PPRE           0x4     /* Post-package repair entry/exit */
  68 #define DRAM_MR4_TH_OFFS        0x5     /* Thermal Offset; vendor specific */
  69 #define DRAM_MR4_TUF            0x7     /* Temperature Update Flag */
  70
  71 #define DRAM_MR4_REFRESH_MASK   0x7
  72 #define DRAM_MR4_SR_ABORT_MASK  0x1
  73 #define DRAM_MR4_PPRE_MASK      0x1
  74 #define DRAM_MR4_TH_OFFS_MASK   0x3
  75 #define DRAM_MR4_TUF_MASK       0x1
  76
  77 /* DRAM Vendor Offsets & Masks (API v2) */
  78 #define DRAM_VENDOR_MR5         0x0
  79 #define DRAM_VENDOR_MR6         0x4
  80 #define DRAM_VENDOR_MR7         0x8
  81 #define DRAM_VENDOR_MR8         0xc
  82 #define DRAM_VENDOR_ERROR       0x10
  83 #define DRAM_VENDOR_MASK        0xff
  84 #define DRAM_VENDOR_SHIFT       24      /* We need to look at byte 3 */
  85
  86 /* DRAM Information Offsets & Masks (API v3) */
  87 #define DRAM_DDR_INFO_MR4       0x0
  88 #define DRAM_DDR_INFO_MR5       0x4
  89 #define DRAM_DDR_INFO_MR6       0x8
  90 #define DRAM_DDR_INFO_MR7       0xc
  91 #define DRAM_DDR_INFO_MR8       0x10
  92 #define DRAM_DDR_INFO_ERROR     0x14
  93 #define DRAM_DDR_INFO_MASK      0xff
  94
  95 /* Reset register bits & masks */
  96 #define DCPU_RESET_SHIFT        0x0
  97 #define DCPU_RESET_MASK         0x1
  98 #define DCPU_CLK_DISABLE_SHIFT  0x2
  99
 100 /* DCPU return codes */
 101 #define DCPU_RET_ERROR_BIT      BIT(31)
 102 #define DCPU_RET_SUCCESS        0x1
 103 #define DCPU_RET_ERR_HEADER     (DCPU_RET_ERROR_BIT | BIT(0))
 104 #define DCPU_RET_ERR_INVAL      (DCPU_RET_ERROR_BIT | BIT(1))
 105 #define DCPU_RET_ERR_CHKSUM     (DCPU_RET_ERROR_BIT | BIT(2))
 106 #define DCPU_RET_ERR_COMMAND    (DCPU_RET_ERROR_BIT | BIT(3))
 107 /* This error code is not firmware defined and only used in the driver. */
 108 #define DCPU_RET_ERR_TIMEDOUT   (DCPU_RET_ERROR_BIT | BIT(4))
 109
 110 /* Firmware magic */
 111 #define DPFE_BE_MAGIC           0xfe1010fe
 112 #define DPFE_LE_MAGIC           0xfe0101fe
 113
 114 /* Error codes */
 115 #define ERR_INVALID_MAGIC       -1
 116 #define ERR_INVALID_SIZE        -2
 117 #define ERR_INVALID_CHKSUM      -3
 118
 119 /* Message types */
 120 #define DPFE_MSG_TYPE_COMMAND   1
 121 #define DPFE_MSG_TYPE_RESPONSE  2
 122
 123 #define DELAY_LOOP_MAX          1000
 124
 125 enum dpfe_msg_fields {
 126         MSG_HEADER,
 127         MSG_COMMAND,
 128         MSG_ARG_COUNT,
 129         MSG_ARG0,
 130         MSG_FIELD_MAX   = 16 /* Max number of arguments */
 131 };
 132
 133 enum dpfe_commands {
 134         DPFE_CMD_GET_INFO,
 135         DPFE_CMD_GET_REFRESH,
 136         DPFE_CMD_GET_VENDOR,
 137         DPFE_CMD_MAX /* Last entry */
 138 };
 139
 140 /*
 141  * Format of the binary firmware file:
 142  *
 143  *   entry
 144  *      0    header
 145  *              value:  0xfe0101fe  <== little endian
 146  *                      0xfe1010fe  <== big endian
 147  *      1    sequence:
 148  *              [31:16] total segments on this build
 149  *              [15:0]  this segment sequence.
 150  *      2    FW version
 151  *      3    IMEM byte size
 152  *      4    DMEM byte size
 153  *           IMEM
 154  *           DMEM
 155  *      last checksum ==> sum of everything
 156  */
 157 struct dpfe_firmware_header {
 158         u32 magic;
 159         u32 sequence;
 160         u32 version;
 161         u32 imem_size;
 162         u32 dmem_size;
 163 };
 164
 165 /* Things we only need during initialization. */
 166 struct init_data {
 167         unsigned int dmem_len;
 168         unsigned int imem_len;
 169         unsigned int chksum;
 170         bool is_big_endian;
 171 };
 172
 173 /* API version and corresponding commands */
 174 struct dpfe_api {
 175         int version;
 176         const char *fw_name;
 177         const struct attribute_group **sysfs_attrs;
 178         u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
 179 };
 180
 181 /* Things we need for as long as we are active. */
 182 struct brcmstb_dpfe_priv {
 183         void __iomem *regs;
 184         void __iomem *dmem;
 185         void __iomem *imem;
 186         struct device *dev;
 187         const struct dpfe_api *dpfe_api;
 188         struct mutex lock;
 189 };
 190
 191 static const char * const error_text[] = {
 192         "Success", "Header code incorrect", "Unknown command or argument",
 193         "Incorrect checksum", "Malformed command", "Timed out",
 194 };
 195
 196 /*
 197  * Forward declaration of our sysfs attribute functions, so we can declare the
 198  * attribute data structures early.
 199  */
 200 static ssize_t show_info(struct device *, struct device_attribute *, char *);
 201 static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
 202 static ssize_t store_refresh(struct device *, struct device_attribute *,
 203                           const char *, size_t);
 204 static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
 205 static ssize_t show_dram(struct device *, struct device_attribute *, char *);
 206
 207 /*
 208  * Declare our attributes early, so they can be referenced in the API data
 209  * structure. We need to do this, because the attributes depend on the API
 210  * version.
 211  */
 212 static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
 213 static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
 214 static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
 215 static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
 216
 217 /* API v2 sysfs attributes */
 218 static struct attribute *dpfe_v2_attrs[] = {
 219         &dev_attr_dpfe_info.attr,
 220         &dev_attr_dpfe_refresh.attr,
 221         &dev_attr_dpfe_vendor.attr,
 222         NULL
 223 };
 224 ATTRIBUTE_GROUPS(dpfe_v2);
 225
 226 /* API v3 sysfs attributes */
 227 static struct attribute *dpfe_v3_attrs[] = {
 228         &dev_attr_dpfe_info.attr,
 229         &dev_attr_dpfe_dram.attr,
 230         NULL
 231 };
 232 ATTRIBUTE_GROUPS(dpfe_v3);
 233
 234 /*
 235  * Old API v2 firmware commands, as defined in the rev 0.61 specification, we
 236  * use a version set to 1 to denote that it is not compatible with the new API
 237  * v2 and onwards.
 238  */
 239 static const struct dpfe_api dpfe_api_old_v2 = {
 240         .version = 1,
 241         .fw_name = "dpfe.bin",
 242         .sysfs_attrs = dpfe_v2_groups,
 243         .command = {
 244                 [DPFE_CMD_GET_INFO] = {
 245                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 246                         [MSG_COMMAND] = 1,
 247                         [MSG_ARG_COUNT] = 1,
 248                         [MSG_ARG0] = 1,
 249                 },
 250                 [DPFE_CMD_GET_REFRESH] = {
 251                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 252                         [MSG_COMMAND] = 2,
 253                         [MSG_ARG_COUNT] = 1,
 254                         [MSG_ARG0] = 1,
 255                 },
 256                 [DPFE_CMD_GET_VENDOR] = {
 257                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 258                         [MSG_COMMAND] = 2,
 259                         [MSG_ARG_COUNT] = 1,
 260                         [MSG_ARG0] = 2,
 261                 },
 262         }
 263 };
 264
 265 /*
 266  * API v2 firmware commands, as defined in the rev 0.8 specification, named new
 267  * v2 here
 268  */
 269 static const struct dpfe_api dpfe_api_new_v2 = {
 270         .version = 2,
 271         .fw_name = NULL, /* We expect the firmware to have been downloaded! */
 272         .sysfs_attrs = dpfe_v2_groups,
 273         .command = {
 274                 [DPFE_CMD_GET_INFO] = {
 275                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 276                         [MSG_COMMAND] = 0x101,
 277                 },
 278                 [DPFE_CMD_GET_REFRESH] = {
 279                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 280                         [MSG_COMMAND] = 0x201,
 281                 },
 282                 [DPFE_CMD_GET_VENDOR] = {
 283                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 284                         [MSG_COMMAND] = 0x202,
 285                 },
 286         }
 287 };
 288
 289 /* API v3 firmware commands */
 290 static const struct dpfe_api dpfe_api_v3 = {
 291         .version = 3,
 292         .fw_name = NULL, /* We expect the firmware to have been downloaded! */
 293         .sysfs_attrs = dpfe_v3_groups,
 294         .command = {
 295                 [DPFE_CMD_GET_INFO] = {
 296                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 297                         [MSG_COMMAND] = 0x0101,
 298                         [MSG_ARG_COUNT] = 1,
 299                         [MSG_ARG0] = 1,
 300                 },
 301                 [DPFE_CMD_GET_REFRESH] = {
 302                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 303                         [MSG_COMMAND] = 0x0202,
 304                         [MSG_ARG_COUNT] = 0,
 305                 },
 306                 /* There's no GET_VENDOR command in API v3. */
 307         },
 308 };
 309
 310 static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
 311 {
 312         u32 val;
 313
 314         mutex_lock(&priv->lock);
 315         val = readl_relaxed(priv->regs + REG_DCPU_RESET);
 316         mutex_unlock(&priv->lock);
 317
 318         return !(val & DCPU_RESET_MASK);
 319 }
 320
 321 static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
 322 {
 323         u32 val;
 324
 325         if (!is_dcpu_enabled(priv))
 326                 return;
 327
 328         mutex_lock(&priv->lock);
 329
 330         /* Put DCPU in reset if it's running. */
 331         val = readl_relaxed(priv->regs + REG_DCPU_RESET);
 332         val |= (1 << DCPU_RESET_SHIFT);
 333         writel_relaxed(val, priv->regs + REG_DCPU_RESET);
 334
 335         mutex_unlock(&priv->lock);
 336 }
 337
 338 static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
 339 {
 340         void __iomem *regs = priv->regs;
 341         u32 val;
 342
 343         mutex_lock(&priv->lock);
 344
 345         /* Clear mailbox registers. */
 346         writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
 347         writel_relaxed(0, regs + REG_TO_HOST_MBOX);
 348
 349         /* Disable DCPU clock gating */
 350         val = readl_relaxed(regs + REG_DCPU_RESET);
 351         val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
 352         writel_relaxed(val, regs + REG_DCPU_RESET);
 353
 354         /* Take DCPU out of reset */
 355         val = readl_relaxed(regs + REG_DCPU_RESET);
 356         val &= ~(1 << DCPU_RESET_SHIFT);
 357         writel_relaxed(val, regs + REG_DCPU_RESET);
 358
 359         mutex_unlock(&priv->lock);
 360 }
 361
 362 static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
 363 {
 364         unsigned int sum = 0;
 365         unsigned int i;
 366
 367         /* Don't include the last field in the checksum. */
 368         for (i = 0; i < max; i++)
 369                 sum += msg[i];
 370
 371         return sum;
 372 }
 373
 374 static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
 375                                  char *buf, ssize_t *size)
 376 {
 377         unsigned int msg_type;
 378         unsigned int offset;
 379         void __iomem *ptr = NULL;
 380
 381         /* There is no need to use this function for API v3 or later. */
 382         if (unlikely(priv->dpfe_api->version >= 3))
 383                 return NULL;
 384
 385         msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
 386         offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
 387
 388         /*
 389          * msg_type == 1: the offset is relative to the message RAM
 390          * msg_type == 0: the offset is relative to the data RAM (this is the
 391          *                previous way of passing data)
 392          * msg_type is anything else: there's critical hardware problem
 393          */
 394         switch (msg_type) {
 395         case 1:
 396                 ptr = priv->regs + DCPU_MSG_RAM_START + offset;
 397                 break;
 398         case 0:
 399                 ptr = priv->dmem + offset;
 400                 break;
 401         default:
 402                 dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
 403                         response);
 404                 if (buf && size)
 405                         *size = sprintf(buf,
 406                                 "FATAL: communication error with DCPU\n");
 407         }
 408
 409         return ptr;
 410 }
 411
 412 static void __finalize_command(struct brcmstb_dpfe_priv *priv)
 413 {
 414         unsigned int release_mbox;
 415
 416         /*
 417          * It depends on the API version which MBOX register we have to write to
 418          * to signal we are done.
 419          */
 420         release_mbox = (priv->dpfe_api->version < 2)
 421                         ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
 422         writel_relaxed(0, priv->regs + release_mbox);
 423 }
 424
 425 static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
 426                           u32 result[])
 427 {
 428         const u32 *msg = priv->dpfe_api->command[cmd];
 429         void __iomem *regs = priv->regs;
 430         unsigned int i, chksum, chksum_idx;
 431         int ret = 0;
 432         u32 resp;
 433
 434         if (cmd >= DPFE_CMD_MAX)
 435                 return -1;
 436
 437         mutex_lock(&priv->lock);
 438
 439         /* Wait for DCPU to become ready */
 440         for (i = 0; i < DELAY_LOOP_MAX; i++) {
 441                 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
 442                 if (resp == 0)
 443                         break;
 444                 msleep(1);
 445         }
 446         if (resp != 0) {
 447                 mutex_unlock(&priv->lock);
 448                 return -ETIMEDOUT;
 449         }
 450
 451         /* Compute checksum over the message */
 452         chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
 453         chksum = get_msg_chksum(msg, chksum_idx);
 454
 455         /* Write command and arguments to message area */
 456         for (i = 0; i < MSG_FIELD_MAX; i++) {
 457                 if (i == chksum_idx)
 458                         writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
 459                 else
 460                         writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
 461         }
 462
 463         /* Tell DCPU there is a command waiting */
 464         writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
 465
 466         /* Wait for DCPU to process the command */
 467         for (i = 0; i < DELAY_LOOP_MAX; i++) {
 468                 /* Read response code */
 469                 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
 470                 if (resp > 0)
 471                         break;
 472                 msleep(1);
 473         }
 474
 475         if (i == DELAY_LOOP_MAX) {
 476                 resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
 477                 ret = -ffs(resp);
 478         } else {
 479                 /* Read response data */
 480                 for (i = 0; i < MSG_FIELD_MAX; i++)
 481                         result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
 482                 chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
 483         }
 484
 485         /* Tell DCPU we are done */
 486         __finalize_command(priv);
 487
 488         mutex_unlock(&priv->lock);
 489
 490         if (ret)
 491                 return ret;
 492
 493         /* Verify response */
 494         chksum = get_msg_chksum(result, chksum_idx);
 495         if (chksum != result[chksum_idx])
 496                 resp = DCPU_RET_ERR_CHKSUM;
 497
 498         if (resp != DCPU_RET_SUCCESS) {
 499                 resp &= ~DCPU_RET_ERROR_BIT;
 500                 ret = -ffs(resp);
 501         }
 502
 503         return ret;
 504 }
 505
 506 /* Ensure that the firmware file loaded meets all the requirements. */
 507 static int __verify_firmware(struct init_data *init,
 508                              const struct firmware *fw)
 509 {
 510         const struct dpfe_firmware_header *header = (void *)fw->data;
 511         unsigned int dmem_size, imem_size, total_size;
 512         bool is_big_endian = false;
 513         const u32 *chksum_ptr;
 514
 515         if (header->magic == DPFE_BE_MAGIC)
 516                 is_big_endian = true;
 517         else if (header->magic != DPFE_LE_MAGIC)
 518                 return ERR_INVALID_MAGIC;
 519
 520         if (is_big_endian) {
 521                 dmem_size = be32_to_cpu(header->dmem_size);
 522                 imem_size = be32_to_cpu(header->imem_size);
 523         } else {
 524                 dmem_size = le32_to_cpu(header->dmem_size);
 525                 imem_size = le32_to_cpu(header->imem_size);
 526         }
 527
 528         /* Data and instruction sections are 32 bit words. */
 529         if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
 530                 return ERR_INVALID_SIZE;
 531
 532         /*
 533          * The header + the data section + the instruction section + the
 534          * checksum must be equal to the total firmware size.
 535          */
 536         total_size = dmem_size + imem_size + sizeof(*header) +
 537                 sizeof(*chksum_ptr);
 538         if (total_size != fw->size)
 539                 return ERR_INVALID_SIZE;
 540
 541         /* The checksum comes at the very end. */
 542         chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
 543
 544         init->is_big_endian = is_big_endian;
 545         init->dmem_len = dmem_size;
 546         init->imem_len = imem_size;
 547         init->chksum = (is_big_endian)
 548                 ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
 549
 550         return 0;
 551 }
 552
 553 /* Verify checksum by reading back the firmware from co-processor RAM. */
 554 static int __verify_fw_checksum(struct init_data *init,
 555                                 struct brcmstb_dpfe_priv *priv,
 556                                 const struct dpfe_firmware_header *header,
 557                                 u32 checksum)
 558 {
 559         u32 magic, sequence, version, sum;
 560         u32 __iomem *dmem = priv->dmem;
 561         u32 __iomem *imem = priv->imem;
 562         unsigned int i;
 563
 564         if (init->is_big_endian) {
 565                 magic = be32_to_cpu(header->magic);
 566                 sequence = be32_to_cpu(header->sequence);
 567                 version = be32_to_cpu(header->version);
 568         } else {
 569                 magic = le32_to_cpu(header->magic);
 570                 sequence = le32_to_cpu(header->sequence);
 571                 version = le32_to_cpu(header->version);
 572         }
 573
 574         sum = magic + sequence + version + init->dmem_len + init->imem_len;
 575
 576         for (i = 0; i < init->dmem_len / sizeof(u32); i++)
 577                 sum += readl_relaxed(dmem + i);
 578
 579         for (i = 0; i < init->imem_len / sizeof(u32); i++)
 580                 sum += readl_relaxed(imem + i);
 581
 582         return (sum == checksum) ? 0 : -1;
 583 }
 584
 585 static int __write_firmware(u32 __iomem *mem, const u32 *fw,
 586                             unsigned int size, bool is_big_endian)
 587 {
 588         unsigned int i;
 589
 590         /* Convert size to 32-bit words. */
 591         size /= sizeof(u32);
 592
 593         /* It is recommended to clear the firmware area first. */
 594         for (i = 0; i < size; i++)
 595                 writel_relaxed(0, mem + i);
 596
 597         /* Now copy it. */
 598         if (is_big_endian) {
 599                 for (i = 0; i < size; i++)
 600                         writel_relaxed(be32_to_cpu(fw[i]), mem + i);
 601         } else {
 602                 for (i = 0; i < size; i++)
 603                         writel_relaxed(le32_to_cpu(fw[i]), mem + i);
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv)
 610 {
 611         const struct dpfe_firmware_header *header;
 612         unsigned int dmem_size, imem_size;
 613         struct device *dev = priv->dev;
 614         bool is_big_endian = false;
 615         const struct firmware *fw;
 616         const u32 *dmem, *imem;
 617         struct init_data init;
 618         const void *fw_blob;
 619         int ret;
 620
 621         /*
 622          * Skip downloading the firmware if the DCPU is already running and
 623          * responding to commands.
 624          */
 625         if (is_dcpu_enabled(priv)) {
 626                 u32 response[MSG_FIELD_MAX];
 627
 628                 ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
 629                 if (!ret)
 630                         return 0;
 631         }
 632
 633         /*
 634          * If the firmware filename is NULL it means the boot firmware has to
 635          * download the DCPU firmware for us. If that didn't work, we have to
 636          * bail, since downloading it ourselves wouldn't work either.
 637          */
 638         if (!priv->dpfe_api->fw_name)
 639                 return -ENODEV;
 640
 641         ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev);
 642         /*
 643          * Defer the firmware download if the firmware file couldn't be found.
 644          * The root file system may not be available yet.
 645          */
 646         if (ret)
 647                 return (ret == -ENOENT) ? -EPROBE_DEFER : ret;
 648
 649         ret = __verify_firmware(&init, fw);
 650         if (ret)
 651                 return -EFAULT;
 652
 653         __disable_dcpu(priv);
 654
 655         is_big_endian = init.is_big_endian;
 656         dmem_size = init.dmem_len;
 657         imem_size = init.imem_len;
 658
 659         /* At the beginning of the firmware blob is a header. */
 660         header = (struct dpfe_firmware_header *)fw->data;
 661         /* Void pointer to the beginning of the actual firmware. */
 662         fw_blob = fw->data + sizeof(*header);
 663         /* IMEM comes right after the header. */
 664         imem = fw_blob;
 665         /* DMEM follows after IMEM. */
 666         dmem = fw_blob + imem_size;
 667
 668         ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
 669         if (ret)
 670                 return ret;
 671         ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
 672         if (ret)
 673                 return ret;
 674
 675         ret = __verify_fw_checksum(&init, priv, header, init.chksum);
 676         if (ret)
 677                 return ret;
 678
 679         __enable_dcpu(priv);
 680
 681         return 0;
 682 }
 683
 684 static ssize_t generic_show(unsigned int command, u32 response[],
 685                             struct brcmstb_dpfe_priv *priv, char *buf)
 686 {
 687         int ret;
 688
 689         if (!priv)
 690                 return sprintf(buf, "ERROR: driver private data not set\n");
 691
 692         ret = __send_command(priv, command, response);
 693         if (ret < 0)
 694                 return sprintf(buf, "ERROR: %s\n", error_text[-ret]);
 695
 696         return 0;
 697 }
 698
 699 static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
 700                          char *buf)
 701 {
 702         u32 response[MSG_FIELD_MAX];
 703         struct brcmstb_dpfe_priv *priv;
 704         unsigned int info;
 705         ssize_t ret;
 706
 707         priv = dev_get_drvdata(dev);
 708         ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
 709         if (ret)
 710                 return ret;
 711
 712         info = response[MSG_ARG0];
 713
 714         return sprintf(buf, "%u.%u.%u.%u\n",
 715                        (info >> 24) & 0xff,
 716                        (info >> 16) & 0xff,
 717                        (info >> 8) & 0xff,
 718                        info & 0xff);
 719 }
 720
 721 static ssize_t show_refresh(struct device *dev,
 722                             struct device_attribute *devattr, char *buf)
 723 {
 724         u32 response[MSG_FIELD_MAX];
 725         void __iomem *info;
 726         struct brcmstb_dpfe_priv *priv;
 727         u8 refresh, sr_abort, ppre, thermal_offs, tuf;
 728         u32 mr4;
 729         ssize_t ret;
 730
 731         priv = dev_get_drvdata(dev);
 732         ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
 733         if (ret)
 734                 return ret;
 735
 736         info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
 737         if (!info)
 738                 return ret;
 739
 740         mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
 741                DRAM_INFO_MR4_MASK;
 742
 743         refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
 744         sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
 745         ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
 746         thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
 747         tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
 748
 749         return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
 750                        readl_relaxed(info + DRAM_INFO_INTERVAL),
 751                        refresh, sr_abort, ppre, thermal_offs, tuf,
 752                        readl_relaxed(info + DRAM_INFO_ERROR));
 753 }
 754
 755 static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
 756                           const char *buf, size_t count)
 757 {
 758         u32 response[MSG_FIELD_MAX];
 759         struct brcmstb_dpfe_priv *priv;
 760         void __iomem *info;
 761         unsigned long val;
 762         int ret;
 763
 764         if (kstrtoul(buf, 0, &val) < 0)
 765                 return -EINVAL;
 766
 767         priv = dev_get_drvdata(dev);
 768         ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
 769         if (ret)
 770                 return ret;
 771
 772         info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
 773         if (!info)
 774                 return -EIO;
 775
 776         writel_relaxed(val, info + DRAM_INFO_INTERVAL);
 777
 778         return count;
 779 }
 780
 781 static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
 782                            char *buf)
 783 {
 784         u32 response[MSG_FIELD_MAX];
 785         struct brcmstb_dpfe_priv *priv;
 786         void __iomem *info;
 787         ssize_t ret;
 788         u32 mr5, mr6, mr7, mr8, err;
 789
 790         priv = dev_get_drvdata(dev);
 791         ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
 792         if (ret)
 793                 return ret;
 794
 795         info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
 796         if (!info)
 797                 return ret;
 798
 799         mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
 800                 DRAM_VENDOR_MASK;
 801         mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
 802                 DRAM_VENDOR_MASK;
 803         mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
 804                 DRAM_VENDOR_MASK;
 805         mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
 806                 DRAM_VENDOR_MASK;
 807         err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
 808
 809         return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
 810 }
 811
 812 static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
 813                          char *buf)
 814 {
 815         u32 response[MSG_FIELD_MAX];
 816         struct brcmstb_dpfe_priv *priv;
 817         ssize_t ret;
 818         u32 mr4, mr5, mr6, mr7, mr8, err;
 819
 820         priv = dev_get_drvdata(dev);
 821         ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
 822         if (ret)
 823                 return ret;
 824
 825         mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
 826         mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
 827         mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
 828         mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
 829         mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
 830         err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
 831
 832         return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
 833                         mr8, err);
 834 }
 835
 836 static int brcmstb_dpfe_resume(struct platform_device *pdev)
 837 {
 838         struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev);
 839
 840         return brcmstb_dpfe_download_firmware(priv);
 841 }
 842
 843 static int brcmstb_dpfe_probe(struct platform_device *pdev)
 844 {
 845         struct device *dev = &pdev->dev;
 846         struct brcmstb_dpfe_priv *priv;
 847         struct resource *res;
 848         int ret;
 849
 850         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 851         if (!priv)
 852                 return -ENOMEM;
 853
 854         priv->dev = dev;
 855
 856         mutex_init(&priv->lock);
 857         platform_set_drvdata(pdev, priv);
 858
 859         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
 860         priv->regs = devm_ioremap_resource(dev, res);
 861         if (IS_ERR(priv->regs)) {
 862                 dev_err(dev, "couldn't map DCPU registers\n");
 863                 return -ENODEV;
 864         }
 865
 866         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
 867         priv->dmem = devm_ioremap_resource(dev, res);
 868         if (IS_ERR(priv->dmem)) {
 869                 dev_err(dev, "Couldn't map DCPU data memory\n");
 870                 return -ENOENT;
 871         }
 872
 873         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
 874         priv->imem = devm_ioremap_resource(dev, res);
 875         if (IS_ERR(priv->imem)) {
 876                 dev_err(dev, "Couldn't map DCPU instruction memory\n");
 877                 return -ENOENT;
 878         }
 879
 880         priv->dpfe_api = of_device_get_match_data(dev);
 881         if (unlikely(!priv->dpfe_api)) {
 882                 /*
 883                  * It should be impossible to end up here, but to be safe we
 884                  * check anyway.
 885                  */
 886                 dev_err(dev, "Couldn't determine API\n");
 887                 return -ENOENT;
 888         }
 889
 890         ret = brcmstb_dpfe_download_firmware(priv);
 891         if (ret) {
 892                 if (ret != -EPROBE_DEFER)
 893                         dev_err(dev, "Couldn't download firmware -- %d\n", ret);
 894                 return ret;
 895         }
 896
 897         ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
 898         if (!ret)
 899                 dev_info(dev, "registered with API v%d.\n",
 900                          priv->dpfe_api->version);
 901
 902         return ret;
 903 }
 904
 905 static int brcmstb_dpfe_remove(struct platform_device *pdev)
 906 {
 907         struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
 908
 909         sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
 910
 911         return 0;
 912 }
 913
 914 static const struct of_device_id brcmstb_dpfe_of_match[] = {
 915         /* Use legacy API v2 for a select number of chips */
 916         { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 },
 917         { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 },
 918         { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 },
 919         { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 },
 920         /* API v3 is the default going forward */
 921         { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
 922         {}
 923 };
 924 MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
 925
 926 static struct platform_driver brcmstb_dpfe_driver = {
 927         .driver = {
 928                 .name = DRVNAME,
 929                 .of_match_table = brcmstb_dpfe_of_match,
 930         },
 931         .probe = brcmstb_dpfe_probe,
 932         .remove = brcmstb_dpfe_remove,
 933         .resume = brcmstb_dpfe_resume,
 934 };
 935
 936 module_platform_driver(brcmstb_dpfe_driver);
 937
 938 MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
 939 MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
 940 MODULE_LICENSE("GPL");