4 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Aneesh V <aneesh@ti.com>
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/kernel.h>
15 #include <linux/reboot.h>
16 #include <linux/platform_data/emif_plat.h>
18 #include <linux/device.h>
19 #include <linux/platform_device.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/module.h>
26 #include <linux/list.h>
27 #include <linux/spinlock.h>
28 #include <memory/jedec_ddr.h>
30 #include "of_memory.h"
33 * struct emif_data - Per device static data for driver's use
34 * @duplicate: Whether the DDR devices attached to this EMIF
35 * instance are exactly same as that on EMIF1. In
36 * this case we can save some memory and processing
37 * @temperature_level: Maximum temperature of LPDDR2 devices attached
38 * to this EMIF - read from MR4 register. If there
39 * are two devices attached to this EMIF, this
40 * value is the maximum of the two temperature
42 * @node: node in the device list
43 * @base: base address of memory-mapped IO registers.
44 * @dev: device pointer.
45 * @addressing table with addressing information from the spec
46 * @regs_cache: An array of 'struct emif_regs' that stores
47 * calculated register values for different
48 * frequencies, to avoid re-calculating them on
49 * each DVFS transition.
50 * @curr_regs: The set of register values used in the last
51 * frequency change (i.e. corresponding to the
52 * frequency in effect at the moment)
53 * @plat_data: Pointer to saved platform data.
54 * @debugfs_root: dentry to the root folder for EMIF in debugfs
55 * @np_ddr: Pointer to ddr device tree node
61 struct list_head node
;
62 unsigned long irq_state
;
65 const struct lpddr2_addressing
*addressing
;
66 struct emif_regs
*regs_cache
[EMIF_MAX_NUM_FREQUENCIES
];
67 struct emif_regs
*curr_regs
;
68 struct emif_platform_data
*plat_data
;
69 struct dentry
*debugfs_root
;
70 struct device_node
*np_ddr
;
73 static struct emif_data
*emif1
;
74 static spinlock_t emif_lock
;
75 static unsigned long irq_state
;
76 static u32 t_ck
; /* DDR clock period in ps */
77 static LIST_HEAD(device_list
);
79 #ifdef CONFIG_DEBUG_FS
80 static void do_emif_regdump_show(struct seq_file
*s
, struct emif_data
*emif
,
81 struct emif_regs
*regs
)
83 u32 type
= emif
->plat_data
->device_info
->type
;
84 u32 ip_rev
= emif
->plat_data
->ip_rev
;
86 seq_printf(s
, "EMIF register cache dump for %dMHz\n",
89 seq_printf(s
, "ref_ctrl_shdw\t: 0x%08x\n", regs
->ref_ctrl_shdw
);
90 seq_printf(s
, "sdram_tim1_shdw\t: 0x%08x\n", regs
->sdram_tim1_shdw
);
91 seq_printf(s
, "sdram_tim2_shdw\t: 0x%08x\n", regs
->sdram_tim2_shdw
);
92 seq_printf(s
, "sdram_tim3_shdw\t: 0x%08x\n", regs
->sdram_tim3_shdw
);
94 if (ip_rev
== EMIF_4D
) {
95 seq_printf(s
, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
96 regs
->read_idle_ctrl_shdw_normal
);
97 seq_printf(s
, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
98 regs
->read_idle_ctrl_shdw_volt_ramp
);
99 } else if (ip_rev
== EMIF_4D5
) {
100 seq_printf(s
, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
101 regs
->dll_calib_ctrl_shdw_normal
);
102 seq_printf(s
, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
103 regs
->dll_calib_ctrl_shdw_volt_ramp
);
106 if (type
== DDR_TYPE_LPDDR2_S2
|| type
== DDR_TYPE_LPDDR2_S4
) {
107 seq_printf(s
, "ref_ctrl_shdw_derated\t: 0x%08x\n",
108 regs
->ref_ctrl_shdw_derated
);
109 seq_printf(s
, "sdram_tim1_shdw_derated\t: 0x%08x\n",
110 regs
->sdram_tim1_shdw_derated
);
111 seq_printf(s
, "sdram_tim3_shdw_derated\t: 0x%08x\n",
112 regs
->sdram_tim3_shdw_derated
);
116 static int emif_regdump_show(struct seq_file
*s
, void *unused
)
118 struct emif_data
*emif
= s
->private;
119 struct emif_regs
**regs_cache
;
123 regs_cache
= emif1
->regs_cache
;
125 regs_cache
= emif
->regs_cache
;
127 for (i
= 0; i
< EMIF_MAX_NUM_FREQUENCIES
&& regs_cache
[i
]; i
++) {
128 do_emif_regdump_show(s
, emif
, regs_cache
[i
]);
135 static int emif_regdump_open(struct inode
*inode
, struct file
*file
)
137 return single_open(file
, emif_regdump_show
, inode
->i_private
);
140 static const struct file_operations emif_regdump_fops
= {
141 .open
= emif_regdump_open
,
143 .release
= single_release
,
146 static int emif_mr4_show(struct seq_file
*s
, void *unused
)
148 struct emif_data
*emif
= s
->private;
150 seq_printf(s
, "MR4=%d\n", emif
->temperature_level
);
154 static int emif_mr4_open(struct inode
*inode
, struct file
*file
)
156 return single_open(file
, emif_mr4_show
, inode
->i_private
);
159 static const struct file_operations emif_mr4_fops
= {
160 .open
= emif_mr4_open
,
162 .release
= single_release
,
165 static int __init_or_module
emif_debugfs_init(struct emif_data
*emif
)
167 struct dentry
*dentry
;
170 dentry
= debugfs_create_dir(dev_name(emif
->dev
), NULL
);
175 emif
->debugfs_root
= dentry
;
177 dentry
= debugfs_create_file("regcache_dump", S_IRUGO
,
178 emif
->debugfs_root
, emif
, &emif_regdump_fops
);
184 dentry
= debugfs_create_file("mr4", S_IRUGO
,
185 emif
->debugfs_root
, emif
, &emif_mr4_fops
);
193 debugfs_remove_recursive(emif
->debugfs_root
);
198 static void __exit
emif_debugfs_exit(struct emif_data
*emif
)
200 debugfs_remove_recursive(emif
->debugfs_root
);
201 emif
->debugfs_root
= NULL
;
204 static inline int __init_or_module
emif_debugfs_init(struct emif_data
*emif
)
209 static inline void __exit
emif_debugfs_exit(struct emif_data
*emif
)
215 * Calculate the period of DDR clock from frequency value
217 static void set_ddr_clk_period(u32 freq
)
219 /* Divide 10^12 by frequency to get period in ps */
220 t_ck
= (u32
)DIV_ROUND_UP_ULL(1000000000000ull, freq
);
224 * Get bus width used by EMIF. Note that this may be different from the
225 * bus width of the DDR devices used. For instance two 16-bit DDR devices
226 * may be connected to a given CS of EMIF. In this case bus width as far
227 * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
229 static u32
get_emif_bus_width(struct emif_data
*emif
)
232 void __iomem
*base
= emif
->base
;
234 width
= (readl(base
+ EMIF_SDRAM_CONFIG
) & NARROW_MODE_MASK
)
235 >> NARROW_MODE_SHIFT
;
236 width
= width
== 0 ? 32 : 16;
242 * Get the CL from SDRAM_CONFIG register
244 static u32
get_cl(struct emif_data
*emif
)
247 void __iomem
*base
= emif
->base
;
249 cl
= (readl(base
+ EMIF_SDRAM_CONFIG
) & CL_MASK
) >> CL_SHIFT
;
254 static void set_lpmode(struct emif_data
*emif
, u8 lpmode
)
257 void __iomem
*base
= emif
->base
;
259 temp
= readl(base
+ EMIF_POWER_MANAGEMENT_CONTROL
);
260 temp
&= ~LP_MODE_MASK
;
261 temp
|= (lpmode
<< LP_MODE_SHIFT
);
262 writel(temp
, base
+ EMIF_POWER_MANAGEMENT_CONTROL
);
265 static void do_freq_update(void)
267 struct emif_data
*emif
;
270 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
273 * The EMIF automatically puts the SDRAM into self-refresh mode
274 * after the EMIF has not performed accesses during
275 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
276 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
277 * to 0x2. If during a small window the following three events
279 * - The SR_TIMING counter expires
280 * - And frequency change is requested
281 * - And OCP access is requested
282 * Then it causes instable clock on the DDR interface.
285 * To avoid the occurrence of the three events, the workaround
286 * is to disable the self-refresh when requesting a frequency
287 * change. Before requesting a frequency change the software must
288 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
289 * frequency change has been done, the software can reprogram
290 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
292 list_for_each_entry(emif
, &device_list
, node
) {
293 if (emif
->lpmode
== EMIF_LP_MODE_SELF_REFRESH
)
294 set_lpmode(emif
, EMIF_LP_MODE_DISABLE
);
298 * TODO: Do FREQ_UPDATE here when an API
299 * is available for this as part of the new
303 list_for_each_entry(emif
, &device_list
, node
) {
304 if (emif
->lpmode
== EMIF_LP_MODE_SELF_REFRESH
)
305 set_lpmode(emif
, EMIF_LP_MODE_SELF_REFRESH
);
309 /* Find addressing table entry based on the device's type and density */
310 static const struct lpddr2_addressing
*get_addressing_table(
311 const struct ddr_device_info
*device_info
)
313 u32 index
, type
, density
;
315 type
= device_info
->type
;
316 density
= device_info
->density
;
319 case DDR_TYPE_LPDDR2_S4
:
322 case DDR_TYPE_LPDDR2_S2
:
324 case DDR_DENSITY_1Gb
:
325 case DDR_DENSITY_2Gb
:
336 return &lpddr2_jedec_addressing_table
[index
];
340 * Find the the right timing table from the array of timing
341 * tables of the device using DDR clock frequency
343 static const struct lpddr2_timings
*get_timings_table(struct emif_data
*emif
,
346 u32 i
, min
, max
, freq_nearest
;
347 const struct lpddr2_timings
*timings
= NULL
;
348 const struct lpddr2_timings
*timings_arr
= emif
->plat_data
->timings
;
349 struct device
*dev
= emif
->dev
;
351 /* Start with a very high frequency - 1GHz */
352 freq_nearest
= 1000000000;
355 * Find the timings table such that:
356 * 1. the frequency range covers the required frequency(safe) AND
357 * 2. the max_freq is closest to the required frequency(optimal)
359 for (i
= 0; i
< emif
->plat_data
->timings_arr_size
; i
++) {
360 max
= timings_arr
[i
].max_freq
;
361 min
= timings_arr
[i
].min_freq
;
362 if ((freq
>= min
) && (freq
<= max
) && (max
< freq_nearest
)) {
364 timings
= &timings_arr
[i
];
369 dev_err(dev
, "%s: couldn't find timings for - %dHz\n",
372 dev_dbg(dev
, "%s: timings table: freq %d, speed bin freq %d\n",
373 __func__
, freq
, freq_nearest
);
378 static u32
get_sdram_ref_ctrl_shdw(u32 freq
,
379 const struct lpddr2_addressing
*addressing
)
381 u32 ref_ctrl_shdw
= 0, val
= 0, freq_khz
, t_refi
;
383 /* Scale down frequency and t_refi to avoid overflow */
384 freq_khz
= freq
/ 1000;
385 t_refi
= addressing
->tREFI_ns
/ 100;
388 * refresh rate to be set is 'tREFI(in us) * freq in MHz
389 * division by 10000 to account for change in units
391 val
= t_refi
* freq_khz
/ 10000;
392 ref_ctrl_shdw
|= val
<< REFRESH_RATE_SHIFT
;
394 return ref_ctrl_shdw
;
397 static u32
get_sdram_tim_1_shdw(const struct lpddr2_timings
*timings
,
398 const struct lpddr2_min_tck
*min_tck
,
399 const struct lpddr2_addressing
*addressing
)
401 u32 tim1
= 0, val
= 0;
403 val
= max(min_tck
->tWTR
, DIV_ROUND_UP(timings
->tWTR
, t_ck
)) - 1;
404 tim1
|= val
<< T_WTR_SHIFT
;
406 if (addressing
->num_banks
== B8
)
407 val
= DIV_ROUND_UP(timings
->tFAW
, t_ck
*4);
409 val
= max(min_tck
->tRRD
, DIV_ROUND_UP(timings
->tRRD
, t_ck
));
410 tim1
|= (val
- 1) << T_RRD_SHIFT
;
412 val
= DIV_ROUND_UP(timings
->tRAS_min
+ timings
->tRPab
, t_ck
) - 1;
413 tim1
|= val
<< T_RC_SHIFT
;
415 val
= max(min_tck
->tRASmin
, DIV_ROUND_UP(timings
->tRAS_min
, t_ck
));
416 tim1
|= (val
- 1) << T_RAS_SHIFT
;
418 val
= max(min_tck
->tWR
, DIV_ROUND_UP(timings
->tWR
, t_ck
)) - 1;
419 tim1
|= val
<< T_WR_SHIFT
;
421 val
= max(min_tck
->tRCD
, DIV_ROUND_UP(timings
->tRCD
, t_ck
)) - 1;
422 tim1
|= val
<< T_RCD_SHIFT
;
424 val
= max(min_tck
->tRPab
, DIV_ROUND_UP(timings
->tRPab
, t_ck
)) - 1;
425 tim1
|= val
<< T_RP_SHIFT
;
430 static u32
get_sdram_tim_1_shdw_derated(const struct lpddr2_timings
*timings
,
431 const struct lpddr2_min_tck
*min_tck
,
432 const struct lpddr2_addressing
*addressing
)
434 u32 tim1
= 0, val
= 0;
436 val
= max(min_tck
->tWTR
, DIV_ROUND_UP(timings
->tWTR
, t_ck
)) - 1;
437 tim1
= val
<< T_WTR_SHIFT
;
440 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
441 * to tFAW for de-rating
443 if (addressing
->num_banks
== B8
) {
444 val
= DIV_ROUND_UP(timings
->tFAW
+ 7500, 4 * t_ck
) - 1;
446 val
= DIV_ROUND_UP(timings
->tRRD
+ 1875, t_ck
);
447 val
= max(min_tck
->tRRD
, val
) - 1;
449 tim1
|= val
<< T_RRD_SHIFT
;
451 val
= DIV_ROUND_UP(timings
->tRAS_min
+ timings
->tRPab
+ 1875, t_ck
);
452 tim1
|= (val
- 1) << T_RC_SHIFT
;
454 val
= DIV_ROUND_UP(timings
->tRAS_min
+ 1875, t_ck
);
455 val
= max(min_tck
->tRASmin
, val
) - 1;
456 tim1
|= val
<< T_RAS_SHIFT
;
458 val
= max(min_tck
->tWR
, DIV_ROUND_UP(timings
->tWR
, t_ck
)) - 1;
459 tim1
|= val
<< T_WR_SHIFT
;
461 val
= max(min_tck
->tRCD
, DIV_ROUND_UP(timings
->tRCD
+ 1875, t_ck
));
462 tim1
|= (val
- 1) << T_RCD_SHIFT
;
464 val
= max(min_tck
->tRPab
, DIV_ROUND_UP(timings
->tRPab
+ 1875, t_ck
));
465 tim1
|= (val
- 1) << T_RP_SHIFT
;
470 static u32
get_sdram_tim_2_shdw(const struct lpddr2_timings
*timings
,
471 const struct lpddr2_min_tck
*min_tck
,
472 const struct lpddr2_addressing
*addressing
,
475 u32 tim2
= 0, val
= 0;
477 val
= min_tck
->tCKE
- 1;
478 tim2
|= val
<< T_CKE_SHIFT
;
480 val
= max(min_tck
->tRTP
, DIV_ROUND_UP(timings
->tRTP
, t_ck
)) - 1;
481 tim2
|= val
<< T_RTP_SHIFT
;
483 /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
484 val
= DIV_ROUND_UP(addressing
->tRFCab_ps
+ 10000, t_ck
) - 1;
485 tim2
|= val
<< T_XSNR_SHIFT
;
487 /* XSRD same as XSNR for LPDDR2 */
488 tim2
|= val
<< T_XSRD_SHIFT
;
490 val
= max(min_tck
->tXP
, DIV_ROUND_UP(timings
->tXP
, t_ck
)) - 1;
491 tim2
|= val
<< T_XP_SHIFT
;
496 static u32
get_sdram_tim_3_shdw(const struct lpddr2_timings
*timings
,
497 const struct lpddr2_min_tck
*min_tck
,
498 const struct lpddr2_addressing
*addressing
,
499 u32 type
, u32 ip_rev
, u32 derated
)
501 u32 tim3
= 0, val
= 0, t_dqsck
;
503 val
= timings
->tRAS_max_ns
/ addressing
->tREFI_ns
- 1;
504 val
= val
> 0xF ? 0xF : val
;
505 tim3
|= val
<< T_RAS_MAX_SHIFT
;
507 val
= DIV_ROUND_UP(addressing
->tRFCab_ps
, t_ck
) - 1;
508 tim3
|= val
<< T_RFC_SHIFT
;
510 t_dqsck
= (derated
== EMIF_DERATED_TIMINGS
) ?
511 timings
->tDQSCK_max_derated
: timings
->tDQSCK_max
;
512 if (ip_rev
== EMIF_4D5
)
513 val
= DIV_ROUND_UP(t_dqsck
+ 1000, t_ck
) - 1;
515 val
= DIV_ROUND_UP(t_dqsck
, t_ck
) - 1;
517 tim3
|= val
<< T_TDQSCKMAX_SHIFT
;
519 val
= DIV_ROUND_UP(timings
->tZQCS
, t_ck
) - 1;
520 tim3
|= val
<< ZQ_ZQCS_SHIFT
;
522 val
= DIV_ROUND_UP(timings
->tCKESR
, t_ck
);
523 val
= max(min_tck
->tCKESR
, val
) - 1;
524 tim3
|= val
<< T_CKESR_SHIFT
;
526 if (ip_rev
== EMIF_4D5
) {
527 tim3
|= (EMIF_T_CSTA
- 1) << T_CSTA_SHIFT
;
529 val
= DIV_ROUND_UP(EMIF_T_PDLL_UL
, 128) - 1;
530 tim3
|= val
<< T_PDLL_UL_SHIFT
;
536 static u32
get_zq_config_reg(const struct lpddr2_addressing
*addressing
,
537 bool cs1_used
, bool cal_resistors_per_cs
)
541 val
= EMIF_ZQCS_INTERVAL_US
* 1000 / addressing
->tREFI_ns
;
542 zq
|= val
<< ZQ_REFINTERVAL_SHIFT
;
544 val
= DIV_ROUND_UP(T_ZQCL_DEFAULT_NS
, T_ZQCS_DEFAULT_NS
) - 1;
545 zq
|= val
<< ZQ_ZQCL_MULT_SHIFT
;
547 val
= DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS
, T_ZQCL_DEFAULT_NS
) - 1;
548 zq
|= val
<< ZQ_ZQINIT_MULT_SHIFT
;
550 zq
|= ZQ_SFEXITEN_ENABLE
<< ZQ_SFEXITEN_SHIFT
;
552 if (cal_resistors_per_cs
)
553 zq
|= ZQ_DUALCALEN_ENABLE
<< ZQ_DUALCALEN_SHIFT
;
555 zq
|= ZQ_DUALCALEN_DISABLE
<< ZQ_DUALCALEN_SHIFT
;
557 zq
|= ZQ_CS0EN_MASK
; /* CS0 is used for sure */
559 val
= cs1_used
? 1 : 0;
560 zq
|= val
<< ZQ_CS1EN_SHIFT
;
565 static u32
get_temp_alert_config(const struct lpddr2_addressing
*addressing
,
566 const struct emif_custom_configs
*custom_configs
, bool cs1_used
,
567 u32 sdram_io_width
, u32 emif_bus_width
)
569 u32 alert
= 0, interval
, devcnt
;
571 if (custom_configs
&& (custom_configs
->mask
&
572 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL
))
573 interval
= custom_configs
->temp_alert_poll_interval_ms
;
575 interval
= TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS
;
577 interval
*= 1000000; /* Convert to ns */
578 interval
/= addressing
->tREFI_ns
; /* Convert to refresh cycles */
579 alert
|= (interval
<< TA_REFINTERVAL_SHIFT
);
582 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
583 * also to this form and subtract to get TA_DEVCNT, which is
586 emif_bus_width
= __fls(emif_bus_width
) - 1;
587 devcnt
= emif_bus_width
- sdram_io_width
;
588 alert
|= devcnt
<< TA_DEVCNT_SHIFT
;
590 /* DEVWDT is in 'log2(x) - 3' form */
591 alert
|= (sdram_io_width
- 2) << TA_DEVWDT_SHIFT
;
593 alert
|= 1 << TA_SFEXITEN_SHIFT
;
594 alert
|= 1 << TA_CS0EN_SHIFT
;
595 alert
|= (cs1_used
? 1 : 0) << TA_CS1EN_SHIFT
;
600 static u32
get_read_idle_ctrl_shdw(u8 volt_ramp
)
602 u32 idle
= 0, val
= 0;
605 * Maximum value in normal conditions and increased frequency
606 * when voltage is ramping
609 val
= READ_IDLE_INTERVAL_DVFS
/ t_ck
/ 64 - 1;
614 * READ_IDLE_CTRL register in EMIF4D has same offset and fields
615 * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
617 idle
|= val
<< DLL_CALIB_INTERVAL_SHIFT
;
618 idle
|= EMIF_READ_IDLE_LEN_VAL
<< ACK_WAIT_SHIFT
;
623 static u32
get_dll_calib_ctrl_shdw(u8 volt_ramp
)
625 u32 calib
= 0, val
= 0;
627 if (volt_ramp
== DDR_VOLTAGE_RAMPING
)
628 val
= DLL_CALIB_INTERVAL_DVFS
/ t_ck
/ 16 - 1;
630 val
= 0; /* Disabled when voltage is stable */
632 calib
|= val
<< DLL_CALIB_INTERVAL_SHIFT
;
633 calib
|= DLL_CALIB_ACK_WAIT_VAL
<< ACK_WAIT_SHIFT
;
638 static u32
get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings
*timings
,
641 u32 phy
= EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY
, val
= 0;
643 val
= RL
+ DIV_ROUND_UP(timings
->tDQSCK_max
, t_ck
) - 1;
644 phy
|= val
<< READ_LATENCY_SHIFT_4D
;
646 if (freq
<= 100000000)
647 val
= EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY
;
648 else if (freq
<= 200000000)
649 val
= EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY
;
651 val
= EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY
;
653 phy
|= val
<< DLL_SLAVE_DLY_CTRL_SHIFT_4D
;
658 static u32
get_phy_ctrl_1_intelliphy_4d5(u32 freq
, u8 cl
)
660 u32 phy
= EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY
, half_delay
;
663 * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
664 * half-delay is not needed else set half-delay
666 if (freq
>= 265000000 && freq
< 267000000)
671 phy
|= half_delay
<< DLL_HALF_DELAY_SHIFT_4D5
;
672 phy
|= ((cl
+ DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS
,
673 t_ck
) - 1) << READ_LATENCY_SHIFT_4D5
);
678 static u32
get_ext_phy_ctrl_2_intelliphy_4d5(void)
680 u32 fifo_we_slave_ratio
;
682 fifo_we_slave_ratio
= DIV_ROUND_CLOSEST(
683 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS
* 256 , t_ck
);
685 return fifo_we_slave_ratio
| fifo_we_slave_ratio
<< 11 |
686 fifo_we_slave_ratio
<< 22;
689 static u32
get_ext_phy_ctrl_3_intelliphy_4d5(void)
691 u32 fifo_we_slave_ratio
;
693 fifo_we_slave_ratio
= DIV_ROUND_CLOSEST(
694 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS
* 256 , t_ck
);
696 return fifo_we_slave_ratio
>> 10 | fifo_we_slave_ratio
<< 1 |
697 fifo_we_slave_ratio
<< 12 | fifo_we_slave_ratio
<< 23;
700 static u32
get_ext_phy_ctrl_4_intelliphy_4d5(void)
702 u32 fifo_we_slave_ratio
;
704 fifo_we_slave_ratio
= DIV_ROUND_CLOSEST(
705 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS
* 256 , t_ck
);
707 return fifo_we_slave_ratio
>> 9 | fifo_we_slave_ratio
<< 2 |
708 fifo_we_slave_ratio
<< 13;
711 static u32
get_pwr_mgmt_ctrl(u32 freq
, struct emif_data
*emif
, u32 ip_rev
)
713 u32 pwr_mgmt_ctrl
= 0, timeout
;
714 u32 lpmode
= EMIF_LP_MODE_SELF_REFRESH
;
715 u32 timeout_perf
= EMIF_LP_MODE_TIMEOUT_PERFORMANCE
;
716 u32 timeout_pwr
= EMIF_LP_MODE_TIMEOUT_POWER
;
717 u32 freq_threshold
= EMIF_LP_MODE_FREQ_THRESHOLD
;
721 struct emif_custom_configs
*cust_cfgs
= emif
->plat_data
->custom_configs
;
723 if (cust_cfgs
&& (cust_cfgs
->mask
& EMIF_CUSTOM_CONFIG_LPMODE
)) {
724 lpmode
= cust_cfgs
->lpmode
;
725 timeout_perf
= cust_cfgs
->lpmode_timeout_performance
;
726 timeout_pwr
= cust_cfgs
->lpmode_timeout_power
;
727 freq_threshold
= cust_cfgs
->lpmode_freq_threshold
;
730 /* Timeout based on DDR frequency */
731 timeout
= freq
>= freq_threshold
? timeout_perf
: timeout_pwr
;
734 * The value to be set in register is "log2(timeout) - 3"
735 * if timeout < 16 load 0 in register
736 * if timeout is not a power of 2, round to next highest power of 2
741 if (timeout
& (timeout
- 1))
743 timeout
= __fls(timeout
) - 3;
747 case EMIF_LP_MODE_CLOCK_STOP
:
748 shift
= CS_TIM_SHIFT
;
751 case EMIF_LP_MODE_SELF_REFRESH
:
752 /* Workaround for errata i735 */
756 shift
= SR_TIM_SHIFT
;
759 case EMIF_LP_MODE_PWR_DN
:
760 shift
= PD_TIM_SHIFT
;
763 case EMIF_LP_MODE_DISABLE
:
769 /* Round to maximum in case of overflow, BUT warn! */
770 if (lpmode
!= EMIF_LP_MODE_DISABLE
&& timeout
> mask
>> shift
) {
771 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
776 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
777 timeout
, mask
>> shift
);
778 timeout
= mask
>> shift
;
781 /* Setup required timing */
782 pwr_mgmt_ctrl
= (timeout
<< shift
) & mask
;
783 /* setup a default mask for rest of the modes */
784 pwr_mgmt_ctrl
|= (SR_TIM_MASK
| CS_TIM_MASK
| PD_TIM_MASK
) &
787 /* No CS_TIM in EMIF_4D5 */
788 if (ip_rev
== EMIF_4D5
)
789 pwr_mgmt_ctrl
&= ~CS_TIM_MASK
;
791 pwr_mgmt_ctrl
|= lpmode
<< LP_MODE_SHIFT
;
793 return pwr_mgmt_ctrl
;
797 * Get the temperature level of the EMIF instance:
798 * Reads the MR4 register of attached SDRAM parts to find out the temperature
799 * level. If there are two parts attached(one on each CS), then the temperature
800 * level for the EMIF instance is the higher of the two temperatures.
802 static void get_temperature_level(struct emif_data
*emif
)
804 u32 temp
, temperature_level
;
809 /* Read mode register 4 */
810 writel(DDR_MR4
, base
+ EMIF_LPDDR2_MODE_REG_CONFIG
);
811 temperature_level
= readl(base
+ EMIF_LPDDR2_MODE_REG_DATA
);
812 temperature_level
= (temperature_level
& MR4_SDRAM_REF_RATE_MASK
) >>
813 MR4_SDRAM_REF_RATE_SHIFT
;
815 if (emif
->plat_data
->device_info
->cs1_used
) {
816 writel(DDR_MR4
| CS_MASK
, base
+ EMIF_LPDDR2_MODE_REG_CONFIG
);
817 temp
= readl(base
+ EMIF_LPDDR2_MODE_REG_DATA
);
818 temp
= (temp
& MR4_SDRAM_REF_RATE_MASK
)
819 >> MR4_SDRAM_REF_RATE_SHIFT
;
820 temperature_level
= max(temp
, temperature_level
);
823 /* treat everything less than nominal(3) in MR4 as nominal */
824 if (unlikely(temperature_level
< SDRAM_TEMP_NOMINAL
))
825 temperature_level
= SDRAM_TEMP_NOMINAL
;
827 /* if we get reserved value in MR4 persist with the existing value */
828 if (likely(temperature_level
!= SDRAM_TEMP_RESERVED_4
))
829 emif
->temperature_level
= temperature_level
;
833 * Program EMIF shadow registers that are not dependent on temperature
836 static void setup_registers(struct emif_data
*emif
, struct emif_regs
*regs
)
838 void __iomem
*base
= emif
->base
;
840 writel(regs
->sdram_tim2_shdw
, base
+ EMIF_SDRAM_TIMING_2_SHDW
);
841 writel(regs
->phy_ctrl_1_shdw
, base
+ EMIF_DDR_PHY_CTRL_1_SHDW
);
842 writel(regs
->pwr_mgmt_ctrl_shdw
,
843 base
+ EMIF_POWER_MANAGEMENT_CTRL_SHDW
);
845 /* Settings specific for EMIF4D5 */
846 if (emif
->plat_data
->ip_rev
!= EMIF_4D5
)
848 writel(regs
->ext_phy_ctrl_2_shdw
, base
+ EMIF_EXT_PHY_CTRL_2_SHDW
);
849 writel(regs
->ext_phy_ctrl_3_shdw
, base
+ EMIF_EXT_PHY_CTRL_3_SHDW
);
850 writel(regs
->ext_phy_ctrl_4_shdw
, base
+ EMIF_EXT_PHY_CTRL_4_SHDW
);
854 * When voltage ramps dll calibration and forced read idle should
857 static void setup_volt_sensitive_regs(struct emif_data
*emif
,
858 struct emif_regs
*regs
, u32 volt_state
)
861 void __iomem
*base
= emif
->base
;
864 * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
865 * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
866 * is an alias of the respective read_idle_ctrl_shdw_* (members of
867 * a union). So, the below code takes care of both cases
869 if (volt_state
== DDR_VOLTAGE_RAMPING
)
870 calib_ctrl
= regs
->dll_calib_ctrl_shdw_volt_ramp
;
872 calib_ctrl
= regs
->dll_calib_ctrl_shdw_normal
;
874 writel(calib_ctrl
, base
+ EMIF_DLL_CALIB_CTRL_SHDW
);
878 * setup_temperature_sensitive_regs() - set the timings for temperature
879 * sensitive registers. This happens once at initialisation time based
880 * on the temperature at boot time and subsequently based on the temperature
881 * alert interrupt. Temperature alert can happen when the temperature
882 * increases or drops. So this function can have the effect of either
883 * derating the timings or going back to nominal values.
885 static void setup_temperature_sensitive_regs(struct emif_data
*emif
,
886 struct emif_regs
*regs
)
888 u32 tim1
, tim3
, ref_ctrl
, type
;
889 void __iomem
*base
= emif
->base
;
892 type
= emif
->plat_data
->device_info
->type
;
894 tim1
= regs
->sdram_tim1_shdw
;
895 tim3
= regs
->sdram_tim3_shdw
;
896 ref_ctrl
= regs
->ref_ctrl_shdw
;
898 /* No de-rating for non-lpddr2 devices */
899 if (type
!= DDR_TYPE_LPDDR2_S2
&& type
!= DDR_TYPE_LPDDR2_S4
)
902 temperature
= emif
->temperature_level
;
903 if (temperature
== SDRAM_TEMP_HIGH_DERATE_REFRESH
) {
904 ref_ctrl
= regs
->ref_ctrl_shdw_derated
;
905 } else if (temperature
== SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS
) {
906 tim1
= regs
->sdram_tim1_shdw_derated
;
907 tim3
= regs
->sdram_tim3_shdw_derated
;
908 ref_ctrl
= regs
->ref_ctrl_shdw_derated
;
912 writel(tim1
, base
+ EMIF_SDRAM_TIMING_1_SHDW
);
913 writel(tim3
, base
+ EMIF_SDRAM_TIMING_3_SHDW
);
914 writel(ref_ctrl
, base
+ EMIF_SDRAM_REFRESH_CTRL_SHDW
);
917 static irqreturn_t
handle_temp_alert(void __iomem
*base
, struct emif_data
*emif
)
920 irqreturn_t ret
= IRQ_HANDLED
;
922 spin_lock_irqsave(&emif_lock
, irq_state
);
923 old_temp_level
= emif
->temperature_level
;
924 get_temperature_level(emif
);
926 if (unlikely(emif
->temperature_level
== old_temp_level
)) {
928 } else if (!emif
->curr_regs
) {
929 dev_err(emif
->dev
, "temperature alert before registers are calculated, not de-rating timings\n");
933 if (emif
->temperature_level
< old_temp_level
||
934 emif
->temperature_level
== SDRAM_TEMP_VERY_HIGH_SHUTDOWN
) {
936 * Temperature coming down - defer handling to thread OR
937 * Temperature far too high - do kernel_power_off() from
940 ret
= IRQ_WAKE_THREAD
;
942 /* Temperature is going up - handle immediately */
943 setup_temperature_sensitive_regs(emif
, emif
->curr_regs
);
948 spin_unlock_irqrestore(&emif_lock
, irq_state
);
952 static irqreturn_t
emif_interrupt_handler(int irq
, void *dev_id
)
955 struct emif_data
*emif
= dev_id
;
956 void __iomem
*base
= emif
->base
;
957 struct device
*dev
= emif
->dev
;
958 irqreturn_t ret
= IRQ_HANDLED
;
960 /* Save the status and clear it */
961 interrupts
= readl(base
+ EMIF_SYSTEM_OCP_INTERRUPT_STATUS
);
962 writel(interrupts
, base
+ EMIF_SYSTEM_OCP_INTERRUPT_STATUS
);
965 * Handle temperature alert
966 * Temperature alert should be same for all ports
967 * So, it's enough to process it only for one of the ports
969 if (interrupts
& TA_SYS_MASK
)
970 ret
= handle_temp_alert(base
, emif
);
972 if (interrupts
& ERR_SYS_MASK
)
973 dev_err(dev
, "Access error from SYS port - %x\n", interrupts
);
975 if (emif
->plat_data
->hw_caps
& EMIF_HW_CAPS_LL_INTERFACE
) {
976 /* Save the status and clear it */
977 interrupts
= readl(base
+ EMIF_LL_OCP_INTERRUPT_STATUS
);
978 writel(interrupts
, base
+ EMIF_LL_OCP_INTERRUPT_STATUS
);
980 if (interrupts
& ERR_LL_MASK
)
981 dev_err(dev
, "Access error from LL port - %x\n",
988 static irqreturn_t
emif_threaded_isr(int irq
, void *dev_id
)
990 struct emif_data
*emif
= dev_id
;
992 if (emif
->temperature_level
== SDRAM_TEMP_VERY_HIGH_SHUTDOWN
) {
993 dev_emerg(emif
->dev
, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
998 spin_lock_irqsave(&emif_lock
, irq_state
);
1000 if (emif
->curr_regs
) {
1001 setup_temperature_sensitive_regs(emif
, emif
->curr_regs
);
1004 dev_err(emif
->dev
, "temperature alert before registers are calculated, not de-rating timings\n");
1007 spin_unlock_irqrestore(&emif_lock
, irq_state
);
1012 static void clear_all_interrupts(struct emif_data
*emif
)
1014 void __iomem
*base
= emif
->base
;
1016 writel(readl(base
+ EMIF_SYSTEM_OCP_INTERRUPT_STATUS
),
1017 base
+ EMIF_SYSTEM_OCP_INTERRUPT_STATUS
);
1018 if (emif
->plat_data
->hw_caps
& EMIF_HW_CAPS_LL_INTERFACE
)
1019 writel(readl(base
+ EMIF_LL_OCP_INTERRUPT_STATUS
),
1020 base
+ EMIF_LL_OCP_INTERRUPT_STATUS
);
1023 static void disable_and_clear_all_interrupts(struct emif_data
*emif
)
1025 void __iomem
*base
= emif
->base
;
1027 /* Disable all interrupts */
1028 writel(readl(base
+ EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET
),
1029 base
+ EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR
);
1030 if (emif
->plat_data
->hw_caps
& EMIF_HW_CAPS_LL_INTERFACE
)
1031 writel(readl(base
+ EMIF_LL_OCP_INTERRUPT_ENABLE_SET
),
1032 base
+ EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR
);
1034 /* Clear all interrupts */
1035 clear_all_interrupts(emif
);
1038 static int __init_or_module
setup_interrupts(struct emif_data
*emif
, u32 irq
)
1040 u32 interrupts
, type
;
1041 void __iomem
*base
= emif
->base
;
1043 type
= emif
->plat_data
->device_info
->type
;
1045 clear_all_interrupts(emif
);
1047 /* Enable interrupts for SYS interface */
1048 interrupts
= EN_ERR_SYS_MASK
;
1049 if (type
== DDR_TYPE_LPDDR2_S2
|| type
== DDR_TYPE_LPDDR2_S4
)
1050 interrupts
|= EN_TA_SYS_MASK
;
1051 writel(interrupts
, base
+ EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET
);
1053 /* Enable interrupts for LL interface */
1054 if (emif
->plat_data
->hw_caps
& EMIF_HW_CAPS_LL_INTERFACE
) {
1055 /* TA need not be enabled for LL */
1056 interrupts
= EN_ERR_LL_MASK
;
1057 writel(interrupts
, base
+ EMIF_LL_OCP_INTERRUPT_ENABLE_SET
);
1060 /* setup IRQ handlers */
1061 return devm_request_threaded_irq(emif
->dev
, irq
,
1062 emif_interrupt_handler
,
1064 0, dev_name(emif
->dev
),
1069 static void __init_or_module
emif_onetime_settings(struct emif_data
*emif
)
1071 u32 pwr_mgmt_ctrl
, zq
, temp_alert_cfg
;
1072 void __iomem
*base
= emif
->base
;
1073 const struct lpddr2_addressing
*addressing
;
1074 const struct ddr_device_info
*device_info
;
1076 device_info
= emif
->plat_data
->device_info
;
1077 addressing
= get_addressing_table(device_info
);
1080 * Init power management settings
1081 * We don't know the frequency yet. Use a high frequency
1082 * value for a conservative timeout setting
1084 pwr_mgmt_ctrl
= get_pwr_mgmt_ctrl(1000000000, emif
,
1085 emif
->plat_data
->ip_rev
);
1086 emif
->lpmode
= (pwr_mgmt_ctrl
& LP_MODE_MASK
) >> LP_MODE_SHIFT
;
1087 writel(pwr_mgmt_ctrl
, base
+ EMIF_POWER_MANAGEMENT_CONTROL
);
1089 /* Init ZQ calibration settings */
1090 zq
= get_zq_config_reg(addressing
, device_info
->cs1_used
,
1091 device_info
->cal_resistors_per_cs
);
1092 writel(zq
, base
+ EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG
);
1094 /* Check temperature level temperature level*/
1095 get_temperature_level(emif
);
1096 if (emif
->temperature_level
== SDRAM_TEMP_VERY_HIGH_SHUTDOWN
)
1097 dev_emerg(emif
->dev
, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1099 /* Init temperature polling */
1100 temp_alert_cfg
= get_temp_alert_config(addressing
,
1101 emif
->plat_data
->custom_configs
, device_info
->cs1_used
,
1102 device_info
->io_width
, get_emif_bus_width(emif
));
1103 writel(temp_alert_cfg
, base
+ EMIF_TEMPERATURE_ALERT_CONFIG
);
1106 * Program external PHY control registers that are not frequency
1109 if (emif
->plat_data
->phy_type
!= EMIF_PHY_TYPE_INTELLIPHY
)
1111 writel(EMIF_EXT_PHY_CTRL_1_VAL
, base
+ EMIF_EXT_PHY_CTRL_1_SHDW
);
1112 writel(EMIF_EXT_PHY_CTRL_5_VAL
, base
+ EMIF_EXT_PHY_CTRL_5_SHDW
);
1113 writel(EMIF_EXT_PHY_CTRL_6_VAL
, base
+ EMIF_EXT_PHY_CTRL_6_SHDW
);
1114 writel(EMIF_EXT_PHY_CTRL_7_VAL
, base
+ EMIF_EXT_PHY_CTRL_7_SHDW
);
1115 writel(EMIF_EXT_PHY_CTRL_8_VAL
, base
+ EMIF_EXT_PHY_CTRL_8_SHDW
);
1116 writel(EMIF_EXT_PHY_CTRL_9_VAL
, base
+ EMIF_EXT_PHY_CTRL_9_SHDW
);
1117 writel(EMIF_EXT_PHY_CTRL_10_VAL
, base
+ EMIF_EXT_PHY_CTRL_10_SHDW
);
1118 writel(EMIF_EXT_PHY_CTRL_11_VAL
, base
+ EMIF_EXT_PHY_CTRL_11_SHDW
);
1119 writel(EMIF_EXT_PHY_CTRL_12_VAL
, base
+ EMIF_EXT_PHY_CTRL_12_SHDW
);
1120 writel(EMIF_EXT_PHY_CTRL_13_VAL
, base
+ EMIF_EXT_PHY_CTRL_13_SHDW
);
1121 writel(EMIF_EXT_PHY_CTRL_14_VAL
, base
+ EMIF_EXT_PHY_CTRL_14_SHDW
);
1122 writel(EMIF_EXT_PHY_CTRL_15_VAL
, base
+ EMIF_EXT_PHY_CTRL_15_SHDW
);
1123 writel(EMIF_EXT_PHY_CTRL_16_VAL
, base
+ EMIF_EXT_PHY_CTRL_16_SHDW
);
1124 writel(EMIF_EXT_PHY_CTRL_17_VAL
, base
+ EMIF_EXT_PHY_CTRL_17_SHDW
);
1125 writel(EMIF_EXT_PHY_CTRL_18_VAL
, base
+ EMIF_EXT_PHY_CTRL_18_SHDW
);
1126 writel(EMIF_EXT_PHY_CTRL_19_VAL
, base
+ EMIF_EXT_PHY_CTRL_19_SHDW
);
1127 writel(EMIF_EXT_PHY_CTRL_20_VAL
, base
+ EMIF_EXT_PHY_CTRL_20_SHDW
);
1128 writel(EMIF_EXT_PHY_CTRL_21_VAL
, base
+ EMIF_EXT_PHY_CTRL_21_SHDW
);
1129 writel(EMIF_EXT_PHY_CTRL_22_VAL
, base
+ EMIF_EXT_PHY_CTRL_22_SHDW
);
1130 writel(EMIF_EXT_PHY_CTRL_23_VAL
, base
+ EMIF_EXT_PHY_CTRL_23_SHDW
);
1131 writel(EMIF_EXT_PHY_CTRL_24_VAL
, base
+ EMIF_EXT_PHY_CTRL_24_SHDW
);
1134 static void get_default_timings(struct emif_data
*emif
)
1136 struct emif_platform_data
*pd
= emif
->plat_data
;
1138 pd
->timings
= lpddr2_jedec_timings
;
1139 pd
->timings_arr_size
= ARRAY_SIZE(lpddr2_jedec_timings
);
1141 dev_warn(emif
->dev
, "%s: using default timings\n", __func__
);
1144 static int is_dev_data_valid(u32 type
, u32 density
, u32 io_width
, u32 phy_type
,
1145 u32 ip_rev
, struct device
*dev
)
1149 valid
= (type
== DDR_TYPE_LPDDR2_S4
||
1150 type
== DDR_TYPE_LPDDR2_S2
)
1151 && (density
>= DDR_DENSITY_64Mb
1152 && density
<= DDR_DENSITY_8Gb
)
1153 && (io_width
>= DDR_IO_WIDTH_8
1154 && io_width
<= DDR_IO_WIDTH_32
);
1156 /* Combinations of EMIF and PHY revisions that we support today */
1159 valid
= valid
&& (phy_type
== EMIF_PHY_TYPE_ATTILAPHY
);
1162 valid
= valid
&& (phy_type
== EMIF_PHY_TYPE_INTELLIPHY
);
1169 dev_err(dev
, "%s: invalid DDR details\n", __func__
);
1173 static int is_custom_config_valid(struct emif_custom_configs
*cust_cfgs
,
1178 if ((cust_cfgs
->mask
& EMIF_CUSTOM_CONFIG_LPMODE
) &&
1179 (cust_cfgs
->lpmode
!= EMIF_LP_MODE_DISABLE
))
1180 valid
= cust_cfgs
->lpmode_freq_threshold
&&
1181 cust_cfgs
->lpmode_timeout_performance
&&
1182 cust_cfgs
->lpmode_timeout_power
;
1184 if (cust_cfgs
->mask
& EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL
)
1185 valid
= valid
&& cust_cfgs
->temp_alert_poll_interval_ms
;
1188 dev_warn(dev
, "%s: invalid custom configs\n", __func__
);
1193 #if defined(CONFIG_OF)
1194 static void __init_or_module
of_get_custom_configs(struct device_node
*np_emif
,
1195 struct emif_data
*emif
)
1197 struct emif_custom_configs
*cust_cfgs
= NULL
;
1199 const int *lpmode
, *poll_intvl
;
1201 lpmode
= of_get_property(np_emif
, "low-power-mode", &len
);
1202 poll_intvl
= of_get_property(np_emif
, "temp-alert-poll-interval", &len
);
1204 if (lpmode
|| poll_intvl
)
1205 cust_cfgs
= devm_kzalloc(emif
->dev
, sizeof(*cust_cfgs
),
1212 cust_cfgs
->mask
|= EMIF_CUSTOM_CONFIG_LPMODE
;
1213 cust_cfgs
->lpmode
= *lpmode
;
1214 of_property_read_u32(np_emif
,
1215 "low-power-mode-timeout-performance",
1216 &cust_cfgs
->lpmode_timeout_performance
);
1217 of_property_read_u32(np_emif
,
1218 "low-power-mode-timeout-power",
1219 &cust_cfgs
->lpmode_timeout_power
);
1220 of_property_read_u32(np_emif
,
1221 "low-power-mode-freq-threshold",
1222 &cust_cfgs
->lpmode_freq_threshold
);
1227 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL
;
1228 cust_cfgs
->temp_alert_poll_interval_ms
= *poll_intvl
;
1231 if (!is_custom_config_valid(cust_cfgs
, emif
->dev
)) {
1232 devm_kfree(emif
->dev
, cust_cfgs
);
1236 emif
->plat_data
->custom_configs
= cust_cfgs
;
1239 static void __init_or_module
of_get_ddr_info(struct device_node
*np_emif
,
1240 struct device_node
*np_ddr
,
1241 struct ddr_device_info
*dev_info
)
1243 u32 density
= 0, io_width
= 0;
1246 if (of_find_property(np_emif
, "cs1-used", &len
))
1247 dev_info
->cs1_used
= true;
1249 if (of_find_property(np_emif
, "cal-resistor-per-cs", &len
))
1250 dev_info
->cal_resistors_per_cs
= true;
1252 if (of_device_is_compatible(np_ddr
, "jedec,lpddr2-s4"))
1253 dev_info
->type
= DDR_TYPE_LPDDR2_S4
;
1254 else if (of_device_is_compatible(np_ddr
, "jedec,lpddr2-s2"))
1255 dev_info
->type
= DDR_TYPE_LPDDR2_S2
;
1257 of_property_read_u32(np_ddr
, "density", &density
);
1258 of_property_read_u32(np_ddr
, "io-width", &io_width
);
1260 /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1261 if (density
& (density
- 1))
1262 dev_info
->density
= 0;
1264 dev_info
->density
= __fls(density
) - 5;
1266 /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1267 if (io_width
& (io_width
- 1))
1268 dev_info
->io_width
= 0;
1270 dev_info
->io_width
= __fls(io_width
) - 1;
1273 static struct emif_data
* __init_or_module
of_get_memory_device_details(
1274 struct device_node
*np_emif
, struct device
*dev
)
1276 struct emif_data
*emif
= NULL
;
1277 struct ddr_device_info
*dev_info
= NULL
;
1278 struct emif_platform_data
*pd
= NULL
;
1279 struct device_node
*np_ddr
;
1282 np_ddr
= of_parse_phandle(np_emif
, "device-handle", 0);
1285 emif
= devm_kzalloc(dev
, sizeof(struct emif_data
), GFP_KERNEL
);
1286 pd
= devm_kzalloc(dev
, sizeof(*pd
), GFP_KERNEL
);
1287 dev_info
= devm_kzalloc(dev
, sizeof(*dev_info
), GFP_KERNEL
);
1289 if (!emif
|| !pd
|| !dev_info
) {
1290 dev_err(dev
, "%s: Out of memory!!\n",
1295 emif
->plat_data
= pd
;
1296 pd
->device_info
= dev_info
;
1298 emif
->np_ddr
= np_ddr
;
1299 emif
->temperature_level
= SDRAM_TEMP_NOMINAL
;
1301 if (of_device_is_compatible(np_emif
, "ti,emif-4d"))
1302 emif
->plat_data
->ip_rev
= EMIF_4D
;
1303 else if (of_device_is_compatible(np_emif
, "ti,emif-4d5"))
1304 emif
->plat_data
->ip_rev
= EMIF_4D5
;
1306 of_property_read_u32(np_emif
, "phy-type", &pd
->phy_type
);
1308 if (of_find_property(np_emif
, "hw-caps-ll-interface", &len
))
1309 pd
->hw_caps
|= EMIF_HW_CAPS_LL_INTERFACE
;
1311 of_get_ddr_info(np_emif
, np_ddr
, dev_info
);
1312 if (!is_dev_data_valid(pd
->device_info
->type
, pd
->device_info
->density
,
1313 pd
->device_info
->io_width
, pd
->phy_type
, pd
->ip_rev
,
1315 dev_err(dev
, "%s: invalid device data!!\n", __func__
);
1319 * For EMIF instances other than EMIF1 see if the devices connected
1320 * are exactly same as on EMIF1(which is typically the case). If so,
1321 * mark it as a duplicate of EMIF1. This will save some memory and
1324 if (emif1
&& emif1
->np_ddr
== np_ddr
) {
1325 emif
->duplicate
= true;
1328 dev_warn(emif
->dev
, "%s: Non-symmetric DDR geometry\n",
1332 of_get_custom_configs(np_emif
, emif
);
1333 emif
->plat_data
->timings
= of_get_ddr_timings(np_ddr
, emif
->dev
,
1334 emif
->plat_data
->device_info
->type
,
1335 &emif
->plat_data
->timings_arr_size
);
1337 emif
->plat_data
->min_tck
= of_get_min_tck(np_ddr
, emif
->dev
);
1348 static struct emif_data
* __init_or_module
of_get_memory_device_details(
1349 struct device_node
*np_emif
, struct device
*dev
)
1355 static struct emif_data
*__init_or_module
get_device_details(
1356 struct platform_device
*pdev
)
1359 struct emif_data
*emif
= NULL
;
1360 struct ddr_device_info
*dev_info
;
1361 struct emif_custom_configs
*cust_cfgs
;
1362 struct emif_platform_data
*pd
;
1366 pd
= pdev
->dev
.platform_data
;
1369 if (!(pd
&& pd
->device_info
&& is_dev_data_valid(pd
->device_info
->type
,
1370 pd
->device_info
->density
, pd
->device_info
->io_width
,
1371 pd
->phy_type
, pd
->ip_rev
, dev
))) {
1372 dev_err(dev
, "%s: invalid device data\n", __func__
);
1376 emif
= devm_kzalloc(dev
, sizeof(*emif
), GFP_KERNEL
);
1377 temp
= devm_kzalloc(dev
, sizeof(*pd
), GFP_KERNEL
);
1378 dev_info
= devm_kzalloc(dev
, sizeof(*dev_info
), GFP_KERNEL
);
1380 if (!emif
|| !pd
|| !dev_info
) {
1381 dev_err(dev
, "%s:%d: allocation error\n", __func__
, __LINE__
);
1385 memcpy(temp
, pd
, sizeof(*pd
));
1387 memcpy(dev_info
, pd
->device_info
, sizeof(*dev_info
));
1389 pd
->device_info
= dev_info
;
1390 emif
->plat_data
= pd
;
1392 emif
->temperature_level
= SDRAM_TEMP_NOMINAL
;
1395 * For EMIF instances other than EMIF1 see if the devices connected
1396 * are exactly same as on EMIF1(which is typically the case). If so,
1397 * mark it as a duplicate of EMIF1 and skip copying timings data.
1398 * This will save some memory and some computation later.
1400 emif
->duplicate
= emif1
&& (memcmp(dev_info
,
1401 emif1
->plat_data
->device_info
,
1402 sizeof(struct ddr_device_info
)) == 0);
1404 if (emif
->duplicate
) {
1409 dev_warn(emif
->dev
, "%s: Non-symmetric DDR geometry\n",
1414 * Copy custom configs - ignore allocation error, if any, as
1415 * custom_configs is not very critical
1417 cust_cfgs
= pd
->custom_configs
;
1418 if (cust_cfgs
&& is_custom_config_valid(cust_cfgs
, dev
)) {
1419 temp
= devm_kzalloc(dev
, sizeof(*cust_cfgs
), GFP_KERNEL
);
1421 memcpy(temp
, cust_cfgs
, sizeof(*cust_cfgs
));
1423 dev_warn(dev
, "%s:%d: allocation error\n", __func__
,
1425 pd
->custom_configs
= temp
;
1429 * Copy timings and min-tck values from platform data. If it is not
1430 * available or if memory allocation fails, use JEDEC defaults
1432 size
= sizeof(struct lpddr2_timings
) * pd
->timings_arr_size
;
1434 temp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
1436 memcpy(temp
, pd
->timings
, sizeof(*pd
->timings
));
1439 dev_warn(dev
, "%s:%d: allocation error\n", __func__
,
1441 get_default_timings(emif
);
1444 get_default_timings(emif
);
1448 temp
= devm_kzalloc(dev
, sizeof(*pd
->min_tck
), GFP_KERNEL
);
1450 memcpy(temp
, pd
->min_tck
, sizeof(*pd
->min_tck
));
1453 dev_warn(dev
, "%s:%d: allocation error\n", __func__
,
1455 pd
->min_tck
= &lpddr2_jedec_min_tck
;
1458 pd
->min_tck
= &lpddr2_jedec_min_tck
;
1468 static int __init_or_module
emif_probe(struct platform_device
*pdev
)
1470 struct emif_data
*emif
;
1471 struct resource
*res
;
1474 if (pdev
->dev
.of_node
)
1475 emif
= of_get_memory_device_details(pdev
->dev
.of_node
, &pdev
->dev
);
1477 emif
= get_device_details(pdev
);
1480 pr_err("%s: error getting device data\n", __func__
);
1484 list_add(&emif
->node
, &device_list
);
1485 emif
->addressing
= get_addressing_table(emif
->plat_data
->device_info
);
1487 /* Save pointers to each other in emif and device structures */
1488 emif
->dev
= &pdev
->dev
;
1489 platform_set_drvdata(pdev
, emif
);
1491 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1493 dev_err(emif
->dev
, "%s: error getting memory resource\n",
1498 emif
->base
= devm_ioremap_resource(emif
->dev
, res
);
1499 if (IS_ERR(emif
->base
))
1502 irq
= platform_get_irq(pdev
, 0);
1504 dev_err(emif
->dev
, "%s: error getting IRQ resource - %d\n",
1509 emif_onetime_settings(emif
);
1510 emif_debugfs_init(emif
);
1511 disable_and_clear_all_interrupts(emif
);
1512 setup_interrupts(emif
, irq
);
1514 /* One-time actions taken on probing the first device */
1517 spin_lock_init(&emif_lock
);
1520 * TODO: register notifiers for frequency and voltage
1521 * change here once the respective frameworks are
1526 dev_info(&pdev
->dev
, "%s: device configured with addr = %p and IRQ%d\n",
1527 __func__
, emif
->base
, irq
);
1534 static int __exit
emif_remove(struct platform_device
*pdev
)
1536 struct emif_data
*emif
= platform_get_drvdata(pdev
);
1538 emif_debugfs_exit(emif
);
1543 static void emif_shutdown(struct platform_device
*pdev
)
1545 struct emif_data
*emif
= platform_get_drvdata(pdev
);
1547 disable_and_clear_all_interrupts(emif
);
1550 static int get_emif_reg_values(struct emif_data
*emif
, u32 freq
,
1551 struct emif_regs
*regs
)
1553 u32 cs1_used
, ip_rev
, phy_type
;
1555 const struct lpddr2_timings
*timings
;
1556 const struct lpddr2_min_tck
*min_tck
;
1557 const struct ddr_device_info
*device_info
;
1558 const struct lpddr2_addressing
*addressing
;
1559 struct emif_data
*emif_for_calc
;
1561 const struct emif_custom_configs
*custom_configs
;
1565 * If the devices on this EMIF instance is duplicate of EMIF1,
1566 * use EMIF1 details for the calculation
1568 emif_for_calc
= emif
->duplicate
? emif1
: emif
;
1569 timings
= get_timings_table(emif_for_calc
, freq
);
1570 addressing
= emif_for_calc
->addressing
;
1571 if (!timings
|| !addressing
) {
1572 dev_err(dev
, "%s: not enough data available for %dHz",
1577 device_info
= emif_for_calc
->plat_data
->device_info
;
1578 type
= device_info
->type
;
1579 cs1_used
= device_info
->cs1_used
;
1580 ip_rev
= emif_for_calc
->plat_data
->ip_rev
;
1581 phy_type
= emif_for_calc
->plat_data
->phy_type
;
1583 min_tck
= emif_for_calc
->plat_data
->min_tck
;
1584 custom_configs
= emif_for_calc
->plat_data
->custom_configs
;
1586 set_ddr_clk_period(freq
);
1588 regs
->ref_ctrl_shdw
= get_sdram_ref_ctrl_shdw(freq
, addressing
);
1589 regs
->sdram_tim1_shdw
= get_sdram_tim_1_shdw(timings
, min_tck
,
1591 regs
->sdram_tim2_shdw
= get_sdram_tim_2_shdw(timings
, min_tck
,
1593 regs
->sdram_tim3_shdw
= get_sdram_tim_3_shdw(timings
, min_tck
,
1594 addressing
, type
, ip_rev
, EMIF_NORMAL_TIMINGS
);
1598 if (phy_type
== EMIF_PHY_TYPE_ATTILAPHY
&& ip_rev
== EMIF_4D
) {
1599 regs
->phy_ctrl_1_shdw
= get_ddr_phy_ctrl_1_attilaphy_4d(
1601 } else if (phy_type
== EMIF_PHY_TYPE_INTELLIPHY
&& ip_rev
== EMIF_4D5
) {
1602 regs
->phy_ctrl_1_shdw
= get_phy_ctrl_1_intelliphy_4d5(freq
, cl
);
1603 regs
->ext_phy_ctrl_2_shdw
= get_ext_phy_ctrl_2_intelliphy_4d5();
1604 regs
->ext_phy_ctrl_3_shdw
= get_ext_phy_ctrl_3_intelliphy_4d5();
1605 regs
->ext_phy_ctrl_4_shdw
= get_ext_phy_ctrl_4_intelliphy_4d5();
1610 /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1611 regs
->pwr_mgmt_ctrl_shdw
=
1612 get_pwr_mgmt_ctrl(freq
, emif_for_calc
, ip_rev
) &
1613 (CS_TIM_MASK
| SR_TIM_MASK
| PD_TIM_MASK
);
1615 if (ip_rev
& EMIF_4D
) {
1616 regs
->read_idle_ctrl_shdw_normal
=
1617 get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE
);
1619 regs
->read_idle_ctrl_shdw_volt_ramp
=
1620 get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING
);
1621 } else if (ip_rev
& EMIF_4D5
) {
1622 regs
->dll_calib_ctrl_shdw_normal
=
1623 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE
);
1625 regs
->dll_calib_ctrl_shdw_volt_ramp
=
1626 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING
);
1629 if (type
== DDR_TYPE_LPDDR2_S2
|| type
== DDR_TYPE_LPDDR2_S4
) {
1630 regs
->ref_ctrl_shdw_derated
= get_sdram_ref_ctrl_shdw(freq
/ 4,
1633 regs
->sdram_tim1_shdw_derated
=
1634 get_sdram_tim_1_shdw_derated(timings
, min_tck
,
1637 regs
->sdram_tim3_shdw_derated
= get_sdram_tim_3_shdw(timings
,
1638 min_tck
, addressing
, type
, ip_rev
,
1639 EMIF_DERATED_TIMINGS
);
1648 * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1649 * given frequency(freq):
1651 * As an optimisation, every EMIF instance other than EMIF1 shares the
1652 * register cache with EMIF1 if the devices connected on this instance
1653 * are same as that on EMIF1(indicated by the duplicate flag)
1655 * If we do not have an entry corresponding to the frequency given, we
1656 * allocate a new entry and calculate the values
1658 * Upon finding the right reg dump, save it in curr_regs. It can be
1659 * directly used for thermal de-rating and voltage ramping changes.
1661 static struct emif_regs
*get_regs(struct emif_data
*emif
, u32 freq
)
1664 struct emif_regs
**regs_cache
;
1665 struct emif_regs
*regs
= NULL
;
1669 if (emif
->curr_regs
&& emif
->curr_regs
->freq
== freq
) {
1670 dev_dbg(dev
, "%s: using curr_regs - %u Hz", __func__
, freq
);
1671 return emif
->curr_regs
;
1674 if (emif
->duplicate
)
1675 regs_cache
= emif1
->regs_cache
;
1677 regs_cache
= emif
->regs_cache
;
1679 for (i
= 0; i
< EMIF_MAX_NUM_FREQUENCIES
&& regs_cache
[i
]; i
++) {
1680 if (regs_cache
[i
]->freq
== freq
) {
1681 regs
= regs_cache
[i
];
1683 "%s: reg dump found in reg cache for %u Hz\n",
1690 * If we don't have an entry for this frequency in the cache create one
1691 * and calculate the values
1694 regs
= devm_kzalloc(emif
->dev
, sizeof(*regs
), GFP_ATOMIC
);
1698 if (get_emif_reg_values(emif
, freq
, regs
)) {
1699 devm_kfree(emif
->dev
, regs
);
1704 * Now look for an un-used entry in the cache and save the
1705 * newly created struct. If there are no free entries
1706 * over-write the last entry
1708 for (i
= 0; i
< EMIF_MAX_NUM_FREQUENCIES
&& regs_cache
[i
]; i
++)
1711 if (i
>= EMIF_MAX_NUM_FREQUENCIES
) {
1712 dev_warn(dev
, "%s: regs_cache full - reusing a slot!!\n",
1714 i
= EMIF_MAX_NUM_FREQUENCIES
- 1;
1715 devm_kfree(emif
->dev
, regs_cache
[i
]);
1717 regs_cache
[i
] = regs
;
1723 static void do_volt_notify_handling(struct emif_data
*emif
, u32 volt_state
)
1725 dev_dbg(emif
->dev
, "%s: voltage notification : %d", __func__
,
1728 if (!emif
->curr_regs
) {
1730 "%s: volt-notify before registers are ready: %d\n",
1731 __func__
, volt_state
);
1735 setup_volt_sensitive_regs(emif
, emif
->curr_regs
, volt_state
);
1739 * TODO: voltage notify handling should be hooked up to
1740 * regulator framework as soon as the necessary support
1741 * is available in mainline kernel. This function is un-used
1744 static void __attribute__((unused
)) volt_notify_handling(u32 volt_state
)
1746 struct emif_data
*emif
;
1748 spin_lock_irqsave(&emif_lock
, irq_state
);
1750 list_for_each_entry(emif
, &device_list
, node
)
1751 do_volt_notify_handling(emif
, volt_state
);
1754 spin_unlock_irqrestore(&emif_lock
, irq_state
);
1757 static void do_freq_pre_notify_handling(struct emif_data
*emif
, u32 new_freq
)
1759 struct emif_regs
*regs
;
1761 regs
= get_regs(emif
, new_freq
);
1765 emif
->curr_regs
= regs
;
1768 * Update the shadow registers:
1769 * Temperature and voltage-ramp sensitive settings are also configured
1770 * in terms of DDR cycles. So, we need to update them too when there
1773 dev_dbg(emif
->dev
, "%s: setting up shadow registers for %uHz",
1774 __func__
, new_freq
);
1775 setup_registers(emif
, regs
);
1776 setup_temperature_sensitive_regs(emif
, regs
);
1777 setup_volt_sensitive_regs(emif
, regs
, DDR_VOLTAGE_STABLE
);
1780 * Part of workaround for errata i728. See do_freq_update()
1783 if (emif
->lpmode
== EMIF_LP_MODE_SELF_REFRESH
)
1784 set_lpmode(emif
, EMIF_LP_MODE_DISABLE
);
1788 * TODO: frequency notify handling should be hooked up to
1789 * clock framework as soon as the necessary support is
1790 * available in mainline kernel. This function is un-used
1793 static void __attribute__((unused
)) freq_pre_notify_handling(u32 new_freq
)
1795 struct emif_data
*emif
;
1798 * NOTE: we are taking the spin-lock here and releases it
1799 * only in post-notifier. This doesn't look good and
1800 * Sparse complains about it, but this seems to be
1801 * un-avoidable. We need to lock a sequence of events
1802 * that is split between EMIF and clock framework.
1804 * 1. EMIF driver updates EMIF timings in shadow registers in the
1805 * frequency pre-notify callback from clock framework
1806 * 2. clock framework sets up the registers for the new frequency
1807 * 3. clock framework initiates a hw-sequence that updates
1808 * the frequency EMIF timings synchronously.
1810 * All these 3 steps should be performed as an atomic operation
1811 * vis-a-vis similar sequence in the EMIF interrupt handler
1812 * for temperature events. Otherwise, there could be race
1813 * conditions that could result in incorrect EMIF timings for
1816 spin_lock_irqsave(&emif_lock
, irq_state
);
1818 list_for_each_entry(emif
, &device_list
, node
)
1819 do_freq_pre_notify_handling(emif
, new_freq
);
1822 static void do_freq_post_notify_handling(struct emif_data
*emif
)
1825 * Part of workaround for errata i728. See do_freq_update()
1828 if (emif
->lpmode
== EMIF_LP_MODE_SELF_REFRESH
)
1829 set_lpmode(emif
, EMIF_LP_MODE_SELF_REFRESH
);
1833 * TODO: frequency notify handling should be hooked up to
1834 * clock framework as soon as the necessary support is
1835 * available in mainline kernel. This function is un-used
1838 static void __attribute__((unused
)) freq_post_notify_handling(void)
1840 struct emif_data
*emif
;
1842 list_for_each_entry(emif
, &device_list
, node
)
1843 do_freq_post_notify_handling(emif
);
1846 * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1849 spin_unlock_irqrestore(&emif_lock
, irq_state
);
1852 #if defined(CONFIG_OF)
1853 static const struct of_device_id emif_of_match
[] = {
1854 { .compatible
= "ti,emif-4d" },
1855 { .compatible
= "ti,emif-4d5" },
1858 MODULE_DEVICE_TABLE(of
, emif_of_match
);
1861 static struct platform_driver emif_driver
= {
1862 .remove
= __exit_p(emif_remove
),
1863 .shutdown
= emif_shutdown
,
1866 .of_match_table
= of_match_ptr(emif_of_match
),
1870 module_platform_driver_probe(emif_driver
, emif_probe
);
1872 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1873 MODULE_LICENSE("GPL");
1874 MODULE_ALIAS("platform:emif");
1875 MODULE_AUTHOR("Texas Instruments Inc");