drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_mtd.h>
  29 #include <linux/of_device.h>
  30 #include <linux/omap-gpmc.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/platform_data/mtd-nand-omap2.h>
  35 #include <linux/platform_data/mtd-onenand-omap2.h>
  36
  37 #include <asm/mach-types.h>
  38
  39 #define DEVICE_NAME             "omap-gpmc"
  40
  41 /* GPMC register offsets */
  42 #define GPMC_REVISION           0x00
  43 #define GPMC_SYSCONFIG          0x10
  44 #define GPMC_SYSSTATUS          0x14
  45 #define GPMC_IRQSTATUS          0x18
  46 #define GPMC_IRQENABLE          0x1c
  47 #define GPMC_TIMEOUT_CONTROL    0x40
  48 #define GPMC_ERR_ADDRESS        0x44
  49 #define GPMC_ERR_TYPE           0x48
  50 #define GPMC_CONFIG             0x50
  51 #define GPMC_STATUS             0x54
  52 #define GPMC_PREFETCH_CONFIG1   0x1e0
  53 #define GPMC_PREFETCH_CONFIG2   0x1e4
  54 #define GPMC_PREFETCH_CONTROL   0x1ec
  55 #define GPMC_PREFETCH_STATUS    0x1f0
  56 #define GPMC_ECC_CONFIG         0x1f4
  57 #define GPMC_ECC_CONTROL        0x1f8
  58 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  59 #define GPMC_ECC1_RESULT        0x200
  60 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  67
  68 /* GPMC ECC control settings */
  69 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  70 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  71 #define GPMC_ECC_CTRL_ECCREG1           0x001
  72 #define GPMC_ECC_CTRL_ECCREG2           0x002
  73 #define GPMC_ECC_CTRL_ECCREG3           0x003
  74 #define GPMC_ECC_CTRL_ECCREG4           0x004
  75 #define GPMC_ECC_CTRL_ECCREG5           0x005
  76 #define GPMC_ECC_CTRL_ECCREG6           0x006
  77 #define GPMC_ECC_CTRL_ECCREG7           0x007
  78 #define GPMC_ECC_CTRL_ECCREG8           0x008
  79 #define GPMC_ECC_CTRL_ECCREG9           0x009
  80
  81 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  82
  83 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  84 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  85 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  86 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  89
  90 #define GPMC_CS0_OFFSET         0x60
  91 #define GPMC_CS_SIZE            0x30
  92 #define GPMC_BCH_SIZE           0x10
  93
  94 #define GPMC_MEM_END            0x3FFFFFFF
  95
  96 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  97 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  98
  99 #define CS_NUM_SHIFT            24
 100 #define ENABLE_PREFETCH         (0x1 << 7)
 101 #define DMA_MPU_MODE            2
 102
 103 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 104 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 105
 106 #define GPMC_HAS_WR_ACCESS              0x1
 107 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 108 #define GPMC_HAS_MUX_AAD                0x4
 109
 110 #define GPMC_NR_WAITPINS                4
 111
 112 #define GPMC_CS_CONFIG1         0x00
 113 #define GPMC_CS_CONFIG2         0x04
 114 #define GPMC_CS_CONFIG3         0x08
 115 #define GPMC_CS_CONFIG4         0x0c
 116 #define GPMC_CS_CONFIG5         0x10
 117 #define GPMC_CS_CONFIG6         0x14
 118 #define GPMC_CS_CONFIG7         0x18
 119 #define GPMC_CS_NAND_COMMAND    0x1c
 120 #define GPMC_CS_NAND_ADDRESS    0x20
 121 #define GPMC_CS_NAND_DATA       0x24
 122
 123 /* Control Commands */
 124 #define GPMC_CONFIG_RDY_BSY     0x00000001
 125 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 126 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 127 #define GPMC_SET_IRQ_STATUS     0x00000004
 128
 129 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 130 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 131 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 132 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 133 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 134 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 135 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 136 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 137 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 138 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 139 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 140 #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
 141 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 142 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 143 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 144 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 145 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 146 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 147 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 148 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 149 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 150 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 151 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 152 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 153
 154 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 155 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 156 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 157 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 158 /* All CONFIG7 bits except reserved bits */
 159 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 160                                          GPMC_CONFIG7_CSVALID_MASK |     \
 161                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 162
 163 #define GPMC_DEVICETYPE_NOR             0
 164 #define GPMC_DEVICETYPE_NAND            2
 165 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 166 #define WR_RD_PIN_MONITORING            0x00600000
 167
 168 #define GPMC_ENABLE_IRQ         0x0000000d
 169
 170 /* ECC commands */
 171 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 172 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 173 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 174
 175 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 176  */
 177 #define GPMC_NR_IRQ             2
 178
 179 struct gpmc_cs_data {
 180         const char *name;
 181
 182 #define GPMC_CS_RESERVED        (1 << 0)
 183         u32 flags;
 184
 185         struct resource mem;
 186 };
 187
 188 struct gpmc_client_irq  {
 189         unsigned                irq;
 190         u32                     bitmask;
 191 };
 192
 193 /* Structure to save gpmc cs context */
 194 struct gpmc_cs_config {
 195         u32 config1;
 196         u32 config2;
 197         u32 config3;
 198         u32 config4;
 199         u32 config5;
 200         u32 config6;
 201         u32 config7;
 202         int is_valid;
 203 };
 204
 205 /*
 206  * Structure to save/restore gpmc context
 207  * to support core off on OMAP3
 208  */
 209 struct omap3_gpmc_regs {
 210         u32 sysconfig;
 211         u32 irqenable;
 212         u32 timeout_ctrl;
 213         u32 config;
 214         u32 prefetch_config1;
 215         u32 prefetch_config2;
 216         u32 prefetch_control;
 217         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 218 };
 219
 220 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 221 static struct irq_chip gpmc_irq_chip;
 222 static int gpmc_irq_start;
 223
 224 static struct resource  gpmc_mem_root;
 225 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 226 static DEFINE_SPINLOCK(gpmc_mem_lock);
 227 /* Define chip-selects as reserved by default until probe completes */
 228 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 229 static unsigned int gpmc_nr_waitpins;
 230 static struct device *gpmc_dev;
 231 static int gpmc_irq;
 232 static resource_size_t phys_base, mem_size;
 233 static unsigned gpmc_capability;
 234 static void __iomem *gpmc_base;
 235
 236 static struct clk *gpmc_l3_clk;
 237
 238 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 239
 240 static void gpmc_write_reg(int idx, u32 val)
 241 {
 242         writel_relaxed(val, gpmc_base + idx);
 243 }
 244
 245 static u32 gpmc_read_reg(int idx)
 246 {
 247         return readl_relaxed(gpmc_base + idx);
 248 }
 249
 250 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 251 {
 252         void __iomem *reg_addr;
 253
 254         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 255         writel_relaxed(val, reg_addr);
 256 }
 257
 258 static u32 gpmc_cs_read_reg(int cs, int idx)
 259 {
 260         void __iomem *reg_addr;
 261
 262         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 263         return readl_relaxed(reg_addr);
 264 }
 265
 266 /* TODO: Add support for gpmc_fck to clock framework and use it */
 267 static unsigned long gpmc_get_fclk_period(void)
 268 {
 269         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 270
 271         rate /= 1000;
 272         rate = 1000000000 / rate;       /* In picoseconds */
 273
 274         return rate;
 275 }
 276
 277 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 278 {
 279         unsigned long tick_ps;
 280
 281         /* Calculate in picosecs to yield more exact results */
 282         tick_ps = gpmc_get_fclk_period();
 283
 284         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 285 }
 286
 287 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 288 {
 289         unsigned long tick_ps;
 290
 291         /* Calculate in picosecs to yield more exact results */
 292         tick_ps = gpmc_get_fclk_period();
 293
 294         return (time_ps + tick_ps - 1) / tick_ps;
 295 }
 296
 297 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 298 {
 299         return ticks * gpmc_get_fclk_period() / 1000;
 300 }
 301
 302 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 303 {
 304         return ticks * gpmc_get_fclk_period();
 305 }
 306
 307 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 308 {
 309         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 310
 311         return ticks * gpmc_get_fclk_period();
 312 }
 313
 314 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 315 {
 316         u32 l;
 317
 318         l = gpmc_cs_read_reg(cs, reg);
 319         if (value)
 320                 l |= mask;
 321         else
 322                 l &= ~mask;
 323         gpmc_cs_write_reg(cs, reg, l);
 324 }
 325
 326 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 327 {
 328         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 329                            GPMC_CONFIG1_TIME_PARA_GRAN,
 330                            p->time_para_granularity);
 331         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 332                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 333         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 334                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 335         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 336                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 337         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 338                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 339         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 340                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 341                            p->cycle2cyclesamecsen);
 342         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 343                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 344                            p->cycle2cyclediffcsen);
 345 }
 346
 347 #ifdef DEBUG
 348 static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 349                                bool raw, bool noval, int shift,
 350                                const char *name)
 351 {
 352         u32 l;
 353         int nr_bits, max_value, mask;
 354
 355         l = gpmc_cs_read_reg(cs, reg);
 356         nr_bits = end_bit - st_bit + 1;
 357         max_value = (1 << nr_bits) - 1;
 358         mask = max_value << st_bit;
 359         l = (l & mask) >> st_bit;
 360         if (shift)
 361                 l = (shift << l);
 362         if (noval && (l == 0))
 363                 return 0;
 364         if (!raw) {
 365                 unsigned int time_ns_min, time_ns, time_ns_max;
 366
 367                 time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0);
 368                 time_ns = gpmc_ticks_to_ns(l);
 369                 time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ?
 370                                                max_value : l + 1);
 371                 pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n",
 372                         name, time_ns, time_ns_min, time_ns_max, l);
 373         } else {
 374                 pr_info("gpmc,%s = <%u>\n", name, l);
 375         }
 376
 377         return l;
 378 }
 379
 380 #define GPMC_PRINT_CONFIG(cs, config) \
 381         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 382                 gpmc_cs_read_reg(cs, config))
 383 #define GPMC_GET_RAW(reg, st, end, field) \
 384         get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
 385 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 386         get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
 387 #define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
 388         get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
 389 #define GPMC_GET_TICKS(reg, st, end, field) \
 390         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
 391
 392 static void gpmc_show_regs(int cs, const char *desc)
 393 {
 394         pr_info("gpmc cs%i %s:\n", cs, desc);
 395         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 396         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 397         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 398         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 399         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 400         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 401 }
 402
 403 /*
 404  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 405  * see commit c9fb809.
 406  */
 407 static void gpmc_cs_show_timings(int cs, const char *desc)
 408 {
 409         gpmc_show_regs(cs, desc);
 410
 411         pr_info("gpmc cs%i access configuration:\n", cs);
 412         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 413         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 414         GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
 415         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 416         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 417         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 418         GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length");
 419         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 420         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 421         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 422         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 423         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 424
 425         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 426
 427         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 428
 429         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 430         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 431
 432         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 433         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 434
 435         pr_info("gpmc cs%i timings configuration:\n", cs);
 436         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 437         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 438         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 439
 440         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 441         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 442         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 443
 444         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 445         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 446         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 447         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 448
 449         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 450         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 451         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 452
 453         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 454
 455         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 456         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 457
 458         GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
 459         GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
 460
 461         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 462         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 463 }
 464 #else
 465 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 466 {
 467 }
 468 #endif
 469
 470 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 471                                int time, const char *name)
 472 {
 473         u32 l;
 474         int ticks, mask, nr_bits;
 475
 476         if (time == 0)
 477                 ticks = 0;
 478         else
 479                 ticks = gpmc_ns_to_ticks(time);
 480         nr_bits = end_bit - st_bit + 1;
 481         mask = (1 << nr_bits) - 1;
 482
 483         if (ticks > mask) {
 484                 pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
 485                        __func__, cs, name, time, ticks, mask);
 486
 487                 return -1;
 488         }
 489
 490         l = gpmc_cs_read_reg(cs, reg);
 491 #ifdef DEBUG
 492         printk(KERN_INFO
 493                 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 494                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 495                         (l >> st_bit) & mask, time);
 496 #endif
 497         l &= ~(mask << st_bit);
 498         l |= ticks << st_bit;
 499         gpmc_cs_write_reg(cs, reg, l);
 500
 501         return 0;
 502 }
 503
 504 #define GPMC_SET_ONE(reg, st, end, field) \
 505         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 506                         t->field, #field) < 0)                  \
 507                 return -1
 508
 509 int gpmc_calc_divider(unsigned int sync_clk)
 510 {
 511         int div;
 512         u32 l;
 513
 514         l = sync_clk + (gpmc_get_fclk_period() - 1);
 515         div = l / gpmc_get_fclk_period();
 516         if (div > 4)
 517                 return -1;
 518         if (div <= 0)
 519                 div = 1;
 520
 521         return div;
 522 }
 523
 524 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 525 {
 526         int div;
 527         u32 l;
 528
 529         gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
 530         div = gpmc_calc_divider(t->sync_clk);
 531         if (div < 0)
 532                 return div;
 533
 534         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 535         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 536         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 537
 538         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 539         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 540         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 541
 542         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 543         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 544         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 545         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 546
 547         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 548         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 549         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 550
 551         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 552
 553         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 554         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 555
 556         GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
 557         GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
 558
 559         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 560                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 561         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 562                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 563
 564         /* caller is expected to have initialized CONFIG1 to cover
 565          * at least sync vs async
 566          */
 567         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 568         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 569 #ifdef DEBUG
 570                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 571                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 572 #endif
 573                 l &= ~0x03;
 574                 l |= (div - 1);
 575                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 576         }
 577
 578         gpmc_cs_bool_timings(cs, &t->bool_timings);
 579         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 580
 581         return 0;
 582 }
 583
 584 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 585 {
 586         u32 l;
 587         u32 mask;
 588
 589         /*
 590          * Ensure that base address is aligned on a
 591          * boundary equal to or greater than size.
 592          */
 593         if (base & (size - 1))
 594                 return -EINVAL;
 595
 596         base >>= GPMC_CHUNK_SHIFT;
 597         mask = (1 << GPMC_SECTION_SHIFT) - size;
 598         mask >>= GPMC_CHUNK_SHIFT;
 599         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 600
 601         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 602         l &= ~GPMC_CONFIG7_MASK;
 603         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 604         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 605         l |= GPMC_CONFIG7_CSVALID;
 606         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 607
 608         return 0;
 609 }
 610
 611 static void gpmc_cs_enable_mem(int cs)
 612 {
 613         u32 l;
 614
 615         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 616         l |= GPMC_CONFIG7_CSVALID;
 617         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 618 }
 619
 620 static void gpmc_cs_disable_mem(int cs)
 621 {
 622         u32 l;
 623
 624         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 625         l &= ~GPMC_CONFIG7_CSVALID;
 626         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 627 }
 628
 629 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 630 {
 631         u32 l;
 632         u32 mask;
 633
 634         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 635         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 636         mask = (l >> 8) & 0x0f;
 637         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 638 }
 639
 640 static int gpmc_cs_mem_enabled(int cs)
 641 {
 642         u32 l;
 643
 644         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 645         return l & GPMC_CONFIG7_CSVALID;
 646 }
 647
 648 static void gpmc_cs_set_reserved(int cs, int reserved)
 649 {
 650         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 651
 652         gpmc->flags |= GPMC_CS_RESERVED;
 653 }
 654
 655 static bool gpmc_cs_reserved(int cs)
 656 {
 657         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 658
 659         return gpmc->flags & GPMC_CS_RESERVED;
 660 }
 661
 662 static void gpmc_cs_set_name(int cs, const char *name)
 663 {
 664         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 665
 666         gpmc->name = name;
 667 }
 668
 669 static const char *gpmc_cs_get_name(int cs)
 670 {
 671         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 672
 673         return gpmc->name;
 674 }
 675
 676 static unsigned long gpmc_mem_align(unsigned long size)
 677 {
 678         int order;
 679
 680         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 681         order = GPMC_CHUNK_SHIFT - 1;
 682         do {
 683                 size >>= 1;
 684                 order++;
 685         } while (size);
 686         size = 1 << order;
 687         return size;
 688 }
 689
 690 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 691 {
 692         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 693         struct resource *res = &gpmc->mem;
 694         int r;
 695
 696         size = gpmc_mem_align(size);
 697         spin_lock(&gpmc_mem_lock);
 698         res->start = base;
 699         res->end = base + size - 1;
 700         r = request_resource(&gpmc_mem_root, res);
 701         spin_unlock(&gpmc_mem_lock);
 702
 703         return r;
 704 }
 705
 706 static int gpmc_cs_delete_mem(int cs)
 707 {
 708         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 709         struct resource *res = &gpmc->mem;
 710         int r;
 711
 712         spin_lock(&gpmc_mem_lock);
 713         r = release_resource(res);
 714         res->start = 0;
 715         res->end = 0;
 716         spin_unlock(&gpmc_mem_lock);
 717
 718         return r;
 719 }
 720
 721 /**
 722  * gpmc_cs_remap - remaps a chip-select physical base address
 723  * @cs:         chip-select to remap
 724  * @base:       physical base address to re-map chip-select to
 725  *
 726  * Re-maps a chip-select to a new physical base address specified by
 727  * "base". Returns 0 on success and appropriate negative error code
 728  * on failure.
 729  */
 730 static int gpmc_cs_remap(int cs, u32 base)
 731 {
 732         int ret;
 733         u32 old_base, size;
 734
 735         if (cs > gpmc_cs_num) {
 736                 pr_err("%s: requested chip-select is disabled\n", __func__);
 737                 return -ENODEV;
 738         }
 739
 740         /*
 741          * Make sure we ignore any device offsets from the GPMC partition
 742          * allocated for the chip select and that the new base confirms
 743          * to the GPMC 16MB minimum granularity.
 744          */
 745         base &= ~(SZ_16M - 1);
 746
 747         gpmc_cs_get_memconf(cs, &old_base, &size);
 748         if (base == old_base)
 749                 return 0;
 750
 751         ret = gpmc_cs_delete_mem(cs);
 752         if (ret < 0)
 753                 return ret;
 754
 755         ret = gpmc_cs_insert_mem(cs, base, size);
 756         if (ret < 0)
 757                 return ret;
 758
 759         ret = gpmc_cs_set_memconf(cs, base, size);
 760
 761         return ret;
 762 }
 763
 764 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 765 {
 766         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 767         struct resource *res = &gpmc->mem;
 768         int r = -1;
 769
 770         if (cs > gpmc_cs_num) {
 771                 pr_err("%s: requested chip-select is disabled\n", __func__);
 772                 return -ENODEV;
 773         }
 774         size = gpmc_mem_align(size);
 775         if (size > (1 << GPMC_SECTION_SHIFT))
 776                 return -ENOMEM;
 777
 778         spin_lock(&gpmc_mem_lock);
 779         if (gpmc_cs_reserved(cs)) {
 780                 r = -EBUSY;
 781                 goto out;
 782         }
 783         if (gpmc_cs_mem_enabled(cs))
 784                 r = adjust_resource(res, res->start & ~(size - 1), size);
 785         if (r < 0)
 786                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 787                                       size, NULL, NULL);
 788         if (r < 0)
 789                 goto out;
 790
 791         /* Disable CS while changing base address and size mask */
 792         gpmc_cs_disable_mem(cs);
 793
 794         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
 795         if (r < 0) {
 796                 release_resource(res);
 797                 goto out;
 798         }
 799
 800         /* Enable CS */
 801         gpmc_cs_enable_mem(cs);
 802         *base = res->start;
 803         gpmc_cs_set_reserved(cs, 1);
 804 out:
 805         spin_unlock(&gpmc_mem_lock);
 806         return r;
 807 }
 808 EXPORT_SYMBOL(gpmc_cs_request);
 809
 810 void gpmc_cs_free(int cs)
 811 {
 812         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 813         struct resource *res = &gpmc->mem;
 814
 815         spin_lock(&gpmc_mem_lock);
 816         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
 817                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 818                 BUG();
 819                 spin_unlock(&gpmc_mem_lock);
 820                 return;
 821         }
 822         gpmc_cs_disable_mem(cs);
 823         if (res->flags)
 824                 release_resource(res);
 825         gpmc_cs_set_reserved(cs, 0);
 826         spin_unlock(&gpmc_mem_lock);
 827 }
 828 EXPORT_SYMBOL(gpmc_cs_free);
 829
 830 /**
 831  * gpmc_configure - write request to configure gpmc
 832  * @cmd: command type
 833  * @wval: value to write
 834  * @return status of the operation
 835  */
 836 int gpmc_configure(int cmd, int wval)
 837 {
 838         u32 regval;
 839
 840         switch (cmd) {
 841         case GPMC_ENABLE_IRQ:
 842                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 843                 break;
 844
 845         case GPMC_SET_IRQ_STATUS:
 846                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 847                 break;
 848
 849         case GPMC_CONFIG_WP:
 850                 regval = gpmc_read_reg(GPMC_CONFIG);
 851                 if (wval)
 852                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 853                 else
 854                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 855                 gpmc_write_reg(GPMC_CONFIG, regval);
 856                 break;
 857
 858         default:
 859                 pr_err("%s: command not supported\n", __func__);
 860                 return -EINVAL;
 861         }
 862
 863         return 0;
 864 }
 865 EXPORT_SYMBOL(gpmc_configure);
 866
 867 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 868 {
 869         int i;
 870
 871         reg->gpmc_status = gpmc_base + GPMC_STATUS;
 872         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
 873                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
 874         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
 875                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
 876         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
 877                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
 878         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
 879         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
 880         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
 881         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
 882         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
 883         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
 884         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
 885         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
 886
 887         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
 888                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
 889                                            GPMC_BCH_SIZE * i;
 890                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
 891                                            GPMC_BCH_SIZE * i;
 892                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
 893                                            GPMC_BCH_SIZE * i;
 894                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
 895                                            GPMC_BCH_SIZE * i;
 896                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
 897                                            i * GPMC_BCH_SIZE;
 898                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
 899                                            i * GPMC_BCH_SIZE;
 900                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
 901                                            i * GPMC_BCH_SIZE;
 902         }
 903 }
 904
 905 int gpmc_get_client_irq(unsigned irq_config)
 906 {
 907         int i;
 908
 909         if (hweight32(irq_config) > 1)
 910                 return 0;
 911
 912         for (i = 0; i < GPMC_NR_IRQ; i++)
 913                 if (gpmc_client_irq[i].bitmask & irq_config)
 914                         return gpmc_client_irq[i].irq;
 915
 916         return 0;
 917 }
 918
 919 static int gpmc_irq_endis(unsigned irq, bool endis)
 920 {
 921         int i;
 922         u32 regval;
 923
 924         for (i = 0; i < GPMC_NR_IRQ; i++)
 925                 if (irq == gpmc_client_irq[i].irq) {
 926                         regval = gpmc_read_reg(GPMC_IRQENABLE);
 927                         if (endis)
 928                                 regval |= gpmc_client_irq[i].bitmask;
 929                         else
 930                                 regval &= ~gpmc_client_irq[i].bitmask;
 931                         gpmc_write_reg(GPMC_IRQENABLE, regval);
 932                         break;
 933                 }
 934
 935         return 0;
 936 }
 937
 938 static void gpmc_irq_disable(struct irq_data *p)
 939 {
 940         gpmc_irq_endis(p->irq, false);
 941 }
 942
 943 static void gpmc_irq_enable(struct irq_data *p)
 944 {
 945         gpmc_irq_endis(p->irq, true);
 946 }
 947
 948 static void gpmc_irq_noop(struct irq_data *data) { }
 949
 950 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 951
 952 static int gpmc_setup_irq(void)
 953 {
 954         int i;
 955         u32 regval;
 956
 957         if (!gpmc_irq)
 958                 return -EINVAL;
 959
 960         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
 961         if (gpmc_irq_start < 0) {
 962                 pr_err("irq_alloc_descs failed\n");
 963                 return gpmc_irq_start;
 964         }
 965
 966         gpmc_irq_chip.name = "gpmc";
 967         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
 968         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
 969         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
 970         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
 971         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
 972         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
 973         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
 974
 975         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
 976         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
 977
 978         for (i = 0; i < GPMC_NR_IRQ; i++) {
 979                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
 980                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
 981                                         &gpmc_irq_chip, handle_simple_irq);
 982                 set_irq_flags(gpmc_client_irq[i].irq,
 983                                 IRQF_VALID | IRQF_NOAUTOEN);
 984         }
 985
 986         /* Disable interrupts */
 987         gpmc_write_reg(GPMC_IRQENABLE, 0);
 988
 989         /* clear interrupts */
 990         regval = gpmc_read_reg(GPMC_IRQSTATUS);
 991         gpmc_write_reg(GPMC_IRQSTATUS, regval);
 992
 993         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 994 }
 995
 996 static int gpmc_free_irq(void)
 997 {
 998         int i;
 999
1000         if (gpmc_irq)
1001                 free_irq(gpmc_irq, NULL);
1002
1003         for (i = 0; i < GPMC_NR_IRQ; i++) {
1004                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1005                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1006                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
1007         }
1008
1009         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1010
1011         return 0;
1012 }
1013
1014 static void gpmc_mem_exit(void)
1015 {
1016         int cs;
1017
1018         for (cs = 0; cs < gpmc_cs_num; cs++) {
1019                 if (!gpmc_cs_mem_enabled(cs))
1020                         continue;
1021                 gpmc_cs_delete_mem(cs);
1022         }
1023
1024 }
1025
1026 static void gpmc_mem_init(void)
1027 {
1028         int cs;
1029
1030         /*
1031          * The first 1MB of GPMC address space is typically mapped to
1032          * the internal ROM. Never allocate the first page, to
1033          * facilitate bug detection; even if we didn't boot from ROM.
1034          */
1035         gpmc_mem_root.start = SZ_1M;
1036         gpmc_mem_root.end = GPMC_MEM_END;
1037
1038         /* Reserve all regions that has been set up by bootloader */
1039         for (cs = 0; cs < gpmc_cs_num; cs++) {
1040                 u32 base, size;
1041
1042                 if (!gpmc_cs_mem_enabled(cs))
1043                         continue;
1044                 gpmc_cs_get_memconf(cs, &base, &size);
1045                 if (gpmc_cs_insert_mem(cs, base, size)) {
1046                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1047                                 __func__, cs, base, base + size);
1048                         gpmc_cs_disable_mem(cs);
1049                 }
1050         }
1051 }
1052
1053 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1054 {
1055         u32 temp;
1056         int div;
1057
1058         div = gpmc_calc_divider(sync_clk);
1059         temp = gpmc_ps_to_ticks(time_ps);
1060         temp = (temp + div - 1) / div;
1061         return gpmc_ticks_to_ps(temp * div);
1062 }
1063
1064 /* XXX: can the cycles be avoided ? */
1065 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1066                                        struct gpmc_device_timings *dev_t,
1067                                        bool mux)
1068 {
1069         u32 temp;
1070
1071         /* adv_rd_off */
1072         temp = dev_t->t_avdp_r;
1073         /* XXX: mux check required ? */
1074         if (mux) {
1075                 /* XXX: t_avdp not to be required for sync, only added for tusb
1076                  * this indirectly necessitates requirement of t_avdp_r and
1077                  * t_avdp_w instead of having a single t_avdp
1078                  */
1079                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1080                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1081         }
1082         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1083
1084         /* oe_on */
1085         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1086         if (mux) {
1087                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1088                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1089                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1090         }
1091         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1092
1093         /* access */
1094         /* XXX: any scope for improvement ?, by combining oe_on
1095          * and clk_activation, need to check whether
1096          * access = clk_activation + round to sync clk ?
1097          */
1098         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1099         temp += gpmc_t->clk_activation;
1100         if (dev_t->cyc_oe)
1101                 temp = max_t(u32, temp, gpmc_t->oe_on +
1102                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1103         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1104
1105         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1106         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1107
1108         /* rd_cycle */
1109         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1110         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1111                                                         gpmc_t->access;
1112         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1113         if (dev_t->t_ce_rdyz)
1114                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1115         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1116
1117         return 0;
1118 }
1119
1120 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1121                                         struct gpmc_device_timings *dev_t,
1122                                         bool mux)
1123 {
1124         u32 temp;
1125
1126         /* adv_wr_off */
1127         temp = dev_t->t_avdp_w;
1128         if (mux) {
1129                 temp = max_t(u32, temp,
1130                         gpmc_t->clk_activation + dev_t->t_avdh);
1131                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1132         }
1133         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1134
1135         /* wr_data_mux_bus */
1136         temp = max_t(u32, dev_t->t_weasu,
1137                         gpmc_t->clk_activation + dev_t->t_rdyo);
1138         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1139          * and in that case remember to handle we_on properly
1140          */
1141         if (mux) {
1142                 temp = max_t(u32, temp,
1143                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1144                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1145                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1146         }
1147         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1148
1149         /* we_on */
1150         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1151                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1152         else
1153                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1154
1155         /* wr_access */
1156         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1157         gpmc_t->wr_access = gpmc_t->access;
1158
1159         /* we_off */
1160         temp = gpmc_t->we_on + dev_t->t_wpl;
1161         temp = max_t(u32, temp,
1162                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1163         temp = max_t(u32, temp,
1164                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1165         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1166
1167         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1168                                                         dev_t->t_wph);
1169
1170         /* wr_cycle */
1171         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1172         temp += gpmc_t->wr_access;
1173         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1174         if (dev_t->t_ce_rdyz)
1175                 temp = max_t(u32, temp,
1176                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1177         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1178
1179         return 0;
1180 }
1181
1182 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1183                                         struct gpmc_device_timings *dev_t,
1184                                         bool mux)
1185 {
1186         u32 temp;
1187
1188         /* adv_rd_off */
1189         temp = dev_t->t_avdp_r;
1190         if (mux)
1191                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1192         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1193
1194         /* oe_on */
1195         temp = dev_t->t_oeasu;
1196         if (mux)
1197                 temp = max_t(u32, temp,
1198                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1199         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1200
1201         /* access */
1202         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1203                                 gpmc_t->oe_on + dev_t->t_oe);
1204         temp = max_t(u32, temp,
1205                                 gpmc_t->cs_on + dev_t->t_ce);
1206         temp = max_t(u32, temp,
1207                                 gpmc_t->adv_on + dev_t->t_aa);
1208         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1209
1210         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1211         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1212
1213         /* rd_cycle */
1214         temp = max_t(u32, dev_t->t_rd_cycle,
1215                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1216         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1217         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1218
1219         return 0;
1220 }
1221
1222 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1223                                          struct gpmc_device_timings *dev_t,
1224                                          bool mux)
1225 {
1226         u32 temp;
1227
1228         /* adv_wr_off */
1229         temp = dev_t->t_avdp_w;
1230         if (mux)
1231                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1232         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1233
1234         /* wr_data_mux_bus */
1235         temp = dev_t->t_weasu;
1236         if (mux) {
1237                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1238                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1239                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1240         }
1241         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1242
1243         /* we_on */
1244         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1245                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1246         else
1247                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1248
1249         /* we_off */
1250         temp = gpmc_t->we_on + dev_t->t_wpl;
1251         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1252
1253         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1254                                                         dev_t->t_wph);
1255
1256         /* wr_cycle */
1257         temp = max_t(u32, dev_t->t_wr_cycle,
1258                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1259         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1260
1261         return 0;
1262 }
1263
1264 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1265                         struct gpmc_device_timings *dev_t)
1266 {
1267         u32 temp;
1268
1269         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1270                                                 gpmc_get_fclk_period();
1271
1272         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1273                                         dev_t->t_bacc,
1274                                         gpmc_t->sync_clk);
1275
1276         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1277         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1278
1279         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1280                 return 0;
1281
1282         if (dev_t->ce_xdelay)
1283                 gpmc_t->bool_timings.cs_extra_delay = true;
1284         if (dev_t->avd_xdelay)
1285                 gpmc_t->bool_timings.adv_extra_delay = true;
1286         if (dev_t->oe_xdelay)
1287                 gpmc_t->bool_timings.oe_extra_delay = true;
1288         if (dev_t->we_xdelay)
1289                 gpmc_t->bool_timings.we_extra_delay = true;
1290
1291         return 0;
1292 }
1293
1294 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1295                                     struct gpmc_device_timings *dev_t,
1296                                     bool sync)
1297 {
1298         u32 temp;
1299
1300         /* cs_on */
1301         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1302
1303         /* adv_on */
1304         temp = dev_t->t_avdasu;
1305         if (dev_t->t_ce_avd)
1306                 temp = max_t(u32, temp,
1307                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1308         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1309
1310         if (sync)
1311                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1312
1313         return 0;
1314 }
1315
1316 /* TODO: remove this function once all peripherals are confirmed to
1317  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1318  * has to be modified to handle timings in ps instead of ns
1319 */
1320 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1321 {
1322         t->cs_on /= 1000;
1323         t->cs_rd_off /= 1000;
1324         t->cs_wr_off /= 1000;
1325         t->adv_on /= 1000;
1326         t->adv_rd_off /= 1000;
1327         t->adv_wr_off /= 1000;
1328         t->we_on /= 1000;
1329         t->we_off /= 1000;
1330         t->oe_on /= 1000;
1331         t->oe_off /= 1000;
1332         t->page_burst_access /= 1000;
1333         t->access /= 1000;
1334         t->rd_cycle /= 1000;
1335         t->wr_cycle /= 1000;
1336         t->bus_turnaround /= 1000;
1337         t->cycle2cycle_delay /= 1000;
1338         t->wait_monitoring /= 1000;
1339         t->clk_activation /= 1000;
1340         t->wr_access /= 1000;
1341         t->wr_data_mux_bus /= 1000;
1342 }
1343
1344 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1345                       struct gpmc_settings *gpmc_s,
1346                       struct gpmc_device_timings *dev_t)
1347 {
1348         bool mux = false, sync = false;
1349
1350         if (gpmc_s) {
1351                 mux = gpmc_s->mux_add_data ? true : false;
1352                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1353         }
1354
1355         memset(gpmc_t, 0, sizeof(*gpmc_t));
1356
1357         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1358
1359         if (gpmc_s && gpmc_s->sync_read)
1360                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1361         else
1362                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1363
1364         if (gpmc_s && gpmc_s->sync_write)
1365                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1366         else
1367                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1368
1369         /* TODO: remove, see function definition */
1370         gpmc_convert_ps_to_ns(gpmc_t);
1371
1372         return 0;
1373 }
1374
1375 /**
1376  * gpmc_cs_program_settings - programs non-timing related settings
1377  * @cs:         GPMC chip-select to program
1378  * @p:          pointer to GPMC settings structure
1379  *
1380  * Programs non-timing related settings for a GPMC chip-select, such as
1381  * bus-width, burst configuration, etc. Function should be called once
1382  * for each chip-select that is being used and must be called before
1383  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1384  * register will be initialised to zero by this function. Returns 0 on
1385  * success and appropriate negative error code on failure.
1386  */
1387 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1388 {
1389         u32 config1;
1390
1391         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1392                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1393                 return -EINVAL;
1394         }
1395
1396         /* Address-data multiplexing not supported for NAND devices */
1397         if (p->device_nand && p->mux_add_data) {
1398                 pr_err("%s: invalid configuration!\n", __func__);
1399                 return -EINVAL;
1400         }
1401
1402         if ((p->mux_add_data > GPMC_MUX_AD) ||
1403             ((p->mux_add_data == GPMC_MUX_AAD) &&
1404              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1405                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1406                 return -EINVAL;
1407         }
1408
1409         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1410         if (p->burst_read || p->burst_write) {
1411                 switch (p->burst_len) {
1412                 case GPMC_BURST_4:
1413                 case GPMC_BURST_8:
1414                 case GPMC_BURST_16:
1415                         break;
1416                 default:
1417                         pr_err("%s: invalid page/burst-length (%d)\n",
1418                                __func__, p->burst_len);
1419                         return -EINVAL;
1420                 }
1421         }
1422
1423         if (p->wait_pin > gpmc_nr_waitpins) {
1424                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1425                 return -EINVAL;
1426         }
1427
1428         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1429
1430         if (p->sync_read)
1431                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1432         if (p->sync_write)
1433                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1434         if (p->wait_on_read)
1435                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1436         if (p->wait_on_write)
1437                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1438         if (p->wait_on_read || p->wait_on_write)
1439                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1440         if (p->device_nand)
1441                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1442         if (p->mux_add_data)
1443                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1444         if (p->burst_read)
1445                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1446         if (p->burst_write)
1447                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1448         if (p->burst_read || p->burst_write) {
1449                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1450                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1451         }
1452
1453         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1454
1455         return 0;
1456 }
1457
1458 #ifdef CONFIG_OF
1459 static const struct of_device_id gpmc_dt_ids[] = {
1460         { .compatible = "ti,omap2420-gpmc" },
1461         { .compatible = "ti,omap2430-gpmc" },
1462         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1463         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1464         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1465         { }
1466 };
1467 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1468
1469 /**
1470  * gpmc_read_settings_dt - read gpmc settings from device-tree
1471  * @np:         pointer to device-tree node for a gpmc child device
1472  * @p:          pointer to gpmc settings structure
1473  *
1474  * Reads the GPMC settings for a GPMC child device from device-tree and
1475  * stores them in the GPMC settings structure passed. The GPMC settings
1476  * structure is initialised to zero by this function and so any
1477  * previously stored settings will be cleared.
1478  */
1479 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1480 {
1481         memset(p, 0, sizeof(struct gpmc_settings));
1482
1483         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1484         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1485         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1486         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1487
1488         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1489                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1490                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1491                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1492                 if (!p->burst_read && !p->burst_write)
1493                         pr_warn("%s: page/burst-length set but not used!\n",
1494                                 __func__);
1495         }
1496
1497         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1498                 p->wait_on_read = of_property_read_bool(np,
1499                                                         "gpmc,wait-on-read");
1500                 p->wait_on_write = of_property_read_bool(np,
1501                                                          "gpmc,wait-on-write");
1502                 if (!p->wait_on_read && !p->wait_on_write)
1503                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1504                                  __func__);
1505         }
1506 }
1507
1508 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1509                                                 struct gpmc_timings *gpmc_t)
1510 {
1511         struct gpmc_bool_timings *p;
1512
1513         if (!np || !gpmc_t)
1514                 return;
1515
1516         memset(gpmc_t, 0, sizeof(*gpmc_t));
1517
1518         /* minimum clock period for syncronous mode */
1519         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1520
1521         /* chip select timtings */
1522         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1523         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1524         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1525
1526         /* ADV signal timings */
1527         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1528         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1529         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1530
1531         /* WE signal timings */
1532         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1533         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1534
1535         /* OE signal timings */
1536         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1537         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1538
1539         /* access and cycle timings */
1540         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1541                              &gpmc_t->page_burst_access);
1542         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1543         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1544         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1545         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1546                              &gpmc_t->bus_turnaround);
1547         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1548                              &gpmc_t->cycle2cycle_delay);
1549         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1550                              &gpmc_t->wait_monitoring);
1551         of_property_read_u32(np, "gpmc,clk-activation-ns",
1552                              &gpmc_t->clk_activation);
1553
1554         /* only applicable to OMAP3+ */
1555         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1556         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1557                              &gpmc_t->wr_data_mux_bus);
1558
1559         /* bool timing parameters */
1560         p = &gpmc_t->bool_timings;
1561
1562         p->cycle2cyclediffcsen =
1563                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1564         p->cycle2cyclesamecsen =
1565                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1566         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1567         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1568         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1569         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1570         p->time_para_granularity =
1571                 of_property_read_bool(np, "gpmc,time-para-granularity");
1572 }
1573
1574 #if IS_ENABLED(CONFIG_MTD_NAND)
1575
1576 static const char * const nand_xfer_types[] = {
1577         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1578         [NAND_OMAP_POLLED]                      = "polled",
1579         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1580         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1581 };
1582
1583 static int gpmc_probe_nand_child(struct platform_device *pdev,
1584                                  struct device_node *child)
1585 {
1586         u32 val;
1587         const char *s;
1588         struct gpmc_timings gpmc_t;
1589         struct omap_nand_platform_data *gpmc_nand_data;
1590
1591         if (of_property_read_u32(child, "reg", &val) < 0) {
1592                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1593                         child->full_name);
1594                 return -ENODEV;
1595         }
1596
1597         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1598                                       GFP_KERNEL);
1599         if (!gpmc_nand_data)
1600                 return -ENOMEM;
1601
1602         gpmc_nand_data->cs = val;
1603         gpmc_nand_data->of_node = child;
1604
1605         /* Detect availability of ELM module */
1606         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1607         if (gpmc_nand_data->elm_of_node == NULL)
1608                 gpmc_nand_data->elm_of_node =
1609                                         of_parse_phandle(child, "elm_id", 0);
1610
1611         /* select ecc-scheme for NAND */
1612         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1613                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1614                 return -ENODEV;
1615         }
1616
1617         if (!strcmp(s, "sw"))
1618                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1619         else if (!strcmp(s, "ham1") ||
1620                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1621                 gpmc_nand_data->ecc_opt =
1622                                 OMAP_ECC_HAM1_CODE_HW;
1623         else if (!strcmp(s, "bch4"))
1624                 if (gpmc_nand_data->elm_of_node)
1625                         gpmc_nand_data->ecc_opt =
1626                                 OMAP_ECC_BCH4_CODE_HW;
1627                 else
1628                         gpmc_nand_data->ecc_opt =
1629                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1630         else if (!strcmp(s, "bch8"))
1631                 if (gpmc_nand_data->elm_of_node)
1632                         gpmc_nand_data->ecc_opt =
1633                                 OMAP_ECC_BCH8_CODE_HW;
1634                 else
1635                         gpmc_nand_data->ecc_opt =
1636                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1637         else if (!strcmp(s, "bch16"))
1638                 if (gpmc_nand_data->elm_of_node)
1639                         gpmc_nand_data->ecc_opt =
1640                                 OMAP_ECC_BCH16_CODE_HW;
1641                 else
1642                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1643         else
1644                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1645
1646         /* select data transfer mode for NAND controller */
1647         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1648                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1649                         if (!strcasecmp(s, nand_xfer_types[val])) {
1650                                 gpmc_nand_data->xfer_type = val;
1651                                 break;
1652                         }
1653
1654         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1655
1656         val = of_get_nand_bus_width(child);
1657         if (val == 16)
1658                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1659
1660         gpmc_read_timings_dt(child, &gpmc_t);
1661         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1662
1663         return 0;
1664 }
1665 #else
1666 static int gpmc_probe_nand_child(struct platform_device *pdev,
1667                                  struct device_node *child)
1668 {
1669         return 0;
1670 }
1671 #endif
1672
1673 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1674 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1675                                  struct device_node *child)
1676 {
1677         u32 val;
1678         struct omap_onenand_platform_data *gpmc_onenand_data;
1679
1680         if (of_property_read_u32(child, "reg", &val) < 0) {
1681                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1682                         child->full_name);
1683                 return -ENODEV;
1684         }
1685
1686         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1687                                          GFP_KERNEL);
1688         if (!gpmc_onenand_data)
1689                 return -ENOMEM;
1690
1691         gpmc_onenand_data->cs = val;
1692         gpmc_onenand_data->of_node = child;
1693         gpmc_onenand_data->dma_channel = -1;
1694
1695         if (!of_property_read_u32(child, "dma-channel", &val))
1696                 gpmc_onenand_data->dma_channel = val;
1697
1698         gpmc_onenand_init(gpmc_onenand_data);
1699
1700         return 0;
1701 }
1702 #else
1703 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1704                                     struct device_node *child)
1705 {
1706         return 0;
1707 }
1708 #endif
1709
1710 /**
1711  * gpmc_probe_generic_child - configures the gpmc for a child device
1712  * @pdev:       pointer to gpmc platform device
1713  * @child:      pointer to device-tree node for child device
1714  *
1715  * Allocates and configures a GPMC chip-select for a child device.
1716  * Returns 0 on success and appropriate negative error code on failure.
1717  */
1718 static int gpmc_probe_generic_child(struct platform_device *pdev,
1719                                 struct device_node *child)
1720 {
1721         struct gpmc_settings gpmc_s;
1722         struct gpmc_timings gpmc_t;
1723         struct resource res;
1724         unsigned long base;
1725         const char *name;
1726         int ret, cs;
1727         u32 val;
1728
1729         if (of_property_read_u32(child, "reg", &cs) < 0) {
1730                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1731                         child->full_name);
1732                 return -ENODEV;
1733         }
1734
1735         if (of_address_to_resource(child, 0, &res) < 0) {
1736                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1737                         child->full_name);
1738                 return -ENODEV;
1739         }
1740
1741         /*
1742          * Check if we have multiple instances of the same device
1743          * on a single chip select. If so, use the already initialized
1744          * timings.
1745          */
1746         name = gpmc_cs_get_name(cs);
1747         if (name && child->name && of_node_cmp(child->name, name) == 0)
1748                         goto no_timings;
1749
1750         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1751         if (ret < 0) {
1752                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1753                 return ret;
1754         }
1755         gpmc_cs_set_name(cs, child->name);
1756
1757         gpmc_read_settings_dt(child, &gpmc_s);
1758         gpmc_read_timings_dt(child, &gpmc_t);
1759
1760         /*
1761          * For some GPMC devices we still need to rely on the bootloader
1762          * timings because the devices can be connected via FPGA.
1763          * REVISIT: Add timing support from slls644g.pdf.
1764          */
1765         if (!gpmc_t.cs_rd_off) {
1766                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1767                         cs);
1768                 gpmc_cs_show_timings(cs,
1769                                      "please add GPMC bootloader timings to .dts");
1770                 goto no_timings;
1771         }
1772
1773         /* CS must be disabled while making changes to gpmc configuration */
1774         gpmc_cs_disable_mem(cs);
1775
1776         /*
1777          * FIXME: gpmc_cs_request() will map the CS to an arbitary
1778          * location in the gpmc address space. When booting with
1779          * device-tree we want the NOR flash to be mapped to the
1780          * location specified in the device-tree blob. So remap the
1781          * CS to this location. Once DT migration is complete should
1782          * just make gpmc_cs_request() map a specific address.
1783          */
1784         ret = gpmc_cs_remap(cs, res.start);
1785         if (ret < 0) {
1786                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1787                         cs, &res.start);
1788                 goto err;
1789         }
1790
1791         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1792         if (ret < 0)
1793                 goto err;
1794
1795         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1796         if (ret < 0)
1797                 goto err;
1798
1799         ret = gpmc_cs_set_timings(cs, &gpmc_t);
1800         if (ret) {
1801                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1802                         child->name);
1803                 goto err;
1804         }
1805
1806         /* Clear limited address i.e. enable A26-A11 */
1807         val = gpmc_read_reg(GPMC_CONFIG);
1808         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1809         gpmc_write_reg(GPMC_CONFIG, val);
1810
1811         /* Enable CS region */
1812         gpmc_cs_enable_mem(cs);
1813
1814 no_timings:
1815         if (of_platform_device_create(child, NULL, &pdev->dev))
1816                 return 0;
1817
1818         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1819         ret = -ENODEV;
1820
1821 err:
1822         gpmc_cs_free(cs);
1823
1824         return ret;
1825 }
1826
1827 static int gpmc_probe_dt(struct platform_device *pdev)
1828 {
1829         int ret;
1830         struct device_node *child;
1831         const struct of_device_id *of_id =
1832                 of_match_device(gpmc_dt_ids, &pdev->dev);
1833
1834         if (!of_id)
1835                 return 0;
1836
1837         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1838                                    &gpmc_cs_num);
1839         if (ret < 0) {
1840                 pr_err("%s: number of chip-selects not defined\n", __func__);
1841                 return ret;
1842         } else if (gpmc_cs_num < 1) {
1843                 pr_err("%s: all chip-selects are disabled\n", __func__);
1844                 return -EINVAL;
1845         } else if (gpmc_cs_num > GPMC_CS_NUM) {
1846                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1847                                          __func__, GPMC_CS_NUM);
1848                 return -EINVAL;
1849         }
1850
1851         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1852                                    &gpmc_nr_waitpins);
1853         if (ret < 0) {
1854                 pr_err("%s: number of wait pins not found!\n", __func__);
1855                 return ret;
1856         }
1857
1858         for_each_available_child_of_node(pdev->dev.of_node, child) {
1859
1860                 if (!child->name)
1861                         continue;
1862
1863                 if (of_node_cmp(child->name, "nand") == 0)
1864                         ret = gpmc_probe_nand_child(pdev, child);
1865                 else if (of_node_cmp(child->name, "onenand") == 0)
1866                         ret = gpmc_probe_onenand_child(pdev, child);
1867                 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1868                          of_node_cmp(child->name, "nor") == 0 ||
1869                          of_node_cmp(child->name, "uart") == 0)
1870                         ret = gpmc_probe_generic_child(pdev, child);
1871
1872                 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1873                          __func__, child->full_name))
1874                         of_node_put(child);
1875         }
1876
1877         return 0;
1878 }
1879 #else
1880 static int gpmc_probe_dt(struct platform_device *pdev)
1881 {
1882         return 0;
1883 }
1884 #endif
1885
1886 static int gpmc_probe(struct platform_device *pdev)
1887 {
1888         int rc;
1889         u32 l;
1890         struct resource *res;
1891
1892         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1893         if (res == NULL)
1894                 return -ENOENT;
1895
1896         phys_base = res->start;
1897         mem_size = resource_size(res);
1898
1899         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1900         if (IS_ERR(gpmc_base))
1901                 return PTR_ERR(gpmc_base);
1902
1903         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1904         if (res == NULL)
1905                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1906         else
1907                 gpmc_irq = res->start;
1908
1909         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
1910         if (IS_ERR(gpmc_l3_clk)) {
1911                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
1912                 gpmc_irq = 0;
1913                 return PTR_ERR(gpmc_l3_clk);
1914         }
1915
1916         if (!clk_get_rate(gpmc_l3_clk)) {
1917                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
1918                 return -EINVAL;
1919         }
1920
1921         pm_runtime_enable(&pdev->dev);
1922         pm_runtime_get_sync(&pdev->dev);
1923
1924         gpmc_dev = &pdev->dev;
1925
1926         l = gpmc_read_reg(GPMC_REVISION);
1927
1928         /*
1929          * FIXME: Once device-tree migration is complete the below flags
1930          * should be populated based upon the device-tree compatible
1931          * string. For now just use the IP revision. OMAP3+ devices have
1932          * the wr_access and wr_data_mux_bus register fields. OMAP4+
1933          * devices support the addr-addr-data multiplex protocol.
1934          *
1935          * GPMC IP revisions:
1936          * - OMAP24xx                   = 2.0
1937          * - OMAP3xxx                   = 5.0
1938          * - OMAP44xx/54xx/AM335x       = 6.0
1939          */
1940         if (GPMC_REVISION_MAJOR(l) > 0x4)
1941                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1942         if (GPMC_REVISION_MAJOR(l) > 0x5)
1943                 gpmc_capability |= GPMC_HAS_MUX_AAD;
1944         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1945                  GPMC_REVISION_MINOR(l));
1946
1947         gpmc_mem_init();
1948
1949         if (gpmc_setup_irq() < 0)
1950                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1951
1952         if (!pdev->dev.of_node) {
1953                 gpmc_cs_num      = GPMC_CS_NUM;
1954                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1955         }
1956
1957         rc = gpmc_probe_dt(pdev);
1958         if (rc < 0) {
1959                 pm_runtime_put_sync(&pdev->dev);
1960                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1961                 return rc;
1962         }
1963
1964         return 0;
1965 }
1966
1967 static int gpmc_remove(struct platform_device *pdev)
1968 {
1969         gpmc_free_irq();
1970         gpmc_mem_exit();
1971         pm_runtime_put_sync(&pdev->dev);
1972         pm_runtime_disable(&pdev->dev);
1973         gpmc_dev = NULL;
1974         return 0;
1975 }
1976
1977 #ifdef CONFIG_PM_SLEEP
1978 static int gpmc_suspend(struct device *dev)
1979 {
1980         omap3_gpmc_save_context();
1981         pm_runtime_put_sync(dev);
1982         return 0;
1983 }
1984
1985 static int gpmc_resume(struct device *dev)
1986 {
1987         pm_runtime_get_sync(dev);
1988         omap3_gpmc_restore_context();
1989         return 0;
1990 }
1991 #endif
1992
1993 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
1994
1995 static struct platform_driver gpmc_driver = {
1996         .probe          = gpmc_probe,
1997         .remove         = gpmc_remove,
1998         .driver         = {
1999                 .name   = DEVICE_NAME,
2000                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2001                 .pm     = &gpmc_pm_ops,
2002         },
2003 };
2004
2005 static __init int gpmc_init(void)
2006 {
2007         return platform_driver_register(&gpmc_driver);
2008 }
2009
2010 static __exit void gpmc_exit(void)
2011 {
2012         platform_driver_unregister(&gpmc_driver);
2013
2014 }
2015
2016 postcore_initcall(gpmc_init);
2017 module_exit(gpmc_exit);
2018
2019 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2020 {
2021         int i;
2022         u32 regval;
2023
2024         regval = gpmc_read_reg(GPMC_IRQSTATUS);
2025
2026         if (!regval)
2027                 return IRQ_NONE;
2028
2029         for (i = 0; i < GPMC_NR_IRQ; i++)
2030                 if (regval & gpmc_client_irq[i].bitmask)
2031                         generic_handle_irq(gpmc_client_irq[i].irq);
2032
2033         gpmc_write_reg(GPMC_IRQSTATUS, regval);
2034
2035         return IRQ_HANDLED;
2036 }
2037
2038 static struct omap3_gpmc_regs gpmc_context;
2039
2040 void omap3_gpmc_save_context(void)
2041 {
2042         int i;
2043
2044         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2045         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2046         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2047         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2048         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2049         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2050         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2051         for (i = 0; i < gpmc_cs_num; i++) {
2052                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2053                 if (gpmc_context.cs_context[i].is_valid) {
2054                         gpmc_context.cs_context[i].config1 =
2055                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2056                         gpmc_context.cs_context[i].config2 =
2057                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2058                         gpmc_context.cs_context[i].config3 =
2059                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2060                         gpmc_context.cs_context[i].config4 =
2061                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2062                         gpmc_context.cs_context[i].config5 =
2063                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2064                         gpmc_context.cs_context[i].config6 =
2065                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2066                         gpmc_context.cs_context[i].config7 =
2067                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2068                 }
2069         }
2070 }
2071
2072 void omap3_gpmc_restore_context(void)
2073 {
2074         int i;
2075
2076         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2077         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2078         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2079         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2080         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2081         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2082         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2083         for (i = 0; i < gpmc_cs_num; i++) {
2084                 if (gpmc_context.cs_context[i].is_valid) {
2085                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2086                                 gpmc_context.cs_context[i].config1);
2087                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2088                                 gpmc_context.cs_context[i].config2);
2089                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2090                                 gpmc_context.cs_context[i].config3);
2091                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2092                                 gpmc_context.cs_context[i].config4);
2093                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2094                                 gpmc_context.cs_context[i].config5);
2095                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2096                                 gpmc_context.cs_context[i].config6);
2097                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2098                                 gpmc_context.cs_context[i].config7);
2099                 }
2100         }
2101 }