1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RPC-IF core driver
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
6 * Copyright (C) 2019 Macronix International Co., Ltd.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
10 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
18 #include <memory/renesas-rpc-if.h>
20 #define RPCIF_CMNCR 0x0000 /* R/W */
21 #define RPCIF_CMNCR_MD BIT(31)
22 #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
27 #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
28 RPCIF_CMNCR_MOIIO1(3) | \
29 RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
30 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
31 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
32 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
33 #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
35 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
37 #define RPCIF_SSLDR 0x0004 /* R/W */
38 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
39 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
40 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
42 #define RPCIF_DRCR 0x000C /* R/W */
43 #define RPCIF_DRCR_SSLN BIT(24)
44 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
45 #define RPCIF_DRCR_RCF BIT(9)
46 #define RPCIF_DRCR_RBE BIT(8)
47 #define RPCIF_DRCR_SSLE BIT(0)
49 #define RPCIF_DRCMR 0x0010 /* R/W */
50 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
51 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
53 #define RPCIF_DREAR 0x0014 /* R/W */
54 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
55 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
57 #define RPCIF_DROPR 0x0018 /* R/W */
59 #define RPCIF_DRENR 0x001C /* R/W */
60 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
61 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
62 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
63 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
64 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
65 #define RPCIF_DRENR_DME BIT(15)
66 #define RPCIF_DRENR_CDE BIT(14)
67 #define RPCIF_DRENR_OCDE BIT(12)
68 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
69 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
71 #define RPCIF_SMCR 0x0020 /* R/W */
72 #define RPCIF_SMCR_SSLKP BIT(8)
73 #define RPCIF_SMCR_SPIRE BIT(2)
74 #define RPCIF_SMCR_SPIWE BIT(1)
75 #define RPCIF_SMCR_SPIE BIT(0)
77 #define RPCIF_SMCMR 0x0024 /* R/W */
78 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
79 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
81 #define RPCIF_SMADR 0x0028 /* R/W */
83 #define RPCIF_SMOPR 0x002C /* R/W */
84 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
85 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
86 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
87 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
89 #define RPCIF_SMENR 0x0030 /* R/W */
90 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
91 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
92 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
93 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
94 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
95 #define RPCIF_SMENR_DME BIT(15)
96 #define RPCIF_SMENR_CDE BIT(14)
97 #define RPCIF_SMENR_OCDE BIT(12)
98 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
99 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
100 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
102 #define RPCIF_SMRDR0 0x0038 /* R */
103 #define RPCIF_SMRDR1 0x003C /* R */
104 #define RPCIF_SMWDR0 0x0040 /* W */
105 #define RPCIF_SMWDR1 0x0044 /* W */
107 #define RPCIF_CMNSR 0x0048 /* R */
108 #define RPCIF_CMNSR_SSLF BIT(1)
109 #define RPCIF_CMNSR_TEND BIT(0)
111 #define RPCIF_DRDMCR 0x0058 /* R/W */
112 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
114 #define RPCIF_DRDRENR 0x005C /* R/W */
115 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
116 #define RPCIF_DRDRENR_ADDRE BIT(8)
117 #define RPCIF_DRDRENR_OPDRE BIT(4)
118 #define RPCIF_DRDRENR_DRDRE BIT(0)
120 #define RPCIF_SMDMCR 0x0060 /* R/W */
121 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
123 #define RPCIF_SMDRENR 0x0064 /* R/W */
124 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
125 #define RPCIF_SMDRENR_ADDRE BIT(8)
126 #define RPCIF_SMDRENR_OPDRE BIT(4)
127 #define RPCIF_SMDRENR_SPIDRE BIT(0)
129 #define RPCIF_PHYCNT 0x007C /* R/W */
130 #define RPCIF_PHYCNT_CAL BIT(31)
131 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
132 #define RPCIF_PHYCNT_EXDS BIT(21)
133 #define RPCIF_PHYCNT_OCT BIT(20)
134 #define RPCIF_PHYCNT_DDRCAL BIT(19)
135 #define RPCIF_PHYCNT_HS BIT(18)
136 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
137 #define RPCIF_PHYCNT_WBUF2 BIT(4)
138 #define RPCIF_PHYCNT_WBUF BIT(2)
139 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
141 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
142 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
144 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
145 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
147 #define RPCIF_PHYINT 0x0088 /* R/W */
148 #define RPCIF_PHYINT_WPVAL BIT(1)
150 #define RPCIF_DIRMAP_SIZE 0x4000000
152 static const struct regmap_range rpcif_volatile_ranges
[] = {
153 regmap_reg_range(RPCIF_SMRDR0
, RPCIF_SMRDR1
),
154 regmap_reg_range(RPCIF_SMWDR0
, RPCIF_SMWDR1
),
155 regmap_reg_range(RPCIF_CMNSR
, RPCIF_CMNSR
),
158 static const struct regmap_access_table rpcif_volatile_table
= {
159 .yes_ranges
= rpcif_volatile_ranges
,
160 .n_yes_ranges
= ARRAY_SIZE(rpcif_volatile_ranges
),
165 * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
166 * with proper width. Requires SMENR_SPIDE to be correctly set before!
168 static int rpcif_reg_read(void *context
, unsigned int reg
, unsigned int *val
)
170 struct rpcif
*rpc
= context
;
172 if (reg
== RPCIF_SMRDR0
|| reg
== RPCIF_SMWDR0
) {
173 u32 spide
= readl(rpc
->base
+ RPCIF_SMENR
) & RPCIF_SMENR_SPIDE(0xF);
176 *val
= readb(rpc
->base
+ reg
);
178 } else if (spide
== 0xC) {
179 *val
= readw(rpc
->base
+ reg
);
181 } else if (spide
!= 0xF) {
186 *val
= readl(rpc
->base
+ reg
);
191 static int rpcif_reg_write(void *context
, unsigned int reg
, unsigned int val
)
193 struct rpcif
*rpc
= context
;
195 if (reg
== RPCIF_SMRDR0
|| reg
== RPCIF_SMWDR0
) {
196 u32 spide
= readl(rpc
->base
+ RPCIF_SMENR
) & RPCIF_SMENR_SPIDE(0xF);
199 writeb(val
, rpc
->base
+ reg
);
201 } else if (spide
== 0xC) {
202 writew(val
, rpc
->base
+ reg
);
204 } else if (spide
!= 0xF) {
209 writel(val
, rpc
->base
+ reg
);
213 static const struct regmap_config rpcif_regmap_config
= {
217 .reg_read
= rpcif_reg_read
,
218 .reg_write
= rpcif_reg_write
,
220 .max_register
= RPCIF_PHYINT
,
221 .volatile_table
= &rpcif_volatile_table
,
224 int rpcif_sw_init(struct rpcif
*rpc
, struct device
*dev
)
226 struct platform_device
*pdev
= to_platform_device(dev
);
227 struct resource
*res
;
231 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "regs");
232 rpc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
233 if (IS_ERR(rpc
->base
))
234 return PTR_ERR(rpc
->base
);
236 rpc
->regmap
= devm_regmap_init(&pdev
->dev
, NULL
, rpc
, &rpcif_regmap_config
);
237 if (IS_ERR(rpc
->regmap
)) {
239 "failed to init regmap for rpcif, error %ld\n",
240 PTR_ERR(rpc
->regmap
));
241 return PTR_ERR(rpc
->regmap
);
244 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dirmap");
245 rpc
->dirmap
= devm_ioremap_resource(&pdev
->dev
, res
);
246 if (IS_ERR(rpc
->dirmap
))
247 return PTR_ERR(rpc
->dirmap
);
248 rpc
->size
= resource_size(res
);
250 rpc
->rstc
= devm_reset_control_get_exclusive(&pdev
->dev
, NULL
);
252 return PTR_ERR_OR_ZERO(rpc
->rstc
);
254 EXPORT_SYMBOL(rpcif_sw_init
);
256 void rpcif_hw_init(struct rpcif
*rpc
, bool hyperflash
)
260 pm_runtime_get_sync(rpc
->dev
);
263 * NOTE: The 0x260 are undocumented bits, but they must be set.
264 * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
265 * 0x0 : the delay is biggest,
266 * 0x1 : the delay is 2nd biggest,
267 * On H3 ES1.x, the value should be 0, while on others,
268 * the value should be 7.
270 regmap_write(rpc
->regmap
, RPCIF_PHYCNT
, RPCIF_PHYCNT_STRTIM(7) |
271 RPCIF_PHYCNT_PHYMEM(hyperflash
? 3 : 0) | 0x260);
274 * NOTE: The 0x1511144 are undocumented bits, but they must be set
275 * for RPCIF_PHYOFFSET1.
276 * The 0x31 are undocumented bits, but they must be set
277 * for RPCIF_PHYOFFSET2.
279 regmap_write(rpc
->regmap
, RPCIF_PHYOFFSET1
, 0x1511144 |
280 RPCIF_PHYOFFSET1_DDRTMG(3));
281 regmap_write(rpc
->regmap
, RPCIF_PHYOFFSET2
, 0x31 |
282 RPCIF_PHYOFFSET2_OCTTMG(4));
285 regmap_update_bits(rpc
->regmap
, RPCIF_PHYINT
,
286 RPCIF_PHYINT_WPVAL
, 0);
288 regmap_write(rpc
->regmap
, RPCIF_CMNCR
, RPCIF_CMNCR_SFDE
|
289 RPCIF_CMNCR_MOIIO_HIZ
| RPCIF_CMNCR_IOFV_HIZ
|
290 RPCIF_CMNCR_BSZ(hyperflash
? 1 : 0));
291 /* Set RCF after BSZ update */
292 regmap_write(rpc
->regmap
, RPCIF_DRCR
, RPCIF_DRCR_RCF
);
293 /* Dummy read according to spec */
294 regmap_read(rpc
->regmap
, RPCIF_DRCR
, &dummy
);
295 regmap_write(rpc
->regmap
, RPCIF_SSLDR
, RPCIF_SSLDR_SPNDL(7) |
296 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
298 pm_runtime_put(rpc
->dev
);
300 rpc
->bus_size
= hyperflash
? 2 : 1;
302 EXPORT_SYMBOL(rpcif_hw_init
);
304 static int wait_msg_xfer_end(struct rpcif
*rpc
)
308 return regmap_read_poll_timeout(rpc
->regmap
, RPCIF_CMNSR
, sts
,
309 sts
& RPCIF_CMNSR_TEND
, 0,
313 static u8
rpcif_bits_set(struct rpcif
*rpc
, u32 nbytes
)
315 if (rpc
->bus_size
== 2)
317 nbytes
= clamp(nbytes
, 1U, 4U);
318 return GENMASK(3, 4 - nbytes
);
321 static u8
rpcif_bit_size(u8 buswidth
)
323 return buswidth
> 4 ? 2 : ilog2(buswidth
);
326 void rpcif_prepare(struct rpcif
*rpc
, const struct rpcif_op
*op
, u64
*offs
,
338 if (op
->cmd
.buswidth
) {
339 rpc
->enable
= RPCIF_SMENR_CDE
|
340 RPCIF_SMENR_CDB(rpcif_bit_size(op
->cmd
.buswidth
));
341 rpc
->command
= RPCIF_SMCMR_CMD(op
->cmd
.opcode
);
343 rpc
->ddr
= RPCIF_SMDRENR_HYPE(0x5);
345 if (op
->ocmd
.buswidth
) {
346 rpc
->enable
|= RPCIF_SMENR_OCDE
|
347 RPCIF_SMENR_OCDB(rpcif_bit_size(op
->ocmd
.buswidth
));
348 rpc
->command
|= RPCIF_SMCMR_OCMD(op
->ocmd
.opcode
);
351 if (op
->addr
.buswidth
) {
353 RPCIF_SMENR_ADB(rpcif_bit_size(op
->addr
.buswidth
));
354 if (op
->addr
.nbytes
== 4)
355 rpc
->enable
|= RPCIF_SMENR_ADE(0xF);
357 rpc
->enable
|= RPCIF_SMENR_ADE(GENMASK(
358 2, 3 - op
->addr
.nbytes
));
360 rpc
->ddr
|= RPCIF_SMDRENR_ADDRE
;
365 rpc
->smadr
= op
->addr
.val
;
368 if (op
->dummy
.buswidth
) {
369 rpc
->enable
|= RPCIF_SMENR_DME
;
370 rpc
->dummy
= RPCIF_SMDMCR_DMCYC(op
->dummy
.ncycles
/
374 if (op
->option
.buswidth
) {
375 rpc
->enable
|= RPCIF_SMENR_OPDE(
376 rpcif_bits_set(rpc
, op
->option
.nbytes
)) |
377 RPCIF_SMENR_OPDB(rpcif_bit_size(op
->option
.buswidth
));
379 rpc
->ddr
|= RPCIF_SMDRENR_OPDRE
;
380 rpc
->option
= op
->option
.val
;
383 rpc
->dir
= op
->data
.dir
;
384 if (op
->data
.buswidth
) {
387 rpc
->buffer
= op
->data
.buf
.in
;
388 switch (op
->data
.dir
) {
390 rpc
->smcr
= RPCIF_SMCR_SPIRE
;
393 rpc
->smcr
= RPCIF_SMCR_SPIWE
;
399 rpc
->ddr
|= RPCIF_SMDRENR_SPIDRE
;
404 nbytes
= op
->data
.nbytes
;
405 rpc
->xferlen
= nbytes
;
407 rpc
->enable
|= RPCIF_SMENR_SPIDB(rpcif_bit_size(op
->data
.buswidth
));
410 EXPORT_SYMBOL(rpcif_prepare
);
412 int rpcif_manual_xfer(struct rpcif
*rpc
)
414 u32 smenr
, smcr
, pos
= 0, max
= rpc
->bus_size
== 2 ? 8 : 4;
417 pm_runtime_get_sync(rpc
->dev
);
419 regmap_update_bits(rpc
->regmap
, RPCIF_PHYCNT
,
420 RPCIF_PHYCNT_CAL
, RPCIF_PHYCNT_CAL
);
421 regmap_update_bits(rpc
->regmap
, RPCIF_CMNCR
,
422 RPCIF_CMNCR_MD
, RPCIF_CMNCR_MD
);
423 regmap_write(rpc
->regmap
, RPCIF_SMCMR
, rpc
->command
);
424 regmap_write(rpc
->regmap
, RPCIF_SMOPR
, rpc
->option
);
425 regmap_write(rpc
->regmap
, RPCIF_SMDMCR
, rpc
->dummy
);
426 regmap_write(rpc
->regmap
, RPCIF_SMDRENR
, rpc
->ddr
);
427 regmap_write(rpc
->regmap
, RPCIF_SMADR
, rpc
->smadr
);
432 while (pos
< rpc
->xferlen
) {
433 u32 bytes_left
= rpc
->xferlen
- pos
;
436 smcr
= rpc
->smcr
| RPCIF_SMCR_SPIE
;
438 /* nbytes may only be 1, 2, 4, or 8 */
439 nbytes
= bytes_left
>= max
? max
: (1 << ilog2(bytes_left
));
440 if (bytes_left
> nbytes
)
441 smcr
|= RPCIF_SMCR_SSLKP
;
443 smenr
|= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc
, nbytes
));
444 regmap_write(rpc
->regmap
, RPCIF_SMENR
, smenr
);
446 memcpy(data
, rpc
->buffer
+ pos
, nbytes
);
448 regmap_write(rpc
->regmap
, RPCIF_SMWDR1
,
450 regmap_write(rpc
->regmap
, RPCIF_SMWDR0
,
453 regmap_write(rpc
->regmap
, RPCIF_SMWDR0
,
457 regmap_write(rpc
->regmap
, RPCIF_SMCR
, smcr
);
458 ret
= wait_msg_xfer_end(rpc
);
463 smenr
= rpc
->enable
&
464 ~RPCIF_SMENR_CDE
& ~RPCIF_SMENR_ADE(0xF);
469 * RPC-IF spoils the data for the commands without an address
470 * phase (like RDID) in the manual mode, so we'll have to work
471 * around this issue by using the external address space read
474 if (!(smenr
& RPCIF_SMENR_ADE(0xF)) && rpc
->dirmap
) {
477 regmap_update_bits(rpc
->regmap
, RPCIF_CMNCR
,
479 regmap_write(rpc
->regmap
, RPCIF_DRCR
,
480 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE
);
481 regmap_write(rpc
->regmap
, RPCIF_DRCMR
, rpc
->command
);
482 regmap_write(rpc
->regmap
, RPCIF_DREAR
,
484 regmap_write(rpc
->regmap
, RPCIF_DROPR
, rpc
->option
);
485 regmap_write(rpc
->regmap
, RPCIF_DRENR
,
486 smenr
& ~RPCIF_SMENR_SPIDE(0xF));
487 regmap_write(rpc
->regmap
, RPCIF_DRDMCR
, rpc
->dummy
);
488 regmap_write(rpc
->regmap
, RPCIF_DRDRENR
, rpc
->ddr
);
489 memcpy_fromio(rpc
->buffer
, rpc
->dirmap
, rpc
->xferlen
);
490 regmap_write(rpc
->regmap
, RPCIF_DRCR
, RPCIF_DRCR_RCF
);
491 /* Dummy read according to spec */
492 regmap_read(rpc
->regmap
, RPCIF_DRCR
, &dummy
);
495 while (pos
< rpc
->xferlen
) {
496 u32 bytes_left
= rpc
->xferlen
- pos
;
499 /* nbytes may only be 1, 2, 4, or 8 */
500 nbytes
= bytes_left
>= max
? max
: (1 << ilog2(bytes_left
));
502 regmap_write(rpc
->regmap
, RPCIF_SMADR
,
504 smenr
&= ~RPCIF_SMENR_SPIDE(0xF);
505 smenr
|= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc
, nbytes
));
506 regmap_write(rpc
->regmap
, RPCIF_SMENR
, smenr
);
507 regmap_write(rpc
->regmap
, RPCIF_SMCR
,
508 rpc
->smcr
| RPCIF_SMCR_SPIE
);
509 ret
= wait_msg_xfer_end(rpc
);
514 regmap_read(rpc
->regmap
, RPCIF_SMRDR1
,
516 regmap_read(rpc
->regmap
, RPCIF_SMRDR0
,
519 regmap_read(rpc
->regmap
, RPCIF_SMRDR0
,
522 memcpy(rpc
->buffer
+ pos
, data
, nbytes
);
528 regmap_write(rpc
->regmap
, RPCIF_SMENR
, rpc
->enable
);
529 regmap_write(rpc
->regmap
, RPCIF_SMCR
,
530 rpc
->smcr
| RPCIF_SMCR_SPIE
);
531 ret
= wait_msg_xfer_end(rpc
);
537 pm_runtime_put(rpc
->dev
);
541 if (reset_control_reset(rpc
->rstc
))
542 dev_err(rpc
->dev
, "Failed to reset HW\n");
543 rpcif_hw_init(rpc
, rpc
->bus_size
== 2);
546 EXPORT_SYMBOL(rpcif_manual_xfer
);
548 ssize_t
rpcif_dirmap_read(struct rpcif
*rpc
, u64 offs
, size_t len
, void *buf
)
550 loff_t from
= offs
& (RPCIF_DIRMAP_SIZE
- 1);
551 size_t size
= RPCIF_DIRMAP_SIZE
- from
;
556 pm_runtime_get_sync(rpc
->dev
);
558 regmap_update_bits(rpc
->regmap
, RPCIF_CMNCR
, RPCIF_CMNCR_MD
, 0);
559 regmap_write(rpc
->regmap
, RPCIF_DRCR
, 0);
560 regmap_write(rpc
->regmap
, RPCIF_DRCMR
, rpc
->command
);
561 regmap_write(rpc
->regmap
, RPCIF_DREAR
,
562 RPCIF_DREAR_EAV(offs
>> 25) | RPCIF_DREAR_EAC(1));
563 regmap_write(rpc
->regmap
, RPCIF_DROPR
, rpc
->option
);
564 regmap_write(rpc
->regmap
, RPCIF_DRENR
,
565 rpc
->enable
& ~RPCIF_SMENR_SPIDE(0xF));
566 regmap_write(rpc
->regmap
, RPCIF_DRDMCR
, rpc
->dummy
);
567 regmap_write(rpc
->regmap
, RPCIF_DRDRENR
, rpc
->ddr
);
569 memcpy_fromio(buf
, rpc
->dirmap
+ from
, len
);
571 pm_runtime_put(rpc
->dev
);
575 EXPORT_SYMBOL(rpcif_dirmap_read
);
577 static int rpcif_probe(struct platform_device
*pdev
)
579 struct platform_device
*vdev
;
580 struct device_node
*flash
;
584 flash
= of_get_next_child(pdev
->dev
.of_node
, NULL
);
586 dev_warn(&pdev
->dev
, "no flash node found\n");
590 if (of_device_is_compatible(flash
, "jedec,spi-nor")) {
592 } else if (of_device_is_compatible(flash
, "cfi-flash")) {
593 name
= "rpc-if-hyperflash";
596 dev_warn(&pdev
->dev
, "unknown flash type\n");
601 vdev
= platform_device_alloc(name
, pdev
->id
);
604 vdev
->dev
.parent
= &pdev
->dev
;
605 platform_set_drvdata(pdev
, vdev
);
607 ret
= platform_device_add(vdev
);
609 platform_device_put(vdev
);
616 static int rpcif_remove(struct platform_device
*pdev
)
618 struct platform_device
*vdev
= platform_get_drvdata(pdev
);
620 platform_device_unregister(vdev
);
625 static const struct of_device_id rpcif_of_match
[] = {
626 { .compatible
= "renesas,rcar-gen3-rpc-if", },
629 MODULE_DEVICE_TABLE(of
, rpcif_of_match
);
631 static struct platform_driver rpcif_driver
= {
632 .probe
= rpcif_probe
,
633 .remove
= rpcif_remove
,
636 .of_match_table
= rpcif_of_match
,
639 module_platform_driver(rpcif_driver
);
641 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
642 MODULE_LICENSE("GPL v2");