1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019 Samsung Electronics Co., Ltd.
4 * Author: Lukasz Luba <l.luba@partner.samsung.com>
8 #include <linux/devfreq.h>
9 #include <linux/devfreq-event.h>
10 #include <linux/device.h>
11 #include <linux/interrupt.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/pm_opp.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21 #include "../jedec_ddr.h"
22 #include "../of_memory.h"
24 #define EXYNOS5_DREXI_TIMINGAREF (0x0030)
25 #define EXYNOS5_DREXI_TIMINGROW0 (0x0034)
26 #define EXYNOS5_DREXI_TIMINGDATA0 (0x0038)
27 #define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C)
28 #define EXYNOS5_DREXI_TIMINGROW1 (0x00E4)
29 #define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8)
30 #define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC)
31 #define CDREX_PAUSE (0x2091c)
32 #define CDREX_LPDDR3PHY_CON3 (0x20a20)
33 #define CDREX_LPDDR3PHY_CLKM_SRC (0x20700)
34 #define EXYNOS5_TIMING_SET_SWI BIT(28)
35 #define USE_MX_MSPLL_TIMINGS (1)
36 #define USE_BPLL_TIMINGS (0)
37 #define EXYNOS5_AREF_NORMAL (0x2e)
39 #define DREX_PPCCLKCON (0x0130)
40 #define DREX_PEREV2CONFIG (0x013c)
41 #define DREX_PMNC_PPC (0xE000)
42 #define DREX_CNTENS_PPC (0xE010)
43 #define DREX_CNTENC_PPC (0xE020)
44 #define DREX_INTENS_PPC (0xE030)
45 #define DREX_INTENC_PPC (0xE040)
46 #define DREX_FLAG_PPC (0xE050)
47 #define DREX_PMCNT2_PPC (0xE130)
50 * A value for register DREX_PMNC_PPC which should be written to reset
51 * the cycle counter CCNT (a reference wall clock). It sets zero to the
54 #define CC_RESET BIT(2)
57 * A value for register DREX_PMNC_PPC which does the reset of all performance
60 #define PPC_COUNTER_RESET BIT(1)
63 * Enables all configured counters (including cycle counter). The value should
64 * be written to the register DREX_PMNC_PPC.
66 #define PPC_ENABLE BIT(0)
68 /* A value for register DREX_PPCCLKCON which enables performance events clock.
69 * Must be written before first access to the performance counters register
70 * set, otherwise it could crash.
72 #define PEREV_CLK_EN BIT(0)
75 * Values which are used to enable counters, interrupts or configure flags of
76 * the performance counters. They configure counter 2 and cycle counter.
78 #define PERF_CNT2 BIT(2)
79 #define PERF_CCNT BIT(31)
82 * Performance event types which are used for setting the preferred event
83 * to track in the counters.
84 * There is a set of different types, the values are from range 0 to 0x6f.
85 * These settings should be written to the configuration register which manages
86 * the type of the event (register DREX_PEREV2CONFIG).
88 #define READ_TRANSFER_CH0 (0x6d)
89 #define READ_TRANSFER_CH1 (0x6f)
91 #define PERF_COUNTER_START_VALUE 0xff000000
92 #define PERF_EVENT_UP_DOWN_THRESHOLD 900000000ULL
95 * struct dmc_opp_table - Operating level desciption
97 * Covers frequency and voltage settings of the DMC operating mode.
99 struct dmc_opp_table
{
105 * struct exynos5_dmc - main structure describing DMC device
107 * The main structure for the Dynamic Memory Controller which covers clocks,
108 * memory regions, HW information, parameters and current operating mode.
113 struct devfreq_simple_ondemand_data gov_data
;
114 void __iomem
*base_drexi0
;
115 void __iomem
*base_drexi1
;
116 struct regmap
*clk_regmap
;
118 unsigned long curr_rate
;
119 unsigned long curr_volt
;
120 unsigned long bypass_rate
;
121 struct dmc_opp_table
*opp
;
122 struct dmc_opp_table opp_bypass
;
124 u32 timings_arr_size
;
128 const struct lpddr3_timings
*timings
;
129 const struct lpddr3_min_tck
*min_tck
;
130 u32 bypass_timing_row
;
131 u32 bypass_timing_data
;
132 u32 bypass_timing_power
;
133 struct regulator
*vdd_mif
;
134 struct clk
*fout_spll
;
135 struct clk
*fout_bpll
;
136 struct clk
*mout_spll
;
137 struct clk
*mout_bpll
;
138 struct clk
*mout_mclk_cdrex
;
139 struct clk
*mout_mx_mspll_ccore
;
140 struct clk
*mx_mspll_ccore_phy
;
141 struct clk
*mout_mx_mspll_ccore_phy
;
142 struct devfreq_event_dev
**counter
;
144 u64 last_overflow_ts
[2];
150 #define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
151 { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
153 #define TIMING_VAL2REG(timing, t_val) \
156 __val = (t_val) << (timing)->bit_beg; \
167 static const struct timing_reg timing_row
[] = {
168 TIMING_FIELD("tRFC", 24, 31),
169 TIMING_FIELD("tRRD", 20, 23),
170 TIMING_FIELD("tRP", 16, 19),
171 TIMING_FIELD("tRCD", 12, 15),
172 TIMING_FIELD("tRC", 6, 11),
173 TIMING_FIELD("tRAS", 0, 5),
176 static const struct timing_reg timing_data
[] = {
177 TIMING_FIELD("tWTR", 28, 31),
178 TIMING_FIELD("tWR", 24, 27),
179 TIMING_FIELD("tRTP", 20, 23),
180 TIMING_FIELD("tW2W-C2C", 14, 14),
181 TIMING_FIELD("tR2R-C2C", 12, 12),
182 TIMING_FIELD("WL", 8, 11),
183 TIMING_FIELD("tDQSCK", 4, 7),
184 TIMING_FIELD("RL", 0, 3),
187 static const struct timing_reg timing_power
[] = {
188 TIMING_FIELD("tFAW", 26, 31),
189 TIMING_FIELD("tXSR", 16, 25),
190 TIMING_FIELD("tXP", 8, 15),
191 TIMING_FIELD("tCKE", 4, 7),
192 TIMING_FIELD("tMRD", 0, 3),
195 #define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \
196 ARRAY_SIZE(timing_power))
198 static int exynos5_counters_set_event(struct exynos5_dmc
*dmc
)
202 for (i
= 0; i
< dmc
->num_counters
; i
++) {
203 if (!dmc
->counter
[i
])
205 ret
= devfreq_event_set_event(dmc
->counter
[i
]);
212 static int exynos5_counters_enable_edev(struct exynos5_dmc
*dmc
)
216 for (i
= 0; i
< dmc
->num_counters
; i
++) {
217 if (!dmc
->counter
[i
])
219 ret
= devfreq_event_enable_edev(dmc
->counter
[i
]);
226 static int exynos5_counters_disable_edev(struct exynos5_dmc
*dmc
)
230 for (i
= 0; i
< dmc
->num_counters
; i
++) {
231 if (!dmc
->counter
[i
])
233 ret
= devfreq_event_disable_edev(dmc
->counter
[i
]);
241 * find_target_freq_id() - Finds requested frequency in local DMC configuration
242 * @dmc: device for which the information is checked
243 * @target_rate: requested frequency in KHz
245 * Seeks in the local DMC driver structure for the requested frequency value
246 * and returns index or error value.
248 static int find_target_freq_idx(struct exynos5_dmc
*dmc
,
249 unsigned long target_rate
)
253 for (i
= dmc
->opp_count
- 1; i
>= 0; i
--)
254 if (dmc
->opp
[i
].freq_hz
<= target_rate
)
261 * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
262 * @dmc: device for which the new settings is going to be applied
263 * @set: boolean variable passing set value
265 * Changes the register set, which holds timing parameters.
266 * There is two register sets: 0 and 1. The register set 0
267 * is used in normal operation when the clock is provided from main PLL.
268 * The bank register set 1 is used when the main PLL frequency is going to be
269 * changed and the clock is taken from alternative, stable source.
270 * This function switches between these banks according to the
271 * currently used clock source.
273 static int exynos5_switch_timing_regs(struct exynos5_dmc
*dmc
, bool set
)
278 ret
= regmap_read(dmc
->clk_regmap
, CDREX_LPDDR3PHY_CON3
, ®
);
283 reg
|= EXYNOS5_TIMING_SET_SWI
;
285 reg
&= ~EXYNOS5_TIMING_SET_SWI
;
287 regmap_write(dmc
->clk_regmap
, CDREX_LPDDR3PHY_CON3
, reg
);
293 * exynos5_init_freq_table() - Initialized PM OPP framework
294 * @dmc: DMC device for which the frequencies are used for OPP init
295 * @profile: devfreq device's profile
297 * Populate the devfreq device's OPP table based on current frequency, voltage.
299 static int exynos5_init_freq_table(struct exynos5_dmc
*dmc
,
300 struct devfreq_dev_profile
*profile
)
306 ret
= dev_pm_opp_of_add_table(dmc
->dev
);
308 dev_err(dmc
->dev
, "Failed to get OPP table\n");
312 dmc
->opp_count
= dev_pm_opp_get_opp_count(dmc
->dev
);
314 dmc
->opp
= devm_kmalloc_array(dmc
->dev
, dmc
->opp_count
,
315 sizeof(struct dmc_opp_table
), GFP_KERNEL
);
319 idx
= dmc
->opp_count
- 1;
320 for (i
= 0, freq
= ULONG_MAX
; i
< dmc
->opp_count
; i
++, freq
--) {
321 struct dev_pm_opp
*opp
;
323 opp
= dev_pm_opp_find_freq_floor(dmc
->dev
, &freq
);
327 dmc
->opp
[idx
- i
].freq_hz
= freq
;
328 dmc
->opp
[idx
- i
].volt_uv
= dev_pm_opp_get_voltage(opp
);
336 dev_pm_opp_of_remove_table(dmc
->dev
);
342 * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
343 * @dmc: device for which the new settings is going to be applied
344 * @param: DRAM parameters which passes timing data
346 * Low-level function for changing timings for DRAM memory clocking from
347 * 'bypass' clock source (fixed frequency @400MHz).
348 * It uses timing bank registers set 1.
350 static void exynos5_set_bypass_dram_timings(struct exynos5_dmc
*dmc
)
352 writel(EXYNOS5_AREF_NORMAL
,
353 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGAREF
);
355 writel(dmc
->bypass_timing_row
,
356 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGROW1
);
357 writel(dmc
->bypass_timing_row
,
358 dmc
->base_drexi1
+ EXYNOS5_DREXI_TIMINGROW1
);
359 writel(dmc
->bypass_timing_data
,
360 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGDATA1
);
361 writel(dmc
->bypass_timing_data
,
362 dmc
->base_drexi1
+ EXYNOS5_DREXI_TIMINGDATA1
);
363 writel(dmc
->bypass_timing_power
,
364 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGPOWER1
);
365 writel(dmc
->bypass_timing_power
,
366 dmc
->base_drexi1
+ EXYNOS5_DREXI_TIMINGPOWER1
);
370 * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
371 * @dmc: device for which the new settings is going to be applied
372 * @target_rate: target frequency of the DMC
374 * Low-level function for changing timings for DRAM memory operating from main
375 * clock source (BPLL), which can have different frequencies. Thus, each
376 * frequency must have corresponding timings register values in order to keep
378 * It uses timing bank registers set 0.
380 static int exynos5_dram_change_timings(struct exynos5_dmc
*dmc
,
381 unsigned long target_rate
)
385 for (idx
= dmc
->opp_count
- 1; idx
>= 0; idx
--)
386 if (dmc
->opp
[idx
].freq_hz
<= target_rate
)
392 writel(EXYNOS5_AREF_NORMAL
,
393 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGAREF
);
395 writel(dmc
->timing_row
[idx
],
396 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGROW0
);
397 writel(dmc
->timing_row
[idx
],
398 dmc
->base_drexi1
+ EXYNOS5_DREXI_TIMINGROW0
);
399 writel(dmc
->timing_data
[idx
],
400 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGDATA0
);
401 writel(dmc
->timing_data
[idx
],
402 dmc
->base_drexi1
+ EXYNOS5_DREXI_TIMINGDATA0
);
403 writel(dmc
->timing_power
[idx
],
404 dmc
->base_drexi0
+ EXYNOS5_DREXI_TIMINGPOWER0
);
405 writel(dmc
->timing_power
[idx
],
406 dmc
->base_drexi1
+ EXYNOS5_DREXI_TIMINGPOWER0
);
412 * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
413 * @dmc: device for which it is going to be set
414 * @target_volt: new voltage which is chosen to be final
416 * Function tries to align voltage to the safe level for 'normal' mode.
417 * It checks the need of higher voltage and changes the value. The target
418 * voltage might be lower that currently set and still the system will be
421 static int exynos5_dmc_align_target_voltage(struct exynos5_dmc
*dmc
,
422 unsigned long target_volt
)
426 if (dmc
->curr_volt
<= target_volt
)
429 ret
= regulator_set_voltage(dmc
->vdd_mif
, target_volt
,
432 dmc
->curr_volt
= target_volt
;
438 * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
439 * @dmc: device for which it is going to be set
440 * @target_volt: new voltage which is chosen to be final
442 * Function tries to align voltage to the safe level for the 'bypass' mode.
443 * It checks the need of higher voltage and changes the value.
444 * The target voltage must not be less than currently needed, because
445 * for current frequency the device might become unstable.
447 static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc
*dmc
,
448 unsigned long target_volt
)
451 unsigned long bypass_volt
= dmc
->opp_bypass
.volt_uv
;
453 target_volt
= max(bypass_volt
, target_volt
);
455 if (dmc
->curr_volt
>= target_volt
)
458 ret
= regulator_set_voltage(dmc
->vdd_mif
, target_volt
,
461 dmc
->curr_volt
= target_volt
;
467 * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
468 * @dmc: device for which it is going to be set
469 * @target_rate: new frequency which is chosen to be final
471 * Function changes the DRAM timings for the temporary 'bypass' mode.
473 static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc
*dmc
,
474 unsigned long target_rate
)
476 int idx
= find_target_freq_idx(dmc
, target_rate
);
481 exynos5_set_bypass_dram_timings(dmc
);
487 * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
488 * @dmc: DMC device for which the switching is going to happen
489 * @target_rate: new frequency which is going to be set as a final
490 * @target_volt: new voltage which is going to be set as a final
492 * Function configures DMC and clocks for operating in temporary 'bypass' mode.
493 * This mode is used only temporary but if required, changes voltage and timings
494 * for DRAM chips. It switches the main clock to stable clock source for the
495 * period of the main PLL reconfiguration.
498 exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc
*dmc
,
499 unsigned long target_rate
,
500 unsigned long target_volt
)
505 * Having higher voltage for a particular frequency does not harm
506 * the chip. Use it for the temporary frequency change when one
507 * voltage manipulation might be avoided.
509 ret
= exynos5_dmc_align_bypass_voltage(dmc
, target_volt
);
514 * Longer delays for DRAM does not cause crash, the opposite does.
516 ret
= exynos5_dmc_align_bypass_dram_timings(dmc
, target_rate
);
521 * Delays are long enough, so use them for the new coming clock.
523 ret
= exynos5_switch_timing_regs(dmc
, USE_MX_MSPLL_TIMINGS
);
529 * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
530 * using safe procedure
531 * @dmc: device for which the frequency is going to be changed
532 * @target_rate: requested new frequency
533 * @target_volt: requested voltage which corresponds to the new frequency
535 * The DMC frequency change procedure requires a few steps.
536 * The main requirement is to change the clock source in the clk mux
537 * for the time of main clock PLL locking. The assumption is that the
538 * alternative clock source set as parent is stable.
539 * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
540 * clock. This requires alignment in DRAM timing parameters for the new
541 * T-period. There is two bank sets for keeping DRAM
542 * timings: set 0 and set 1. The set 0 is used when main clock source is
543 * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
544 * the two bank sets is part of the process.
545 * The voltage must also be aligned to the minimum required level. There is
546 * this intermediate step with switching to 'bypass' parent clock source.
547 * if the old voltage is lower, it requires an increase of the voltage level.
548 * The complexity of the voltage manipulation is hidden in low level function.
549 * In this function there is last alignment of the voltage level at the end.
552 exynos5_dmc_change_freq_and_volt(struct exynos5_dmc
*dmc
,
553 unsigned long target_rate
,
554 unsigned long target_volt
)
558 ret
= exynos5_dmc_switch_to_bypass_configuration(dmc
, target_rate
,
564 * Voltage is set at least to a level needed for this frequency,
565 * so switching clock source is safe now.
567 clk_prepare_enable(dmc
->fout_spll
);
568 clk_prepare_enable(dmc
->mout_spll
);
569 clk_prepare_enable(dmc
->mout_mx_mspll_ccore
);
571 ret
= clk_set_parent(dmc
->mout_mclk_cdrex
, dmc
->mout_mx_mspll_ccore
);
576 * We are safe to increase the timings for current bypass frequency.
577 * Thanks to this the settings will be ready for the upcoming clock
580 exynos5_dram_change_timings(dmc
, target_rate
);
582 clk_set_rate(dmc
->fout_bpll
, target_rate
);
584 ret
= exynos5_switch_timing_regs(dmc
, USE_BPLL_TIMINGS
);
588 ret
= clk_set_parent(dmc
->mout_mclk_cdrex
, dmc
->mout_bpll
);
593 * Make sure if the voltage is not from 'bypass' settings and align to
594 * the right level for power efficiency.
596 ret
= exynos5_dmc_align_target_voltage(dmc
, target_volt
);
599 clk_disable_unprepare(dmc
->mout_mx_mspll_ccore
);
600 clk_disable_unprepare(dmc
->mout_spll
);
601 clk_disable_unprepare(dmc
->fout_spll
);
607 * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
609 * @dmc: device for which the frequency is going to be changed
610 * @freq: requested frequency in KHz
611 * @target_rate: returned frequency which is the same or lower than
613 * @target_volt: returned voltage which corresponds to the returned
616 * Function gets requested frequency and checks OPP framework for needed
617 * frequency and voltage. It populates the values 'target_rate' and
618 * 'target_volt' or returns error value when OPP framework fails.
620 static int exynos5_dmc_get_volt_freq(struct exynos5_dmc
*dmc
,
622 unsigned long *target_rate
,
623 unsigned long *target_volt
, u32 flags
)
625 struct dev_pm_opp
*opp
;
627 opp
= devfreq_recommended_opp(dmc
->dev
, freq
, flags
);
631 *target_rate
= dev_pm_opp_get_freq(opp
);
632 *target_volt
= dev_pm_opp_get_voltage(opp
);
639 * exynos5_dmc_target() - Function responsible for changing frequency of DMC
640 * @dev: device for which the frequency is going to be changed
641 * @freq: requested frequency in KHz
642 * @flags: flags provided for this frequency change request
644 * An entry function provided to the devfreq framework which provides frequency
645 * change of the DMC. The function gets the possible rate from OPP table based
646 * on requested frequency. It calls the next function responsible for the
647 * frequency and voltage change. In case of failure, does not set 'curr_rate'
648 * and returns error value to the framework.
650 static int exynos5_dmc_target(struct device
*dev
, unsigned long *freq
,
653 struct exynos5_dmc
*dmc
= dev_get_drvdata(dev
);
654 unsigned long target_rate
= 0;
655 unsigned long target_volt
= 0;
658 ret
= exynos5_dmc_get_volt_freq(dmc
, freq
, &target_rate
, &target_volt
,
664 if (target_rate
== dmc
->curr_rate
)
667 mutex_lock(&dmc
->lock
);
669 ret
= exynos5_dmc_change_freq_and_volt(dmc
, target_rate
, target_volt
);
672 mutex_unlock(&dmc
->lock
);
676 dmc
->curr_rate
= target_rate
;
678 mutex_unlock(&dmc
->lock
);
683 * exynos5_counters_get() - Gets the performance counters values.
684 * @dmc: device for which the counters are going to be checked
685 * @load_count: variable which is populated with counter value
686 * @total_count: variable which is used as 'wall clock' reference
688 * Function which provides performance counters values. It sums up counters for
689 * two DMC channels. The 'total_count' is used as a reference and max value.
690 * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
692 static int exynos5_counters_get(struct exynos5_dmc
*dmc
,
693 unsigned long *load_count
,
694 unsigned long *total_count
)
696 unsigned long total
= 0;
697 struct devfreq_event_data event
;
702 /* Take into account only read+write counters, but stop all */
703 for (i
= 0; i
< dmc
->num_counters
; i
++) {
704 if (!dmc
->counter
[i
])
707 ret
= devfreq_event_get_event(dmc
->counter
[i
], &event
);
711 *load_count
+= event
.load_count
;
713 if (total
< event
.total_count
)
714 total
= event
.total_count
;
717 *total_count
= total
;
723 * exynos5_dmc_start_perf_events() - Setup and start performance event counters
724 * @dmc: device for which the counters are going to be checked
725 * @beg_value: initial value for the counter
727 * Function which enables needed counters, interrupts and sets initial values
728 * then starts the counters.
730 static void exynos5_dmc_start_perf_events(struct exynos5_dmc
*dmc
,
733 /* Enable interrupts for counter 2 */
734 writel(PERF_CNT2
, dmc
->base_drexi0
+ DREX_INTENS_PPC
);
735 writel(PERF_CNT2
, dmc
->base_drexi1
+ DREX_INTENS_PPC
);
737 /* Enable counter 2 and CCNT */
738 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi0
+ DREX_CNTENS_PPC
);
739 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi1
+ DREX_CNTENS_PPC
);
741 /* Clear overflow flag for all counters */
742 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi0
+ DREX_FLAG_PPC
);
743 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi1
+ DREX_FLAG_PPC
);
745 /* Reset all counters */
746 writel(CC_RESET
| PPC_COUNTER_RESET
, dmc
->base_drexi0
+ DREX_PMNC_PPC
);
747 writel(CC_RESET
| PPC_COUNTER_RESET
, dmc
->base_drexi1
+ DREX_PMNC_PPC
);
750 * Set start value for the counters, the number of samples that
751 * will be gathered is calculated as: 0xffffffff - beg_value
753 writel(beg_value
, dmc
->base_drexi0
+ DREX_PMCNT2_PPC
);
754 writel(beg_value
, dmc
->base_drexi1
+ DREX_PMCNT2_PPC
);
756 /* Start all counters */
757 writel(PPC_ENABLE
, dmc
->base_drexi0
+ DREX_PMNC_PPC
);
758 writel(PPC_ENABLE
, dmc
->base_drexi1
+ DREX_PMNC_PPC
);
762 * exynos5_dmc_perf_events_calc() - Calculate utilization
763 * @dmc: device for which the counters are going to be checked
764 * @diff_ts: time between last interrupt and current one
766 * Function which calculates needed utilization for the devfreq governor.
767 * It prepares values for 'busy_time' and 'total_time' based on elapsed time
768 * between interrupts, which approximates utilization.
770 static void exynos5_dmc_perf_events_calc(struct exynos5_dmc
*dmc
, u64 diff_ts
)
773 * This is a simple algorithm for managing traffic on DMC.
774 * When there is almost no load the counters overflow every 4s,
775 * no mater the DMC frequency.
776 * The high load might be approximated using linear function.
777 * Knowing that, simple calculation can provide 'busy_time' and
778 * 'total_time' to the devfreq governor which picks up target
780 * We want a fast ramp up and slow decay in frequency change function.
782 if (diff_ts
< PERF_EVENT_UP_DOWN_THRESHOLD
) {
784 * Set higher utilization for the simple_ondemand governor.
785 * The governor should increase the frequency of the DMC.
791 * Set low utilization for the simple_ondemand governor.
792 * The governor should decrease the frequency of the DMC.
798 dev_dbg(dmc
->dev
, "diff_ts=%llu\n", diff_ts
);
802 * exynos5_dmc_perf_events_check() - Checks the status of the counters
803 * @dmc: device for which the counters are going to be checked
805 * Function which is called from threaded IRQ to check the counters state
806 * and to call approximation for the needed utilization.
808 static void exynos5_dmc_perf_events_check(struct exynos5_dmc
*dmc
)
815 /* Stop all counters */
816 writel(0, dmc
->base_drexi0
+ DREX_PMNC_PPC
);
817 writel(0, dmc
->base_drexi1
+ DREX_PMNC_PPC
);
819 /* Check the source in interrupt flag registers (which channel) */
820 val
= readl(dmc
->base_drexi0
+ DREX_FLAG_PPC
);
822 diff_ts
= ts
- dmc
->last_overflow_ts
[0];
823 dmc
->last_overflow_ts
[0] = ts
;
824 dev_dbg(dmc
->dev
, "drex0 0xE050 val= 0x%08x\n", val
);
826 val
= readl(dmc
->base_drexi1
+ DREX_FLAG_PPC
);
827 diff_ts
= ts
- dmc
->last_overflow_ts
[1];
828 dmc
->last_overflow_ts
[1] = ts
;
829 dev_dbg(dmc
->dev
, "drex1 0xE050 val= 0x%08x\n", val
);
832 exynos5_dmc_perf_events_calc(dmc
, diff_ts
);
834 exynos5_dmc_start_perf_events(dmc
, PERF_COUNTER_START_VALUE
);
838 * exynos5_dmc_enable_perf_events() - Enable performance events
839 * @dmc: device for which the counters are going to be checked
841 * Function which is setup needed environment and enables counters.
843 static void exynos5_dmc_enable_perf_events(struct exynos5_dmc
*dmc
)
847 /* Enable Performance Event Clock */
848 writel(PEREV_CLK_EN
, dmc
->base_drexi0
+ DREX_PPCCLKCON
);
849 writel(PEREV_CLK_EN
, dmc
->base_drexi1
+ DREX_PPCCLKCON
);
851 /* Select read transfers as performance event2 */
852 writel(READ_TRANSFER_CH0
, dmc
->base_drexi0
+ DREX_PEREV2CONFIG
);
853 writel(READ_TRANSFER_CH1
, dmc
->base_drexi1
+ DREX_PEREV2CONFIG
);
856 dmc
->last_overflow_ts
[0] = ts
;
857 dmc
->last_overflow_ts
[1] = ts
;
859 /* Devfreq shouldn't be faster than initialization, play safe though. */
865 * exynos5_dmc_disable_perf_events() - Disable performance events
866 * @dmc: device for which the counters are going to be checked
868 * Function which stops, disables performance event counters and interrupts.
870 static void exynos5_dmc_disable_perf_events(struct exynos5_dmc
*dmc
)
872 /* Stop all counters */
873 writel(0, dmc
->base_drexi0
+ DREX_PMNC_PPC
);
874 writel(0, dmc
->base_drexi1
+ DREX_PMNC_PPC
);
876 /* Disable interrupts for counter 2 */
877 writel(PERF_CNT2
, dmc
->base_drexi0
+ DREX_INTENC_PPC
);
878 writel(PERF_CNT2
, dmc
->base_drexi1
+ DREX_INTENC_PPC
);
880 /* Disable counter 2 and CCNT */
881 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi0
+ DREX_CNTENC_PPC
);
882 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi1
+ DREX_CNTENC_PPC
);
884 /* Clear overflow flag for all counters */
885 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi0
+ DREX_FLAG_PPC
);
886 writel(PERF_CNT2
| PERF_CCNT
, dmc
->base_drexi1
+ DREX_FLAG_PPC
);
890 * exynos5_dmc_get_status() - Read current DMC performance statistics.
891 * @dev: device for which the statistics are requested
892 * @stat: structure which has statistic fields
894 * Function reads the DMC performance counters and calculates 'busy_time'
895 * and 'total_time'. To protect from overflow, the values are shifted right
896 * by 10. After read out the counters are setup to count again.
898 static int exynos5_dmc_get_status(struct device
*dev
,
899 struct devfreq_dev_status
*stat
)
901 struct exynos5_dmc
*dmc
= dev_get_drvdata(dev
);
902 unsigned long load
, total
;
905 if (dmc
->in_irq_mode
) {
906 stat
->current_frequency
= dmc
->curr_rate
;
907 stat
->busy_time
= dmc
->load
;
908 stat
->total_time
= dmc
->total
;
910 ret
= exynos5_counters_get(dmc
, &load
, &total
);
914 /* To protect from overflow, divide by 1024 */
915 stat
->busy_time
= load
>> 10;
916 stat
->total_time
= total
>> 10;
918 ret
= exynos5_counters_set_event(dmc
);
920 dev_err(dev
, "could not set event counter\n");
929 * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
930 * @dev: device for which the framework checks operating frequency
931 * @freq: returned frequency value
933 * It returns the currently used frequency of the DMC. The real operating
934 * frequency might be lower when the clock source value could not be divided
935 * to the requested value.
937 static int exynos5_dmc_get_cur_freq(struct device
*dev
, unsigned long *freq
)
939 struct exynos5_dmc
*dmc
= dev_get_drvdata(dev
);
941 mutex_lock(&dmc
->lock
);
942 *freq
= dmc
->curr_rate
;
943 mutex_unlock(&dmc
->lock
);
949 * exynos5_dmc_df_profile - Devfreq governor's profile structure
951 * It provides to the devfreq framework needed functions and polling period.
953 static struct devfreq_dev_profile exynos5_dmc_df_profile
= {
954 .target
= exynos5_dmc_target
,
955 .get_dev_status
= exynos5_dmc_get_status
,
956 .get_cur_freq
= exynos5_dmc_get_cur_freq
,
960 * exynos5_dmc_align_initial_frequency() - Align initial frequency value
961 * @dmc: device for which the frequency is going to be set
962 * @bootloader_init_freq: initial frequency set by the bootloader in KHz
964 * The initial bootloader frequency, which is present during boot, might be
965 * different that supported frequency values in the driver. It is possible
966 * due to different PLL settings or used PLL as a source.
967 * This function provides the 'initial_freq' for the devfreq framework
968 * statistics engine which supports only registered values. Thus, some alignment
972 exynos5_dmc_align_init_freq(struct exynos5_dmc
*dmc
,
973 unsigned long bootloader_init_freq
)
975 unsigned long aligned_freq
;
978 idx
= find_target_freq_idx(dmc
, bootloader_init_freq
);
980 aligned_freq
= dmc
->opp
[idx
].freq_hz
;
982 aligned_freq
= dmc
->opp
[dmc
->opp_count
- 1].freq_hz
;
988 * create_timings_aligned() - Create register values and align with standard
989 * @dmc: device for which the frequency is going to be set
990 * @idx: speed bin in the OPP table
991 * @clk_period_ps: the period of the clock, known as tCK
993 * The function calculates timings and creates a register value ready for
994 * a frequency transition. The register contains a few timings. They are
995 * shifted by a known offset. The timing value is calculated based on memory
996 * specyfication: minimal time required and minimal cycles required.
998 static int create_timings_aligned(struct exynos5_dmc
*dmc
, u32
*reg_timing_row
,
999 u32
*reg_timing_data
, u32
*reg_timing_power
,
1003 const struct timing_reg
*reg
;
1005 if (clk_period_ps
== 0)
1008 *reg_timing_row
= 0;
1009 *reg_timing_data
= 0;
1010 *reg_timing_power
= 0;
1012 val
= dmc
->timings
->tRFC
/ clk_period_ps
;
1013 val
+= dmc
->timings
->tRFC
% clk_period_ps
? 1 : 0;
1014 val
= max(val
, dmc
->min_tck
->tRFC
);
1015 reg
= &timing_row
[0];
1016 *reg_timing_row
|= TIMING_VAL2REG(reg
, val
);
1018 val
= dmc
->timings
->tRRD
/ clk_period_ps
;
1019 val
+= dmc
->timings
->tRRD
% clk_period_ps
? 1 : 0;
1020 val
= max(val
, dmc
->min_tck
->tRRD
);
1021 reg
= &timing_row
[1];
1022 *reg_timing_row
|= TIMING_VAL2REG(reg
, val
);
1024 val
= dmc
->timings
->tRPab
/ clk_period_ps
;
1025 val
+= dmc
->timings
->tRPab
% clk_period_ps
? 1 : 0;
1026 val
= max(val
, dmc
->min_tck
->tRPab
);
1027 reg
= &timing_row
[2];
1028 *reg_timing_row
|= TIMING_VAL2REG(reg
, val
);
1030 val
= dmc
->timings
->tRCD
/ clk_period_ps
;
1031 val
+= dmc
->timings
->tRCD
% clk_period_ps
? 1 : 0;
1032 val
= max(val
, dmc
->min_tck
->tRCD
);
1033 reg
= &timing_row
[3];
1034 *reg_timing_row
|= TIMING_VAL2REG(reg
, val
);
1036 val
= dmc
->timings
->tRC
/ clk_period_ps
;
1037 val
+= dmc
->timings
->tRC
% clk_period_ps
? 1 : 0;
1038 val
= max(val
, dmc
->min_tck
->tRC
);
1039 reg
= &timing_row
[4];
1040 *reg_timing_row
|= TIMING_VAL2REG(reg
, val
);
1042 val
= dmc
->timings
->tRAS
/ clk_period_ps
;
1043 val
+= dmc
->timings
->tRAS
% clk_period_ps
? 1 : 0;
1044 val
= max(val
, dmc
->min_tck
->tRAS
);
1045 reg
= &timing_row
[5];
1046 *reg_timing_row
|= TIMING_VAL2REG(reg
, val
);
1048 /* data related timings */
1049 val
= dmc
->timings
->tWTR
/ clk_period_ps
;
1050 val
+= dmc
->timings
->tWTR
% clk_period_ps
? 1 : 0;
1051 val
= max(val
, dmc
->min_tck
->tWTR
);
1052 reg
= &timing_data
[0];
1053 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1055 val
= dmc
->timings
->tWR
/ clk_period_ps
;
1056 val
+= dmc
->timings
->tWR
% clk_period_ps
? 1 : 0;
1057 val
= max(val
, dmc
->min_tck
->tWR
);
1058 reg
= &timing_data
[1];
1059 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1061 val
= dmc
->timings
->tRTP
/ clk_period_ps
;
1062 val
+= dmc
->timings
->tRTP
% clk_period_ps
? 1 : 0;
1063 val
= max(val
, dmc
->min_tck
->tRTP
);
1064 reg
= &timing_data
[2];
1065 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1067 val
= dmc
->timings
->tW2W_C2C
/ clk_period_ps
;
1068 val
+= dmc
->timings
->tW2W_C2C
% clk_period_ps
? 1 : 0;
1069 val
= max(val
, dmc
->min_tck
->tW2W_C2C
);
1070 reg
= &timing_data
[3];
1071 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1073 val
= dmc
->timings
->tR2R_C2C
/ clk_period_ps
;
1074 val
+= dmc
->timings
->tR2R_C2C
% clk_period_ps
? 1 : 0;
1075 val
= max(val
, dmc
->min_tck
->tR2R_C2C
);
1076 reg
= &timing_data
[4];
1077 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1079 val
= dmc
->timings
->tWL
/ clk_period_ps
;
1080 val
+= dmc
->timings
->tWL
% clk_period_ps
? 1 : 0;
1081 val
= max(val
, dmc
->min_tck
->tWL
);
1082 reg
= &timing_data
[5];
1083 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1085 val
= dmc
->timings
->tDQSCK
/ clk_period_ps
;
1086 val
+= dmc
->timings
->tDQSCK
% clk_period_ps
? 1 : 0;
1087 val
= max(val
, dmc
->min_tck
->tDQSCK
);
1088 reg
= &timing_data
[6];
1089 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1091 val
= dmc
->timings
->tRL
/ clk_period_ps
;
1092 val
+= dmc
->timings
->tRL
% clk_period_ps
? 1 : 0;
1093 val
= max(val
, dmc
->min_tck
->tRL
);
1094 reg
= &timing_data
[7];
1095 *reg_timing_data
|= TIMING_VAL2REG(reg
, val
);
1097 /* power related timings */
1098 val
= dmc
->timings
->tFAW
/ clk_period_ps
;
1099 val
+= dmc
->timings
->tFAW
% clk_period_ps
? 1 : 0;
1100 val
= max(val
, dmc
->min_tck
->tFAW
);
1101 reg
= &timing_power
[0];
1102 *reg_timing_power
|= TIMING_VAL2REG(reg
, val
);
1104 val
= dmc
->timings
->tXSR
/ clk_period_ps
;
1105 val
+= dmc
->timings
->tXSR
% clk_period_ps
? 1 : 0;
1106 val
= max(val
, dmc
->min_tck
->tXSR
);
1107 reg
= &timing_power
[1];
1108 *reg_timing_power
|= TIMING_VAL2REG(reg
, val
);
1110 val
= dmc
->timings
->tXP
/ clk_period_ps
;
1111 val
+= dmc
->timings
->tXP
% clk_period_ps
? 1 : 0;
1112 val
= max(val
, dmc
->min_tck
->tXP
);
1113 reg
= &timing_power
[2];
1114 *reg_timing_power
|= TIMING_VAL2REG(reg
, val
);
1116 val
= dmc
->timings
->tCKE
/ clk_period_ps
;
1117 val
+= dmc
->timings
->tCKE
% clk_period_ps
? 1 : 0;
1118 val
= max(val
, dmc
->min_tck
->tCKE
);
1119 reg
= &timing_power
[3];
1120 *reg_timing_power
|= TIMING_VAL2REG(reg
, val
);
1122 val
= dmc
->timings
->tMRD
/ clk_period_ps
;
1123 val
+= dmc
->timings
->tMRD
% clk_period_ps
? 1 : 0;
1124 val
= max(val
, dmc
->min_tck
->tMRD
);
1125 reg
= &timing_power
[4];
1126 *reg_timing_power
|= TIMING_VAL2REG(reg
, val
);
1132 * of_get_dram_timings() - helper function for parsing DT settings for DRAM
1133 * @dmc: device for which the frequency is going to be set
1135 * The function parses DT entries with DRAM information.
1137 static int of_get_dram_timings(struct exynos5_dmc
*dmc
)
1141 struct device_node
*np_ddr
;
1142 u32 freq_mhz
, clk_period_ps
;
1144 np_ddr
= of_parse_phandle(dmc
->dev
->of_node
, "device-handle", 0);
1146 dev_warn(dmc
->dev
, "could not find 'device-handle' in DT\n");
1150 dmc
->timing_row
= devm_kmalloc_array(dmc
->dev
, TIMING_COUNT
,
1151 sizeof(u32
), GFP_KERNEL
);
1152 if (!dmc
->timing_row
)
1155 dmc
->timing_data
= devm_kmalloc_array(dmc
->dev
, TIMING_COUNT
,
1156 sizeof(u32
), GFP_KERNEL
);
1157 if (!dmc
->timing_data
)
1160 dmc
->timing_power
= devm_kmalloc_array(dmc
->dev
, TIMING_COUNT
,
1161 sizeof(u32
), GFP_KERNEL
);
1162 if (!dmc
->timing_power
)
1165 dmc
->timings
= of_lpddr3_get_ddr_timings(np_ddr
, dmc
->dev
,
1167 &dmc
->timings_arr_size
);
1168 if (!dmc
->timings
) {
1169 of_node_put(np_ddr
);
1170 dev_warn(dmc
->dev
, "could not get timings from DT\n");
1174 dmc
->min_tck
= of_lpddr3_get_min_tck(np_ddr
, dmc
->dev
);
1175 if (!dmc
->min_tck
) {
1176 of_node_put(np_ddr
);
1177 dev_warn(dmc
->dev
, "could not get tck from DT\n");
1181 /* Sorted array of OPPs with frequency ascending */
1182 for (idx
= 0; idx
< dmc
->opp_count
; idx
++) {
1183 freq_mhz
= dmc
->opp
[idx
].freq_hz
/ 1000000;
1184 clk_period_ps
= 1000000 / freq_mhz
;
1186 ret
= create_timings_aligned(dmc
, &dmc
->timing_row
[idx
],
1187 &dmc
->timing_data
[idx
],
1188 &dmc
->timing_power
[idx
],
1192 of_node_put(np_ddr
);
1194 /* Take the highest frequency's timings as 'bypass' */
1195 dmc
->bypass_timing_row
= dmc
->timing_row
[idx
- 1];
1196 dmc
->bypass_timing_data
= dmc
->timing_data
[idx
- 1];
1197 dmc
->bypass_timing_power
= dmc
->timing_power
[idx
- 1];
1203 * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
1204 * @dmc: DMC structure containing needed fields
1206 * Get the needed clocks defined in DT device, enable and set the right parents.
1207 * Read current frequency and initialize the initial rate for governor.
1209 static int exynos5_dmc_init_clks(struct exynos5_dmc
*dmc
)
1212 unsigned long target_volt
= 0;
1213 unsigned long target_rate
= 0;
1216 dmc
->fout_spll
= devm_clk_get(dmc
->dev
, "fout_spll");
1217 if (IS_ERR(dmc
->fout_spll
))
1218 return PTR_ERR(dmc
->fout_spll
);
1220 dmc
->fout_bpll
= devm_clk_get(dmc
->dev
, "fout_bpll");
1221 if (IS_ERR(dmc
->fout_bpll
))
1222 return PTR_ERR(dmc
->fout_bpll
);
1224 dmc
->mout_mclk_cdrex
= devm_clk_get(dmc
->dev
, "mout_mclk_cdrex");
1225 if (IS_ERR(dmc
->mout_mclk_cdrex
))
1226 return PTR_ERR(dmc
->mout_mclk_cdrex
);
1228 dmc
->mout_bpll
= devm_clk_get(dmc
->dev
, "mout_bpll");
1229 if (IS_ERR(dmc
->mout_bpll
))
1230 return PTR_ERR(dmc
->mout_bpll
);
1232 dmc
->mout_mx_mspll_ccore
= devm_clk_get(dmc
->dev
,
1233 "mout_mx_mspll_ccore");
1234 if (IS_ERR(dmc
->mout_mx_mspll_ccore
))
1235 return PTR_ERR(dmc
->mout_mx_mspll_ccore
);
1237 dmc
->mout_spll
= devm_clk_get(dmc
->dev
, "ff_dout_spll2");
1238 if (IS_ERR(dmc
->mout_spll
)) {
1239 dmc
->mout_spll
= devm_clk_get(dmc
->dev
, "mout_sclk_spll");
1240 if (IS_ERR(dmc
->mout_spll
))
1241 return PTR_ERR(dmc
->mout_spll
);
1245 * Convert frequency to KHz values and set it for the governor.
1247 dmc
->curr_rate
= clk_get_rate(dmc
->mout_mclk_cdrex
);
1248 dmc
->curr_rate
= exynos5_dmc_align_init_freq(dmc
, dmc
->curr_rate
);
1249 exynos5_dmc_df_profile
.initial_freq
= dmc
->curr_rate
;
1251 ret
= exynos5_dmc_get_volt_freq(dmc
, &dmc
->curr_rate
, &target_rate
,
1256 dmc
->curr_volt
= target_volt
;
1258 clk_set_parent(dmc
->mout_mx_mspll_ccore
, dmc
->mout_spll
);
1260 dmc
->bypass_rate
= clk_get_rate(dmc
->mout_mx_mspll_ccore
);
1262 clk_prepare_enable(dmc
->fout_bpll
);
1263 clk_prepare_enable(dmc
->mout_bpll
);
1266 * Some bootloaders do not set clock routes correctly.
1267 * Stop one path in clocks to PHY.
1269 regmap_read(dmc
->clk_regmap
, CDREX_LPDDR3PHY_CLKM_SRC
, &tmp
);
1270 tmp
&= ~(BIT(1) | BIT(0));
1271 regmap_write(dmc
->clk_regmap
, CDREX_LPDDR3PHY_CLKM_SRC
, tmp
);
1277 * exynos5_performance_counters_init() - Initializes performance DMC's counters
1278 * @dmc: DMC for which it does the setup
1280 * Initialization of performance counters in DMC for estimating usage.
1281 * The counter's values are used for calculation of a memory bandwidth and based
1282 * on that the governor changes the frequency.
1283 * The counters are not used when the governor is GOVERNOR_USERSPACE.
1285 static int exynos5_performance_counters_init(struct exynos5_dmc
*dmc
)
1290 dmc
->num_counters
= devfreq_event_get_edev_count(dmc
->dev
);
1291 if (dmc
->num_counters
< 0) {
1292 dev_err(dmc
->dev
, "could not get devfreq-event counters\n");
1293 return dmc
->num_counters
;
1296 counters_size
= sizeof(struct devfreq_event_dev
) * dmc
->num_counters
;
1297 dmc
->counter
= devm_kzalloc(dmc
->dev
, counters_size
, GFP_KERNEL
);
1301 for (i
= 0; i
< dmc
->num_counters
; i
++) {
1303 devfreq_event_get_edev_by_phandle(dmc
->dev
, i
);
1304 if (IS_ERR_OR_NULL(dmc
->counter
[i
]))
1305 return -EPROBE_DEFER
;
1308 ret
= exynos5_counters_enable_edev(dmc
);
1310 dev_err(dmc
->dev
, "could not enable event counter\n");
1314 ret
= exynos5_counters_set_event(dmc
);
1316 exynos5_counters_disable_edev(dmc
);
1317 dev_err(dmc
->dev
, "could not set event counter\n");
1325 * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
1326 * @dmc: device which is used for changing this feature
1327 * @set: a boolean state passing enable/disable request
1329 * There is a need of pausing DREX DMC when divider or MUX in clock tree
1330 * changes its configuration. In such situation access to the memory is blocked
1331 * in DMC automatically. This feature is used when clock frequency change
1332 * request appears and touches clock tree.
1334 static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc
*dmc
)
1339 ret
= regmap_read(dmc
->clk_regmap
, CDREX_PAUSE
, &val
);
1344 regmap_write(dmc
->clk_regmap
, CDREX_PAUSE
, val
);
1349 static irqreturn_t
dmc_irq_thread(int irq
, void *priv
)
1352 struct exynos5_dmc
*dmc
= priv
;
1354 mutex_lock(&dmc
->df
->lock
);
1355 exynos5_dmc_perf_events_check(dmc
);
1356 res
= update_devfreq(dmc
->df
);
1357 mutex_unlock(&dmc
->df
->lock
);
1360 dev_warn(dmc
->dev
, "devfreq failed with %d\n", res
);
1366 * exynos5_dmc_probe() - Probe function for the DMC driver
1367 * @pdev: platform device for which the driver is going to be initialized
1369 * Initialize basic components: clocks, regulators, performance counters, etc.
1370 * Read out product version and based on the information setup
1371 * internal structures for the controller (frequency and voltage) and for DRAM
1372 * memory parameters: timings for each operating frequency.
1373 * Register new devfreq device for controlling DVFS of the DMC.
1375 static int exynos5_dmc_probe(struct platform_device
*pdev
)
1378 struct device
*dev
= &pdev
->dev
;
1379 struct device_node
*np
= dev
->of_node
;
1380 struct exynos5_dmc
*dmc
;
1383 dmc
= devm_kzalloc(dev
, sizeof(*dmc
), GFP_KERNEL
);
1387 mutex_init(&dmc
->lock
);
1390 platform_set_drvdata(pdev
, dmc
);
1392 dmc
->base_drexi0
= devm_platform_ioremap_resource(pdev
, 0);
1393 if (IS_ERR(dmc
->base_drexi0
))
1394 return PTR_ERR(dmc
->base_drexi0
);
1396 dmc
->base_drexi1
= devm_platform_ioremap_resource(pdev
, 1);
1397 if (IS_ERR(dmc
->base_drexi1
))
1398 return PTR_ERR(dmc
->base_drexi1
);
1400 dmc
->clk_regmap
= syscon_regmap_lookup_by_phandle(np
,
1401 "samsung,syscon-clk");
1402 if (IS_ERR(dmc
->clk_regmap
))
1403 return PTR_ERR(dmc
->clk_regmap
);
1405 ret
= exynos5_init_freq_table(dmc
, &exynos5_dmc_df_profile
);
1407 dev_warn(dev
, "couldn't initialize frequency settings\n");
1411 dmc
->vdd_mif
= devm_regulator_get(dev
, "vdd");
1412 if (IS_ERR(dmc
->vdd_mif
)) {
1413 ret
= PTR_ERR(dmc
->vdd_mif
);
1417 ret
= exynos5_dmc_init_clks(dmc
);
1421 ret
= of_get_dram_timings(dmc
);
1423 dev_warn(dev
, "couldn't initialize timings settings\n");
1427 ret
= exynos5_dmc_set_pause_on_switching(dmc
);
1429 dev_warn(dev
, "couldn't get access to PAUSE register\n");
1433 /* There is two modes in which the driver works: polling or IRQ */
1434 irq
[0] = platform_get_irq_byname(pdev
, "drex_0");
1435 irq
[1] = platform_get_irq_byname(pdev
, "drex_1");
1436 if (irq
[0] > 0 && irq
[1] > 0) {
1437 ret
= devm_request_threaded_irq(dev
, irq
[0], NULL
,
1438 dmc_irq_thread
, IRQF_ONESHOT
,
1439 dev_name(dev
), dmc
);
1441 dev_err(dev
, "couldn't grab IRQ\n");
1445 ret
= devm_request_threaded_irq(dev
, irq
[1], NULL
,
1446 dmc_irq_thread
, IRQF_ONESHOT
,
1447 dev_name(dev
), dmc
);
1449 dev_err(dev
, "couldn't grab IRQ\n");
1454 * Setup default thresholds for the devfreq governor.
1455 * The values are chosen based on experiments.
1457 dmc
->gov_data
.upthreshold
= 55;
1458 dmc
->gov_data
.downdifferential
= 5;
1460 exynos5_dmc_enable_perf_events(dmc
);
1462 dmc
->in_irq_mode
= 1;
1464 ret
= exynos5_performance_counters_init(dmc
);
1466 dev_warn(dev
, "couldn't probe performance counters\n");
1471 * Setup default thresholds for the devfreq governor.
1472 * The values are chosen based on experiments.
1474 dmc
->gov_data
.upthreshold
= 30;
1475 dmc
->gov_data
.downdifferential
= 5;
1477 exynos5_dmc_df_profile
.polling_ms
= 500;
1481 dmc
->df
= devm_devfreq_add_device(dev
, &exynos5_dmc_df_profile
,
1482 DEVFREQ_GOV_SIMPLE_ONDEMAND
,
1485 if (IS_ERR(dmc
->df
)) {
1486 ret
= PTR_ERR(dmc
->df
);
1487 goto err_devfreq_add
;
1490 if (dmc
->in_irq_mode
)
1491 exynos5_dmc_start_perf_events(dmc
, PERF_COUNTER_START_VALUE
);
1493 dev_info(dev
, "DMC initialized\n");
1498 if (dmc
->in_irq_mode
)
1499 exynos5_dmc_disable_perf_events(dmc
);
1501 exynos5_counters_disable_edev(dmc
);
1503 clk_disable_unprepare(dmc
->mout_bpll
);
1504 clk_disable_unprepare(dmc
->fout_bpll
);
1510 * exynos5_dmc_remove() - Remove function for the platform device
1511 * @pdev: platform device which is going to be removed
1513 * The function relies on 'devm' framework function which automatically
1514 * clean the device's resources. It just calls explicitly disable function for
1515 * the performance counters.
1517 static int exynos5_dmc_remove(struct platform_device
*pdev
)
1519 struct exynos5_dmc
*dmc
= dev_get_drvdata(&pdev
->dev
);
1521 if (dmc
->in_irq_mode
)
1522 exynos5_dmc_disable_perf_events(dmc
);
1524 exynos5_counters_disable_edev(dmc
);
1526 clk_disable_unprepare(dmc
->mout_bpll
);
1527 clk_disable_unprepare(dmc
->fout_bpll
);
1529 dev_pm_opp_remove_table(dmc
->dev
);
1534 static const struct of_device_id exynos5_dmc_of_match
[] = {
1535 { .compatible
= "samsung,exynos5422-dmc", },
1538 MODULE_DEVICE_TABLE(of
, exynos5_dmc_of_match
);
1540 static struct platform_driver exynos5_dmc_platdrv
= {
1541 .probe
= exynos5_dmc_probe
,
1542 .remove
= exynos5_dmc_remove
,
1544 .name
= "exynos5-dmc",
1545 .of_match_table
= exynos5_dmc_of_match
,
1548 module_platform_driver(exynos5_dmc_platdrv
);
1549 MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change");
1550 MODULE_LICENSE("GPL v2");
1551 MODULE_AUTHOR("Lukasz Luba");