2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
19 #define MC_INTSTATUS 0x000
20 #define MC_INT_DECERR_MTS (1 << 16)
21 #define MC_INT_SECERR_SEC (1 << 13)
22 #define MC_INT_DECERR_VPR (1 << 12)
23 #define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
24 #define MC_INT_INVALID_SMMU_PAGE (1 << 10)
25 #define MC_INT_ARBITRATION_EMEM (1 << 9)
26 #define MC_INT_SECURITY_VIOLATION (1 << 8)
27 #define MC_INT_DECERR_EMEM (1 << 6)
29 #define MC_INTMASK 0x004
31 #define MC_ERR_STATUS 0x08
32 #define MC_ERR_STATUS_TYPE_SHIFT 28
33 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
34 #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
35 #define MC_ERR_STATUS_READABLE (1 << 27)
36 #define MC_ERR_STATUS_WRITABLE (1 << 26)
37 #define MC_ERR_STATUS_NONSECURE (1 << 25)
38 #define MC_ERR_STATUS_ADR_HI_SHIFT 20
39 #define MC_ERR_STATUS_ADR_HI_MASK 0x3
40 #define MC_ERR_STATUS_SECURITY (1 << 17)
41 #define MC_ERR_STATUS_RW (1 << 16)
42 #define MC_ERR_STATUS_CLIENT_MASK 0x7f
44 #define MC_ERR_ADR 0x0c
46 #define MC_EMEM_ARB_CFG 0x90
47 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
48 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
49 #define MC_EMEM_ARB_MISC0 0xd8
51 static const struct of_device_id tegra_mc_of_match
[] = {
52 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
53 { .compatible
= "nvidia,tegra30-mc", .data
= &tegra30_mc_soc
},
55 #ifdef CONFIG_ARCH_TEGRA_114_SOC
56 { .compatible
= "nvidia,tegra114-mc", .data
= &tegra114_mc_soc
},
58 #ifdef CONFIG_ARCH_TEGRA_124_SOC
59 { .compatible
= "nvidia,tegra124-mc", .data
= &tegra124_mc_soc
},
63 MODULE_DEVICE_TABLE(of
, tegra_mc_of_match
);
65 static int tegra_mc_setup_latency_allowance(struct tegra_mc
*mc
)
67 unsigned long long tick
;
71 /* compute the number of MC clock cycles per tick */
72 tick
= mc
->tick
* clk_get_rate(mc
->clk
);
73 do_div(tick
, NSEC_PER_SEC
);
75 value
= readl(mc
->regs
+ MC_EMEM_ARB_CFG
);
76 value
&= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK
;
77 value
|= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick
);
78 writel(value
, mc
->regs
+ MC_EMEM_ARB_CFG
);
80 /* write latency allowance defaults */
81 for (i
= 0; i
< mc
->soc
->num_clients
; i
++) {
82 const struct tegra_mc_la
*la
= &mc
->soc
->clients
[i
].la
;
85 value
= readl(mc
->regs
+ la
->reg
);
86 value
&= ~(la
->mask
<< la
->shift
);
87 value
|= (la
->def
& la
->mask
) << la
->shift
;
88 writel(value
, mc
->regs
+ la
->reg
);
94 static const char *const status_names
[32] = {
95 [ 1] = "External interrupt",
96 [ 6] = "EMEM address decode error",
97 [ 8] = "Security violation",
98 [ 9] = "EMEM arbitration error",
100 [11] = "Invalid APB ASID update",
101 [12] = "VPR violation",
102 [13] = "Secure carveout violation",
103 [16] = "MTS carveout violation",
106 static const char *const error_names
[8] = {
107 [2] = "EMEM decode error",
108 [3] = "TrustZone violation",
109 [4] = "Carveout violation",
110 [6] = "SMMU translation error",
113 static irqreturn_t
tegra_mc_irq(int irq
, void *data
)
115 struct tegra_mc
*mc
= data
;
116 unsigned long status
, mask
;
119 /* mask all interrupts to avoid flooding */
120 status
= mc_readl(mc
, MC_INTSTATUS
);
121 mask
= mc_readl(mc
, MC_INTMASK
);
123 for_each_set_bit(bit
, &status
, 32) {
124 const char *error
= status_names
[bit
] ?: "unknown";
125 const char *client
= "unknown", *desc
;
126 const char *direction
, *secure
;
127 phys_addr_t addr
= 0;
133 value
= mc_readl(mc
, MC_ERR_STATUS
);
135 #ifdef CONFIG_PHYS_ADDR_T_64BIT
136 if (mc
->soc
->num_address_bits
> 32) {
137 addr
= ((value
>> MC_ERR_STATUS_ADR_HI_SHIFT
) &
138 MC_ERR_STATUS_ADR_HI_MASK
);
143 if (value
& MC_ERR_STATUS_RW
)
148 if (value
& MC_ERR_STATUS_SECURITY
)
153 id
= value
& MC_ERR_STATUS_CLIENT_MASK
;
155 for (i
= 0; i
< mc
->soc
->num_clients
; i
++) {
156 if (mc
->soc
->clients
[i
].id
== id
) {
157 client
= mc
->soc
->clients
[i
].name
;
162 type
= (value
& MC_ERR_STATUS_TYPE_MASK
) >>
163 MC_ERR_STATUS_TYPE_SHIFT
;
164 desc
= error_names
[type
];
166 switch (value
& MC_ERR_STATUS_TYPE_MASK
) {
167 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE
:
171 if (value
& MC_ERR_STATUS_READABLE
)
176 if (value
& MC_ERR_STATUS_WRITABLE
)
181 if (value
& MC_ERR_STATUS_NONSECURE
)
195 value
= mc_readl(mc
, MC_ERR_ADR
);
198 dev_err_ratelimited(mc
->dev
, "%s: %s%s @%pa: %s (%s%s)\n",
199 client
, secure
, direction
, &addr
, error
,
203 /* clear interrupts */
204 mc_writel(mc
, status
, MC_INTSTATUS
);
209 static int tegra_mc_probe(struct platform_device
*pdev
)
211 const struct of_device_id
*match
;
212 struct resource
*res
;
217 match
= of_match_node(tegra_mc_of_match
, pdev
->dev
.of_node
);
221 mc
= devm_kzalloc(&pdev
->dev
, sizeof(*mc
), GFP_KERNEL
);
225 platform_set_drvdata(pdev
, mc
);
226 mc
->soc
= match
->data
;
227 mc
->dev
= &pdev
->dev
;
229 /* length of MC tick in nanoseconds */
232 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
233 mc
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
234 if (IS_ERR(mc
->regs
))
235 return PTR_ERR(mc
->regs
);
237 mc
->clk
= devm_clk_get(&pdev
->dev
, "mc");
238 if (IS_ERR(mc
->clk
)) {
239 dev_err(&pdev
->dev
, "failed to get MC clock: %ld\n",
241 return PTR_ERR(mc
->clk
);
244 err
= tegra_mc_setup_latency_allowance(mc
);
246 dev_err(&pdev
->dev
, "failed to setup latency allowance: %d\n",
251 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU
)) {
252 mc
->smmu
= tegra_smmu_probe(&pdev
->dev
, mc
->soc
->smmu
, mc
);
253 if (IS_ERR(mc
->smmu
)) {
254 dev_err(&pdev
->dev
, "failed to probe SMMU: %ld\n",
256 return PTR_ERR(mc
->smmu
);
260 mc
->irq
= platform_get_irq(pdev
, 0);
262 dev_err(&pdev
->dev
, "interrupt not specified\n");
266 err
= devm_request_irq(&pdev
->dev
, mc
->irq
, tegra_mc_irq
, IRQF_SHARED
,
267 dev_name(&pdev
->dev
), mc
);
269 dev_err(&pdev
->dev
, "failed to request IRQ#%u: %d\n", mc
->irq
,
274 value
= MC_INT_DECERR_MTS
| MC_INT_SECERR_SEC
| MC_INT_DECERR_VPR
|
275 MC_INT_INVALID_APB_ASID_UPDATE
| MC_INT_INVALID_SMMU_PAGE
|
276 MC_INT_ARBITRATION_EMEM
| MC_INT_SECURITY_VIOLATION
|
278 mc_writel(mc
, value
, MC_INTMASK
);
283 static struct platform_driver tegra_mc_driver
= {
286 .of_match_table
= tegra_mc_of_match
,
287 .suppress_bind_attrs
= true,
289 .prevent_deferred_probe
= true,
290 .probe
= tegra_mc_probe
,
293 static int tegra_mc_init(void)
295 return platform_driver_register(&tegra_mc_driver
);
297 arch_initcall(tegra_mc_init
);
299 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
300 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
301 MODULE_LICENSE("GPL v2");