2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <asm/cacheflush.h>
14 #include <dt-bindings/memory/tegra114-mc.h>
18 static const struct tegra_mc_client tegra114_mc_clients
[] = {
22 .swgroup
= TEGRA_SWGROUP_PTC
,
26 .swgroup
= TEGRA_SWGROUP_DC
,
40 .swgroup
= TEGRA_SWGROUP_DCB
,
54 .swgroup
= TEGRA_SWGROUP_DC
,
68 .swgroup
= TEGRA_SWGROUP_DCB
,
82 .swgroup
= TEGRA_SWGROUP_DC
,
96 .swgroup
= TEGRA_SWGROUP_DCB
,
110 .swgroup
= TEGRA_SWGROUP_EPP
,
124 .swgroup
= TEGRA_SWGROUP_G2
,
138 .swgroup
= TEGRA_SWGROUP_G2
,
152 .swgroup
= TEGRA_SWGROUP_AVPC
,
166 .swgroup
= TEGRA_SWGROUP_DC
,
179 .name
= "displayhcb",
180 .swgroup
= TEGRA_SWGROUP_DCB
,
194 .swgroup
= TEGRA_SWGROUP_NV
,
208 .swgroup
= TEGRA_SWGROUP_NV
,
222 .swgroup
= TEGRA_SWGROUP_G2
,
236 .swgroup
= TEGRA_SWGROUP_HDA
,
249 .name
= "host1xdmar",
250 .swgroup
= TEGRA_SWGROUP_HC
,
264 .swgroup
= TEGRA_SWGROUP_HC
,
278 .swgroup
= TEGRA_SWGROUP_NV
,
292 .swgroup
= TEGRA_SWGROUP_MSENC
,
305 .name
= "ppcsahbdmar",
306 .swgroup
= TEGRA_SWGROUP_PPCS
,
319 .name
= "ppcsahbslvr",
320 .swgroup
= TEGRA_SWGROUP_PPCS
,
334 .swgroup
= TEGRA_SWGROUP_NV
,
348 .swgroup
= TEGRA_SWGROUP_VDE
,
362 .swgroup
= TEGRA_SWGROUP_VDE
,
376 .swgroup
= TEGRA_SWGROUP_VDE
,
390 .swgroup
= TEGRA_SWGROUP_VDE
,
404 .swgroup
= TEGRA_SWGROUP_MPCORELP
,
414 .swgroup
= TEGRA_SWGROUP_MPCORE
,
424 .swgroup
= TEGRA_SWGROUP_EPP
,
438 .swgroup
= TEGRA_SWGROUP_EPP
,
452 .swgroup
= TEGRA_SWGROUP_EPP
,
466 .swgroup
= TEGRA_SWGROUP_MSENC
,
480 .swgroup
= TEGRA_SWGROUP_VI
,
494 .swgroup
= TEGRA_SWGROUP_VI
,
508 .swgroup
= TEGRA_SWGROUP_VI
,
522 .swgroup
= TEGRA_SWGROUP_VI
,
536 .swgroup
= TEGRA_SWGROUP_G2
,
550 .swgroup
= TEGRA_SWGROUP_AVPC
,
564 .swgroup
= TEGRA_SWGROUP_NV
,
578 .swgroup
= TEGRA_SWGROUP_NV
,
592 .swgroup
= TEGRA_SWGROUP_HDA
,
606 .swgroup
= TEGRA_SWGROUP_HC
,
620 .swgroup
= TEGRA_SWGROUP_ISP
,
634 .swgroup
= TEGRA_SWGROUP_MPCORELP
,
644 .swgroup
= TEGRA_SWGROUP_MPCORE
,
653 .name
= "ppcsahbdmaw",
654 .swgroup
= TEGRA_SWGROUP_PPCS
,
667 .name
= "ppcsahbslvw",
668 .swgroup
= TEGRA_SWGROUP_PPCS
,
682 .swgroup
= TEGRA_SWGROUP_VDE
,
696 .swgroup
= TEGRA_SWGROUP_VDE
,
710 .swgroup
= TEGRA_SWGROUP_VDE
,
724 .swgroup
= TEGRA_SWGROUP_VDE
,
737 .name
= "xusb_hostr",
738 .swgroup
= TEGRA_SWGROUP_XUSB_HOST
,
751 .name
= "xusb_hostw",
752 .swgroup
= TEGRA_SWGROUP_XUSB_HOST
,
766 .swgroup
= TEGRA_SWGROUP_XUSB_DEV
,
780 .swgroup
= TEGRA_SWGROUP_XUSB_DEV
,
794 .swgroup
= TEGRA_SWGROUP_NV
,
808 .swgroup
= TEGRA_SWGROUP_NV
,
822 .swgroup
= TEGRA_SWGROUP_NV
,
836 .swgroup
= TEGRA_SWGROUP_NV
,
850 .swgroup
= TEGRA_SWGROUP_EMUCIF
,
860 .swgroup
= TEGRA_SWGROUP_EMUCIF
,
870 .swgroup
= TEGRA_SWGROUP_TSEC
,
884 .swgroup
= TEGRA_SWGROUP_TSEC
,
898 static const struct tegra_smmu_swgroup tegra114_swgroups
[] = {
899 { .name
= "dc", .swgroup
= TEGRA_SWGROUP_DC
, .reg
= 0x240 },
900 { .name
= "dcb", .swgroup
= TEGRA_SWGROUP_DCB
, .reg
= 0x244 },
901 { .name
= "epp", .swgroup
= TEGRA_SWGROUP_EPP
, .reg
= 0x248 },
902 { .name
= "g2", .swgroup
= TEGRA_SWGROUP_G2
, .reg
= 0x24c },
903 { .name
= "avpc", .swgroup
= TEGRA_SWGROUP_AVPC
, .reg
= 0x23c },
904 { .name
= "nv", .swgroup
= TEGRA_SWGROUP_NV
, .reg
= 0x268 },
905 { .name
= "hda", .swgroup
= TEGRA_SWGROUP_HDA
, .reg
= 0x254 },
906 { .name
= "hc", .swgroup
= TEGRA_SWGROUP_HC
, .reg
= 0x250 },
907 { .name
= "msenc", .swgroup
= TEGRA_SWGROUP_MSENC
, .reg
= 0x264 },
908 { .name
= "ppcs", .swgroup
= TEGRA_SWGROUP_PPCS
, .reg
= 0x270 },
909 { .name
= "vde", .swgroup
= TEGRA_SWGROUP_VDE
, .reg
= 0x27c },
910 { .name
= "vi", .swgroup
= TEGRA_SWGROUP_VI
, .reg
= 0x280 },
911 { .name
= "isp", .swgroup
= TEGRA_SWGROUP_ISP
, .reg
= 0x258 },
912 { .name
= "xusb_host", .swgroup
= TEGRA_SWGROUP_XUSB_HOST
, .reg
= 0x288 },
913 { .name
= "xusb_dev", .swgroup
= TEGRA_SWGROUP_XUSB_DEV
, .reg
= 0x28c },
914 { .name
= "tsec", .swgroup
= TEGRA_SWGROUP_TSEC
, .reg
= 0x294 },
917 static void tegra114_flush_dcache(struct page
*page
, unsigned long offset
,
920 phys_addr_t phys
= page_to_phys(page
) + offset
;
921 void *virt
= page_address(page
) + offset
;
923 __cpuc_flush_dcache_area(virt
, size
);
924 outer_flush_range(phys
, phys
+ size
);
927 static const struct tegra_smmu_ops tegra114_smmu_ops
= {
928 .flush_dcache
= tegra114_flush_dcache
,
931 static const struct tegra_smmu_soc tegra114_smmu_soc
= {
932 .clients
= tegra114_mc_clients
,
933 .num_clients
= ARRAY_SIZE(tegra114_mc_clients
),
934 .swgroups
= tegra114_swgroups
,
935 .num_swgroups
= ARRAY_SIZE(tegra114_swgroups
),
936 .supports_round_robin_arbitration
= false,
937 .supports_request_limit
= false,
939 .ops
= &tegra114_smmu_ops
,
942 const struct tegra_mc_soc tegra114_mc_soc
= {
943 .clients
= tegra114_mc_clients
,
944 .num_clients
= ARRAY_SIZE(tegra114_mc_clients
),
945 .num_address_bits
= 32,
947 .client_id_mask
= 0x7f,
948 .smmu
= &tegra114_smmu_soc
,