]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/memory/tegra/tegra124.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
[mirror_ubuntu-jammy-kernel.git] / drivers / memory / tegra / tegra124.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/of.h>
7 #include <linux/mm.h>
8
9 #include <dt-bindings/memory/tegra124-mc.h>
10
11 #include "mc.h"
12
13 #define MC_EMEM_ARB_CFG 0x90
14 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
15 #define MC_EMEM_ARB_TIMING_RCD 0x98
16 #define MC_EMEM_ARB_TIMING_RP 0x9c
17 #define MC_EMEM_ARB_TIMING_RC 0xa0
18 #define MC_EMEM_ARB_TIMING_RAS 0xa4
19 #define MC_EMEM_ARB_TIMING_FAW 0xa8
20 #define MC_EMEM_ARB_TIMING_RRD 0xac
21 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
22 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
23 #define MC_EMEM_ARB_TIMING_R2R 0xb8
24 #define MC_EMEM_ARB_TIMING_W2W 0xbc
25 #define MC_EMEM_ARB_TIMING_R2W 0xc0
26 #define MC_EMEM_ARB_TIMING_W2R 0xc4
27 #define MC_EMEM_ARB_DA_TURNS 0xd0
28 #define MC_EMEM_ARB_DA_COVERS 0xd4
29 #define MC_EMEM_ARB_MISC0 0xd8
30 #define MC_EMEM_ARB_MISC1 0xdc
31 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
32
33 static const unsigned long tegra124_mc_emem_regs[] = {
34 MC_EMEM_ARB_CFG,
35 MC_EMEM_ARB_OUTSTANDING_REQ,
36 MC_EMEM_ARB_TIMING_RCD,
37 MC_EMEM_ARB_TIMING_RP,
38 MC_EMEM_ARB_TIMING_RC,
39 MC_EMEM_ARB_TIMING_RAS,
40 MC_EMEM_ARB_TIMING_FAW,
41 MC_EMEM_ARB_TIMING_RRD,
42 MC_EMEM_ARB_TIMING_RAP2PRE,
43 MC_EMEM_ARB_TIMING_WAP2PRE,
44 MC_EMEM_ARB_TIMING_R2R,
45 MC_EMEM_ARB_TIMING_W2W,
46 MC_EMEM_ARB_TIMING_R2W,
47 MC_EMEM_ARB_TIMING_W2R,
48 MC_EMEM_ARB_DA_TURNS,
49 MC_EMEM_ARB_DA_COVERS,
50 MC_EMEM_ARB_MISC0,
51 MC_EMEM_ARB_MISC1,
52 MC_EMEM_ARB_RING1_THROTTLE
53 };
54
55 static const struct tegra_mc_client tegra124_mc_clients[] = {
56 {
57 .id = 0x00,
58 .name = "ptcr",
59 .swgroup = TEGRA_SWGROUP_PTC,
60 }, {
61 .id = 0x01,
62 .name = "display0a",
63 .swgroup = TEGRA_SWGROUP_DC,
64 .smmu = {
65 .reg = 0x228,
66 .bit = 1,
67 },
68 .la = {
69 .reg = 0x2e8,
70 .shift = 0,
71 .mask = 0xff,
72 .def = 0xc2,
73 },
74 }, {
75 .id = 0x02,
76 .name = "display0ab",
77 .swgroup = TEGRA_SWGROUP_DCB,
78 .smmu = {
79 .reg = 0x228,
80 .bit = 2,
81 },
82 .la = {
83 .reg = 0x2f4,
84 .shift = 0,
85 .mask = 0xff,
86 .def = 0xc6,
87 },
88 }, {
89 .id = 0x03,
90 .name = "display0b",
91 .swgroup = TEGRA_SWGROUP_DC,
92 .smmu = {
93 .reg = 0x228,
94 .bit = 3,
95 },
96 .la = {
97 .reg = 0x2e8,
98 .shift = 16,
99 .mask = 0xff,
100 .def = 0x50,
101 },
102 }, {
103 .id = 0x04,
104 .name = "display0bb",
105 .swgroup = TEGRA_SWGROUP_DCB,
106 .smmu = {
107 .reg = 0x228,
108 .bit = 4,
109 },
110 .la = {
111 .reg = 0x2f4,
112 .shift = 16,
113 .mask = 0xff,
114 .def = 0x50,
115 },
116 }, {
117 .id = 0x05,
118 .name = "display0c",
119 .swgroup = TEGRA_SWGROUP_DC,
120 .smmu = {
121 .reg = 0x228,
122 .bit = 5,
123 },
124 .la = {
125 .reg = 0x2ec,
126 .shift = 0,
127 .mask = 0xff,
128 .def = 0x50,
129 },
130 }, {
131 .id = 0x06,
132 .name = "display0cb",
133 .swgroup = TEGRA_SWGROUP_DCB,
134 .smmu = {
135 .reg = 0x228,
136 .bit = 6,
137 },
138 .la = {
139 .reg = 0x2f8,
140 .shift = 0,
141 .mask = 0xff,
142 .def = 0x50,
143 },
144 }, {
145 .id = 0x0e,
146 .name = "afir",
147 .swgroup = TEGRA_SWGROUP_AFI,
148 .smmu = {
149 .reg = 0x228,
150 .bit = 14,
151 },
152 .la = {
153 .reg = 0x2e0,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x13,
157 },
158 }, {
159 .id = 0x0f,
160 .name = "avpcarm7r",
161 .swgroup = TEGRA_SWGROUP_AVPC,
162 .smmu = {
163 .reg = 0x228,
164 .bit = 15,
165 },
166 .la = {
167 .reg = 0x2e4,
168 .shift = 0,
169 .mask = 0xff,
170 .def = 0x04,
171 },
172 }, {
173 .id = 0x10,
174 .name = "displayhc",
175 .swgroup = TEGRA_SWGROUP_DC,
176 .smmu = {
177 .reg = 0x228,
178 .bit = 16,
179 },
180 .la = {
181 .reg = 0x2f0,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x50,
185 },
186 }, {
187 .id = 0x11,
188 .name = "displayhcb",
189 .swgroup = TEGRA_SWGROUP_DCB,
190 .smmu = {
191 .reg = 0x228,
192 .bit = 17,
193 },
194 .la = {
195 .reg = 0x2fc,
196 .shift = 0,
197 .mask = 0xff,
198 .def = 0x50,
199 },
200 }, {
201 .id = 0x15,
202 .name = "hdar",
203 .swgroup = TEGRA_SWGROUP_HDA,
204 .smmu = {
205 .reg = 0x228,
206 .bit = 21,
207 },
208 .la = {
209 .reg = 0x318,
210 .shift = 0,
211 .mask = 0xff,
212 .def = 0x24,
213 },
214 }, {
215 .id = 0x16,
216 .name = "host1xdmar",
217 .swgroup = TEGRA_SWGROUP_HC,
218 .smmu = {
219 .reg = 0x228,
220 .bit = 22,
221 },
222 .la = {
223 .reg = 0x310,
224 .shift = 0,
225 .mask = 0xff,
226 .def = 0x1e,
227 },
228 }, {
229 .id = 0x17,
230 .name = "host1xr",
231 .swgroup = TEGRA_SWGROUP_HC,
232 .smmu = {
233 .reg = 0x228,
234 .bit = 23,
235 },
236 .la = {
237 .reg = 0x310,
238 .shift = 16,
239 .mask = 0xff,
240 .def = 0x50,
241 },
242 }, {
243 .id = 0x1c,
244 .name = "msencsrd",
245 .swgroup = TEGRA_SWGROUP_MSENC,
246 .smmu = {
247 .reg = 0x228,
248 .bit = 28,
249 },
250 .la = {
251 .reg = 0x328,
252 .shift = 0,
253 .mask = 0xff,
254 .def = 0x23,
255 },
256 }, {
257 .id = 0x1d,
258 .name = "ppcsahbdmar",
259 .swgroup = TEGRA_SWGROUP_PPCS,
260 .smmu = {
261 .reg = 0x228,
262 .bit = 29,
263 },
264 .la = {
265 .reg = 0x344,
266 .shift = 0,
267 .mask = 0xff,
268 .def = 0x49,
269 },
270 }, {
271 .id = 0x1e,
272 .name = "ppcsahbslvr",
273 .swgroup = TEGRA_SWGROUP_PPCS,
274 .smmu = {
275 .reg = 0x228,
276 .bit = 30,
277 },
278 .la = {
279 .reg = 0x344,
280 .shift = 16,
281 .mask = 0xff,
282 .def = 0x1a,
283 },
284 }, {
285 .id = 0x1f,
286 .name = "satar",
287 .swgroup = TEGRA_SWGROUP_SATA,
288 .smmu = {
289 .reg = 0x228,
290 .bit = 31,
291 },
292 .la = {
293 .reg = 0x350,
294 .shift = 0,
295 .mask = 0xff,
296 .def = 0x65,
297 },
298 }, {
299 .id = 0x22,
300 .name = "vdebsevr",
301 .swgroup = TEGRA_SWGROUP_VDE,
302 .smmu = {
303 .reg = 0x22c,
304 .bit = 2,
305 },
306 .la = {
307 .reg = 0x354,
308 .shift = 0,
309 .mask = 0xff,
310 .def = 0x4f,
311 },
312 }, {
313 .id = 0x23,
314 .name = "vdember",
315 .swgroup = TEGRA_SWGROUP_VDE,
316 .smmu = {
317 .reg = 0x22c,
318 .bit = 3,
319 },
320 .la = {
321 .reg = 0x354,
322 .shift = 16,
323 .mask = 0xff,
324 .def = 0x3d,
325 },
326 }, {
327 .id = 0x24,
328 .name = "vdemcer",
329 .swgroup = TEGRA_SWGROUP_VDE,
330 .smmu = {
331 .reg = 0x22c,
332 .bit = 4,
333 },
334 .la = {
335 .reg = 0x358,
336 .shift = 0,
337 .mask = 0xff,
338 .def = 0x66,
339 },
340 }, {
341 .id = 0x25,
342 .name = "vdetper",
343 .swgroup = TEGRA_SWGROUP_VDE,
344 .smmu = {
345 .reg = 0x22c,
346 .bit = 5,
347 },
348 .la = {
349 .reg = 0x358,
350 .shift = 16,
351 .mask = 0xff,
352 .def = 0xa5,
353 },
354 }, {
355 .id = 0x26,
356 .name = "mpcorelpr",
357 .swgroup = TEGRA_SWGROUP_MPCORELP,
358 .la = {
359 .reg = 0x324,
360 .shift = 0,
361 .mask = 0xff,
362 .def = 0x04,
363 },
364 }, {
365 .id = 0x27,
366 .name = "mpcorer",
367 .swgroup = TEGRA_SWGROUP_MPCORE,
368 .la = {
369 .reg = 0x320,
370 .shift = 0,
371 .mask = 0xff,
372 .def = 0x04,
373 },
374 }, {
375 .id = 0x2b,
376 .name = "msencswr",
377 .swgroup = TEGRA_SWGROUP_MSENC,
378 .smmu = {
379 .reg = 0x22c,
380 .bit = 11,
381 },
382 .la = {
383 .reg = 0x328,
384 .shift = 16,
385 .mask = 0xff,
386 .def = 0x80,
387 },
388 }, {
389 .id = 0x31,
390 .name = "afiw",
391 .swgroup = TEGRA_SWGROUP_AFI,
392 .smmu = {
393 .reg = 0x22c,
394 .bit = 17,
395 },
396 .la = {
397 .reg = 0x2e0,
398 .shift = 16,
399 .mask = 0xff,
400 .def = 0x80,
401 },
402 }, {
403 .id = 0x32,
404 .name = "avpcarm7w",
405 .swgroup = TEGRA_SWGROUP_AVPC,
406 .smmu = {
407 .reg = 0x22c,
408 .bit = 18,
409 },
410 .la = {
411 .reg = 0x2e4,
412 .shift = 16,
413 .mask = 0xff,
414 .def = 0x80,
415 },
416 }, {
417 .id = 0x35,
418 .name = "hdaw",
419 .swgroup = TEGRA_SWGROUP_HDA,
420 .smmu = {
421 .reg = 0x22c,
422 .bit = 21,
423 },
424 .la = {
425 .reg = 0x318,
426 .shift = 16,
427 .mask = 0xff,
428 .def = 0x80,
429 },
430 }, {
431 .id = 0x36,
432 .name = "host1xw",
433 .swgroup = TEGRA_SWGROUP_HC,
434 .smmu = {
435 .reg = 0x22c,
436 .bit = 22,
437 },
438 .la = {
439 .reg = 0x314,
440 .shift = 0,
441 .mask = 0xff,
442 .def = 0x80,
443 },
444 }, {
445 .id = 0x38,
446 .name = "mpcorelpw",
447 .swgroup = TEGRA_SWGROUP_MPCORELP,
448 .la = {
449 .reg = 0x324,
450 .shift = 16,
451 .mask = 0xff,
452 .def = 0x80,
453 },
454 }, {
455 .id = 0x39,
456 .name = "mpcorew",
457 .swgroup = TEGRA_SWGROUP_MPCORE,
458 .la = {
459 .reg = 0x320,
460 .shift = 16,
461 .mask = 0xff,
462 .def = 0x80,
463 },
464 }, {
465 .id = 0x3b,
466 .name = "ppcsahbdmaw",
467 .swgroup = TEGRA_SWGROUP_PPCS,
468 .smmu = {
469 .reg = 0x22c,
470 .bit = 27,
471 },
472 .la = {
473 .reg = 0x348,
474 .shift = 0,
475 .mask = 0xff,
476 .def = 0x80,
477 },
478 }, {
479 .id = 0x3c,
480 .name = "ppcsahbslvw",
481 .swgroup = TEGRA_SWGROUP_PPCS,
482 .smmu = {
483 .reg = 0x22c,
484 .bit = 28,
485 },
486 .la = {
487 .reg = 0x348,
488 .shift = 16,
489 .mask = 0xff,
490 .def = 0x80,
491 },
492 }, {
493 .id = 0x3d,
494 .name = "sataw",
495 .swgroup = TEGRA_SWGROUP_SATA,
496 .smmu = {
497 .reg = 0x22c,
498 .bit = 29,
499 },
500 .la = {
501 .reg = 0x350,
502 .shift = 16,
503 .mask = 0xff,
504 .def = 0x65,
505 },
506 }, {
507 .id = 0x3e,
508 .name = "vdebsevw",
509 .swgroup = TEGRA_SWGROUP_VDE,
510 .smmu = {
511 .reg = 0x22c,
512 .bit = 30,
513 },
514 .la = {
515 .reg = 0x35c,
516 .shift = 0,
517 .mask = 0xff,
518 .def = 0x80,
519 },
520 }, {
521 .id = 0x3f,
522 .name = "vdedbgw",
523 .swgroup = TEGRA_SWGROUP_VDE,
524 .smmu = {
525 .reg = 0x22c,
526 .bit = 31,
527 },
528 .la = {
529 .reg = 0x35c,
530 .shift = 16,
531 .mask = 0xff,
532 .def = 0x80,
533 },
534 }, {
535 .id = 0x40,
536 .name = "vdembew",
537 .swgroup = TEGRA_SWGROUP_VDE,
538 .smmu = {
539 .reg = 0x230,
540 .bit = 0,
541 },
542 .la = {
543 .reg = 0x360,
544 .shift = 0,
545 .mask = 0xff,
546 .def = 0x80,
547 },
548 }, {
549 .id = 0x41,
550 .name = "vdetpmw",
551 .swgroup = TEGRA_SWGROUP_VDE,
552 .smmu = {
553 .reg = 0x230,
554 .bit = 1,
555 },
556 .la = {
557 .reg = 0x360,
558 .shift = 16,
559 .mask = 0xff,
560 .def = 0x80,
561 },
562 }, {
563 .id = 0x44,
564 .name = "ispra",
565 .swgroup = TEGRA_SWGROUP_ISP2,
566 .smmu = {
567 .reg = 0x230,
568 .bit = 4,
569 },
570 .la = {
571 .reg = 0x370,
572 .shift = 0,
573 .mask = 0xff,
574 .def = 0x18,
575 },
576 }, {
577 .id = 0x46,
578 .name = "ispwa",
579 .swgroup = TEGRA_SWGROUP_ISP2,
580 .smmu = {
581 .reg = 0x230,
582 .bit = 6,
583 },
584 .la = {
585 .reg = 0x374,
586 .shift = 0,
587 .mask = 0xff,
588 .def = 0x80,
589 },
590 }, {
591 .id = 0x47,
592 .name = "ispwb",
593 .swgroup = TEGRA_SWGROUP_ISP2,
594 .smmu = {
595 .reg = 0x230,
596 .bit = 7,
597 },
598 .la = {
599 .reg = 0x374,
600 .shift = 16,
601 .mask = 0xff,
602 .def = 0x80,
603 },
604 }, {
605 .id = 0x4a,
606 .name = "xusb_hostr",
607 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
608 .smmu = {
609 .reg = 0x230,
610 .bit = 10,
611 },
612 .la = {
613 .reg = 0x37c,
614 .shift = 0,
615 .mask = 0xff,
616 .def = 0x39,
617 },
618 }, {
619 .id = 0x4b,
620 .name = "xusb_hostw",
621 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
622 .smmu = {
623 .reg = 0x230,
624 .bit = 11,
625 },
626 .la = {
627 .reg = 0x37c,
628 .shift = 16,
629 .mask = 0xff,
630 .def = 0x80,
631 },
632 }, {
633 .id = 0x4c,
634 .name = "xusb_devr",
635 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
636 .smmu = {
637 .reg = 0x230,
638 .bit = 12,
639 },
640 .la = {
641 .reg = 0x380,
642 .shift = 0,
643 .mask = 0xff,
644 .def = 0x39,
645 },
646 }, {
647 .id = 0x4d,
648 .name = "xusb_devw",
649 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
650 .smmu = {
651 .reg = 0x230,
652 .bit = 13,
653 },
654 .la = {
655 .reg = 0x380,
656 .shift = 16,
657 .mask = 0xff,
658 .def = 0x80,
659 },
660 }, {
661 .id = 0x4e,
662 .name = "isprab",
663 .swgroup = TEGRA_SWGROUP_ISP2B,
664 .smmu = {
665 .reg = 0x230,
666 .bit = 14,
667 },
668 .la = {
669 .reg = 0x384,
670 .shift = 0,
671 .mask = 0xff,
672 .def = 0x18,
673 },
674 }, {
675 .id = 0x50,
676 .name = "ispwab",
677 .swgroup = TEGRA_SWGROUP_ISP2B,
678 .smmu = {
679 .reg = 0x230,
680 .bit = 16,
681 },
682 .la = {
683 .reg = 0x388,
684 .shift = 0,
685 .mask = 0xff,
686 .def = 0x80,
687 },
688 }, {
689 .id = 0x51,
690 .name = "ispwbb",
691 .swgroup = TEGRA_SWGROUP_ISP2B,
692 .smmu = {
693 .reg = 0x230,
694 .bit = 17,
695 },
696 .la = {
697 .reg = 0x388,
698 .shift = 16,
699 .mask = 0xff,
700 .def = 0x80,
701 },
702 }, {
703 .id = 0x54,
704 .name = "tsecsrd",
705 .swgroup = TEGRA_SWGROUP_TSEC,
706 .smmu = {
707 .reg = 0x230,
708 .bit = 20,
709 },
710 .la = {
711 .reg = 0x390,
712 .shift = 0,
713 .mask = 0xff,
714 .def = 0x9b,
715 },
716 }, {
717 .id = 0x55,
718 .name = "tsecswr",
719 .swgroup = TEGRA_SWGROUP_TSEC,
720 .smmu = {
721 .reg = 0x230,
722 .bit = 21,
723 },
724 .la = {
725 .reg = 0x390,
726 .shift = 16,
727 .mask = 0xff,
728 .def = 0x80,
729 },
730 }, {
731 .id = 0x56,
732 .name = "a9avpscr",
733 .swgroup = TEGRA_SWGROUP_A9AVP,
734 .smmu = {
735 .reg = 0x230,
736 .bit = 22,
737 },
738 .la = {
739 .reg = 0x3a4,
740 .shift = 0,
741 .mask = 0xff,
742 .def = 0x04,
743 },
744 }, {
745 .id = 0x57,
746 .name = "a9avpscw",
747 .swgroup = TEGRA_SWGROUP_A9AVP,
748 .smmu = {
749 .reg = 0x230,
750 .bit = 23,
751 },
752 .la = {
753 .reg = 0x3a4,
754 .shift = 16,
755 .mask = 0xff,
756 .def = 0x80,
757 },
758 }, {
759 .id = 0x58,
760 .name = "gpusrd",
761 .swgroup = TEGRA_SWGROUP_GPU,
762 .smmu = {
763 /* read-only */
764 .reg = 0x230,
765 .bit = 24,
766 },
767 .la = {
768 .reg = 0x3c8,
769 .shift = 0,
770 .mask = 0xff,
771 .def = 0x1a,
772 },
773 }, {
774 .id = 0x59,
775 .name = "gpuswr",
776 .swgroup = TEGRA_SWGROUP_GPU,
777 .smmu = {
778 /* read-only */
779 .reg = 0x230,
780 .bit = 25,
781 },
782 .la = {
783 .reg = 0x3c8,
784 .shift = 16,
785 .mask = 0xff,
786 .def = 0x80,
787 },
788 }, {
789 .id = 0x5a,
790 .name = "displayt",
791 .swgroup = TEGRA_SWGROUP_DC,
792 .smmu = {
793 .reg = 0x230,
794 .bit = 26,
795 },
796 .la = {
797 .reg = 0x2f0,
798 .shift = 16,
799 .mask = 0xff,
800 .def = 0x50,
801 },
802 }, {
803 .id = 0x60,
804 .name = "sdmmcra",
805 .swgroup = TEGRA_SWGROUP_SDMMC1A,
806 .smmu = {
807 .reg = 0x234,
808 .bit = 0,
809 },
810 .la = {
811 .reg = 0x3b8,
812 .shift = 0,
813 .mask = 0xff,
814 .def = 0x49,
815 },
816 }, {
817 .id = 0x61,
818 .name = "sdmmcraa",
819 .swgroup = TEGRA_SWGROUP_SDMMC2A,
820 .smmu = {
821 .reg = 0x234,
822 .bit = 1,
823 },
824 .la = {
825 .reg = 0x3bc,
826 .shift = 0,
827 .mask = 0xff,
828 .def = 0x49,
829 },
830 }, {
831 .id = 0x62,
832 .name = "sdmmcr",
833 .swgroup = TEGRA_SWGROUP_SDMMC3A,
834 .smmu = {
835 .reg = 0x234,
836 .bit = 2,
837 },
838 .la = {
839 .reg = 0x3c0,
840 .shift = 0,
841 .mask = 0xff,
842 .def = 0x49,
843 },
844 }, {
845 .id = 0x63,
846 .swgroup = TEGRA_SWGROUP_SDMMC4A,
847 .name = "sdmmcrab",
848 .smmu = {
849 .reg = 0x234,
850 .bit = 3,
851 },
852 .la = {
853 .reg = 0x3c4,
854 .shift = 0,
855 .mask = 0xff,
856 .def = 0x49,
857 },
858 }, {
859 .id = 0x64,
860 .name = "sdmmcwa",
861 .swgroup = TEGRA_SWGROUP_SDMMC1A,
862 .smmu = {
863 .reg = 0x234,
864 .bit = 4,
865 },
866 .la = {
867 .reg = 0x3b8,
868 .shift = 16,
869 .mask = 0xff,
870 .def = 0x80,
871 },
872 }, {
873 .id = 0x65,
874 .name = "sdmmcwaa",
875 .swgroup = TEGRA_SWGROUP_SDMMC2A,
876 .smmu = {
877 .reg = 0x234,
878 .bit = 5,
879 },
880 .la = {
881 .reg = 0x3bc,
882 .shift = 16,
883 .mask = 0xff,
884 .def = 0x80,
885 },
886 }, {
887 .id = 0x66,
888 .name = "sdmmcw",
889 .swgroup = TEGRA_SWGROUP_SDMMC3A,
890 .smmu = {
891 .reg = 0x234,
892 .bit = 6,
893 },
894 .la = {
895 .reg = 0x3c0,
896 .shift = 16,
897 .mask = 0xff,
898 .def = 0x80,
899 },
900 }, {
901 .id = 0x67,
902 .name = "sdmmcwab",
903 .swgroup = TEGRA_SWGROUP_SDMMC4A,
904 .smmu = {
905 .reg = 0x234,
906 .bit = 7,
907 },
908 .la = {
909 .reg = 0x3c4,
910 .shift = 16,
911 .mask = 0xff,
912 .def = 0x80,
913 },
914 }, {
915 .id = 0x6c,
916 .name = "vicsrd",
917 .swgroup = TEGRA_SWGROUP_VIC,
918 .smmu = {
919 .reg = 0x234,
920 .bit = 12,
921 },
922 .la = {
923 .reg = 0x394,
924 .shift = 0,
925 .mask = 0xff,
926 .def = 0x1a,
927 },
928 }, {
929 .id = 0x6d,
930 .name = "vicswr",
931 .swgroup = TEGRA_SWGROUP_VIC,
932 .smmu = {
933 .reg = 0x234,
934 .bit = 13,
935 },
936 .la = {
937 .reg = 0x394,
938 .shift = 16,
939 .mask = 0xff,
940 .def = 0x80,
941 },
942 }, {
943 .id = 0x72,
944 .name = "viw",
945 .swgroup = TEGRA_SWGROUP_VI,
946 .smmu = {
947 .reg = 0x234,
948 .bit = 18,
949 },
950 .la = {
951 .reg = 0x398,
952 .shift = 0,
953 .mask = 0xff,
954 .def = 0x80,
955 },
956 }, {
957 .id = 0x73,
958 .name = "displayd",
959 .swgroup = TEGRA_SWGROUP_DC,
960 .smmu = {
961 .reg = 0x234,
962 .bit = 19,
963 },
964 .la = {
965 .reg = 0x3c8,
966 .shift = 0,
967 .mask = 0xff,
968 .def = 0x50,
969 },
970 },
971 };
972
973 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
974 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
975 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
976 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
977 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
978 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
979 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
980 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
981 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
982 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
983 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
984 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
985 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
986 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
987 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
988 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
989 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
990 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
991 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
992 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
993 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
994 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
995 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
996 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
997 };
998
999 static const unsigned int tegra124_group_display[] = {
1000 TEGRA_SWGROUP_DC,
1001 TEGRA_SWGROUP_DCB,
1002 };
1003
1004 static const struct tegra_smmu_group_soc tegra124_groups[] = {
1005 {
1006 .name = "display",
1007 .swgroups = tegra124_group_display,
1008 .num_swgroups = ARRAY_SIZE(tegra124_group_display),
1009 },
1010 };
1011
1012 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
1013 { \
1014 .name = #_name, \
1015 .id = TEGRA124_MC_RESET_##_name, \
1016 .control = _control, \
1017 .status = _status, \
1018 .bit = _bit, \
1019 }
1020
1021 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1022 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1023 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1024 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1025 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1026 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1027 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1028 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1029 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1030 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1031 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1032 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1033 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1034 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1035 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1036 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1037 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1038 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1039 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1040 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1041 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1042 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1043 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1044 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1045 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1046 };
1047
1048 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1049 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1050 .clients = tegra124_mc_clients,
1051 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1052 .swgroups = tegra124_swgroups,
1053 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1054 .groups = tegra124_groups,
1055 .num_groups = ARRAY_SIZE(tegra124_groups),
1056 .supports_round_robin_arbitration = true,
1057 .supports_request_limit = true,
1058 .num_tlb_lines = 32,
1059 .num_asids = 128,
1060 };
1061
1062 const struct tegra_mc_soc tegra124_mc_soc = {
1063 .clients = tegra124_mc_clients,
1064 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1065 .num_address_bits = 34,
1066 .atom_size = 32,
1067 .client_id_mask = 0x7f,
1068 .smmu = &tegra124_smmu_soc,
1069 .emem_regs = tegra124_mc_emem_regs,
1070 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1071 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1072 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1073 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1074 .reset_ops = &tegra_mc_reset_ops_common,
1075 .resets = tegra124_mc_resets,
1076 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1077 };
1078 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1079
1080 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1081 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1082 .clients = tegra124_mc_clients,
1083 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1084 .swgroups = tegra124_swgroups,
1085 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1086 .groups = tegra124_groups,
1087 .num_groups = ARRAY_SIZE(tegra124_groups),
1088 .supports_round_robin_arbitration = true,
1089 .supports_request_limit = true,
1090 .num_tlb_lines = 32,
1091 .num_asids = 128,
1092 };
1093
1094 const struct tegra_mc_soc tegra132_mc_soc = {
1095 .clients = tegra124_mc_clients,
1096 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1097 .num_address_bits = 34,
1098 .atom_size = 32,
1099 .client_id_mask = 0x7f,
1100 .smmu = &tegra132_smmu_soc,
1101 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1102 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1103 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1104 .reset_ops = &tegra_mc_reset_ops_common,
1105 .resets = tegra124_mc_resets,
1106 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1107 };
1108 #endif /* CONFIG_ARCH_TEGRA_132_SOC */
Ubuntu Jammy Linux kernel mirror