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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / drivers / memory / tegra / tegra210.c
1 /*
2 * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <dt-bindings/memory/tegra210-mc.h>
10
11 #include "mc.h"
12
13 static const struct tegra_mc_client tegra210_mc_clients[] = {
14 {
15 .id = 0x00,
16 .name = "ptcr",
17 .swgroup = TEGRA_SWGROUP_PTC,
18 }, {
19 .id = 0x01,
20 .name = "display0a",
21 .swgroup = TEGRA_SWGROUP_DC,
22 .smmu = {
23 .reg = 0x228,
24 .bit = 1,
25 },
26 .la = {
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
31 },
32 }, {
33 .id = 0x02,
34 .name = "display0ab",
35 .swgroup = TEGRA_SWGROUP_DCB,
36 .smmu = {
37 .reg = 0x228,
38 .bit = 2,
39 },
40 .la = {
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0xc6,
45 },
46 }, {
47 .id = 0x03,
48 .name = "display0b",
49 .swgroup = TEGRA_SWGROUP_DC,
50 .smmu = {
51 .reg = 0x228,
52 .bit = 3,
53 },
54 .la = {
55 .reg = 0x2e8,
56 .shift = 16,
57 .mask = 0xff,
58 .def = 0x50,
59 },
60 }, {
61 .id = 0x04,
62 .name = "display0bb",
63 .swgroup = TEGRA_SWGROUP_DCB,
64 .smmu = {
65 .reg = 0x228,
66 .bit = 4,
67 },
68 .la = {
69 .reg = 0x2f4,
70 .shift = 16,
71 .mask = 0xff,
72 .def = 0x50,
73 },
74 }, {
75 .id = 0x05,
76 .name = "display0c",
77 .swgroup = TEGRA_SWGROUP_DC,
78 .smmu = {
79 .reg = 0x228,
80 .bit = 5,
81 },
82 .la = {
83 .reg = 0x2ec,
84 .shift = 0,
85 .mask = 0xff,
86 .def = 0x50,
87 },
88 }, {
89 .id = 0x06,
90 .name = "display0cb",
91 .swgroup = TEGRA_SWGROUP_DCB,
92 .smmu = {
93 .reg = 0x228,
94 .bit = 6,
95 },
96 .la = {
97 .reg = 0x2f8,
98 .shift = 0,
99 .mask = 0xff,
100 .def = 0x50,
101 },
102 }, {
103 .id = 0x0e,
104 .name = "afir",
105 .swgroup = TEGRA_SWGROUP_AFI,
106 .smmu = {
107 .reg = 0x228,
108 .bit = 14,
109 },
110 .la = {
111 .reg = 0x2e0,
112 .shift = 0,
113 .mask = 0xff,
114 .def = 0x13,
115 },
116 }, {
117 .id = 0x0f,
118 .name = "avpcarm7r",
119 .swgroup = TEGRA_SWGROUP_AVPC,
120 .smmu = {
121 .reg = 0x228,
122 .bit = 15,
123 },
124 .la = {
125 .reg = 0x2e4,
126 .shift = 0,
127 .mask = 0xff,
128 .def = 0x04,
129 },
130 }, {
131 .id = 0x10,
132 .name = "displayhc",
133 .swgroup = TEGRA_SWGROUP_DC,
134 .smmu = {
135 .reg = 0x228,
136 .bit = 16,
137 },
138 .la = {
139 .reg = 0x2f0,
140 .shift = 0,
141 .mask = 0xff,
142 .def = 0x50,
143 },
144 }, {
145 .id = 0x11,
146 .name = "displayhcb",
147 .swgroup = TEGRA_SWGROUP_DCB,
148 .smmu = {
149 .reg = 0x228,
150 .bit = 17,
151 },
152 .la = {
153 .reg = 0x2fc,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x50,
157 },
158 }, {
159 .id = 0x15,
160 .name = "hdar",
161 .swgroup = TEGRA_SWGROUP_HDA,
162 .smmu = {
163 .reg = 0x228,
164 .bit = 21,
165 },
166 .la = {
167 .reg = 0x318,
168 .shift = 0,
169 .mask = 0xff,
170 .def = 0x24,
171 },
172 }, {
173 .id = 0x16,
174 .name = "host1xdmar",
175 .swgroup = TEGRA_SWGROUP_HC,
176 .smmu = {
177 .reg = 0x228,
178 .bit = 22,
179 },
180 .la = {
181 .reg = 0x310,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x1e,
185 },
186 }, {
187 .id = 0x17,
188 .name = "host1xr",
189 .swgroup = TEGRA_SWGROUP_HC,
190 .smmu = {
191 .reg = 0x228,
192 .bit = 23,
193 },
194 .la = {
195 .reg = 0x310,
196 .shift = 16,
197 .mask = 0xff,
198 .def = 0x50,
199 },
200 }, {
201 .id = 0x1c,
202 .name = "nvencsrd",
203 .swgroup = TEGRA_SWGROUP_NVENC,
204 .smmu = {
205 .reg = 0x228,
206 .bit = 28,
207 },
208 .la = {
209 .reg = 0x328,
210 .shift = 0,
211 .mask = 0xff,
212 .def = 0x23,
213 },
214 }, {
215 .id = 0x1d,
216 .name = "ppcsahbdmar",
217 .swgroup = TEGRA_SWGROUP_PPCS,
218 .smmu = {
219 .reg = 0x228,
220 .bit = 29,
221 },
222 .la = {
223 .reg = 0x344,
224 .shift = 0,
225 .mask = 0xff,
226 .def = 0x49,
227 },
228 }, {
229 .id = 0x1e,
230 .name = "ppcsahbslvr",
231 .swgroup = TEGRA_SWGROUP_PPCS,
232 .smmu = {
233 .reg = 0x228,
234 .bit = 30,
235 },
236 .la = {
237 .reg = 0x344,
238 .shift = 16,
239 .mask = 0xff,
240 .def = 0x1a,
241 },
242 }, {
243 .id = 0x1f,
244 .name = "satar",
245 .swgroup = TEGRA_SWGROUP_SATA,
246 .smmu = {
247 .reg = 0x228,
248 .bit = 31,
249 },
250 .la = {
251 .reg = 0x350,
252 .shift = 0,
253 .mask = 0xff,
254 .def = 0x65,
255 },
256 }, {
257 .id = 0x27,
258 .name = "mpcorer",
259 .swgroup = TEGRA_SWGROUP_MPCORE,
260 .la = {
261 .reg = 0x320,
262 .shift = 0,
263 .mask = 0xff,
264 .def = 0x04,
265 },
266 }, {
267 .id = 0x2b,
268 .name = "nvencswr",
269 .swgroup = TEGRA_SWGROUP_NVENC,
270 .smmu = {
271 .reg = 0x22c,
272 .bit = 11,
273 },
274 .la = {
275 .reg = 0x328,
276 .shift = 16,
277 .mask = 0xff,
278 .def = 0x80,
279 },
280 }, {
281 .id = 0x31,
282 .name = "afiw",
283 .swgroup = TEGRA_SWGROUP_AFI,
284 .smmu = {
285 .reg = 0x22c,
286 .bit = 17,
287 },
288 .la = {
289 .reg = 0x2e0,
290 .shift = 16,
291 .mask = 0xff,
292 .def = 0x80,
293 },
294 }, {
295 .id = 0x32,
296 .name = "avpcarm7w",
297 .swgroup = TEGRA_SWGROUP_AVPC,
298 .smmu = {
299 .reg = 0x22c,
300 .bit = 18,
301 },
302 .la = {
303 .reg = 0x2e4,
304 .shift = 16,
305 .mask = 0xff,
306 .def = 0x80,
307 },
308 }, {
309 .id = 0x35,
310 .name = "hdaw",
311 .swgroup = TEGRA_SWGROUP_HDA,
312 .smmu = {
313 .reg = 0x22c,
314 .bit = 21,
315 },
316 .la = {
317 .reg = 0x318,
318 .shift = 16,
319 .mask = 0xff,
320 .def = 0x80,
321 },
322 }, {
323 .id = 0x36,
324 .name = "host1xw",
325 .swgroup = TEGRA_SWGROUP_HC,
326 .smmu = {
327 .reg = 0x22c,
328 .bit = 22,
329 },
330 .la = {
331 .reg = 0x314,
332 .shift = 0,
333 .mask = 0xff,
334 .def = 0x80,
335 },
336 }, {
337 .id = 0x39,
338 .name = "mpcorew",
339 .swgroup = TEGRA_SWGROUP_MPCORE,
340 .la = {
341 .reg = 0x320,
342 .shift = 16,
343 .mask = 0xff,
344 .def = 0x80,
345 },
346 }, {
347 .id = 0x3b,
348 .name = "ppcsahbdmaw",
349 .swgroup = TEGRA_SWGROUP_PPCS,
350 .smmu = {
351 .reg = 0x22c,
352 .bit = 27,
353 },
354 .la = {
355 .reg = 0x348,
356 .shift = 0,
357 .mask = 0xff,
358 .def = 0x80,
359 },
360 }, {
361 .id = 0x3c,
362 .name = "ppcsahbslvw",
363 .swgroup = TEGRA_SWGROUP_PPCS,
364 .smmu = {
365 .reg = 0x22c,
366 .bit = 28,
367 },
368 .la = {
369 .reg = 0x348,
370 .shift = 16,
371 .mask = 0xff,
372 .def = 0x80,
373 },
374 }, {
375 .id = 0x3d,
376 .name = "sataw",
377 .swgroup = TEGRA_SWGROUP_SATA,
378 .smmu = {
379 .reg = 0x22c,
380 .bit = 29,
381 },
382 .la = {
383 .reg = 0x350,
384 .shift = 16,
385 .mask = 0xff,
386 .def = 0x65,
387 },
388 }, {
389 .id = 0x44,
390 .name = "ispra",
391 .swgroup = TEGRA_SWGROUP_ISP2,
392 .smmu = {
393 .reg = 0x230,
394 .bit = 4,
395 },
396 .la = {
397 .reg = 0x370,
398 .shift = 0,
399 .mask = 0xff,
400 .def = 0x18,
401 },
402 }, {
403 .id = 0x46,
404 .name = "ispwa",
405 .swgroup = TEGRA_SWGROUP_ISP2,
406 .smmu = {
407 .reg = 0x230,
408 .bit = 6,
409 },
410 .la = {
411 .reg = 0x374,
412 .shift = 0,
413 .mask = 0xff,
414 .def = 0x80,
415 },
416 }, {
417 .id = 0x47,
418 .name = "ispwb",
419 .swgroup = TEGRA_SWGROUP_ISP2,
420 .smmu = {
421 .reg = 0x230,
422 .bit = 7,
423 },
424 .la = {
425 .reg = 0x374,
426 .shift = 16,
427 .mask = 0xff,
428 .def = 0x80,
429 },
430 }, {
431 .id = 0x4a,
432 .name = "xusb_hostr",
433 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
434 .smmu = {
435 .reg = 0x230,
436 .bit = 10,
437 },
438 .la = {
439 .reg = 0x37c,
440 .shift = 0,
441 .mask = 0xff,
442 .def = 0x39,
443 },
444 }, {
445 .id = 0x4b,
446 .name = "xusb_hostw",
447 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
448 .smmu = {
449 .reg = 0x230,
450 .bit = 11,
451 },
452 .la = {
453 .reg = 0x37c,
454 .shift = 16,
455 .mask = 0xff,
456 .def = 0x80,
457 },
458 }, {
459 .id = 0x4c,
460 .name = "xusb_devr",
461 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
462 .smmu = {
463 .reg = 0x230,
464 .bit = 12,
465 },
466 .la = {
467 .reg = 0x380,
468 .shift = 0,
469 .mask = 0xff,
470 .def = 0x39,
471 },
472 }, {
473 .id = 0x4d,
474 .name = "xusb_devw",
475 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
476 .smmu = {
477 .reg = 0x230,
478 .bit = 13,
479 },
480 .la = {
481 .reg = 0x380,
482 .shift = 16,
483 .mask = 0xff,
484 .def = 0x80,
485 },
486 }, {
487 .id = 0x4e,
488 .name = "isprab",
489 .swgroup = TEGRA_SWGROUP_ISP2B,
490 .smmu = {
491 .reg = 0x230,
492 .bit = 14,
493 },
494 .la = {
495 .reg = 0x384,
496 .shift = 0,
497 .mask = 0xff,
498 .def = 0x18,
499 },
500 }, {
501 .id = 0x50,
502 .name = "ispwab",
503 .swgroup = TEGRA_SWGROUP_ISP2B,
504 .smmu = {
505 .reg = 0x230,
506 .bit = 16,
507 },
508 .la = {
509 .reg = 0x388,
510 .shift = 0,
511 .mask = 0xff,
512 .def = 0x80,
513 },
514 }, {
515 .id = 0x51,
516 .name = "ispwbb",
517 .swgroup = TEGRA_SWGROUP_ISP2B,
518 .smmu = {
519 .reg = 0x230,
520 .bit = 17,
521 },
522 .la = {
523 .reg = 0x388,
524 .shift = 16,
525 .mask = 0xff,
526 .def = 0x80,
527 },
528 }, {
529 .id = 0x54,
530 .name = "tsecsrd",
531 .swgroup = TEGRA_SWGROUP_TSEC,
532 .smmu = {
533 .reg = 0x230,
534 .bit = 20,
535 },
536 .la = {
537 .reg = 0x390,
538 .shift = 0,
539 .mask = 0xff,
540 .def = 0x9b,
541 },
542 }, {
543 .id = 0x55,
544 .name = "tsecswr",
545 .swgroup = TEGRA_SWGROUP_TSEC,
546 .smmu = {
547 .reg = 0x230,
548 .bit = 21,
549 },
550 .la = {
551 .reg = 0x390,
552 .shift = 16,
553 .mask = 0xff,
554 .def = 0x80,
555 },
556 }, {
557 .id = 0x56,
558 .name = "a9avpscr",
559 .swgroup = TEGRA_SWGROUP_A9AVP,
560 .smmu = {
561 .reg = 0x230,
562 .bit = 22,
563 },
564 .la = {
565 .reg = 0x3a4,
566 .shift = 0,
567 .mask = 0xff,
568 .def = 0x04,
569 },
570 }, {
571 .id = 0x57,
572 .name = "a9avpscw",
573 .swgroup = TEGRA_SWGROUP_A9AVP,
574 .smmu = {
575 .reg = 0x230,
576 .bit = 23,
577 },
578 .la = {
579 .reg = 0x3a4,
580 .shift = 16,
581 .mask = 0xff,
582 .def = 0x80,
583 },
584 }, {
585 .id = 0x58,
586 .name = "gpusrd",
587 .swgroup = TEGRA_SWGROUP_GPU,
588 .smmu = {
589 /* read-only */
590 .reg = 0x230,
591 .bit = 24,
592 },
593 .la = {
594 .reg = 0x3c8,
595 .shift = 0,
596 .mask = 0xff,
597 .def = 0x1a,
598 },
599 }, {
600 .id = 0x59,
601 .name = "gpuswr",
602 .swgroup = TEGRA_SWGROUP_GPU,
603 .smmu = {
604 /* read-only */
605 .reg = 0x230,
606 .bit = 25,
607 },
608 .la = {
609 .reg = 0x3c8,
610 .shift = 16,
611 .mask = 0xff,
612 .def = 0x80,
613 },
614 }, {
615 .id = 0x5a,
616 .name = "displayt",
617 .swgroup = TEGRA_SWGROUP_DC,
618 .smmu = {
619 .reg = 0x230,
620 .bit = 26,
621 },
622 .la = {
623 .reg = 0x2f0,
624 .shift = 16,
625 .mask = 0xff,
626 .def = 0x50,
627 },
628 }, {
629 .id = 0x60,
630 .name = "sdmmcra",
631 .swgroup = TEGRA_SWGROUP_SDMMC1A,
632 .smmu = {
633 .reg = 0x234,
634 .bit = 0,
635 },
636 .la = {
637 .reg = 0x3b8,
638 .shift = 0,
639 .mask = 0xff,
640 .def = 0x49,
641 },
642 }, {
643 .id = 0x61,
644 .name = "sdmmcraa",
645 .swgroup = TEGRA_SWGROUP_SDMMC2A,
646 .smmu = {
647 .reg = 0x234,
648 .bit = 1,
649 },
650 .la = {
651 .reg = 0x3bc,
652 .shift = 0,
653 .mask = 0xff,
654 .def = 0x49,
655 },
656 }, {
657 .id = 0x62,
658 .name = "sdmmcr",
659 .swgroup = TEGRA_SWGROUP_SDMMC3A,
660 .smmu = {
661 .reg = 0x234,
662 .bit = 2,
663 },
664 .la = {
665 .reg = 0x3c0,
666 .shift = 0,
667 .mask = 0xff,
668 .def = 0x49,
669 },
670 }, {
671 .id = 0x63,
672 .swgroup = TEGRA_SWGROUP_SDMMC4A,
673 .name = "sdmmcrab",
674 .smmu = {
675 .reg = 0x234,
676 .bit = 3,
677 },
678 .la = {
679 .reg = 0x3c4,
680 .shift = 0,
681 .mask = 0xff,
682 .def = 0x49,
683 },
684 }, {
685 .id = 0x64,
686 .name = "sdmmcwa",
687 .swgroup = TEGRA_SWGROUP_SDMMC1A,
688 .smmu = {
689 .reg = 0x234,
690 .bit = 4,
691 },
692 .la = {
693 .reg = 0x3b8,
694 .shift = 16,
695 .mask = 0xff,
696 .def = 0x80,
697 },
698 }, {
699 .id = 0x65,
700 .name = "sdmmcwaa",
701 .swgroup = TEGRA_SWGROUP_SDMMC2A,
702 .smmu = {
703 .reg = 0x234,
704 .bit = 5,
705 },
706 .la = {
707 .reg = 0x3bc,
708 .shift = 16,
709 .mask = 0xff,
710 .def = 0x80,
711 },
712 }, {
713 .id = 0x66,
714 .name = "sdmmcw",
715 .swgroup = TEGRA_SWGROUP_SDMMC3A,
716 .smmu = {
717 .reg = 0x234,
718 .bit = 6,
719 },
720 .la = {
721 .reg = 0x3c0,
722 .shift = 16,
723 .mask = 0xff,
724 .def = 0x80,
725 },
726 }, {
727 .id = 0x67,
728 .name = "sdmmcwab",
729 .swgroup = TEGRA_SWGROUP_SDMMC4A,
730 .smmu = {
731 .reg = 0x234,
732 .bit = 7,
733 },
734 .la = {
735 .reg = 0x3c4,
736 .shift = 16,
737 .mask = 0xff,
738 .def = 0x80,
739 },
740 }, {
741 .id = 0x6c,
742 .name = "vicsrd",
743 .swgroup = TEGRA_SWGROUP_VIC,
744 .smmu = {
745 .reg = 0x234,
746 .bit = 12,
747 },
748 .la = {
749 .reg = 0x394,
750 .shift = 0,
751 .mask = 0xff,
752 .def = 0x1a,
753 },
754 }, {
755 .id = 0x6d,
756 .name = "vicswr",
757 .swgroup = TEGRA_SWGROUP_VIC,
758 .smmu = {
759 .reg = 0x234,
760 .bit = 13,
761 },
762 .la = {
763 .reg = 0x394,
764 .shift = 16,
765 .mask = 0xff,
766 .def = 0x80,
767 },
768 }, {
769 .id = 0x72,
770 .name = "viw",
771 .swgroup = TEGRA_SWGROUP_VI,
772 .smmu = {
773 .reg = 0x234,
774 .bit = 18,
775 },
776 .la = {
777 .reg = 0x398,
778 .shift = 0,
779 .mask = 0xff,
780 .def = 0x80,
781 },
782 }, {
783 .id = 0x73,
784 .name = "displayd",
785 .swgroup = TEGRA_SWGROUP_DC,
786 .smmu = {
787 .reg = 0x234,
788 .bit = 19,
789 },
790 .la = {
791 .reg = 0x3c8,
792 .shift = 0,
793 .mask = 0xff,
794 .def = 0x50,
795 },
796 }, {
797 .id = 0x78,
798 .name = "nvdecsrd",
799 .swgroup = TEGRA_SWGROUP_NVDEC,
800 .smmu = {
801 .reg = 0x234,
802 .bit = 24,
803 },
804 .la = {
805 .reg = 0x3d8,
806 .shift = 0,
807 .mask = 0xff,
808 .def = 0x23,
809 },
810 }, {
811 .id = 0x79,
812 .name = "nvdecswr",
813 .swgroup = TEGRA_SWGROUP_NVDEC,
814 .smmu = {
815 .reg = 0x234,
816 .bit = 25,
817 },
818 .la = {
819 .reg = 0x3d8,
820 .shift = 16,
821 .mask = 0xff,
822 .def = 0x80,
823 },
824 }, {
825 .id = 0x7a,
826 .name = "aper",
827 .swgroup = TEGRA_SWGROUP_APE,
828 .smmu = {
829 .reg = 0x234,
830 .bit = 26,
831 },
832 .la = {
833 .reg = 0x3dc,
834 .shift = 0,
835 .mask = 0xff,
836 .def = 0xff,
837 },
838 }, {
839 .id = 0x7b,
840 .name = "apew",
841 .swgroup = TEGRA_SWGROUP_APE,
842 .smmu = {
843 .reg = 0x234,
844 .bit = 27,
845 },
846 .la = {
847 .reg = 0x3dc,
848 .shift = 0,
849 .mask = 0xff,
850 .def = 0x80,
851 },
852 }, {
853 .id = 0x7e,
854 .name = "nvjpgsrd",
855 .swgroup = TEGRA_SWGROUP_NVJPG,
856 .smmu = {
857 .reg = 0x234,
858 .bit = 30,
859 },
860 .la = {
861 .reg = 0x3e4,
862 .shift = 0,
863 .mask = 0xff,
864 .def = 0x23,
865 },
866 }, {
867 .id = 0x7f,
868 .name = "nvjpgswr",
869 .swgroup = TEGRA_SWGROUP_NVJPG,
870 .smmu = {
871 .reg = 0x234,
872 .bit = 31,
873 },
874 .la = {
875 .reg = 0x3e4,
876 .shift = 16,
877 .mask = 0xff,
878 .def = 0x80,
879 },
880 }, {
881 .id = 0x80,
882 .name = "sesrd",
883 .swgroup = TEGRA_SWGROUP_SE,
884 .smmu = {
885 .reg = 0xb98,
886 .bit = 0,
887 },
888 .la = {
889 .reg = 0x3e0,
890 .shift = 0,
891 .mask = 0xff,
892 .def = 0x2e,
893 },
894 }, {
895 .id = 0x81,
896 .name = "seswr",
897 .swgroup = TEGRA_SWGROUP_SE,
898 .smmu = {
899 .reg = 0xb98,
900 .bit = 1,
901 },
902 .la = {
903 .reg = 0xb98,
904 .shift = 16,
905 .mask = 0xff,
906 .def = 0x80,
907 },
908 }, {
909 .id = 0x82,
910 .name = "axiapr",
911 .swgroup = TEGRA_SWGROUP_AXIAP,
912 .smmu = {
913 .reg = 0xb98,
914 .bit = 2,
915 },
916 .la = {
917 .reg = 0x3a0,
918 .shift = 0,
919 .mask = 0xff,
920 .def = 0xff,
921 },
922 }, {
923 .id = 0x83,
924 .name = "axiapw",
925 .swgroup = TEGRA_SWGROUP_AXIAP,
926 .smmu = {
927 .reg = 0xb98,
928 .bit = 3,
929 },
930 .la = {
931 .reg = 0x3a0,
932 .shift = 16,
933 .mask = 0xff,
934 .def = 0x80,
935 },
936 }, {
937 .id = 0x84,
938 .name = "etrr",
939 .swgroup = TEGRA_SWGROUP_ETR,
940 .smmu = {
941 .reg = 0xb98,
942 .bit = 4,
943 },
944 .la = {
945 .reg = 0x3ec,
946 .shift = 0,
947 .mask = 0xff,
948 .def = 0xff,
949 },
950 }, {
951 .id = 0x85,
952 .name = "etrw",
953 .swgroup = TEGRA_SWGROUP_ETR,
954 .smmu = {
955 .reg = 0xb98,
956 .bit = 5,
957 },
958 .la = {
959 .reg = 0x3ec,
960 .shift = 16,
961 .mask = 0xff,
962 .def = 0xff,
963 },
964 }, {
965 .id = 0x86,
966 .name = "tsecsrdb",
967 .swgroup = TEGRA_SWGROUP_TSECB,
968 .smmu = {
969 .reg = 0xb98,
970 .bit = 6,
971 },
972 .la = {
973 .reg = 0x3f0,
974 .shift = 0,
975 .mask = 0xff,
976 .def = 0x9b,
977 },
978 }, {
979 .id = 0x87,
980 .name = "tsecswrb",
981 .swgroup = TEGRA_SWGROUP_TSECB,
982 .smmu = {
983 .reg = 0xb98,
984 .bit = 7,
985 },
986 .la = {
987 .reg = 0x3f0,
988 .shift = 16,
989 .mask = 0xff,
990 .def = 0x80,
991 },
992 }, {
993 .id = 0x88,
994 .name = "gpusrd2",
995 .swgroup = TEGRA_SWGROUP_GPU,
996 .smmu = {
997 /* read-only */
998 .reg = 0xb98,
999 .bit = 8,
1000 },
1001 .la = {
1002 .reg = 0x3e8,
1003 .shift = 0,
1004 .mask = 0xff,
1005 .def = 0x1a,
1006 },
1007 }, {
1008 .id = 0x89,
1009 .name = "gpuswr2",
1010 .swgroup = TEGRA_SWGROUP_GPU,
1011 .smmu = {
1012 /* read-only */
1013 .reg = 0xb98,
1014 .bit = 9,
1015 },
1016 .la = {
1017 .reg = 0x3e8,
1018 .shift = 16,
1019 .mask = 0xff,
1020 .def = 0x80,
1021 },
1022 },
1023 };
1024
1025 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1026 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1027 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1028 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1029 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1030 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1031 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1032 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1033 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1034 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1035 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1036 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1037 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1038 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1039 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1040 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1041 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1042 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1043 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1044 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1045 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1046 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1047 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1048 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1049 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1050 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1051 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1052 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1053 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1054 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1055 };
1056
1057 static const unsigned int tegra210_group_display[] = {
1058 TEGRA_SWGROUP_DC,
1059 TEGRA_SWGROUP_DCB,
1060 };
1061
1062 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1063 {
1064 .name = "display",
1065 .swgroups = tegra210_group_display,
1066 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1067 },
1068 };
1069
1070 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1071 .clients = tegra210_mc_clients,
1072 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1073 .swgroups = tegra210_swgroups,
1074 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1075 .groups = tegra210_groups,
1076 .num_groups = ARRAY_SIZE(tegra210_groups),
1077 .supports_round_robin_arbitration = true,
1078 .supports_request_limit = true,
1079 .num_tlb_lines = 32,
1080 .num_asids = 128,
1081 };
1082
1083 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
1084 { \
1085 .name = #_name, \
1086 .id = TEGRA210_MC_RESET_##_name, \
1087 .control = _control, \
1088 .status = _status, \
1089 .bit = _bit, \
1090 }
1091
1092 static const struct tegra_mc_reset tegra210_mc_resets[] = {
1093 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1094 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1095 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1096 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1097 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1098 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1099 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1100 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1101 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1102 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1103 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1104 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1105 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1106 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1107 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1108 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1109 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1110 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1111 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1112 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1113 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1114 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1115 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1116 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1117 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1118 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1119 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1120 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1121 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1122 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1123 };
1124
1125 const struct tegra_mc_soc tegra210_mc_soc = {
1126 .clients = tegra210_mc_clients,
1127 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1128 .num_address_bits = 34,
1129 .atom_size = 64,
1130 .client_id_mask = 0xff,
1131 .smmu = &tegra210_smmu_soc,
1132 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1133 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1134 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1135 .reset_ops = &tegra_mc_reset_ops_common,
1136 .resets = tegra210_mc_resets,
1137 .num_resets = ARRAY_SIZE(tegra210_mc_resets),
1138 };
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