2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
10 * U8500 PRCM Unit interface driver
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/spinlock.h>
20 #include <linux/slab.h>
21 #include <linux/mutex.h>
22 #include <linux/completion.h>
23 #include <linux/irq.h>
24 #include <linux/jiffies.h>
25 #include <linux/bitops.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/mfd/core.h>
30 #include <linux/mfd/dbx500-prcmu.h>
31 #include <linux/mfd/abx500/ab8500.h>
32 #include <linux/regulator/db8500-prcmu.h>
33 #include <linux/regulator/machine.h>
34 #include <asm/hardware/gic.h>
35 #include <mach/hardware.h>
36 #include <mach/irqs.h>
37 #include <mach/db8500-regs.h>
39 #include "dbx500-prcmu-regs.h"
41 /* Offset for the firmware version within the TCPM */
42 #define PRCMU_FW_VERSION_OFFSET 0xA4
44 /* Index of different voltages to be used when accessing AVSData */
45 #define PRCM_AVS_BASE 0x2FC
46 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
47 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
48 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
49 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
50 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
51 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
52 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
53 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
54 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
55 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
56 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
57 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
58 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
60 #define PRCM_AVS_VOLTAGE 0
61 #define PRCM_AVS_VOLTAGE_MASK 0x3f
62 #define PRCM_AVS_ISSLOWSTARTUP 6
63 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
64 #define PRCM_AVS_ISMODEENABLE 7
65 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
67 #define PRCM_BOOT_STATUS 0xFFF
68 #define PRCM_ROMCODE_A2P 0xFFE
69 #define PRCM_ROMCODE_P2A 0xFFD
70 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
72 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
74 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
75 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
76 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
77 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
78 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
79 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
80 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
81 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
84 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
85 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
86 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
87 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
88 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
89 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
92 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
93 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
94 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
95 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
96 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
97 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
99 /* Mailbox 0 headers */
100 #define MB0H_POWER_STATE_TRANS 0
101 #define MB0H_CONFIG_WAKEUPS_EXE 1
102 #define MB0H_READ_WAKEUP_ACK 3
103 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
105 #define MB0H_WAKEUP_EXE 2
106 #define MB0H_WAKEUP_SLEEP 5
109 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
110 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
111 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
112 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
113 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
114 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
117 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
118 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
119 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
120 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
121 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
122 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
123 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
125 /* Mailbox 1 headers */
126 #define MB1H_ARM_APE_OPP 0x0
127 #define MB1H_RESET_MODEM 0x2
128 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
129 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
130 #define MB1H_RELEASE_USB_WAKEUP 0x5
131 #define MB1H_PLL_ON_OFF 0x6
133 /* Mailbox 1 Requests */
134 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
135 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
136 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
137 #define PLL_SOC0_OFF 0x1
138 #define PLL_SOC0_ON 0x2
139 #define PLL_SOC1_OFF 0x4
140 #define PLL_SOC1_ON 0x8
143 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
144 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
145 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
146 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
148 /* Mailbox 2 headers */
150 #define MB2H_AUTO_PWR 0x1
153 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
154 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
155 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
156 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
157 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
158 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
159 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
160 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
161 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
162 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
165 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
166 #define HWACC_PWR_ST_OK 0xFE
168 /* Mailbox 3 headers */
170 #define MB3H_SIDETONE 0x1
171 #define MB3H_SYSCLK 0xE
173 /* Mailbox 3 Requests */
174 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
175 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
176 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
177 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
178 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
179 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
180 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
182 /* Mailbox 4 headers */
183 #define MB4H_DDR_INIT 0x0
184 #define MB4H_MEM_ST 0x1
185 #define MB4H_HOTDOG 0x12
186 #define MB4H_HOTMON 0x13
187 #define MB4H_HOT_PERIOD 0x14
188 #define MB4H_A9WDOG_CONF 0x16
189 #define MB4H_A9WDOG_EN 0x17
190 #define MB4H_A9WDOG_DIS 0x18
191 #define MB4H_A9WDOG_LOAD 0x19
192 #define MB4H_A9WDOG_KICK 0x20
194 /* Mailbox 4 Requests */
195 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
196 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
197 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
198 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
199 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
200 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
201 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
202 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
203 #define HOTMON_CONFIG_LOW BIT(0)
204 #define HOTMON_CONFIG_HIGH BIT(1)
205 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
206 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
207 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
208 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
209 #define A9WDOG_AUTO_OFF_EN BIT(7)
210 #define A9WDOG_AUTO_OFF_DIS 0
211 #define A9WDOG_ID_MASK 0xf
213 /* Mailbox 5 Requests */
214 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
215 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
216 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
217 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
218 #define PRCMU_I2C_WRITE(slave) \
219 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
220 #define PRCMU_I2C_READ(slave) \
221 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
222 #define PRCMU_I2C_STOP_EN BIT(3)
225 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
226 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
227 #define I2C_WR_OK 0x1
228 #define I2C_RD_OK 0x2
232 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
238 #define WAKEUP_BIT_RTC BIT(0)
239 #define WAKEUP_BIT_RTT0 BIT(1)
240 #define WAKEUP_BIT_RTT1 BIT(2)
241 #define WAKEUP_BIT_HSI0 BIT(3)
242 #define WAKEUP_BIT_HSI1 BIT(4)
243 #define WAKEUP_BIT_CA_WAKE BIT(5)
244 #define WAKEUP_BIT_USB BIT(6)
245 #define WAKEUP_BIT_ABB BIT(7)
246 #define WAKEUP_BIT_ABB_FIFO BIT(8)
247 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
248 #define WAKEUP_BIT_CA_SLEEP BIT(10)
249 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
250 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
251 #define WAKEUP_BIT_ANC_OK BIT(13)
252 #define WAKEUP_BIT_SW_ERROR BIT(14)
253 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
254 #define WAKEUP_BIT_ARM BIT(17)
255 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
256 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
257 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
258 #define WAKEUP_BIT_GPIO0 BIT(23)
259 #define WAKEUP_BIT_GPIO1 BIT(24)
260 #define WAKEUP_BIT_GPIO2 BIT(25)
261 #define WAKEUP_BIT_GPIO3 BIT(26)
262 #define WAKEUP_BIT_GPIO4 BIT(27)
263 #define WAKEUP_BIT_GPIO5 BIT(28)
264 #define WAKEUP_BIT_GPIO6 BIT(29)
265 #define WAKEUP_BIT_GPIO7 BIT(30)
266 #define WAKEUP_BIT_GPIO8 BIT(31)
270 struct prcmu_fw_version version
;
274 * This vector maps irq numbers to the bits in the bit field used in
275 * communication with the PRCMU firmware.
277 * The reason for having this is to keep the irq numbers contiguous even though
278 * the bits in the bit field are not. (The bits also have a tendency to move
279 * around, to further complicate matters.)
281 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
282 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
283 static u32 prcmu_irq_bit
[NUM_PRCMU_WAKEUPS
] = {
295 IRQ_ENTRY(HOTMON_LOW
),
296 IRQ_ENTRY(HOTMON_HIGH
),
297 IRQ_ENTRY(MODEM_SW_RESET_REQ
),
309 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
310 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
311 static u32 prcmu_wakeup_bit
[NUM_PRCMU_WAKEUP_INDICES
] = {
319 WAKEUP_ENTRY(ABB_FIFO
),
324 * mb0_transfer - state needed for mailbox 0 communication.
325 * @lock: The transaction lock.
326 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
328 * @mask_work: Work structure used for (un)masking wakeup interrupts.
329 * @req: Request data that need to persist between requests.
333 spinlock_t dbb_irqs_lock
;
334 struct work_struct mask_work
;
335 struct mutex ac_wake_lock
;
336 struct completion ac_wake_work
;
345 * mb1_transfer - state needed for mailbox 1 communication.
346 * @lock: The transaction lock.
347 * @work: The transaction completion structure.
348 * @ape_opp: The current APE OPP.
349 * @ack: Reply ("acknowledge") data.
353 struct completion work
;
359 u8 ape_voltage_status
;
364 * mb2_transfer - state needed for mailbox 2 communication.
365 * @lock: The transaction lock.
366 * @work: The transaction completion structure.
367 * @auto_pm_lock: The autonomous power management configuration lock.
368 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
369 * @req: Request data that need to persist between requests.
370 * @ack: Reply ("acknowledge") data.
374 struct completion work
;
375 spinlock_t auto_pm_lock
;
376 bool auto_pm_enabled
;
383 * mb3_transfer - state needed for mailbox 3 communication.
384 * @lock: The request lock.
385 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
386 * @sysclk_work: Work structure used for sysclk requests.
390 struct mutex sysclk_lock
;
391 struct completion sysclk_work
;
395 * mb4_transfer - state needed for mailbox 4 communication.
396 * @lock: The transaction lock.
397 * @work: The transaction completion structure.
401 struct completion work
;
405 * mb5_transfer - state needed for mailbox 5 communication.
406 * @lock: The transaction lock.
407 * @work: The transaction completion structure.
408 * @ack: Reply ("acknowledge") data.
412 struct completion work
;
419 static atomic_t ac_wake_req_state
= ATOMIC_INIT(0);
421 /* Functions definition */
422 static void compute_armss_rate(void);
425 static DEFINE_SPINLOCK(prcmu_lock
);
426 static DEFINE_SPINLOCK(clkout_lock
);
428 /* Global var to runtime determine TCDM base for v2 or v1 */
429 static __iomem
void *tcdm_base
;
444 static DEFINE_SPINLOCK(clk_mgt_lock
);
446 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
447 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
448 struct clk_mgt clk_mgt
[PRCMU_NUM_REG_CLOCKS
] = {
449 CLK_MGT_ENTRY(SGACLK
, PLL_DIV
, false),
450 CLK_MGT_ENTRY(UARTCLK
, PLL_FIX
, true),
451 CLK_MGT_ENTRY(MSP02CLK
, PLL_FIX
, true),
452 CLK_MGT_ENTRY(MSP1CLK
, PLL_FIX
, true),
453 CLK_MGT_ENTRY(I2CCLK
, PLL_FIX
, true),
454 CLK_MGT_ENTRY(SDMMCCLK
, PLL_DIV
, true),
455 CLK_MGT_ENTRY(SLIMCLK
, PLL_FIX
, true),
456 CLK_MGT_ENTRY(PER1CLK
, PLL_DIV
, true),
457 CLK_MGT_ENTRY(PER2CLK
, PLL_DIV
, true),
458 CLK_MGT_ENTRY(PER3CLK
, PLL_DIV
, true),
459 CLK_MGT_ENTRY(PER5CLK
, PLL_DIV
, true),
460 CLK_MGT_ENTRY(PER6CLK
, PLL_DIV
, true),
461 CLK_MGT_ENTRY(PER7CLK
, PLL_DIV
, true),
462 CLK_MGT_ENTRY(LCDCLK
, PLL_FIX
, true),
463 CLK_MGT_ENTRY(BMLCLK
, PLL_DIV
, true),
464 CLK_MGT_ENTRY(HSITXCLK
, PLL_DIV
, true),
465 CLK_MGT_ENTRY(HSIRXCLK
, PLL_DIV
, true),
466 CLK_MGT_ENTRY(HDMICLK
, PLL_FIX
, false),
467 CLK_MGT_ENTRY(APEATCLK
, PLL_DIV
, true),
468 CLK_MGT_ENTRY(APETRACECLK
, PLL_DIV
, true),
469 CLK_MGT_ENTRY(MCDECLK
, PLL_DIV
, true),
470 CLK_MGT_ENTRY(IPI2CCLK
, PLL_FIX
, true),
471 CLK_MGT_ENTRY(DSIALTCLK
, PLL_FIX
, false),
472 CLK_MGT_ENTRY(DMACLK
, PLL_DIV
, true),
473 CLK_MGT_ENTRY(B2R2CLK
, PLL_DIV
, true),
474 CLK_MGT_ENTRY(TVCLK
, PLL_FIX
, true),
475 CLK_MGT_ENTRY(SSPCLK
, PLL_FIX
, true),
476 CLK_MGT_ENTRY(RNGCLK
, PLL_FIX
, true),
477 CLK_MGT_ENTRY(UICCCLK
, PLL_FIX
, false),
486 static struct dsiclk dsiclk
[2] = {
488 .divsel_mask
= PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK
,
489 .divsel_shift
= PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT
,
490 .divsel
= PRCM_DSI_PLLOUT_SEL_PHI
,
493 .divsel_mask
= PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK
,
494 .divsel_shift
= PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT
,
495 .divsel
= PRCM_DSI_PLLOUT_SEL_PHI
,
505 static struct dsiescclk dsiescclk
[3] = {
507 .en
= PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN
,
508 .div_mask
= PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK
,
509 .div_shift
= PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT
,
512 .en
= PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN
,
513 .div_mask
= PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK
,
514 .div_shift
= PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT
,
517 .en
= PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN
,
518 .div_mask
= PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK
,
519 .div_shift
= PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT
,
525 * Used by MCDE to setup all necessary PRCMU registers
527 #define PRCMU_RESET_DSIPLL 0x00004000
528 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
530 #define PRCMU_CLK_PLL_DIV_SHIFT 0
531 #define PRCMU_CLK_PLL_SW_SHIFT 5
532 #define PRCMU_CLK_38 (1 << 9)
533 #define PRCMU_CLK_38_SRC (1 << 10)
534 #define PRCMU_CLK_38_DIV (1 << 11)
536 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
537 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
539 /* DPI 50000000 Hz */
540 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
541 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
542 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
544 /* D=101, N=1, R=4, SELDIV2=0 */
545 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
547 #define PRCMU_ENABLE_PLLDSI 0x00000001
548 #define PRCMU_DISABLE_PLLDSI 0x00000000
549 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
550 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
551 /* ESC clk, div0=1, div1=1, div2=3 */
552 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
553 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
554 #define PRCMU_DSI_RESET_SW 0x00000007
556 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
558 int db8500_prcmu_enable_dsipll(void)
562 /* Clear DSIPLL_RESETN */
563 writel(PRCMU_RESET_DSIPLL
, PRCM_APE_RESETN_CLR
);
564 /* Unclamp DSIPLL in/out */
565 writel(PRCMU_UNCLAMP_DSIPLL
, PRCM_MMIP_LS_CLAMP_CLR
);
567 /* Set DSI PLL FREQ */
568 writel(PRCMU_PLLDSI_FREQ_SETTING
, PRCM_PLLDSI_FREQ
);
569 writel(PRCMU_DSI_PLLOUT_SEL_SETTING
, PRCM_DSI_PLLOUT_SEL
);
570 /* Enable Escape clocks */
571 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV
, PRCM_DSITVCLK_DIV
);
574 writel(PRCMU_ENABLE_PLLDSI
, PRCM_PLLDSI_ENABLE
);
576 writel(PRCMU_DSI_RESET_SW
, PRCM_DSI_SW_RESET
);
577 for (i
= 0; i
< 10; i
++) {
578 if ((readl(PRCM_PLLDSI_LOCKP
) & PRCMU_PLLDSI_LOCKP_LOCKED
)
579 == PRCMU_PLLDSI_LOCKP_LOCKED
)
583 /* Set DSIPLL_RESETN */
584 writel(PRCMU_RESET_DSIPLL
, PRCM_APE_RESETN_SET
);
588 int db8500_prcmu_disable_dsipll(void)
590 /* Disable dsi pll */
591 writel(PRCMU_DISABLE_PLLDSI
, PRCM_PLLDSI_ENABLE
);
592 /* Disable escapeclock */
593 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV
, PRCM_DSITVCLK_DIV
);
597 int db8500_prcmu_set_display_clocks(void)
601 spin_lock_irqsave(&clk_mgt_lock
, flags
);
603 /* Grab the HW semaphore. */
604 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
607 writel(PRCMU_DSI_CLOCK_SETTING
, PRCM_HDMICLK_MGT
);
608 writel(PRCMU_DSI_LP_CLOCK_SETTING
, PRCM_TVCLK_MGT
);
609 writel(PRCMU_DPI_CLOCK_SETTING
, PRCM_LCDCLK_MGT
);
611 /* Release the HW semaphore. */
614 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
619 u32
db8500_prcmu_read(unsigned int reg
)
621 return readl(_PRCMU_BASE
+ reg
);
624 void db8500_prcmu_write(unsigned int reg
, u32 value
)
628 spin_lock_irqsave(&prcmu_lock
, flags
);
629 writel(value
, (_PRCMU_BASE
+ reg
));
630 spin_unlock_irqrestore(&prcmu_lock
, flags
);
633 void db8500_prcmu_write_masked(unsigned int reg
, u32 mask
, u32 value
)
638 spin_lock_irqsave(&prcmu_lock
, flags
);
639 val
= readl(_PRCMU_BASE
+ reg
);
640 val
= ((val
& ~mask
) | (value
& mask
));
641 writel(val
, (_PRCMU_BASE
+ reg
));
642 spin_unlock_irqrestore(&prcmu_lock
, flags
);
645 struct prcmu_fw_version
*prcmu_get_fw_version(void)
647 return fw_info
.valid
? &fw_info
.version
: NULL
;
650 bool prcmu_has_arm_maxopp(void)
652 return (readb(tcdm_base
+ PRCM_AVS_VARM_MAX_OPP
) &
653 PRCM_AVS_ISMODEENABLE_MASK
) == PRCM_AVS_ISMODEENABLE_MASK
;
657 * prcmu_get_boot_status - PRCMU boot status checking
658 * Returns: the current PRCMU boot status
660 int prcmu_get_boot_status(void)
662 return readb(tcdm_base
+ PRCM_BOOT_STATUS
);
666 * prcmu_set_rc_a2p - This function is used to run few power state sequences
667 * @val: Value to be set, i.e. transition requested
668 * Returns: 0 on success, -EINVAL on invalid argument
670 * This function is used to run the following power state sequences -
671 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
673 int prcmu_set_rc_a2p(enum romcode_write val
)
675 if (val
< RDY_2_DS
|| val
> RDY_2_XP70_RST
)
677 writeb(val
, (tcdm_base
+ PRCM_ROMCODE_A2P
));
682 * prcmu_get_rc_p2a - This function is used to get power state sequences
683 * Returns: the power transition that has last happened
685 * This function can return the following transitions-
686 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
688 enum romcode_read
prcmu_get_rc_p2a(void)
690 return readb(tcdm_base
+ PRCM_ROMCODE_P2A
);
694 * prcmu_get_current_mode - Return the current XP70 power mode
695 * Returns: Returns the current AP(ARM) power mode: init,
696 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
698 enum ap_pwrst
prcmu_get_xp70_current_state(void)
700 return readb(tcdm_base
+ PRCM_XP70_CUR_PWR_STATE
);
704 * prcmu_config_clkout - Configure one of the programmable clock outputs.
705 * @clkout: The CLKOUT number (0 or 1).
706 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
707 * @div: The divider to be applied.
709 * Configures one of the programmable clock outputs (CLKOUTs).
710 * @div should be in the range [1,63] to request a configuration, or 0 to
711 * inform that the configuration is no longer requested.
713 int prcmu_config_clkout(u8 clkout
, u8 source
, u8 div
)
715 static int requests
[2];
725 BUG_ON((clkout
== 0) && (source
> PRCMU_CLKSRC_CLK009
));
727 if (!div
&& !requests
[clkout
])
732 div_mask
= PRCM_CLKOCR_CLKODIV0_MASK
;
733 mask
= (PRCM_CLKOCR_CLKODIV0_MASK
| PRCM_CLKOCR_CLKOSEL0_MASK
);
734 bits
= ((source
<< PRCM_CLKOCR_CLKOSEL0_SHIFT
) |
735 (div
<< PRCM_CLKOCR_CLKODIV0_SHIFT
));
738 div_mask
= PRCM_CLKOCR_CLKODIV1_MASK
;
739 mask
= (PRCM_CLKOCR_CLKODIV1_MASK
| PRCM_CLKOCR_CLKOSEL1_MASK
|
740 PRCM_CLKOCR_CLK1TYPE
);
741 bits
= ((source
<< PRCM_CLKOCR_CLKOSEL1_SHIFT
) |
742 (div
<< PRCM_CLKOCR_CLKODIV1_SHIFT
));
747 spin_lock_irqsave(&clkout_lock
, flags
);
749 val
= readl(PRCM_CLKOCR
);
750 if (val
& div_mask
) {
752 if ((val
& mask
) != bits
) {
754 goto unlock_and_return
;
757 if ((val
& mask
& ~div_mask
) != bits
) {
759 goto unlock_and_return
;
763 writel((bits
| (val
& ~mask
)), PRCM_CLKOCR
);
764 requests
[clkout
] += (div
? 1 : -1);
767 spin_unlock_irqrestore(&clkout_lock
, flags
);
772 int db8500_prcmu_set_power_state(u8 state
, bool keep_ulp_clk
, bool keep_ap_pll
)
776 BUG_ON((state
< PRCMU_AP_SLEEP
) || (PRCMU_AP_DEEP_IDLE
< state
));
778 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
780 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(0))
783 writeb(MB0H_POWER_STATE_TRANS
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB0
));
784 writeb(state
, (tcdm_base
+ PRCM_REQ_MB0_AP_POWER_STATE
));
785 writeb((keep_ap_pll
? 1 : 0), (tcdm_base
+ PRCM_REQ_MB0_AP_PLL_STATE
));
786 writeb((keep_ulp_clk
? 1 : 0),
787 (tcdm_base
+ PRCM_REQ_MB0_ULP_CLOCK_STATE
));
788 writeb(0, (tcdm_base
+ PRCM_REQ_MB0_DO_NOT_WFI
));
789 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET
);
791 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
796 u8
db8500_prcmu_get_power_state_result(void)
798 return readb(tcdm_base
+ PRCM_ACK_MB0_AP_PWRSTTR_STATUS
);
801 /* This function decouple the gic from the prcmu */
802 int db8500_prcmu_gic_decouple(void)
804 u32 val
= readl(PRCM_A9_MASK_REQ
);
806 /* Set bit 0 register value to 1 */
807 writel(val
| PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ
,
810 /* Make sure the register is updated */
811 readl(PRCM_A9_MASK_REQ
);
813 /* Wait a few cycles for the gic mask completion */
819 /* This function recouple the gic with the prcmu */
820 int db8500_prcmu_gic_recouple(void)
822 u32 val
= readl(PRCM_A9_MASK_REQ
);
824 /* Set bit 0 register value to 0 */
825 writel(val
& ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ
, PRCM_A9_MASK_REQ
);
830 #define PRCMU_GIC_NUMBER_REGS 5
833 * This function checks if there are pending irq on the gic. It only
834 * makes sense if the gic has been decoupled before with the
835 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
836 * disables the forwarding of the interrupt to any CPU interface. It
837 * does not prevent the interrupt from changing state, for example
838 * becoming pending, or active and pending if it is already
839 * active. Hence, we have to check the interrupt is pending *and* is
842 bool db8500_prcmu_gic_pending_irq(void)
844 u32 pr
; /* Pending register */
845 u32 er
; /* Enable register */
846 void __iomem
*dist_base
= __io_address(U8500_GIC_DIST_BASE
);
849 /* 5 registers. STI & PPI not skipped */
850 for (i
= 0; i
< PRCMU_GIC_NUMBER_REGS
; i
++) {
852 pr
= readl_relaxed(dist_base
+ GIC_DIST_PENDING_SET
+ i
* 4);
853 er
= readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
856 return true; /* There is a pending interrupt */
863 * This function checks if there are pending interrupt on the
864 * prcmu which has been delegated to monitor the irqs with the
865 * db8500_prcmu_copy_gic_settings function.
867 bool db8500_prcmu_pending_irq(void)
872 for (i
= 0; i
< PRCMU_GIC_NUMBER_REGS
- 1; i
++) {
873 it
= readl(PRCM_ARMITVAL31TO0
+ i
* 4);
874 im
= readl(PRCM_ARMITMSK31TO0
+ i
* 4);
876 return true; /* There is a pending interrupt */
883 * This function checks if the specified cpu is in in WFI. It's usage
884 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
885 * function. Of course passing smp_processor_id() to this function will
886 * always return false...
888 bool db8500_prcmu_is_cpu_in_wfi(int cpu
)
890 return readl(PRCM_ARM_WFI_STANDBY
) & cpu
? PRCM_ARM_WFI_STANDBY_WFI1
:
891 PRCM_ARM_WFI_STANDBY_WFI0
;
895 * This function copies the gic SPI settings to the prcmu in order to
896 * monitor them and abort/finish the retention/off sequence or state.
898 int db8500_prcmu_copy_gic_settings(void)
900 u32 er
; /* Enable register */
901 void __iomem
*dist_base
= __io_address(U8500_GIC_DIST_BASE
);
904 /* We skip the STI and PPI */
905 for (i
= 0; i
< PRCMU_GIC_NUMBER_REGS
- 1; i
++) {
906 er
= readl_relaxed(dist_base
+
907 GIC_DIST_ENABLE_SET
+ (i
+ 1) * 4);
908 writel(er
, PRCM_ARMITMSK31TO0
+ i
* 4);
914 /* This function should only be called while mb0_transfer.lock is held. */
915 static void config_wakeups(void)
917 const u8 header
[2] = {
918 MB0H_CONFIG_WAKEUPS_EXE
,
919 MB0H_CONFIG_WAKEUPS_SLEEP
921 static u32 last_dbb_events
;
922 static u32 last_abb_events
;
927 dbb_events
= mb0_transfer
.req
.dbb_irqs
| mb0_transfer
.req
.dbb_wakeups
;
928 dbb_events
|= (WAKEUP_BIT_AC_WAKE_ACK
| WAKEUP_BIT_AC_SLEEP_ACK
);
930 abb_events
= mb0_transfer
.req
.abb_events
;
932 if ((dbb_events
== last_dbb_events
) && (abb_events
== last_abb_events
))
935 for (i
= 0; i
< 2; i
++) {
936 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(0))
938 writel(dbb_events
, (tcdm_base
+ PRCM_REQ_MB0_WAKEUP_8500
));
939 writel(abb_events
, (tcdm_base
+ PRCM_REQ_MB0_WAKEUP_4500
));
940 writeb(header
[i
], (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB0
));
941 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET
);
943 last_dbb_events
= dbb_events
;
944 last_abb_events
= abb_events
;
947 void db8500_prcmu_enable_wakeups(u32 wakeups
)
953 BUG_ON(wakeups
!= (wakeups
& VALID_WAKEUPS
));
955 for (i
= 0, bits
= 0; i
< NUM_PRCMU_WAKEUP_INDICES
; i
++) {
956 if (wakeups
& BIT(i
))
957 bits
|= prcmu_wakeup_bit
[i
];
960 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
962 mb0_transfer
.req
.dbb_wakeups
= bits
;
965 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
968 void db8500_prcmu_config_abb_event_readout(u32 abb_events
)
972 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
974 mb0_transfer
.req
.abb_events
= abb_events
;
977 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
980 void db8500_prcmu_get_abb_event_buffer(void __iomem
**buf
)
982 if (readb(tcdm_base
+ PRCM_ACK_MB0_READ_POINTER
) & 1)
983 *buf
= (tcdm_base
+ PRCM_ACK_MB0_WAKEUP_1_4500
);
985 *buf
= (tcdm_base
+ PRCM_ACK_MB0_WAKEUP_0_4500
);
989 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
990 * @opp: The new ARM operating point to which transition is to be made
991 * Returns: 0 on success, non-zero on failure
993 * This function sets the the operating point of the ARM.
995 int db8500_prcmu_set_arm_opp(u8 opp
)
999 if (opp
< ARM_NO_CHANGE
|| opp
> ARM_EXTCLK
)
1004 mutex_lock(&mb1_transfer
.lock
);
1006 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1009 writeb(MB1H_ARM_APE_OPP
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1010 writeb(opp
, (tcdm_base
+ PRCM_REQ_MB1_ARM_OPP
));
1011 writeb(APE_NO_CHANGE
, (tcdm_base
+ PRCM_REQ_MB1_APE_OPP
));
1013 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1014 wait_for_completion(&mb1_transfer
.work
);
1016 if ((mb1_transfer
.ack
.header
!= MB1H_ARM_APE_OPP
) ||
1017 (mb1_transfer
.ack
.arm_opp
!= opp
))
1020 compute_armss_rate();
1021 mutex_unlock(&mb1_transfer
.lock
);
1027 * db8500_prcmu_get_arm_opp - get the current ARM OPP
1029 * Returns: the current ARM OPP
1031 int db8500_prcmu_get_arm_opp(void)
1033 return readb(tcdm_base
+ PRCM_ACK_MB1_CURRENT_ARM_OPP
);
1037 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1039 * Returns: the current DDR OPP
1041 int db8500_prcmu_get_ddr_opp(void)
1043 return readb(PRCM_DDR_SUBSYS_APE_MINBW
);
1047 * db8500_set_ddr_opp - set the appropriate DDR OPP
1048 * @opp: The new DDR operating point to which transition is to be made
1049 * Returns: 0 on success, non-zero on failure
1051 * This function sets the operating point of the DDR.
1053 int db8500_prcmu_set_ddr_opp(u8 opp
)
1055 if (opp
< DDR_100_OPP
|| opp
> DDR_25_OPP
)
1057 /* Changing the DDR OPP can hang the hardware pre-v21 */
1058 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
1059 writeb(opp
, PRCM_DDR_SUBSYS_APE_MINBW
);
1064 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1065 static void request_even_slower_clocks(bool enable
)
1067 void __iomem
*clock_reg
[] = {
1071 unsigned long flags
;
1074 spin_lock_irqsave(&clk_mgt_lock
, flags
);
1076 /* Grab the HW semaphore. */
1077 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
1080 for (i
= 0; i
< ARRAY_SIZE(clock_reg
); i
++) {
1084 val
= readl(clock_reg
[i
]);
1085 div
= (val
& PRCM_CLK_MGT_CLKPLLDIV_MASK
);
1087 if ((div
<= 1) || (div
> 15)) {
1088 pr_err("prcmu: Bad clock divider %d in %s\n",
1090 goto unlock_and_return
;
1095 goto unlock_and_return
;
1098 val
= ((val
& ~PRCM_CLK_MGT_CLKPLLDIV_MASK
) |
1099 (div
& PRCM_CLK_MGT_CLKPLLDIV_MASK
));
1100 writel(val
, clock_reg
[i
]);
1104 /* Release the HW semaphore. */
1105 writel(0, PRCM_SEM
);
1107 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
1111 * db8500_set_ape_opp - set the appropriate APE OPP
1112 * @opp: The new APE operating point to which transition is to be made
1113 * Returns: 0 on success, non-zero on failure
1115 * This function sets the operating point of the APE.
1117 int db8500_prcmu_set_ape_opp(u8 opp
)
1121 if (opp
== mb1_transfer
.ape_opp
)
1124 mutex_lock(&mb1_transfer
.lock
);
1126 if (mb1_transfer
.ape_opp
== APE_50_PARTLY_25_OPP
)
1127 request_even_slower_clocks(false);
1129 if ((opp
!= APE_100_OPP
) && (mb1_transfer
.ape_opp
!= APE_100_OPP
))
1132 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1135 writeb(MB1H_ARM_APE_OPP
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1136 writeb(ARM_NO_CHANGE
, (tcdm_base
+ PRCM_REQ_MB1_ARM_OPP
));
1137 writeb(((opp
== APE_50_PARTLY_25_OPP
) ? APE_50_OPP
: opp
),
1138 (tcdm_base
+ PRCM_REQ_MB1_APE_OPP
));
1140 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1141 wait_for_completion(&mb1_transfer
.work
);
1143 if ((mb1_transfer
.ack
.header
!= MB1H_ARM_APE_OPP
) ||
1144 (mb1_transfer
.ack
.ape_opp
!= opp
))
1148 if ((!r
&& (opp
== APE_50_PARTLY_25_OPP
)) ||
1149 (r
&& (mb1_transfer
.ape_opp
== APE_50_PARTLY_25_OPP
)))
1150 request_even_slower_clocks(true);
1152 mb1_transfer
.ape_opp
= opp
;
1154 mutex_unlock(&mb1_transfer
.lock
);
1160 * db8500_prcmu_get_ape_opp - get the current APE OPP
1162 * Returns: the current APE OPP
1164 int db8500_prcmu_get_ape_opp(void)
1166 return readb(tcdm_base
+ PRCM_ACK_MB1_CURRENT_APE_OPP
);
1170 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1171 * @enable: true to request the higher voltage, false to drop a request.
1173 * Calls to this function to enable and disable requests must be balanced.
1175 int prcmu_request_ape_opp_100_voltage(bool enable
)
1179 static unsigned int requests
;
1181 mutex_lock(&mb1_transfer
.lock
);
1184 if (0 != requests
++)
1185 goto unlock_and_return
;
1186 header
= MB1H_REQUEST_APE_OPP_100_VOLT
;
1188 if (requests
== 0) {
1190 goto unlock_and_return
;
1191 } else if (1 != requests
--) {
1192 goto unlock_and_return
;
1194 header
= MB1H_RELEASE_APE_OPP_100_VOLT
;
1197 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1200 writeb(header
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1202 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1203 wait_for_completion(&mb1_transfer
.work
);
1205 if ((mb1_transfer
.ack
.header
!= header
) ||
1206 ((mb1_transfer
.ack
.ape_voltage_status
& BIT(0)) != 0))
1210 mutex_unlock(&mb1_transfer
.lock
);
1216 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1218 * This function releases the power state requirements of a USB wakeup.
1220 int prcmu_release_usb_wakeup_state(void)
1224 mutex_lock(&mb1_transfer
.lock
);
1226 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1229 writeb(MB1H_RELEASE_USB_WAKEUP
,
1230 (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1232 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1233 wait_for_completion(&mb1_transfer
.work
);
1235 if ((mb1_transfer
.ack
.header
!= MB1H_RELEASE_USB_WAKEUP
) ||
1236 ((mb1_transfer
.ack
.ape_voltage_status
& BIT(0)) != 0))
1239 mutex_unlock(&mb1_transfer
.lock
);
1244 static int request_pll(u8 clock
, bool enable
)
1248 if (clock
== PRCMU_PLLSOC0
)
1249 clock
= (enable
? PLL_SOC0_ON
: PLL_SOC0_OFF
);
1250 else if (clock
== PRCMU_PLLSOC1
)
1251 clock
= (enable
? PLL_SOC1_ON
: PLL_SOC1_OFF
);
1255 mutex_lock(&mb1_transfer
.lock
);
1257 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1260 writeb(MB1H_PLL_ON_OFF
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1261 writeb(clock
, (tcdm_base
+ PRCM_REQ_MB1_PLL_ON_OFF
));
1263 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1264 wait_for_completion(&mb1_transfer
.work
);
1266 if (mb1_transfer
.ack
.header
!= MB1H_PLL_ON_OFF
)
1269 mutex_unlock(&mb1_transfer
.lock
);
1275 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1276 * @epod_id: The EPOD to set
1277 * @epod_state: The new EPOD state
1279 * This function sets the state of a EPOD (power domain). It may not be called
1280 * from interrupt context.
1282 int db8500_prcmu_set_epod(u16 epod_id
, u8 epod_state
)
1285 bool ram_retention
= false;
1288 /* check argument */
1289 BUG_ON(epod_id
>= NUM_EPOD_ID
);
1291 /* set flag if retention is possible */
1293 case EPOD_ID_SVAMMDSP
:
1294 case EPOD_ID_SIAMMDSP
:
1295 case EPOD_ID_ESRAM12
:
1296 case EPOD_ID_ESRAM34
:
1297 ram_retention
= true;
1301 /* check argument */
1302 BUG_ON(epod_state
> EPOD_STATE_ON
);
1303 BUG_ON(epod_state
== EPOD_STATE_RAMRET
&& !ram_retention
);
1306 mutex_lock(&mb2_transfer
.lock
);
1308 /* wait for mailbox */
1309 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(2))
1312 /* fill in mailbox */
1313 for (i
= 0; i
< NUM_EPOD_ID
; i
++)
1314 writeb(EPOD_STATE_NO_CHANGE
, (tcdm_base
+ PRCM_REQ_MB2
+ i
));
1315 writeb(epod_state
, (tcdm_base
+ PRCM_REQ_MB2
+ epod_id
));
1317 writeb(MB2H_DPS
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB2
));
1319 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET
);
1322 * The current firmware version does not handle errors correctly,
1323 * and we cannot recover if there is an error.
1324 * This is expected to change when the firmware is updated.
1326 if (!wait_for_completion_timeout(&mb2_transfer
.work
,
1327 msecs_to_jiffies(20000))) {
1328 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1331 goto unlock_and_return
;
1334 if (mb2_transfer
.ack
.status
!= HWACC_PWR_ST_OK
)
1338 mutex_unlock(&mb2_transfer
.lock
);
1343 * prcmu_configure_auto_pm - Configure autonomous power management.
1344 * @sleep: Configuration for ApSleep.
1345 * @idle: Configuration for ApIdle.
1347 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config
*sleep
,
1348 struct prcmu_auto_pm_config
*idle
)
1352 unsigned long flags
;
1354 BUG_ON((sleep
== NULL
) || (idle
== NULL
));
1356 sleep_cfg
= (sleep
->sva_auto_pm_enable
& 0xF);
1357 sleep_cfg
= ((sleep_cfg
<< 4) | (sleep
->sia_auto_pm_enable
& 0xF));
1358 sleep_cfg
= ((sleep_cfg
<< 8) | (sleep
->sva_power_on
& 0xFF));
1359 sleep_cfg
= ((sleep_cfg
<< 8) | (sleep
->sia_power_on
& 0xFF));
1360 sleep_cfg
= ((sleep_cfg
<< 4) | (sleep
->sva_policy
& 0xF));
1361 sleep_cfg
= ((sleep_cfg
<< 4) | (sleep
->sia_policy
& 0xF));
1363 idle_cfg
= (idle
->sva_auto_pm_enable
& 0xF);
1364 idle_cfg
= ((idle_cfg
<< 4) | (idle
->sia_auto_pm_enable
& 0xF));
1365 idle_cfg
= ((idle_cfg
<< 8) | (idle
->sva_power_on
& 0xFF));
1366 idle_cfg
= ((idle_cfg
<< 8) | (idle
->sia_power_on
& 0xFF));
1367 idle_cfg
= ((idle_cfg
<< 4) | (idle
->sva_policy
& 0xF));
1368 idle_cfg
= ((idle_cfg
<< 4) | (idle
->sia_policy
& 0xF));
1370 spin_lock_irqsave(&mb2_transfer
.auto_pm_lock
, flags
);
1373 * The autonomous power management configuration is done through
1374 * fields in mailbox 2, but these fields are only used as shared
1375 * variables - i.e. there is no need to send a message.
1377 writel(sleep_cfg
, (tcdm_base
+ PRCM_REQ_MB2_AUTO_PM_SLEEP
));
1378 writel(idle_cfg
, (tcdm_base
+ PRCM_REQ_MB2_AUTO_PM_IDLE
));
1380 mb2_transfer
.auto_pm_enabled
=
1381 ((sleep
->sva_auto_pm_enable
== PRCMU_AUTO_PM_ON
) ||
1382 (sleep
->sia_auto_pm_enable
== PRCMU_AUTO_PM_ON
) ||
1383 (idle
->sva_auto_pm_enable
== PRCMU_AUTO_PM_ON
) ||
1384 (idle
->sia_auto_pm_enable
== PRCMU_AUTO_PM_ON
));
1386 spin_unlock_irqrestore(&mb2_transfer
.auto_pm_lock
, flags
);
1388 EXPORT_SYMBOL(prcmu_configure_auto_pm
);
1390 bool prcmu_is_auto_pm_enabled(void)
1392 return mb2_transfer
.auto_pm_enabled
;
1395 static int request_sysclk(bool enable
)
1398 unsigned long flags
;
1402 mutex_lock(&mb3_transfer
.sysclk_lock
);
1404 spin_lock_irqsave(&mb3_transfer
.lock
, flags
);
1406 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(3))
1409 writeb((enable
? ON
: OFF
), (tcdm_base
+ PRCM_REQ_MB3_SYSCLK_MGT
));
1411 writeb(MB3H_SYSCLK
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB3
));
1412 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET
);
1414 spin_unlock_irqrestore(&mb3_transfer
.lock
, flags
);
1417 * The firmware only sends an ACK if we want to enable the
1418 * SysClk, and it succeeds.
1420 if (enable
&& !wait_for_completion_timeout(&mb3_transfer
.sysclk_work
,
1421 msecs_to_jiffies(20000))) {
1422 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1427 mutex_unlock(&mb3_transfer
.sysclk_lock
);
1432 static int request_timclk(bool enable
)
1434 u32 val
= (PRCM_TCR_DOZE_MODE
| PRCM_TCR_TENSEL_MASK
);
1437 val
|= PRCM_TCR_STOP_TIMERS
;
1438 writel(val
, PRCM_TCR
);
1443 static int request_clock(u8 clock
, bool enable
)
1446 unsigned long flags
;
1448 spin_lock_irqsave(&clk_mgt_lock
, flags
);
1450 /* Grab the HW semaphore. */
1451 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
1454 val
= readl(clk_mgt
[clock
].reg
);
1456 val
|= (PRCM_CLK_MGT_CLKEN
| clk_mgt
[clock
].pllsw
);
1458 clk_mgt
[clock
].pllsw
= (val
& PRCM_CLK_MGT_CLKPLLSW_MASK
);
1459 val
&= ~(PRCM_CLK_MGT_CLKEN
| PRCM_CLK_MGT_CLKPLLSW_MASK
);
1461 writel(val
, clk_mgt
[clock
].reg
);
1463 /* Release the HW semaphore. */
1464 writel(0, PRCM_SEM
);
1466 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
1471 static int request_sga_clock(u8 clock
, bool enable
)
1477 val
= readl(PRCM_CGATING_BYPASS
);
1478 writel(val
| PRCM_CGATING_BYPASS_ICN2
, PRCM_CGATING_BYPASS
);
1481 ret
= request_clock(clock
, enable
);
1483 if (!ret
&& !enable
) {
1484 val
= readl(PRCM_CGATING_BYPASS
);
1485 writel(val
& ~PRCM_CGATING_BYPASS_ICN2
, PRCM_CGATING_BYPASS
);
1491 static inline bool plldsi_locked(void)
1493 return (readl(PRCM_PLLDSI_LOCKP
) &
1494 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10
|
1495 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3
)) ==
1496 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10
|
1497 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3
);
1500 static int request_plldsi(bool enable
)
1505 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP
|
1506 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI
), (enable
?
1507 PRCM_MMIP_LS_CLAMP_CLR
: PRCM_MMIP_LS_CLAMP_SET
));
1509 val
= readl(PRCM_PLLDSI_ENABLE
);
1511 val
|= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
;
1513 val
&= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
;
1514 writel(val
, PRCM_PLLDSI_ENABLE
);
1518 bool locked
= plldsi_locked();
1520 for (i
= 10; !locked
&& (i
> 0); --i
) {
1522 locked
= plldsi_locked();
1525 writel(PRCM_APE_RESETN_DSIPLL_RESETN
,
1526 PRCM_APE_RESETN_SET
);
1528 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP
|
1529 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI
),
1530 PRCM_MMIP_LS_CLAMP_SET
);
1531 val
&= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
;
1532 writel(val
, PRCM_PLLDSI_ENABLE
);
1536 writel(PRCM_APE_RESETN_DSIPLL_RESETN
, PRCM_APE_RESETN_CLR
);
1541 static int request_dsiclk(u8 n
, bool enable
)
1545 val
= readl(PRCM_DSI_PLLOUT_SEL
);
1546 val
&= ~dsiclk
[n
].divsel_mask
;
1547 val
|= ((enable
? dsiclk
[n
].divsel
: PRCM_DSI_PLLOUT_SEL_OFF
) <<
1548 dsiclk
[n
].divsel_shift
);
1549 writel(val
, PRCM_DSI_PLLOUT_SEL
);
1553 static int request_dsiescclk(u8 n
, bool enable
)
1557 val
= readl(PRCM_DSITVCLK_DIV
);
1558 enable
? (val
|= dsiescclk
[n
].en
) : (val
&= ~dsiescclk
[n
].en
);
1559 writel(val
, PRCM_DSITVCLK_DIV
);
1564 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1565 * @clock: The clock for which the request is made.
1566 * @enable: Whether the clock should be enabled (true) or disabled (false).
1568 * This function should only be used by the clock implementation.
1569 * Do not use it from any other place!
1571 int db8500_prcmu_request_clock(u8 clock
, bool enable
)
1573 if (clock
== PRCMU_SGACLK
)
1574 return request_sga_clock(clock
, enable
);
1575 else if (clock
< PRCMU_NUM_REG_CLOCKS
)
1576 return request_clock(clock
, enable
);
1577 else if (clock
== PRCMU_TIMCLK
)
1578 return request_timclk(enable
);
1579 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
1580 return request_dsiclk((clock
- PRCMU_DSI0CLK
), enable
);
1581 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
1582 return request_dsiescclk((clock
- PRCMU_DSI0ESCCLK
), enable
);
1583 else if (clock
== PRCMU_PLLDSI
)
1584 return request_plldsi(enable
);
1585 else if (clock
== PRCMU_SYSCLK
)
1586 return request_sysclk(enable
);
1587 else if ((clock
== PRCMU_PLLSOC0
) || (clock
== PRCMU_PLLSOC1
))
1588 return request_pll(clock
, enable
);
1593 static unsigned long pll_rate(void __iomem
*reg
, unsigned long src_rate
,
1604 rate
*= ((val
& PRCM_PLL_FREQ_D_MASK
) >> PRCM_PLL_FREQ_D_SHIFT
);
1606 d
= ((val
& PRCM_PLL_FREQ_N_MASK
) >> PRCM_PLL_FREQ_N_SHIFT
);
1610 d
= ((val
& PRCM_PLL_FREQ_R_MASK
) >> PRCM_PLL_FREQ_R_SHIFT
);
1614 if (val
& PRCM_PLL_FREQ_SELDIV2
)
1617 if ((branch
== PLL_FIX
) || ((branch
== PLL_DIV
) &&
1618 (val
& PRCM_PLL_FREQ_DIV2EN
) &&
1619 ((reg
== PRCM_PLLSOC0_FREQ
) ||
1620 (reg
== PRCM_PLLARM_FREQ
) ||
1621 (reg
== PRCM_PLLDDR_FREQ
))))
1624 (void)do_div(rate
, div
);
1626 return (unsigned long)rate
;
1629 #define ROOT_CLOCK_RATE 38400000
1631 static unsigned long clock_rate(u8 clock
)
1635 unsigned long rate
= ROOT_CLOCK_RATE
;
1637 val
= readl(clk_mgt
[clock
].reg
);
1639 if (val
& PRCM_CLK_MGT_CLK38
) {
1640 if (clk_mgt
[clock
].clk38div
&& (val
& PRCM_CLK_MGT_CLK38DIV
))
1645 val
|= clk_mgt
[clock
].pllsw
;
1646 pllsw
= (val
& PRCM_CLK_MGT_CLKPLLSW_MASK
);
1648 if (pllsw
== PRCM_CLK_MGT_CLKPLLSW_SOC0
)
1649 rate
= pll_rate(PRCM_PLLSOC0_FREQ
, rate
, clk_mgt
[clock
].branch
);
1650 else if (pllsw
== PRCM_CLK_MGT_CLKPLLSW_SOC1
)
1651 rate
= pll_rate(PRCM_PLLSOC1_FREQ
, rate
, clk_mgt
[clock
].branch
);
1652 else if (pllsw
== PRCM_CLK_MGT_CLKPLLSW_DDR
)
1653 rate
= pll_rate(PRCM_PLLDDR_FREQ
, rate
, clk_mgt
[clock
].branch
);
1657 if ((clock
== PRCMU_SGACLK
) &&
1658 (val
& PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
)) {
1659 u64 r
= (rate
* 10);
1661 (void)do_div(r
, 25);
1662 return (unsigned long)r
;
1664 val
&= PRCM_CLK_MGT_CLKPLLDIV_MASK
;
1670 static unsigned long latest_armss_rate
;
1671 static unsigned long armss_rate(void)
1673 return latest_armss_rate
;
1676 static void compute_armss_rate(void)
1681 r
= readl(PRCM_ARM_CHGCLKREQ
);
1683 if (r
& PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ
) {
1684 /* External ARMCLKFIX clock */
1686 rate
= pll_rate(PRCM_PLLDDR_FREQ
, ROOT_CLOCK_RATE
, PLL_FIX
);
1688 /* Check PRCM_ARM_CHGCLKREQ divider */
1689 if (!(r
& PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL
))
1692 /* Check PRCM_ARMCLKFIX_MGT divider */
1693 r
= readl(PRCM_ARMCLKFIX_MGT
);
1694 r
&= PRCM_CLK_MGT_CLKPLLDIV_MASK
;
1697 } else {/* ARM PLL */
1698 rate
= pll_rate(PRCM_PLLARM_FREQ
, ROOT_CLOCK_RATE
, PLL_DIV
);
1701 latest_armss_rate
= rate
;
1704 static unsigned long dsiclk_rate(u8 n
)
1709 divsel
= readl(PRCM_DSI_PLLOUT_SEL
);
1710 divsel
= ((divsel
& dsiclk
[n
].divsel_mask
) >> dsiclk
[n
].divsel_shift
);
1712 if (divsel
== PRCM_DSI_PLLOUT_SEL_OFF
)
1713 divsel
= dsiclk
[n
].divsel
;
1716 case PRCM_DSI_PLLOUT_SEL_PHI_4
:
1718 case PRCM_DSI_PLLOUT_SEL_PHI_2
:
1720 case PRCM_DSI_PLLOUT_SEL_PHI
:
1721 return pll_rate(PRCM_PLLDSI_FREQ
, clock_rate(PRCMU_HDMICLK
),
1728 static unsigned long dsiescclk_rate(u8 n
)
1732 div
= readl(PRCM_DSITVCLK_DIV
);
1733 div
= ((div
& dsiescclk
[n
].div_mask
) >> (dsiescclk
[n
].div_shift
));
1734 return clock_rate(PRCMU_TVCLK
) / max((u32
)1, div
);
1737 unsigned long prcmu_clock_rate(u8 clock
)
1739 if (clock
< PRCMU_NUM_REG_CLOCKS
)
1740 return clock_rate(clock
);
1741 else if (clock
== PRCMU_TIMCLK
)
1742 return ROOT_CLOCK_RATE
/ 16;
1743 else if (clock
== PRCMU_SYSCLK
)
1744 return ROOT_CLOCK_RATE
;
1745 else if (clock
== PRCMU_PLLSOC0
)
1746 return pll_rate(PRCM_PLLSOC0_FREQ
, ROOT_CLOCK_RATE
, PLL_RAW
);
1747 else if (clock
== PRCMU_PLLSOC1
)
1748 return pll_rate(PRCM_PLLSOC1_FREQ
, ROOT_CLOCK_RATE
, PLL_RAW
);
1749 else if (clock
== PRCMU_ARMSS
)
1750 return armss_rate();
1751 else if (clock
== PRCMU_PLLDDR
)
1752 return pll_rate(PRCM_PLLDDR_FREQ
, ROOT_CLOCK_RATE
, PLL_RAW
);
1753 else if (clock
== PRCMU_PLLDSI
)
1754 return pll_rate(PRCM_PLLDSI_FREQ
, clock_rate(PRCMU_HDMICLK
),
1756 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
1757 return dsiclk_rate(clock
- PRCMU_DSI0CLK
);
1758 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
1759 return dsiescclk_rate(clock
- PRCMU_DSI0ESCCLK
);
1764 static unsigned long clock_source_rate(u32 clk_mgt_val
, int branch
)
1766 if (clk_mgt_val
& PRCM_CLK_MGT_CLK38
)
1767 return ROOT_CLOCK_RATE
;
1768 clk_mgt_val
&= PRCM_CLK_MGT_CLKPLLSW_MASK
;
1769 if (clk_mgt_val
== PRCM_CLK_MGT_CLKPLLSW_SOC0
)
1770 return pll_rate(PRCM_PLLSOC0_FREQ
, ROOT_CLOCK_RATE
, branch
);
1771 else if (clk_mgt_val
== PRCM_CLK_MGT_CLKPLLSW_SOC1
)
1772 return pll_rate(PRCM_PLLSOC1_FREQ
, ROOT_CLOCK_RATE
, branch
);
1773 else if (clk_mgt_val
== PRCM_CLK_MGT_CLKPLLSW_DDR
)
1774 return pll_rate(PRCM_PLLDDR_FREQ
, ROOT_CLOCK_RATE
, branch
);
1779 static u32
clock_divider(unsigned long src_rate
, unsigned long rate
)
1783 div
= (src_rate
/ rate
);
1786 if (rate
< (src_rate
/ div
))
1791 static long round_clock_rate(u8 clock
, unsigned long rate
)
1795 unsigned long src_rate
;
1798 val
= readl(clk_mgt
[clock
].reg
);
1799 src_rate
= clock_source_rate((val
| clk_mgt
[clock
].pllsw
),
1800 clk_mgt
[clock
].branch
);
1801 div
= clock_divider(src_rate
, rate
);
1802 if (val
& PRCM_CLK_MGT_CLK38
) {
1803 if (clk_mgt
[clock
].clk38div
) {
1809 } else if ((clock
== PRCMU_SGACLK
) && (div
== 3)) {
1810 u64 r
= (src_rate
* 10);
1812 (void)do_div(r
, 25);
1814 return (unsigned long)r
;
1816 rounded_rate
= (src_rate
/ min(div
, (u32
)31));
1818 return rounded_rate
;
1821 #define MIN_PLL_VCO_RATE 600000000ULL
1822 #define MAX_PLL_VCO_RATE 1680640000ULL
1824 static long round_plldsi_rate(unsigned long rate
)
1826 long rounded_rate
= 0;
1827 unsigned long src_rate
;
1831 src_rate
= clock_rate(PRCMU_HDMICLK
);
1834 for (r
= 7; (rem
> 0) && (r
> 0); r
--) {
1838 (void)do_div(d
, src_rate
);
1844 if (((2 * d
) < (r
* MIN_PLL_VCO_RATE
)) ||
1845 ((r
* MAX_PLL_VCO_RATE
) < (2 * d
)))
1849 if (rounded_rate
== 0)
1850 rounded_rate
= (long)d
;
1853 if ((rate
- d
) < rem
) {
1855 rounded_rate
= (long)d
;
1858 return rounded_rate
;
1861 static long round_dsiclk_rate(unsigned long rate
)
1864 unsigned long src_rate
;
1867 src_rate
= pll_rate(PRCM_PLLDSI_FREQ
, clock_rate(PRCMU_HDMICLK
),
1869 div
= clock_divider(src_rate
, rate
);
1870 rounded_rate
= (src_rate
/ ((div
> 2) ? 4 : div
));
1872 return rounded_rate
;
1875 static long round_dsiescclk_rate(unsigned long rate
)
1878 unsigned long src_rate
;
1881 src_rate
= clock_rate(PRCMU_TVCLK
);
1882 div
= clock_divider(src_rate
, rate
);
1883 rounded_rate
= (src_rate
/ min(div
, (u32
)255));
1885 return rounded_rate
;
1888 long prcmu_round_clock_rate(u8 clock
, unsigned long rate
)
1890 if (clock
< PRCMU_NUM_REG_CLOCKS
)
1891 return round_clock_rate(clock
, rate
);
1892 else if (clock
== PRCMU_PLLDSI
)
1893 return round_plldsi_rate(rate
);
1894 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
1895 return round_dsiclk_rate(rate
);
1896 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
1897 return round_dsiescclk_rate(rate
);
1899 return (long)prcmu_clock_rate(clock
);
1902 static void set_clock_rate(u8 clock
, unsigned long rate
)
1906 unsigned long src_rate
;
1907 unsigned long flags
;
1909 spin_lock_irqsave(&clk_mgt_lock
, flags
);
1911 /* Grab the HW semaphore. */
1912 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
1915 val
= readl(clk_mgt
[clock
].reg
);
1916 src_rate
= clock_source_rate((val
| clk_mgt
[clock
].pllsw
),
1917 clk_mgt
[clock
].branch
);
1918 div
= clock_divider(src_rate
, rate
);
1919 if (val
& PRCM_CLK_MGT_CLK38
) {
1920 if (clk_mgt
[clock
].clk38div
) {
1922 val
|= PRCM_CLK_MGT_CLK38DIV
;
1924 val
&= ~PRCM_CLK_MGT_CLK38DIV
;
1926 } else if (clock
== PRCMU_SGACLK
) {
1927 val
&= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK
|
1928 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
);
1930 u64 r
= (src_rate
* 10);
1932 (void)do_div(r
, 25);
1934 val
|= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
;
1938 val
|= min(div
, (u32
)31);
1940 val
&= ~PRCM_CLK_MGT_CLKPLLDIV_MASK
;
1941 val
|= min(div
, (u32
)31);
1943 writel(val
, clk_mgt
[clock
].reg
);
1945 /* Release the HW semaphore. */
1946 writel(0, PRCM_SEM
);
1948 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
1951 static int set_plldsi_rate(unsigned long rate
)
1953 unsigned long src_rate
;
1958 src_rate
= clock_rate(PRCMU_HDMICLK
);
1961 for (r
= 7; (rem
> 0) && (r
> 0); r
--) {
1966 (void)do_div(d
, src_rate
);
1971 hwrate
= (d
* src_rate
);
1972 if (((2 * hwrate
) < (r
* MIN_PLL_VCO_RATE
)) ||
1973 ((r
* MAX_PLL_VCO_RATE
) < (2 * hwrate
)))
1975 (void)do_div(hwrate
, r
);
1976 if (rate
< hwrate
) {
1978 pll_freq
= (((u32
)d
<< PRCM_PLL_FREQ_D_SHIFT
) |
1979 (r
<< PRCM_PLL_FREQ_R_SHIFT
));
1982 if ((rate
- hwrate
) < rem
) {
1983 rem
= (rate
- hwrate
);
1984 pll_freq
= (((u32
)d
<< PRCM_PLL_FREQ_D_SHIFT
) |
1985 (r
<< PRCM_PLL_FREQ_R_SHIFT
));
1991 pll_freq
|= (1 << PRCM_PLL_FREQ_N_SHIFT
);
1992 writel(pll_freq
, PRCM_PLLDSI_FREQ
);
1997 static void set_dsiclk_rate(u8 n
, unsigned long rate
)
2002 div
= clock_divider(pll_rate(PRCM_PLLDSI_FREQ
,
2003 clock_rate(PRCMU_HDMICLK
), PLL_RAW
), rate
);
2005 dsiclk
[n
].divsel
= (div
== 1) ? PRCM_DSI_PLLOUT_SEL_PHI
:
2006 (div
== 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2
:
2007 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4
;
2009 val
= readl(PRCM_DSI_PLLOUT_SEL
);
2010 val
&= ~dsiclk
[n
].divsel_mask
;
2011 val
|= (dsiclk
[n
].divsel
<< dsiclk
[n
].divsel_shift
);
2012 writel(val
, PRCM_DSI_PLLOUT_SEL
);
2015 static void set_dsiescclk_rate(u8 n
, unsigned long rate
)
2020 div
= clock_divider(clock_rate(PRCMU_TVCLK
), rate
);
2021 val
= readl(PRCM_DSITVCLK_DIV
);
2022 val
&= ~dsiescclk
[n
].div_mask
;
2023 val
|= (min(div
, (u32
)255) << dsiescclk
[n
].div_shift
);
2024 writel(val
, PRCM_DSITVCLK_DIV
);
2027 int prcmu_set_clock_rate(u8 clock
, unsigned long rate
)
2029 if (clock
< PRCMU_NUM_REG_CLOCKS
)
2030 set_clock_rate(clock
, rate
);
2031 else if (clock
== PRCMU_PLLDSI
)
2032 return set_plldsi_rate(rate
);
2033 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
2034 set_dsiclk_rate((clock
- PRCMU_DSI0CLK
), rate
);
2035 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
2036 set_dsiescclk_rate((clock
- PRCMU_DSI0ESCCLK
), rate
);
2040 int db8500_prcmu_config_esram0_deep_sleep(u8 state
)
2042 if ((state
> ESRAM0_DEEP_SLEEP_STATE_RET
) ||
2043 (state
< ESRAM0_DEEP_SLEEP_STATE_OFF
))
2046 mutex_lock(&mb4_transfer
.lock
);
2048 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2051 writeb(MB4H_MEM_ST
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2052 writeb(((DDR_PWR_STATE_OFFHIGHLAT
<< 4) | DDR_PWR_STATE_ON
),
2053 (tcdm_base
+ PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE
));
2054 writeb(DDR_PWR_STATE_ON
,
2055 (tcdm_base
+ PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE
));
2056 writeb(state
, (tcdm_base
+ PRCM_REQ_MB4_ESRAM0_ST
));
2058 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2059 wait_for_completion(&mb4_transfer
.work
);
2061 mutex_unlock(&mb4_transfer
.lock
);
2066 int db8500_prcmu_config_hotdog(u8 threshold
)
2068 mutex_lock(&mb4_transfer
.lock
);
2070 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2073 writeb(threshold
, (tcdm_base
+ PRCM_REQ_MB4_HOTDOG_THRESHOLD
));
2074 writeb(MB4H_HOTDOG
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2076 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2077 wait_for_completion(&mb4_transfer
.work
);
2079 mutex_unlock(&mb4_transfer
.lock
);
2084 int db8500_prcmu_config_hotmon(u8 low
, u8 high
)
2086 mutex_lock(&mb4_transfer
.lock
);
2088 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2091 writeb(low
, (tcdm_base
+ PRCM_REQ_MB4_HOTMON_LOW
));
2092 writeb(high
, (tcdm_base
+ PRCM_REQ_MB4_HOTMON_HIGH
));
2093 writeb((HOTMON_CONFIG_LOW
| HOTMON_CONFIG_HIGH
),
2094 (tcdm_base
+ PRCM_REQ_MB4_HOTMON_CONFIG
));
2095 writeb(MB4H_HOTMON
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2097 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2098 wait_for_completion(&mb4_transfer
.work
);
2100 mutex_unlock(&mb4_transfer
.lock
);
2105 static int config_hot_period(u16 val
)
2107 mutex_lock(&mb4_transfer
.lock
);
2109 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2112 writew(val
, (tcdm_base
+ PRCM_REQ_MB4_HOT_PERIOD
));
2113 writeb(MB4H_HOT_PERIOD
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2115 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2116 wait_for_completion(&mb4_transfer
.work
);
2118 mutex_unlock(&mb4_transfer
.lock
);
2123 int db8500_prcmu_start_temp_sense(u16 cycles32k
)
2125 if (cycles32k
== 0xFFFF)
2128 return config_hot_period(cycles32k
);
2131 int db8500_prcmu_stop_temp_sense(void)
2133 return config_hot_period(0xFFFF);
2136 static int prcmu_a9wdog(u8 cmd
, u8 d0
, u8 d1
, u8 d2
, u8 d3
)
2139 mutex_lock(&mb4_transfer
.lock
);
2141 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2144 writeb(d0
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_0
));
2145 writeb(d1
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_1
));
2146 writeb(d2
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_2
));
2147 writeb(d3
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_3
));
2149 writeb(cmd
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2151 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2152 wait_for_completion(&mb4_transfer
.work
);
2154 mutex_unlock(&mb4_transfer
.lock
);
2160 int db8500_prcmu_config_a9wdog(u8 num
, bool sleep_auto_off
)
2162 BUG_ON(num
== 0 || num
> 0xf);
2163 return prcmu_a9wdog(MB4H_A9WDOG_CONF
, num
, 0, 0,
2164 sleep_auto_off
? A9WDOG_AUTO_OFF_EN
:
2165 A9WDOG_AUTO_OFF_DIS
);
2168 int db8500_prcmu_enable_a9wdog(u8 id
)
2170 return prcmu_a9wdog(MB4H_A9WDOG_EN
, id
, 0, 0, 0);
2173 int db8500_prcmu_disable_a9wdog(u8 id
)
2175 return prcmu_a9wdog(MB4H_A9WDOG_DIS
, id
, 0, 0, 0);
2178 int db8500_prcmu_kick_a9wdog(u8 id
)
2180 return prcmu_a9wdog(MB4H_A9WDOG_KICK
, id
, 0, 0, 0);
2184 * timeout is 28 bit, in ms.
2186 int db8500_prcmu_load_a9wdog(u8 id
, u32 timeout
)
2188 return prcmu_a9wdog(MB4H_A9WDOG_LOAD
,
2189 (id
& A9WDOG_ID_MASK
) |
2191 * Put the lowest 28 bits of timeout at
2192 * offset 4. Four first bits are used for id.
2194 (u8
)((timeout
<< 4) & 0xf0),
2195 (u8
)((timeout
>> 4) & 0xff),
2196 (u8
)((timeout
>> 12) & 0xff),
2197 (u8
)((timeout
>> 20) & 0xff));
2201 * prcmu_abb_read() - Read register value(s) from the ABB.
2202 * @slave: The I2C slave address.
2203 * @reg: The (start) register address.
2204 * @value: The read out value(s).
2205 * @size: The number of registers to read.
2207 * Reads register value(s) from the ABB.
2208 * @size has to be 1 for the current firmware version.
2210 int prcmu_abb_read(u8 slave
, u8 reg
, u8
*value
, u8 size
)
2217 mutex_lock(&mb5_transfer
.lock
);
2219 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(5))
2222 writeb(0, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB5
));
2223 writeb(PRCMU_I2C_READ(slave
), (tcdm_base
+ PRCM_REQ_MB5_I2C_SLAVE_OP
));
2224 writeb(PRCMU_I2C_STOP_EN
, (tcdm_base
+ PRCM_REQ_MB5_I2C_HW_BITS
));
2225 writeb(reg
, (tcdm_base
+ PRCM_REQ_MB5_I2C_REG
));
2226 writeb(0, (tcdm_base
+ PRCM_REQ_MB5_I2C_VAL
));
2228 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET
);
2230 if (!wait_for_completion_timeout(&mb5_transfer
.work
,
2231 msecs_to_jiffies(20000))) {
2232 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2236 r
= ((mb5_transfer
.ack
.status
== I2C_RD_OK
) ? 0 : -EIO
);
2240 *value
= mb5_transfer
.ack
.value
;
2242 mutex_unlock(&mb5_transfer
.lock
);
2248 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2249 * @slave: The I2C slave address.
2250 * @reg: The (start) register address.
2251 * @value: The value(s) to write.
2252 * @mask: The mask(s) to use.
2253 * @size: The number of registers to write.
2255 * Writes masked register value(s) to the ABB.
2256 * For each @value, only the bits set to 1 in the corresponding @mask
2257 * will be written. The other bits are not changed.
2258 * @size has to be 1 for the current firmware version.
2260 int prcmu_abb_write_masked(u8 slave
, u8 reg
, u8
*value
, u8
*mask
, u8 size
)
2267 mutex_lock(&mb5_transfer
.lock
);
2269 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(5))
2272 writeb(~*mask
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB5
));
2273 writeb(PRCMU_I2C_WRITE(slave
), (tcdm_base
+ PRCM_REQ_MB5_I2C_SLAVE_OP
));
2274 writeb(PRCMU_I2C_STOP_EN
, (tcdm_base
+ PRCM_REQ_MB5_I2C_HW_BITS
));
2275 writeb(reg
, (tcdm_base
+ PRCM_REQ_MB5_I2C_REG
));
2276 writeb(*value
, (tcdm_base
+ PRCM_REQ_MB5_I2C_VAL
));
2278 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET
);
2280 if (!wait_for_completion_timeout(&mb5_transfer
.work
,
2281 msecs_to_jiffies(20000))) {
2282 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2286 r
= ((mb5_transfer
.ack
.status
== I2C_WR_OK
) ? 0 : -EIO
);
2289 mutex_unlock(&mb5_transfer
.lock
);
2295 * prcmu_abb_write() - Write register value(s) to the ABB.
2296 * @slave: The I2C slave address.
2297 * @reg: The (start) register address.
2298 * @value: The value(s) to write.
2299 * @size: The number of registers to write.
2301 * Writes register value(s) to the ABB.
2302 * @size has to be 1 for the current firmware version.
2304 int prcmu_abb_write(u8 slave
, u8 reg
, u8
*value
, u8 size
)
2308 return prcmu_abb_write_masked(slave
, reg
, value
, &mask
, size
);
2312 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2314 int prcmu_ac_wake_req(void)
2319 mutex_lock(&mb0_transfer
.ac_wake_lock
);
2321 val
= readl(PRCM_HOSTACCESS_REQ
);
2322 if (val
& PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
)
2323 goto unlock_and_return
;
2325 atomic_set(&ac_wake_req_state
, 1);
2328 * Force Modem Wake-up before hostaccess_req ping-pong.
2329 * It prevents Modem to enter in Sleep while acking the hostaccess
2330 * request. The 31us delay has been calculated by HWI.
2332 val
|= PRCM_HOSTACCESS_REQ_WAKE_REQ
;
2333 writel(val
, PRCM_HOSTACCESS_REQ
);
2337 val
|= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
;
2338 writel(val
, PRCM_HOSTACCESS_REQ
);
2340 if (!wait_for_completion_timeout(&mb0_transfer
.ac_wake_work
,
2341 msecs_to_jiffies(5000))) {
2342 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2343 db8500_prcmu_debug_dump(__func__
, true, true);
2345 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2351 mutex_unlock(&mb0_transfer
.ac_wake_lock
);
2356 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2358 void prcmu_ac_sleep_req()
2362 mutex_lock(&mb0_transfer
.ac_wake_lock
);
2364 val
= readl(PRCM_HOSTACCESS_REQ
);
2365 if (!(val
& PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
))
2366 goto unlock_and_return
;
2368 writel((val
& ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
),
2369 PRCM_HOSTACCESS_REQ
);
2371 if (!wait_for_completion_timeout(&mb0_transfer
.ac_wake_work
,
2372 msecs_to_jiffies(5000))) {
2373 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2377 atomic_set(&ac_wake_req_state
, 0);
2380 mutex_unlock(&mb0_transfer
.ac_wake_lock
);
2383 bool db8500_prcmu_is_ac_wake_requested(void)
2385 return (atomic_read(&ac_wake_req_state
) != 0);
2389 * db8500_prcmu_system_reset - System reset
2391 * Saves the reset reason code and then sets the APE_SOFTRST register which
2392 * fires interrupt to fw
2394 void db8500_prcmu_system_reset(u16 reset_code
)
2396 writew(reset_code
, (tcdm_base
+ PRCM_SW_RST_REASON
));
2397 writel(1, PRCM_APE_SOFTRST
);
2401 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2403 * Retrieves the reset reason code stored by prcmu_system_reset() before
2406 u16
db8500_prcmu_get_reset_code(void)
2408 return readw(tcdm_base
+ PRCM_SW_RST_REASON
);
2412 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2414 void db8500_prcmu_modem_reset(void)
2416 mutex_lock(&mb1_transfer
.lock
);
2418 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
2421 writeb(MB1H_RESET_MODEM
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
2422 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
2423 wait_for_completion(&mb1_transfer
.work
);
2426 * No need to check return from PRCMU as modem should go in reset state
2427 * This state is already managed by upper layer
2430 mutex_unlock(&mb1_transfer
.lock
);
2433 static void ack_dbb_wakeup(void)
2435 unsigned long flags
;
2437 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
2439 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(0))
2442 writeb(MB0H_READ_WAKEUP_ACK
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB0
));
2443 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET
);
2445 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
2448 static inline void print_unknown_header_warning(u8 n
, u8 header
)
2450 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2454 static bool read_mailbox_0(void)
2461 header
= readb(tcdm_base
+ PRCM_MBOX_HEADER_ACK_MB0
);
2463 case MB0H_WAKEUP_EXE
:
2464 case MB0H_WAKEUP_SLEEP
:
2465 if (readb(tcdm_base
+ PRCM_ACK_MB0_READ_POINTER
) & 1)
2466 ev
= readl(tcdm_base
+ PRCM_ACK_MB0_WAKEUP_1_8500
);
2468 ev
= readl(tcdm_base
+ PRCM_ACK_MB0_WAKEUP_0_8500
);
2470 if (ev
& (WAKEUP_BIT_AC_WAKE_ACK
| WAKEUP_BIT_AC_SLEEP_ACK
))
2471 complete(&mb0_transfer
.ac_wake_work
);
2472 if (ev
& WAKEUP_BIT_SYSCLK_OK
)
2473 complete(&mb3_transfer
.sysclk_work
);
2475 ev
&= mb0_transfer
.req
.dbb_irqs
;
2477 for (n
= 0; n
< NUM_PRCMU_WAKEUPS
; n
++) {
2478 if (ev
& prcmu_irq_bit
[n
])
2479 generic_handle_irq(IRQ_PRCMU_BASE
+ n
);
2484 print_unknown_header_warning(0, header
);
2488 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR
);
2492 static bool read_mailbox_1(void)
2494 mb1_transfer
.ack
.header
= readb(tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
);
2495 mb1_transfer
.ack
.arm_opp
= readb(tcdm_base
+
2496 PRCM_ACK_MB1_CURRENT_ARM_OPP
);
2497 mb1_transfer
.ack
.ape_opp
= readb(tcdm_base
+
2498 PRCM_ACK_MB1_CURRENT_APE_OPP
);
2499 mb1_transfer
.ack
.ape_voltage_status
= readb(tcdm_base
+
2500 PRCM_ACK_MB1_APE_VOLTAGE_STATUS
);
2501 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR
);
2502 complete(&mb1_transfer
.work
);
2506 static bool read_mailbox_2(void)
2508 mb2_transfer
.ack
.status
= readb(tcdm_base
+ PRCM_ACK_MB2_DPS_STATUS
);
2509 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR
);
2510 complete(&mb2_transfer
.work
);
2514 static bool read_mailbox_3(void)
2516 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR
);
2520 static bool read_mailbox_4(void)
2523 bool do_complete
= true;
2525 header
= readb(tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
);
2530 case MB4H_HOT_PERIOD
:
2531 case MB4H_A9WDOG_CONF
:
2532 case MB4H_A9WDOG_EN
:
2533 case MB4H_A9WDOG_DIS
:
2534 case MB4H_A9WDOG_LOAD
:
2535 case MB4H_A9WDOG_KICK
:
2538 print_unknown_header_warning(4, header
);
2539 do_complete
= false;
2543 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR
);
2546 complete(&mb4_transfer
.work
);
2551 static bool read_mailbox_5(void)
2553 mb5_transfer
.ack
.status
= readb(tcdm_base
+ PRCM_ACK_MB5_I2C_STATUS
);
2554 mb5_transfer
.ack
.value
= readb(tcdm_base
+ PRCM_ACK_MB5_I2C_VAL
);
2555 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR
);
2556 complete(&mb5_transfer
.work
);
2560 static bool read_mailbox_6(void)
2562 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR
);
2566 static bool read_mailbox_7(void)
2568 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR
);
2572 static bool (* const read_mailbox
[NUM_MB
])(void) = {
2583 static irqreturn_t
prcmu_irq_handler(int irq
, void *data
)
2589 bits
= (readl(PRCM_ARM_IT1_VAL
) & ALL_MBOX_BITS
);
2590 if (unlikely(!bits
))
2594 for (n
= 0; bits
; n
++) {
2595 if (bits
& MBOX_BIT(n
)) {
2596 bits
-= MBOX_BIT(n
);
2597 if (read_mailbox
[n
]())
2598 r
= IRQ_WAKE_THREAD
;
2604 static irqreturn_t
prcmu_irq_thread_fn(int irq
, void *data
)
2610 static void prcmu_mask_work(struct work_struct
*work
)
2612 unsigned long flags
;
2614 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
2618 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
2621 static void prcmu_irq_mask(struct irq_data
*d
)
2623 unsigned long flags
;
2625 spin_lock_irqsave(&mb0_transfer
.dbb_irqs_lock
, flags
);
2627 mb0_transfer
.req
.dbb_irqs
&= ~prcmu_irq_bit
[d
->irq
- IRQ_PRCMU_BASE
];
2629 spin_unlock_irqrestore(&mb0_transfer
.dbb_irqs_lock
, flags
);
2631 if (d
->irq
!= IRQ_PRCMU_CA_SLEEP
)
2632 schedule_work(&mb0_transfer
.mask_work
);
2635 static void prcmu_irq_unmask(struct irq_data
*d
)
2637 unsigned long flags
;
2639 spin_lock_irqsave(&mb0_transfer
.dbb_irqs_lock
, flags
);
2641 mb0_transfer
.req
.dbb_irqs
|= prcmu_irq_bit
[d
->irq
- IRQ_PRCMU_BASE
];
2643 spin_unlock_irqrestore(&mb0_transfer
.dbb_irqs_lock
, flags
);
2645 if (d
->irq
!= IRQ_PRCMU_CA_SLEEP
)
2646 schedule_work(&mb0_transfer
.mask_work
);
2649 static void noop(struct irq_data
*d
)
2653 static struct irq_chip prcmu_irq_chip
= {
2655 .irq_disable
= prcmu_irq_mask
,
2657 .irq_mask
= prcmu_irq_mask
,
2658 .irq_unmask
= prcmu_irq_unmask
,
2661 static char *fw_project_name(u8 project
)
2664 case PRCMU_FW_PROJECT_U8500
:
2666 case PRCMU_FW_PROJECT_U8500_C2
:
2668 case PRCMU_FW_PROJECT_U9500
:
2670 case PRCMU_FW_PROJECT_U9500_C2
:
2672 case PRCMU_FW_PROJECT_U8520
:
2674 case PRCMU_FW_PROJECT_U8420
:
2681 void __init
db8500_prcmu_early_init(void)
2684 if (cpu_is_u8500v2()) {
2685 void *tcpm_base
= ioremap_nocache(U8500_PRCMU_TCPM_BASE
, SZ_4K
);
2687 if (tcpm_base
!= NULL
) {
2689 version
= readl(tcpm_base
+ PRCMU_FW_VERSION_OFFSET
);
2690 fw_info
.version
.project
= version
& 0xFF;
2691 fw_info
.version
.api_version
= (version
>> 8) & 0xFF;
2692 fw_info
.version
.func_version
= (version
>> 16) & 0xFF;
2693 fw_info
.version
.errata
= (version
>> 24) & 0xFF;
2694 fw_info
.valid
= true;
2695 pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2696 fw_project_name(fw_info
.version
.project
),
2697 (version
>> 8) & 0xFF, (version
>> 16) & 0xFF,
2698 (version
>> 24) & 0xFF);
2702 tcdm_base
= __io_address(U8500_PRCMU_TCDM_BASE
);
2704 pr_err("prcmu: Unsupported chip version\n");
2708 spin_lock_init(&mb0_transfer
.lock
);
2709 spin_lock_init(&mb0_transfer
.dbb_irqs_lock
);
2710 mutex_init(&mb0_transfer
.ac_wake_lock
);
2711 init_completion(&mb0_transfer
.ac_wake_work
);
2712 mutex_init(&mb1_transfer
.lock
);
2713 init_completion(&mb1_transfer
.work
);
2714 mb1_transfer
.ape_opp
= APE_NO_CHANGE
;
2715 mutex_init(&mb2_transfer
.lock
);
2716 init_completion(&mb2_transfer
.work
);
2717 spin_lock_init(&mb2_transfer
.auto_pm_lock
);
2718 spin_lock_init(&mb3_transfer
.lock
);
2719 mutex_init(&mb3_transfer
.sysclk_lock
);
2720 init_completion(&mb3_transfer
.sysclk_work
);
2721 mutex_init(&mb4_transfer
.lock
);
2722 init_completion(&mb4_transfer
.work
);
2723 mutex_init(&mb5_transfer
.lock
);
2724 init_completion(&mb5_transfer
.work
);
2726 INIT_WORK(&mb0_transfer
.mask_work
, prcmu_mask_work
);
2728 /* Initalize irqs. */
2729 for (i
= 0; i
< NUM_PRCMU_WAKEUPS
; i
++) {
2732 irq
= IRQ_PRCMU_BASE
+ i
;
2733 irq_set_chip_and_handler(irq
, &prcmu_irq_chip
,
2735 set_irq_flags(irq
, IRQF_VALID
);
2737 compute_armss_rate();
2740 static void __init
init_prcm_registers(void)
2744 val
= readl(PRCM_A9PL_FORCE_CLKEN
);
2745 val
&= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN
|
2746 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN
);
2747 writel(val
, (PRCM_A9PL_FORCE_CLKEN
));
2751 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2753 static struct regulator_consumer_supply db8500_vape_consumers
[] = {
2754 REGULATOR_SUPPLY("v-ape", NULL
),
2755 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2756 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2757 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2758 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2759 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2760 /* "v-mmc" changed to "vcore" in the mainline kernel */
2761 REGULATOR_SUPPLY("vcore", "sdi0"),
2762 REGULATOR_SUPPLY("vcore", "sdi1"),
2763 REGULATOR_SUPPLY("vcore", "sdi2"),
2764 REGULATOR_SUPPLY("vcore", "sdi3"),
2765 REGULATOR_SUPPLY("vcore", "sdi4"),
2766 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2767 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2768 /* "v-uart" changed to "vcore" in the mainline kernel */
2769 REGULATOR_SUPPLY("vcore", "uart0"),
2770 REGULATOR_SUPPLY("vcore", "uart1"),
2771 REGULATOR_SUPPLY("vcore", "uart2"),
2772 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2773 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2774 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2777 static struct regulator_consumer_supply db8500_vsmps2_consumers
[] = {
2778 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2779 /* AV8100 regulator */
2780 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2783 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers
[] = {
2784 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2785 REGULATOR_SUPPLY("vsupply", "mcde"),
2788 /* SVA MMDSP regulator switch */
2789 static struct regulator_consumer_supply db8500_svammdsp_consumers
[] = {
2790 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2793 /* SVA pipe regulator switch */
2794 static struct regulator_consumer_supply db8500_svapipe_consumers
[] = {
2795 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2798 /* SIA MMDSP regulator switch */
2799 static struct regulator_consumer_supply db8500_siammdsp_consumers
[] = {
2800 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2803 /* SIA pipe regulator switch */
2804 static struct regulator_consumer_supply db8500_siapipe_consumers
[] = {
2805 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2808 static struct regulator_consumer_supply db8500_sga_consumers
[] = {
2809 REGULATOR_SUPPLY("v-mali", NULL
),
2812 /* ESRAM1 and 2 regulator switch */
2813 static struct regulator_consumer_supply db8500_esram12_consumers
[] = {
2814 REGULATOR_SUPPLY("esram12", "cm_control"),
2817 /* ESRAM3 and 4 regulator switch */
2818 static struct regulator_consumer_supply db8500_esram34_consumers
[] = {
2819 REGULATOR_SUPPLY("v-esram34", "mcde"),
2820 REGULATOR_SUPPLY("esram34", "cm_control"),
2821 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2824 static struct regulator_init_data db8500_regulators
[DB8500_NUM_REGULATORS
] = {
2825 [DB8500_REGULATOR_VAPE
] = {
2827 .name
= "db8500-vape",
2828 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2831 .consumer_supplies
= db8500_vape_consumers
,
2832 .num_consumer_supplies
= ARRAY_SIZE(db8500_vape_consumers
),
2834 [DB8500_REGULATOR_VARM
] = {
2836 .name
= "db8500-varm",
2837 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2840 [DB8500_REGULATOR_VMODEM
] = {
2842 .name
= "db8500-vmodem",
2843 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2846 [DB8500_REGULATOR_VPLL
] = {
2848 .name
= "db8500-vpll",
2849 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2852 [DB8500_REGULATOR_VSMPS1
] = {
2854 .name
= "db8500-vsmps1",
2855 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2858 [DB8500_REGULATOR_VSMPS2
] = {
2860 .name
= "db8500-vsmps2",
2861 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2863 .consumer_supplies
= db8500_vsmps2_consumers
,
2864 .num_consumer_supplies
= ARRAY_SIZE(db8500_vsmps2_consumers
),
2866 [DB8500_REGULATOR_VSMPS3
] = {
2868 .name
= "db8500-vsmps3",
2869 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2872 [DB8500_REGULATOR_VRF1
] = {
2874 .name
= "db8500-vrf1",
2875 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2878 [DB8500_REGULATOR_SWITCH_SVAMMDSP
] = {
2879 /* dependency to u8500-vape is handled outside regulator framework */
2881 .name
= "db8500-sva-mmdsp",
2882 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2884 .consumer_supplies
= db8500_svammdsp_consumers
,
2885 .num_consumer_supplies
= ARRAY_SIZE(db8500_svammdsp_consumers
),
2887 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET
] = {
2889 /* "ret" means "retention" */
2890 .name
= "db8500-sva-mmdsp-ret",
2891 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2894 [DB8500_REGULATOR_SWITCH_SVAPIPE
] = {
2895 /* dependency to u8500-vape is handled outside regulator framework */
2897 .name
= "db8500-sva-pipe",
2898 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2900 .consumer_supplies
= db8500_svapipe_consumers
,
2901 .num_consumer_supplies
= ARRAY_SIZE(db8500_svapipe_consumers
),
2903 [DB8500_REGULATOR_SWITCH_SIAMMDSP
] = {
2904 /* dependency to u8500-vape is handled outside regulator framework */
2906 .name
= "db8500-sia-mmdsp",
2907 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2909 .consumer_supplies
= db8500_siammdsp_consumers
,
2910 .num_consumer_supplies
= ARRAY_SIZE(db8500_siammdsp_consumers
),
2912 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET
] = {
2914 .name
= "db8500-sia-mmdsp-ret",
2915 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2918 [DB8500_REGULATOR_SWITCH_SIAPIPE
] = {
2919 /* dependency to u8500-vape is handled outside regulator framework */
2921 .name
= "db8500-sia-pipe",
2922 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2924 .consumer_supplies
= db8500_siapipe_consumers
,
2925 .num_consumer_supplies
= ARRAY_SIZE(db8500_siapipe_consumers
),
2927 [DB8500_REGULATOR_SWITCH_SGA
] = {
2928 .supply_regulator
= "db8500-vape",
2930 .name
= "db8500-sga",
2931 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2933 .consumer_supplies
= db8500_sga_consumers
,
2934 .num_consumer_supplies
= ARRAY_SIZE(db8500_sga_consumers
),
2937 [DB8500_REGULATOR_SWITCH_B2R2_MCDE
] = {
2938 .supply_regulator
= "db8500-vape",
2940 .name
= "db8500-b2r2-mcde",
2941 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2943 .consumer_supplies
= db8500_b2r2_mcde_consumers
,
2944 .num_consumer_supplies
= ARRAY_SIZE(db8500_b2r2_mcde_consumers
),
2946 [DB8500_REGULATOR_SWITCH_ESRAM12
] = {
2948 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2949 * no need to hold Vape
2952 .name
= "db8500-esram12",
2953 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2955 .consumer_supplies
= db8500_esram12_consumers
,
2956 .num_consumer_supplies
= ARRAY_SIZE(db8500_esram12_consumers
),
2958 [DB8500_REGULATOR_SWITCH_ESRAM12RET
] = {
2960 .name
= "db8500-esram12-ret",
2961 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2964 [DB8500_REGULATOR_SWITCH_ESRAM34
] = {
2966 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2967 * no need to hold Vape
2970 .name
= "db8500-esram34",
2971 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2973 .consumer_supplies
= db8500_esram34_consumers
,
2974 .num_consumer_supplies
= ARRAY_SIZE(db8500_esram34_consumers
),
2976 [DB8500_REGULATOR_SWITCH_ESRAM34RET
] = {
2978 .name
= "db8500-esram34-ret",
2979 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2984 static struct resource ab8500_resources
[] = {
2986 .start
= IRQ_DB8500_AB8500
,
2987 .end
= IRQ_DB8500_AB8500
,
2988 .flags
= IORESOURCE_IRQ
2992 static struct mfd_cell db8500_prcmu_devs
[] = {
2994 .name
= "db8500-prcmu-regulators",
2995 .of_compatible
= "stericsson,db8500-prcmu-regulator",
2996 .platform_data
= &db8500_regulators
,
2997 .pdata_size
= sizeof(db8500_regulators
),
3000 .name
= "cpufreq-u8500",
3001 .of_compatible
= "stericsson,cpufreq-u8500",
3004 .name
= "ab8500-core",
3005 .of_compatible
= "stericsson,ab8500",
3006 .num_resources
= ARRAY_SIZE(ab8500_resources
),
3007 .resources
= ab8500_resources
,
3008 .id
= AB8500_VERSION_AB8500
,
3013 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3016 static int __devinit
db8500_prcmu_probe(struct platform_device
*pdev
)
3018 struct ab8500_platform_data
*ab8500_platdata
= pdev
->dev
.platform_data
;
3019 struct device_node
*np
= pdev
->dev
.of_node
;
3020 int irq
= 0, err
= 0, i
;
3025 init_prcm_registers();
3027 /* Clean up the mailbox interrupts after pre-kernel code. */
3028 writel(ALL_MBOX_BITS
, PRCM_ARM_IT1_CLR
);
3031 irq
= platform_get_irq(pdev
, 0);
3033 if (!np
|| irq
<= 0)
3034 irq
= IRQ_DB8500_PRCMU1
;
3036 err
= request_threaded_irq(irq
, prcmu_irq_handler
,
3037 prcmu_irq_thread_fn
, IRQF_NO_SUSPEND
, "prcmu", NULL
);
3039 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3044 for (i
= 0; i
< ARRAY_SIZE(db8500_prcmu_devs
); i
++) {
3045 if (!strcmp(db8500_prcmu_devs
[i
].name
, "ab8500-core")) {
3046 db8500_prcmu_devs
[i
].platform_data
= ab8500_platdata
;
3047 db8500_prcmu_devs
[i
].pdata_size
= sizeof(struct ab8500_platform_data
);
3051 if (cpu_is_u8500v20_or_later())
3052 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET
);
3054 err
= mfd_add_devices(&pdev
->dev
, 0, db8500_prcmu_devs
,
3055 ARRAY_SIZE(db8500_prcmu_devs
), NULL
, 0, NULL
);
3057 pr_err("prcmu: Failed to add subdevices\n");
3061 pr_info("DB8500 PRCMU initialized\n");
3066 static const struct of_device_id db8500_prcmu_match
[] = {
3067 { .compatible
= "stericsson,db8500-prcmu"},
3071 static struct platform_driver db8500_prcmu_driver
= {
3073 .name
= "db8500-prcmu",
3074 .owner
= THIS_MODULE
,
3075 .of_match_table
= db8500_prcmu_match
,
3077 .probe
= db8500_prcmu_probe
,
3080 static int __init
db8500_prcmu_init(void)
3082 return platform_driver_register(&db8500_prcmu_driver
);
3085 core_initcall(db8500_prcmu_init
);
3087 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3088 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3089 MODULE_LICENSE("GPL v2");