2 * Intel Sunrisepoint LPSS core support.
4 * Copyright (C) 2015, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/dmi.h>
21 #include <linux/idr.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/mfd/core.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/property.h>
29 #include <linux/seq_file.h>
30 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include "intel-lpss.h"
34 #define LPSS_DEV_OFFSET 0x000
35 #define LPSS_DEV_SIZE 0x200
36 #define LPSS_PRIV_OFFSET 0x200
37 #define LPSS_PRIV_SIZE 0x100
38 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
39 #define LPSS_IDMA64_OFFSET 0x800
40 #define LPSS_IDMA64_SIZE 0x800
42 /* Offsets from lpss->priv */
43 #define LPSS_PRIV_RESETS 0x04
44 #define LPSS_PRIV_RESETS_FUNC BIT(2)
45 #define LPSS_PRIV_RESETS_IDMA 0x3
47 #define LPSS_PRIV_ACTIVELTR 0x10
48 #define LPSS_PRIV_IDLELTR 0x14
50 #define LPSS_PRIV_LTR_REQ BIT(15)
51 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
52 #define LPSS_PRIV_LTR_SCALE_1US 0x800
53 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
54 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
56 #define LPSS_PRIV_SSP_REG 0x20
57 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
59 #define LPSS_PRIV_REMAP_ADDR 0x40
61 #define LPSS_PRIV_CAPS 0xfc
62 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
63 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
64 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
66 /* This matches the type field in CAPS register */
67 enum intel_lpss_dev_type
{
74 const struct intel_lpss_platform_info
*info
;
75 enum intel_lpss_dev_type type
;
77 struct clk_lookup
*clock
;
78 struct mfd_cell
*cell
;
81 u32 priv_ctx
[LPSS_PRIV_REG_COUNT
];
86 struct dentry
*debugfs
;
89 static const struct resource intel_lpss_dev_resources
[] = {
90 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET
, LPSS_DEV_SIZE
, "lpss_dev"),
91 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET
, LPSS_PRIV_SIZE
, "lpss_priv"),
95 static const struct resource intel_lpss_idma64_resources
[] = {
96 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET
, LPSS_IDMA64_SIZE
),
100 #define LPSS_IDMA64_DRIVER_NAME "idma64"
103 * Cells needs to be ordered so that the iDMA is created first. This is
104 * because we need to be sure the DMA is available when the host controller
107 static const struct mfd_cell intel_lpss_idma64_cell
= {
108 .name
= LPSS_IDMA64_DRIVER_NAME
,
109 .num_resources
= ARRAY_SIZE(intel_lpss_idma64_resources
),
110 .resources
= intel_lpss_idma64_resources
,
113 static const struct mfd_cell intel_lpss_i2c_cell
= {
114 .name
= "i2c_designware",
115 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
116 .resources
= intel_lpss_dev_resources
,
119 static const struct mfd_cell intel_lpss_uart_cell
= {
120 .name
= "dw-apb-uart",
121 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
122 .resources
= intel_lpss_dev_resources
,
125 static const struct mfd_cell intel_lpss_spi_cell
= {
126 .name
= "pxa2xx-spi",
127 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
128 .resources
= intel_lpss_dev_resources
,
131 static DEFINE_IDA(intel_lpss_devid_ida
);
132 static struct dentry
*intel_lpss_debugfs
;
134 static const struct dmi_system_id mtrr_large_wc_region
[] = {
136 .ident
= "Dell Computer Corporation",
138 DMI_MATCH(DMI_SYS_VENDOR
, "Dell Inc."),
139 DMI_MATCH(DMI_PRODUCT_NAME
, "XPS 13 7390 2-in-1"),
145 static int intel_lpss_request_dma_module(const char *name
)
147 static bool intel_lpss_dma_requested
;
149 if (intel_lpss_dma_requested
)
152 intel_lpss_dma_requested
= true;
153 return request_module("%s", name
);
156 static void intel_lpss_cache_ltr(struct intel_lpss
*lpss
)
158 lpss
->active_ltr
= readl(lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
159 lpss
->idle_ltr
= readl(lpss
->priv
+ LPSS_PRIV_IDLELTR
);
162 static int intel_lpss_debugfs_add(struct intel_lpss
*lpss
)
166 dir
= debugfs_create_dir(dev_name(lpss
->dev
), intel_lpss_debugfs
);
170 /* Cache the values into lpss structure */
171 intel_lpss_cache_ltr(lpss
);
173 debugfs_create_x32("capabilities", S_IRUGO
, dir
, &lpss
->caps
);
174 debugfs_create_x32("active_ltr", S_IRUGO
, dir
, &lpss
->active_ltr
);
175 debugfs_create_x32("idle_ltr", S_IRUGO
, dir
, &lpss
->idle_ltr
);
181 static void intel_lpss_debugfs_remove(struct intel_lpss
*lpss
)
183 debugfs_remove_recursive(lpss
->debugfs
);
186 static void intel_lpss_ltr_set(struct device
*dev
, s32 val
)
188 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
192 * Program latency tolerance (LTR) accordingly what has been asked
193 * by the PM QoS layer or disable it in case we were passed
194 * negative value or PM_QOS_LATENCY_ANY.
196 ltr
= readl(lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
198 if (val
== PM_QOS_LATENCY_ANY
|| val
< 0) {
199 ltr
&= ~LPSS_PRIV_LTR_REQ
;
201 ltr
|= LPSS_PRIV_LTR_REQ
;
202 ltr
&= ~LPSS_PRIV_LTR_SCALE_MASK
;
203 ltr
&= ~LPSS_PRIV_LTR_VALUE_MASK
;
205 if (val
> LPSS_PRIV_LTR_VALUE_MASK
)
206 ltr
|= LPSS_PRIV_LTR_SCALE_32US
| val
>> 5;
208 ltr
|= LPSS_PRIV_LTR_SCALE_1US
| val
;
211 if (ltr
== lpss
->active_ltr
)
214 writel(ltr
, lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
215 writel(ltr
, lpss
->priv
+ LPSS_PRIV_IDLELTR
);
217 /* Cache the values into lpss structure */
218 intel_lpss_cache_ltr(lpss
);
221 static void intel_lpss_ltr_expose(struct intel_lpss
*lpss
)
223 lpss
->dev
->power
.set_latency_tolerance
= intel_lpss_ltr_set
;
224 dev_pm_qos_expose_latency_tolerance(lpss
->dev
);
227 static void intel_lpss_ltr_hide(struct intel_lpss
*lpss
)
229 dev_pm_qos_hide_latency_tolerance(lpss
->dev
);
230 lpss
->dev
->power
.set_latency_tolerance
= NULL
;
233 static int intel_lpss_assign_devs(struct intel_lpss
*lpss
)
235 const struct mfd_cell
*cell
;
238 type
= lpss
->caps
& LPSS_PRIV_CAPS_TYPE_MASK
;
239 type
>>= LPSS_PRIV_CAPS_TYPE_SHIFT
;
243 cell
= &intel_lpss_i2c_cell
;
246 cell
= &intel_lpss_uart_cell
;
249 cell
= &intel_lpss_spi_cell
;
255 lpss
->cell
= devm_kmemdup(lpss
->dev
, cell
, sizeof(*cell
), GFP_KERNEL
);
264 static bool intel_lpss_has_idma(const struct intel_lpss
*lpss
)
266 return (lpss
->caps
& LPSS_PRIV_CAPS_NO_IDMA
) == 0;
269 static void intel_lpss_set_remap_addr(const struct intel_lpss
*lpss
)
271 resource_size_t addr
= lpss
->info
->mem
->start
;
273 lo_hi_writeq(addr
, lpss
->priv
+ LPSS_PRIV_REMAP_ADDR
);
276 static void intel_lpss_deassert_reset(const struct intel_lpss
*lpss
)
278 u32 value
= LPSS_PRIV_RESETS_FUNC
| LPSS_PRIV_RESETS_IDMA
;
280 /* Bring out the device from reset */
281 writel(value
, lpss
->priv
+ LPSS_PRIV_RESETS
);
284 static void intel_lpss_init_dev(const struct intel_lpss
*lpss
)
286 u32 value
= LPSS_PRIV_SSP_REG_DIS_DMA_FIN
;
288 /* Set the device in reset state */
289 writel(0, lpss
->priv
+ LPSS_PRIV_RESETS
);
291 intel_lpss_deassert_reset(lpss
);
293 intel_lpss_set_remap_addr(lpss
);
295 if (!intel_lpss_has_idma(lpss
))
298 /* Make sure that SPI multiblock DMA transfers are re-enabled */
299 if (lpss
->type
== LPSS_DEV_SPI
)
300 writel(value
, lpss
->priv
+ LPSS_PRIV_SSP_REG
);
303 static void intel_lpss_unregister_clock_tree(struct clk
*clk
)
308 parent
= clk_get_parent(clk
);
314 static int intel_lpss_register_clock_divider(struct intel_lpss
*lpss
,
319 struct clk
*tmp
= *clk
;
321 snprintf(name
, sizeof(name
), "%s-enable", devname
);
322 tmp
= clk_register_gate(NULL
, name
, __clk_get_name(tmp
), 0,
323 lpss
->priv
, 0, 0, NULL
);
327 snprintf(name
, sizeof(name
), "%s-div", devname
);
328 tmp
= clk_register_fractional_divider(NULL
, name
, __clk_get_name(tmp
),
329 0, lpss
->priv
, 1, 15, 16, 15, 0,
335 snprintf(name
, sizeof(name
), "%s-update", devname
);
336 tmp
= clk_register_gate(NULL
, name
, __clk_get_name(tmp
),
337 CLK_SET_RATE_PARENT
, lpss
->priv
, 31, 0, NULL
);
345 static int intel_lpss_register_clock(struct intel_lpss
*lpss
)
347 const struct mfd_cell
*cell
= lpss
->cell
;
352 if (!lpss
->info
->clk_rate
)
356 clk
= clk_register_fixed_rate(NULL
, dev_name(lpss
->dev
), NULL
, 0,
357 lpss
->info
->clk_rate
);
361 snprintf(devname
, sizeof(devname
), "%s.%d", cell
->name
, lpss
->devid
);
364 * Support for clock divider only if it has some preset value.
365 * Otherwise we assume that the divider is not used.
367 if (lpss
->type
!= LPSS_DEV_I2C
) {
368 ret
= intel_lpss_register_clock_divider(lpss
, devname
, &clk
);
370 goto err_clk_register
;
375 /* Clock for the host controller */
376 lpss
->clock
= clkdev_create(clk
, lpss
->info
->clk_con_id
, "%s", devname
);
378 goto err_clk_register
;
385 intel_lpss_unregister_clock_tree(clk
);
390 static void intel_lpss_unregister_clock(struct intel_lpss
*lpss
)
392 if (IS_ERR_OR_NULL(lpss
->clk
))
395 clkdev_drop(lpss
->clock
);
396 intel_lpss_unregister_clock_tree(lpss
->clk
);
399 int intel_lpss_probe(struct device
*dev
,
400 const struct intel_lpss_platform_info
*info
)
402 struct intel_lpss
*lpss
;
405 if (!info
|| !info
->mem
|| info
->irq
<= 0)
408 lpss
= devm_kzalloc(dev
, sizeof(*lpss
), GFP_KERNEL
);
412 if (dmi_check_system(mtrr_large_wc_region
))
413 lpss
->priv
= devm_ioremap_uc(dev
, info
->mem
->start
+ LPSS_PRIV_OFFSET
,
416 lpss
->priv
= devm_ioremap(dev
, info
->mem
->start
+ LPSS_PRIV_OFFSET
,
423 lpss
->caps
= readl(lpss
->priv
+ LPSS_PRIV_CAPS
);
425 dev_set_drvdata(dev
, lpss
);
427 ret
= intel_lpss_assign_devs(lpss
);
431 lpss
->cell
->properties
= info
->properties
;
433 intel_lpss_init_dev(lpss
);
435 lpss
->devid
= ida_simple_get(&intel_lpss_devid_ida
, 0, 0, GFP_KERNEL
);
439 ret
= intel_lpss_register_clock(lpss
);
441 goto err_clk_register
;
443 intel_lpss_ltr_expose(lpss
);
445 ret
= intel_lpss_debugfs_add(lpss
);
447 dev_warn(dev
, "Failed to create debugfs entries\n");
449 if (intel_lpss_has_idma(lpss
)) {
451 * Ensure the DMA driver is loaded before the host
452 * controller device appears, so that the host controller
453 * driver can request its DMA channels as early as
456 * If the DMA module is not there that's OK as well.
458 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME
);
460 ret
= mfd_add_devices(dev
, lpss
->devid
, &intel_lpss_idma64_cell
,
461 1, info
->mem
, info
->irq
, NULL
);
463 dev_warn(dev
, "Failed to add %s, fallback to PIO\n",
464 LPSS_IDMA64_DRIVER_NAME
);
467 ret
= mfd_add_devices(dev
, lpss
->devid
, lpss
->cell
,
468 1, info
->mem
, info
->irq
, NULL
);
475 intel_lpss_debugfs_remove(lpss
);
476 intel_lpss_ltr_hide(lpss
);
477 intel_lpss_unregister_clock(lpss
);
480 ida_simple_remove(&intel_lpss_devid_ida
, lpss
->devid
);
484 EXPORT_SYMBOL_GPL(intel_lpss_probe
);
486 void intel_lpss_remove(struct device
*dev
)
488 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
490 mfd_remove_devices(dev
);
491 intel_lpss_debugfs_remove(lpss
);
492 intel_lpss_ltr_hide(lpss
);
493 intel_lpss_unregister_clock(lpss
);
494 ida_simple_remove(&intel_lpss_devid_ida
, lpss
->devid
);
496 EXPORT_SYMBOL_GPL(intel_lpss_remove
);
498 static int resume_lpss_device(struct device
*dev
, void *data
)
500 pm_runtime_resume(dev
);
504 int intel_lpss_prepare(struct device
*dev
)
507 * Resume both child devices before entering system sleep. This
508 * ensures that they are in proper state before they get suspended.
510 device_for_each_child_reverse(dev
, NULL
, resume_lpss_device
);
513 EXPORT_SYMBOL_GPL(intel_lpss_prepare
);
515 int intel_lpss_suspend(struct device
*dev
)
517 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
520 /* Save device context */
521 for (i
= 0; i
< LPSS_PRIV_REG_COUNT
; i
++)
522 lpss
->priv_ctx
[i
] = readl(lpss
->priv
+ i
* 4);
525 * If the device type is not UART, then put the controller into
526 * reset. UART cannot be put into reset since S3/S0ix fail when
527 * no_console_suspend flag is enabled.
529 if (lpss
->type
!= LPSS_DEV_UART
)
530 writel(0, lpss
->priv
+ LPSS_PRIV_RESETS
);
534 EXPORT_SYMBOL_GPL(intel_lpss_suspend
);
536 int intel_lpss_resume(struct device
*dev
)
538 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
541 intel_lpss_deassert_reset(lpss
);
543 /* Restore device context */
544 for (i
= 0; i
< LPSS_PRIV_REG_COUNT
; i
++)
545 writel(lpss
->priv_ctx
[i
], lpss
->priv
+ i
* 4);
549 EXPORT_SYMBOL_GPL(intel_lpss_resume
);
551 static int __init
intel_lpss_init(void)
553 intel_lpss_debugfs
= debugfs_create_dir("intel_lpss", NULL
);
556 module_init(intel_lpss_init
);
558 static void __exit
intel_lpss_exit(void)
560 ida_destroy(&intel_lpss_devid_ida
);
561 debugfs_remove(intel_lpss_debugfs
);
563 module_exit(intel_lpss_exit
);
565 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
566 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
567 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
568 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
569 MODULE_DESCRIPTION("Intel LPSS core driver");
570 MODULE_LICENSE("GPL v2");