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[mirror_ubuntu-bionic-kernel.git] / drivers / mfd / lpc_ich.c
1 /*
2 * lpc_ich.c - LPC interface for Intel ICH
3 *
4 * LPC bridge function of the Intel ICH contains many other
5 * functional units, such as Interrupt controllers, Timers,
6 * Power Management, System Management, GPIO, RTC, and LPC
7 * Configuration Registers.
8 *
9 * This driver is derived from lpc_sch.
10
11 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 * Author: Aaron Sierra <asierra@xes-inc.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License 2 as published
16 * by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * This driver supports the following I/O Controller hubs:
28 * (See the intel documentation on http://developer.intel.com.)
29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
30 * document number 290687-002, 298242-027: 82801BA (ICH2)
31 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
33 * document number 290744-001, 290745-025: 82801DB (ICH4)
34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
35 * document number 273599-001, 273645-002: 82801E (C-ICH)
36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
37 * document number 300641-004, 300884-013: 6300ESB
38 * document number 301473-002, 301474-026: 82801F (ICH6)
39 * document number 313082-001, 313075-006: 631xESB, 632xESB
40 * document number 307013-003, 307014-024: 82801G (ICH7)
41 * document number 322896-001, 322897-001: NM10
42 * document number 313056-003, 313057-017: 82801H (ICH8)
43 * document number 316972-004, 316973-012: 82801I (ICH9)
44 * document number 319973-002, 319974-002: 82801J (ICH10)
45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
46 * document number 320066-003, 320257-008: EP80597 (IICH)
47 * document number 324645-001, 324646-001: Cougar Point (CPT)
48 * document number TBD : Patsburg (PBG)
49 * document number TBD : DH89xxCC
50 * document number TBD : Panther Point
51 * document number TBD : Lynx Point
52 * document number TBD : Lynx Point-LP
53 * document number TBD : Wellsburg
54 * document number TBD : Avoton SoC
55 * document number TBD : Coleto Creek
56 * document number TBD : Wildcat Point-LP
57 * document number TBD : 9 Series
58 * document number TBD : Lewisburg
59 */
60
61 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
62
63 #include <linux/kernel.h>
64 #include <linux/module.h>
65 #include <linux/errno.h>
66 #include <linux/acpi.h>
67 #include <linux/pci.h>
68 #include <linux/mfd/core.h>
69 #include <linux/mfd/lpc_ich.h>
70 #include <linux/platform_data/itco_wdt.h>
71
72 #define ACPIBASE 0x40
73 #define ACPIBASE_GPE_OFF 0x28
74 #define ACPIBASE_GPE_END 0x2f
75 #define ACPIBASE_SMI_OFF 0x30
76 #define ACPIBASE_SMI_END 0x33
77 #define ACPIBASE_PMC_OFF 0x08
78 #define ACPIBASE_PMC_END 0x0c
79 #define ACPIBASE_TCO_OFF 0x60
80 #define ACPIBASE_TCO_END 0x7f
81 #define ACPICTRL_PMCBASE 0x44
82
83 #define ACPIBASE_GCS_OFF 0x3410
84 #define ACPIBASE_GCS_END 0x3414
85
86 #define SPIBASE_BYT 0x54
87 #define SPIBASE_BYT_SZ 512
88 #define SPIBASE_BYT_EN BIT(1)
89
90 #define SPIBASE_LPT 0x3800
91 #define SPIBASE_LPT_SZ 512
92 #define BCR 0xdc
93 #define BCR_WPD BIT(0)
94
95 #define GPIOBASE_ICH0 0x58
96 #define GPIOCTRL_ICH0 0x5C
97 #define GPIOBASE_ICH6 0x48
98 #define GPIOCTRL_ICH6 0x4C
99
100 #define RCBABASE 0xf0
101
102 #define wdt_io_res(i) wdt_res(0, i)
103 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
104 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
105
106 struct lpc_ich_priv {
107 int chipset;
108
109 int abase; /* ACPI base */
110 int actrl_pbase; /* ACPI control or PMC base */
111 int gbase; /* GPIO base */
112 int gctrl; /* GPIO control */
113
114 int abase_save; /* Cached ACPI base value */
115 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
116 int gctrl_save; /* Cached GPIO control value */
117 };
118
119 static struct resource wdt_ich_res[] = {
120 /* ACPI - TCO */
121 {
122 .flags = IORESOURCE_IO,
123 },
124 /* ACPI - SMI */
125 {
126 .flags = IORESOURCE_IO,
127 },
128 /* GCS or PMC */
129 {
130 .flags = IORESOURCE_MEM,
131 },
132 };
133
134 static struct resource gpio_ich_res[] = {
135 /* GPIO */
136 {
137 .flags = IORESOURCE_IO,
138 },
139 /* ACPI - GPE0 */
140 {
141 .flags = IORESOURCE_IO,
142 },
143 };
144
145 static struct resource intel_spi_res[] = {
146 {
147 .flags = IORESOURCE_MEM,
148 }
149 };
150
151 static struct mfd_cell lpc_ich_wdt_cell = {
152 .name = "iTCO_wdt",
153 .num_resources = ARRAY_SIZE(wdt_ich_res),
154 .resources = wdt_ich_res,
155 .ignore_resource_conflicts = true,
156 };
157
158 static struct mfd_cell lpc_ich_gpio_cell = {
159 .name = "gpio_ich",
160 .num_resources = ARRAY_SIZE(gpio_ich_res),
161 .resources = gpio_ich_res,
162 .ignore_resource_conflicts = true,
163 };
164
165
166 static struct mfd_cell lpc_ich_spi_cell = {
167 .name = "intel-spi",
168 .num_resources = ARRAY_SIZE(intel_spi_res),
169 .resources = intel_spi_res,
170 .ignore_resource_conflicts = true,
171 };
172
173 /* chipset related info */
174 enum lpc_chipsets {
175 LPC_ICH = 0, /* ICH */
176 LPC_ICH0, /* ICH0 */
177 LPC_ICH2, /* ICH2 */
178 LPC_ICH2M, /* ICH2-M */
179 LPC_ICH3, /* ICH3-S */
180 LPC_ICH3M, /* ICH3-M */
181 LPC_ICH4, /* ICH4 */
182 LPC_ICH4M, /* ICH4-M */
183 LPC_CICH, /* C-ICH */
184 LPC_ICH5, /* ICH5 & ICH5R */
185 LPC_6300ESB, /* 6300ESB */
186 LPC_ICH6, /* ICH6 & ICH6R */
187 LPC_ICH6M, /* ICH6-M */
188 LPC_ICH6W, /* ICH6W & ICH6RW */
189 LPC_631XESB, /* 631xESB/632xESB */
190 LPC_ICH7, /* ICH7 & ICH7R */
191 LPC_ICH7DH, /* ICH7DH */
192 LPC_ICH7M, /* ICH7-M & ICH7-U */
193 LPC_ICH7MDH, /* ICH7-M DH */
194 LPC_NM10, /* NM10 */
195 LPC_ICH8, /* ICH8 & ICH8R */
196 LPC_ICH8DH, /* ICH8DH */
197 LPC_ICH8DO, /* ICH8DO */
198 LPC_ICH8M, /* ICH8M */
199 LPC_ICH8ME, /* ICH8M-E */
200 LPC_ICH9, /* ICH9 */
201 LPC_ICH9R, /* ICH9R */
202 LPC_ICH9DH, /* ICH9DH */
203 LPC_ICH9DO, /* ICH9DO */
204 LPC_ICH9M, /* ICH9M */
205 LPC_ICH9ME, /* ICH9M-E */
206 LPC_ICH10, /* ICH10 */
207 LPC_ICH10R, /* ICH10R */
208 LPC_ICH10D, /* ICH10D */
209 LPC_ICH10DO, /* ICH10DO */
210 LPC_PCH, /* PCH Desktop Full Featured */
211 LPC_PCHM, /* PCH Mobile Full Featured */
212 LPC_P55, /* P55 */
213 LPC_PM55, /* PM55 */
214 LPC_H55, /* H55 */
215 LPC_QM57, /* QM57 */
216 LPC_H57, /* H57 */
217 LPC_HM55, /* HM55 */
218 LPC_Q57, /* Q57 */
219 LPC_HM57, /* HM57 */
220 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
221 LPC_QS57, /* QS57 */
222 LPC_3400, /* 3400 */
223 LPC_3420, /* 3420 */
224 LPC_3450, /* 3450 */
225 LPC_EP80579, /* EP80579 */
226 LPC_CPT, /* Cougar Point */
227 LPC_CPTD, /* Cougar Point Desktop */
228 LPC_CPTM, /* Cougar Point Mobile */
229 LPC_PBG, /* Patsburg */
230 LPC_DH89XXCC, /* DH89xxCC */
231 LPC_PPT, /* Panther Point */
232 LPC_LPT, /* Lynx Point */
233 LPC_LPT_LP, /* Lynx Point-LP */
234 LPC_WBG, /* Wellsburg */
235 LPC_AVN, /* Avoton SoC */
236 LPC_BAYTRAIL, /* Bay Trail SoC */
237 LPC_COLETO, /* Coleto Creek */
238 LPC_WPT_LP, /* Wildcat Point-LP */
239 LPC_BRASWELL, /* Braswell SoC */
240 LPC_LEWISBURG, /* Lewisburg */
241 LPC_9S, /* 9 Series */
242 };
243
244 static struct lpc_ich_info lpc_chipset_info[] = {
245 [LPC_ICH] = {
246 .name = "ICH",
247 .iTCO_version = 1,
248 },
249 [LPC_ICH0] = {
250 .name = "ICH0",
251 .iTCO_version = 1,
252 },
253 [LPC_ICH2] = {
254 .name = "ICH2",
255 .iTCO_version = 1,
256 },
257 [LPC_ICH2M] = {
258 .name = "ICH2-M",
259 .iTCO_version = 1,
260 },
261 [LPC_ICH3] = {
262 .name = "ICH3-S",
263 .iTCO_version = 1,
264 },
265 [LPC_ICH3M] = {
266 .name = "ICH3-M",
267 .iTCO_version = 1,
268 },
269 [LPC_ICH4] = {
270 .name = "ICH4",
271 .iTCO_version = 1,
272 },
273 [LPC_ICH4M] = {
274 .name = "ICH4-M",
275 .iTCO_version = 1,
276 },
277 [LPC_CICH] = {
278 .name = "C-ICH",
279 .iTCO_version = 1,
280 },
281 [LPC_ICH5] = {
282 .name = "ICH5 or ICH5R",
283 .iTCO_version = 1,
284 },
285 [LPC_6300ESB] = {
286 .name = "6300ESB",
287 .iTCO_version = 1,
288 },
289 [LPC_ICH6] = {
290 .name = "ICH6 or ICH6R",
291 .iTCO_version = 2,
292 .gpio_version = ICH_V6_GPIO,
293 },
294 [LPC_ICH6M] = {
295 .name = "ICH6-M",
296 .iTCO_version = 2,
297 .gpio_version = ICH_V6_GPIO,
298 },
299 [LPC_ICH6W] = {
300 .name = "ICH6W or ICH6RW",
301 .iTCO_version = 2,
302 .gpio_version = ICH_V6_GPIO,
303 },
304 [LPC_631XESB] = {
305 .name = "631xESB/632xESB",
306 .iTCO_version = 2,
307 .gpio_version = ICH_V6_GPIO,
308 },
309 [LPC_ICH7] = {
310 .name = "ICH7 or ICH7R",
311 .iTCO_version = 2,
312 .gpio_version = ICH_V7_GPIO,
313 },
314 [LPC_ICH7DH] = {
315 .name = "ICH7DH",
316 .iTCO_version = 2,
317 .gpio_version = ICH_V7_GPIO,
318 },
319 [LPC_ICH7M] = {
320 .name = "ICH7-M or ICH7-U",
321 .iTCO_version = 2,
322 .gpio_version = ICH_V7_GPIO,
323 },
324 [LPC_ICH7MDH] = {
325 .name = "ICH7-M DH",
326 .iTCO_version = 2,
327 .gpio_version = ICH_V7_GPIO,
328 },
329 [LPC_NM10] = {
330 .name = "NM10",
331 .iTCO_version = 2,
332 .gpio_version = ICH_V7_GPIO,
333 },
334 [LPC_ICH8] = {
335 .name = "ICH8 or ICH8R",
336 .iTCO_version = 2,
337 .gpio_version = ICH_V7_GPIO,
338 },
339 [LPC_ICH8DH] = {
340 .name = "ICH8DH",
341 .iTCO_version = 2,
342 .gpio_version = ICH_V7_GPIO,
343 },
344 [LPC_ICH8DO] = {
345 .name = "ICH8DO",
346 .iTCO_version = 2,
347 .gpio_version = ICH_V7_GPIO,
348 },
349 [LPC_ICH8M] = {
350 .name = "ICH8M",
351 .iTCO_version = 2,
352 .gpio_version = ICH_V7_GPIO,
353 },
354 [LPC_ICH8ME] = {
355 .name = "ICH8M-E",
356 .iTCO_version = 2,
357 .gpio_version = ICH_V7_GPIO,
358 },
359 [LPC_ICH9] = {
360 .name = "ICH9",
361 .iTCO_version = 2,
362 .gpio_version = ICH_V9_GPIO,
363 },
364 [LPC_ICH9R] = {
365 .name = "ICH9R",
366 .iTCO_version = 2,
367 .gpio_version = ICH_V9_GPIO,
368 },
369 [LPC_ICH9DH] = {
370 .name = "ICH9DH",
371 .iTCO_version = 2,
372 .gpio_version = ICH_V9_GPIO,
373 },
374 [LPC_ICH9DO] = {
375 .name = "ICH9DO",
376 .iTCO_version = 2,
377 .gpio_version = ICH_V9_GPIO,
378 },
379 [LPC_ICH9M] = {
380 .name = "ICH9M",
381 .iTCO_version = 2,
382 .gpio_version = ICH_V9_GPIO,
383 },
384 [LPC_ICH9ME] = {
385 .name = "ICH9M-E",
386 .iTCO_version = 2,
387 .gpio_version = ICH_V9_GPIO,
388 },
389 [LPC_ICH10] = {
390 .name = "ICH10",
391 .iTCO_version = 2,
392 .gpio_version = ICH_V10CONS_GPIO,
393 },
394 [LPC_ICH10R] = {
395 .name = "ICH10R",
396 .iTCO_version = 2,
397 .gpio_version = ICH_V10CONS_GPIO,
398 },
399 [LPC_ICH10D] = {
400 .name = "ICH10D",
401 .iTCO_version = 2,
402 .gpio_version = ICH_V10CORP_GPIO,
403 },
404 [LPC_ICH10DO] = {
405 .name = "ICH10DO",
406 .iTCO_version = 2,
407 .gpio_version = ICH_V10CORP_GPIO,
408 },
409 [LPC_PCH] = {
410 .name = "PCH Desktop Full Featured",
411 .iTCO_version = 2,
412 .gpio_version = ICH_V5_GPIO,
413 },
414 [LPC_PCHM] = {
415 .name = "PCH Mobile Full Featured",
416 .iTCO_version = 2,
417 .gpio_version = ICH_V5_GPIO,
418 },
419 [LPC_P55] = {
420 .name = "P55",
421 .iTCO_version = 2,
422 .gpio_version = ICH_V5_GPIO,
423 },
424 [LPC_PM55] = {
425 .name = "PM55",
426 .iTCO_version = 2,
427 .gpio_version = ICH_V5_GPIO,
428 },
429 [LPC_H55] = {
430 .name = "H55",
431 .iTCO_version = 2,
432 .gpio_version = ICH_V5_GPIO,
433 },
434 [LPC_QM57] = {
435 .name = "QM57",
436 .iTCO_version = 2,
437 .gpio_version = ICH_V5_GPIO,
438 },
439 [LPC_H57] = {
440 .name = "H57",
441 .iTCO_version = 2,
442 .gpio_version = ICH_V5_GPIO,
443 },
444 [LPC_HM55] = {
445 .name = "HM55",
446 .iTCO_version = 2,
447 .gpio_version = ICH_V5_GPIO,
448 },
449 [LPC_Q57] = {
450 .name = "Q57",
451 .iTCO_version = 2,
452 .gpio_version = ICH_V5_GPIO,
453 },
454 [LPC_HM57] = {
455 .name = "HM57",
456 .iTCO_version = 2,
457 .gpio_version = ICH_V5_GPIO,
458 },
459 [LPC_PCHMSFF] = {
460 .name = "PCH Mobile SFF Full Featured",
461 .iTCO_version = 2,
462 .gpio_version = ICH_V5_GPIO,
463 },
464 [LPC_QS57] = {
465 .name = "QS57",
466 .iTCO_version = 2,
467 .gpio_version = ICH_V5_GPIO,
468 },
469 [LPC_3400] = {
470 .name = "3400",
471 .iTCO_version = 2,
472 .gpio_version = ICH_V5_GPIO,
473 },
474 [LPC_3420] = {
475 .name = "3420",
476 .iTCO_version = 2,
477 .gpio_version = ICH_V5_GPIO,
478 },
479 [LPC_3450] = {
480 .name = "3450",
481 .iTCO_version = 2,
482 .gpio_version = ICH_V5_GPIO,
483 },
484 [LPC_EP80579] = {
485 .name = "EP80579",
486 .iTCO_version = 2,
487 },
488 [LPC_CPT] = {
489 .name = "Cougar Point",
490 .iTCO_version = 2,
491 .gpio_version = ICH_V5_GPIO,
492 },
493 [LPC_CPTD] = {
494 .name = "Cougar Point Desktop",
495 .iTCO_version = 2,
496 .gpio_version = ICH_V5_GPIO,
497 },
498 [LPC_CPTM] = {
499 .name = "Cougar Point Mobile",
500 .iTCO_version = 2,
501 .gpio_version = ICH_V5_GPIO,
502 },
503 [LPC_PBG] = {
504 .name = "Patsburg",
505 .iTCO_version = 2,
506 },
507 [LPC_DH89XXCC] = {
508 .name = "DH89xxCC",
509 .iTCO_version = 2,
510 },
511 [LPC_PPT] = {
512 .name = "Panther Point",
513 .iTCO_version = 2,
514 .gpio_version = ICH_V5_GPIO,
515 },
516 [LPC_LPT] = {
517 .name = "Lynx Point",
518 .iTCO_version = 2,
519 .gpio_version = ICH_V5_GPIO,
520 .spi_type = INTEL_SPI_LPT,
521 },
522 [LPC_LPT_LP] = {
523 .name = "Lynx Point_LP",
524 .iTCO_version = 2,
525 .spi_type = INTEL_SPI_LPT,
526 },
527 [LPC_WBG] = {
528 .name = "Wellsburg",
529 .iTCO_version = 2,
530 },
531 [LPC_AVN] = {
532 .name = "Avoton SoC",
533 .iTCO_version = 3,
534 .gpio_version = AVOTON_GPIO,
535 },
536 [LPC_BAYTRAIL] = {
537 .name = "Bay Trail SoC",
538 .iTCO_version = 3,
539 .spi_type = INTEL_SPI_BYT,
540 },
541 [LPC_COLETO] = {
542 .name = "Coleto Creek",
543 .iTCO_version = 2,
544 },
545 [LPC_WPT_LP] = {
546 .name = "Wildcat Point_LP",
547 .iTCO_version = 2,
548 .spi_type = INTEL_SPI_LPT,
549 },
550 [LPC_BRASWELL] = {
551 .name = "Braswell SoC",
552 .iTCO_version = 3,
553 .spi_type = INTEL_SPI_BYT,
554 },
555 [LPC_LEWISBURG] = {
556 .name = "Lewisburg",
557 .iTCO_version = 2,
558 },
559 [LPC_9S] = {
560 .name = "9 Series",
561 .iTCO_version = 2,
562 .gpio_version = ICH_V5_GPIO,
563 },
564 };
565
566 /*
567 * This data only exists for exporting the supported PCI ids
568 * via MODULE_DEVICE_TABLE. We do not actually register a
569 * pci_driver, because the I/O Controller Hub has also other
570 * functions that probably will be registered by other drivers.
571 */
572 static const struct pci_device_id lpc_ich_ids[] = {
573 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
574 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
575 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
576 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
577 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
578 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
579 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
580 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
581 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
582 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
583 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
584 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
585 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
586 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
587 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
588 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
589 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
590 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
591 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
592 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
593 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
594 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
595 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
596 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
597 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
598 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
599 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
600 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
601 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
602 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
603 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
604 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
605 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
606 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
607 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
608 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
609 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
610 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
611 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
612 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
613 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
614 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
615 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
616 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
617 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
618 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
619 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
620 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
621 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
622 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
623 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
624 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
625 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
626 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
627 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
628 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
629 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
630 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
631 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
632 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
633 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
634 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
635 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
636 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
637 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
638 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
639 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
640 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
641 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
642 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
643 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
644 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
645 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
646 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
647 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
648 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
649 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
650 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
651 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
652 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
653 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
654 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
655 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
656 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
657 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
658 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
659 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
660 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
661 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
662 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
663 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
664 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
665 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
666 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
667 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
668 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
669 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
670 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
671 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
672 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
673 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
674 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
675 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
676 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
677 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
678 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
679 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
680 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
681 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
682 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
683 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
684 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
685 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
686 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
687 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
688 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
689 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
690 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
691 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
692 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
693 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
694 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
695 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
696 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
697 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
698 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
699 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
700 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
701 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
702 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
703 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
704 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
705 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
706 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
707 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
708 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
709 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
710 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
711 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
712 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
713 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
714 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
715 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
716 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
717 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
718 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
719 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
720 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
721 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
722 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
723 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
724 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
725 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
726 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
727 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
728 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
729 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
730 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
731 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
732 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
733 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
734 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
735 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
736 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
737 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
738 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
739 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
740 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
741 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
742 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
743 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
744 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
745 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
746 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
747 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
748 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
749 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
750 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
751 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
752 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
753 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
754 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
755 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
756 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
757 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
758 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
759 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
760 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
761 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
762 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
763 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
764 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
765 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
766 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
767 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
768 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
769 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
770 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
771 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
772 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
773 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
774 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
775 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
776 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
777 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
778 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
779 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
780 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
781 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
782 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
783 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
784 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
785 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
786 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
787 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
788 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
789 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
790 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
791 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
792 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
793 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
794 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
795 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
796 { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
797 { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
798 { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
799 { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
800 { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
801 { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
802 { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
803 { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
804 { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
805 { 0, }, /* End of list */
806 };
807 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
808
809 static void lpc_ich_restore_config_space(struct pci_dev *dev)
810 {
811 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
812
813 if (priv->abase_save >= 0) {
814 pci_write_config_byte(dev, priv->abase, priv->abase_save);
815 priv->abase_save = -1;
816 }
817
818 if (priv->actrl_pbase_save >= 0) {
819 pci_write_config_byte(dev, priv->actrl_pbase,
820 priv->actrl_pbase_save);
821 priv->actrl_pbase_save = -1;
822 }
823
824 if (priv->gctrl_save >= 0) {
825 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
826 priv->gctrl_save = -1;
827 }
828 }
829
830 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
831 {
832 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
833 u8 reg_save;
834
835 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
836 case 3:
837 /*
838 * Some chipsets (eg Avoton) enable the ACPI space in the
839 * ACPI BASE register.
840 */
841 pci_read_config_byte(dev, priv->abase, &reg_save);
842 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
843 priv->abase_save = reg_save;
844 break;
845 default:
846 /*
847 * Most chipsets enable the ACPI space in the ACPI control
848 * register.
849 */
850 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
851 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
852 priv->actrl_pbase_save = reg_save;
853 break;
854 }
855 }
856
857 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
858 {
859 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
860 u8 reg_save;
861
862 pci_read_config_byte(dev, priv->gctrl, &reg_save);
863 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
864 priv->gctrl_save = reg_save;
865 }
866
867 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
868 {
869 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
870 u8 reg_save;
871
872 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
873 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
874
875 priv->actrl_pbase_save = reg_save;
876 }
877
878 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
879 {
880 struct itco_wdt_platform_data *pdata;
881 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
882 struct lpc_ich_info *info;
883 struct mfd_cell *cell = &lpc_ich_wdt_cell;
884
885 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
886 if (!pdata)
887 return -ENOMEM;
888
889 info = &lpc_chipset_info[priv->chipset];
890
891 pdata->version = info->iTCO_version;
892 strlcpy(pdata->name, info->name, sizeof(pdata->name));
893
894 cell->platform_data = pdata;
895 cell->pdata_size = sizeof(*pdata);
896 return 0;
897 }
898
899 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
900 {
901 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
902 struct mfd_cell *cell = &lpc_ich_gpio_cell;
903
904 cell->platform_data = &lpc_chipset_info[priv->chipset];
905 cell->pdata_size = sizeof(struct lpc_ich_info);
906 }
907
908 /*
909 * We don't check for resource conflict globally. There are 2 or 3 independent
910 * GPIO groups and it's enough to have access to one of these to instantiate
911 * the device.
912 */
913 static int lpc_ich_check_conflict_gpio(struct resource *res)
914 {
915 int ret;
916 u8 use_gpio = 0;
917
918 if (resource_size(res) >= 0x50 &&
919 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
920 use_gpio |= 1 << 2;
921
922 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
923 use_gpio |= 1 << 1;
924
925 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
926 if (!ret)
927 use_gpio |= 1 << 0;
928
929 return use_gpio ? use_gpio : ret;
930 }
931
932 static int lpc_ich_init_gpio(struct pci_dev *dev)
933 {
934 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
935 u32 base_addr_cfg;
936 u32 base_addr;
937 int ret;
938 bool acpi_conflict = false;
939 struct resource *res;
940
941 /* Setup power management base register */
942 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
943 base_addr = base_addr_cfg & 0x0000ff80;
944 if (!base_addr) {
945 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
946 lpc_ich_gpio_cell.num_resources--;
947 goto gpe0_done;
948 }
949
950 res = &gpio_ich_res[ICH_RES_GPE0];
951 res->start = base_addr + ACPIBASE_GPE_OFF;
952 res->end = base_addr + ACPIBASE_GPE_END;
953 ret = acpi_check_resource_conflict(res);
954 if (ret) {
955 /*
956 * This isn't fatal for the GPIO, but we have to make sure that
957 * the platform_device subsystem doesn't see this resource
958 * or it will register an invalid region.
959 */
960 lpc_ich_gpio_cell.num_resources--;
961 acpi_conflict = true;
962 } else {
963 lpc_ich_enable_acpi_space(dev);
964 }
965
966 gpe0_done:
967 /* Setup GPIO base register */
968 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
969 base_addr = base_addr_cfg & 0x0000ff80;
970 if (!base_addr) {
971 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
972 ret = -ENODEV;
973 goto gpio_done;
974 }
975
976 /* Older devices provide fewer GPIO and have a smaller resource size. */
977 res = &gpio_ich_res[ICH_RES_GPIO];
978 res->start = base_addr;
979 switch (lpc_chipset_info[priv->chipset].gpio_version) {
980 case ICH_V5_GPIO:
981 case ICH_V10CORP_GPIO:
982 res->end = res->start + 128 - 1;
983 break;
984 default:
985 res->end = res->start + 64 - 1;
986 break;
987 }
988
989 ret = lpc_ich_check_conflict_gpio(res);
990 if (ret < 0) {
991 /* this isn't necessarily fatal for the GPIO */
992 acpi_conflict = true;
993 goto gpio_done;
994 }
995 lpc_chipset_info[priv->chipset].use_gpio = ret;
996 lpc_ich_enable_gpio_space(dev);
997
998 lpc_ich_finalize_gpio_cell(dev);
999 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1000 &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1001
1002 gpio_done:
1003 if (acpi_conflict)
1004 pr_warn("Resource conflict(s) found affecting %s\n",
1005 lpc_ich_gpio_cell.name);
1006 return ret;
1007 }
1008
1009 static int lpc_ich_init_wdt(struct pci_dev *dev)
1010 {
1011 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1012 u32 base_addr_cfg;
1013 u32 base_addr;
1014 int ret;
1015 struct resource *res;
1016
1017 /* If we have ACPI based watchdog use that instead */
1018 if (acpi_has_watchdog())
1019 return -ENODEV;
1020
1021 /* Setup power management base register */
1022 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1023 base_addr = base_addr_cfg & 0x0000ff80;
1024 if (!base_addr) {
1025 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1026 ret = -ENODEV;
1027 goto wdt_done;
1028 }
1029
1030 res = wdt_io_res(ICH_RES_IO_TCO);
1031 res->start = base_addr + ACPIBASE_TCO_OFF;
1032 res->end = base_addr + ACPIBASE_TCO_END;
1033
1034 res = wdt_io_res(ICH_RES_IO_SMI);
1035 res->start = base_addr + ACPIBASE_SMI_OFF;
1036 res->end = base_addr + ACPIBASE_SMI_END;
1037
1038 lpc_ich_enable_acpi_space(dev);
1039
1040 /*
1041 * iTCO v2:
1042 * Get the Memory-Mapped GCS register. To get access to it
1043 * we have to read RCBA from PCI Config space 0xf0 and use
1044 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1045 *
1046 * iTCO v3:
1047 * Get the Power Management Configuration register. To get access
1048 * to it we have to read the PMC BASE from config space and address
1049 * the register at offset 0x8.
1050 */
1051 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1052 /* Don't register iomem for TCO ver 1 */
1053 lpc_ich_wdt_cell.num_resources--;
1054 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1055 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1056 base_addr = base_addr_cfg & 0xffffc000;
1057 if (!(base_addr_cfg & 1)) {
1058 dev_notice(&dev->dev, "RCBA is disabled by "
1059 "hardware/BIOS, device disabled\n");
1060 ret = -ENODEV;
1061 goto wdt_done;
1062 }
1063 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1064 res->start = base_addr + ACPIBASE_GCS_OFF;
1065 res->end = base_addr + ACPIBASE_GCS_END;
1066 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1067 lpc_ich_enable_pmc_space(dev);
1068 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1069 base_addr = base_addr_cfg & 0xfffffe00;
1070
1071 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1072 res->start = base_addr + ACPIBASE_PMC_OFF;
1073 res->end = base_addr + ACPIBASE_PMC_END;
1074 }
1075
1076 ret = lpc_ich_finalize_wdt_cell(dev);
1077 if (ret)
1078 goto wdt_done;
1079
1080 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1081 &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1082
1083 wdt_done:
1084 return ret;
1085 }
1086
1087 static int lpc_ich_init_spi(struct pci_dev *dev)
1088 {
1089 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1090 struct resource *res = &intel_spi_res[0];
1091 struct intel_spi_boardinfo *info;
1092 u32 spi_base, rcba, bcr;
1093
1094 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1095 if (!info)
1096 return -ENOMEM;
1097
1098 info->type = lpc_chipset_info[priv->chipset].spi_type;
1099
1100 switch (info->type) {
1101 case INTEL_SPI_BYT:
1102 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1103 if (spi_base & SPIBASE_BYT_EN) {
1104 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1105 res->end = res->start + SPIBASE_BYT_SZ - 1;
1106 }
1107 break;
1108
1109 case INTEL_SPI_LPT:
1110 pci_read_config_dword(dev, RCBABASE, &rcba);
1111 if (rcba & 1) {
1112 spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1113 res->start = spi_base + SPIBASE_LPT;
1114 res->end = res->start + SPIBASE_LPT_SZ - 1;
1115
1116 /*
1117 * Try to make the flash chip writeable now by
1118 * setting BCR_WPD. It it fails we tell the driver
1119 * that it can only read the chip.
1120 */
1121 pci_read_config_dword(dev, BCR, &bcr);
1122 if (!(bcr & BCR_WPD)) {
1123 bcr |= BCR_WPD;
1124 pci_write_config_dword(dev, BCR, bcr);
1125 pci_read_config_dword(dev, BCR, &bcr);
1126 }
1127 info->writeable = !!(bcr & BCR_WPD);
1128 }
1129 break;
1130
1131 default:
1132 return -EINVAL;
1133 }
1134
1135 if (!res->start)
1136 return -ENODEV;
1137
1138 lpc_ich_spi_cell.platform_data = info;
1139 lpc_ich_spi_cell.pdata_size = sizeof(*info);
1140
1141 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1142 &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1143 }
1144
1145 static int lpc_ich_probe(struct pci_dev *dev,
1146 const struct pci_device_id *id)
1147 {
1148 struct lpc_ich_priv *priv;
1149 int ret;
1150 bool cell_added = false;
1151
1152 priv = devm_kzalloc(&dev->dev,
1153 sizeof(struct lpc_ich_priv), GFP_KERNEL);
1154 if (!priv)
1155 return -ENOMEM;
1156
1157 priv->chipset = id->driver_data;
1158
1159 priv->actrl_pbase_save = -1;
1160 priv->abase_save = -1;
1161
1162 priv->abase = ACPIBASE;
1163 priv->actrl_pbase = ACPICTRL_PMCBASE;
1164
1165 priv->gctrl_save = -1;
1166 if (priv->chipset <= LPC_ICH5) {
1167 priv->gbase = GPIOBASE_ICH0;
1168 priv->gctrl = GPIOCTRL_ICH0;
1169 } else {
1170 priv->gbase = GPIOBASE_ICH6;
1171 priv->gctrl = GPIOCTRL_ICH6;
1172 }
1173
1174 pci_set_drvdata(dev, priv);
1175
1176 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1177 ret = lpc_ich_init_wdt(dev);
1178 if (!ret)
1179 cell_added = true;
1180 }
1181
1182 if (lpc_chipset_info[priv->chipset].gpio_version) {
1183 ret = lpc_ich_init_gpio(dev);
1184 if (!ret)
1185 cell_added = true;
1186 }
1187
1188 if (lpc_chipset_info[priv->chipset].spi_type) {
1189 ret = lpc_ich_init_spi(dev);
1190 if (!ret)
1191 cell_added = true;
1192 }
1193
1194 /*
1195 * We only care if at least one or none of the cells registered
1196 * successfully.
1197 */
1198 if (!cell_added) {
1199 dev_warn(&dev->dev, "No MFD cells added\n");
1200 lpc_ich_restore_config_space(dev);
1201 return -ENODEV;
1202 }
1203
1204 return 0;
1205 }
1206
1207 static void lpc_ich_remove(struct pci_dev *dev)
1208 {
1209 mfd_remove_devices(&dev->dev);
1210 lpc_ich_restore_config_space(dev);
1211 }
1212
1213 static struct pci_driver lpc_ich_driver = {
1214 .name = "lpc_ich",
1215 .id_table = lpc_ich_ids,
1216 .probe = lpc_ich_probe,
1217 .remove = lpc_ich_remove,
1218 };
1219
1220 module_pci_driver(lpc_ich_driver);
1221
1222 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1223 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1224 MODULE_LICENSE("GPL");
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