drivers/mfd/lpc_ich.c

   1 /*
   2  *  lpc_ich.c - LPC interface for Intel ICH
   3  *
   4  *  LPC bridge function of the Intel ICH contains many other
   5  *  functional units, such as Interrupt controllers, Timers,
   6  *  Power Management, System Management, GPIO, RTC, and LPC
   7  *  Configuration Registers.
   8  *
   9  *  This driver is derived from lpc_sch.
  10
  11  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
  12  *  Author: Aaron Sierra <asierra@xes-inc.com>
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License 2 as published
  16  *  by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *  This driver supports the following I/O Controller hubs:
  28  *      (See the intel documentation on http://developer.intel.com.)
  29  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  30  *      document number 290687-002, 298242-027: 82801BA (ICH2)
  31  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  32  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  33  *      document number 290744-001, 290745-025: 82801DB (ICH4)
  34  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  35  *      document number 273599-001, 273645-002: 82801E (C-ICH)
  36  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  37  *      document number 300641-004, 300884-013: 6300ESB
  38  *      document number 301473-002, 301474-026: 82801F (ICH6)
  39  *      document number 313082-001, 313075-006: 631xESB, 632xESB
  40  *      document number 307013-003, 307014-024: 82801G (ICH7)
  41  *      document number 322896-001, 322897-001: NM10
  42  *      document number 313056-003, 313057-017: 82801H (ICH8)
  43  *      document number 316972-004, 316973-012: 82801I (ICH9)
  44  *      document number 319973-002, 319974-002: 82801J (ICH10)
  45  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  46  *      document number 320066-003, 320257-008: EP80597 (IICH)
  47  *      document number 324645-001, 324646-001: Cougar Point (CPT)
  48  *      document number TBD : Patsburg (PBG)
  49  *      document number TBD : DH89xxCC
  50  *      document number TBD : Panther Point
  51  *      document number TBD : Lynx Point
  52  */
  53
  54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  55
  56 #include <linux/init.h>
  57 #include <linux/kernel.h>
  58 #include <linux/module.h>
  59 #include <linux/errno.h>
  60 #include <linux/acpi.h>
  61 #include <linux/pci.h>
  62 #include <linux/mfd/core.h>
  63 #include <linux/mfd/lpc_ich.h>
  64
  65 #define ACPIBASE                0x40
  66 #define ACPIBASE_GPE_OFF        0x28
  67 #define ACPIBASE_GPE_END        0x2f
  68 #define ACPIBASE_SMI_OFF        0x30
  69 #define ACPIBASE_SMI_END        0x33
  70 #define ACPIBASE_TCO_OFF        0x60
  71 #define ACPIBASE_TCO_END        0x7f
  72 #define ACPICTRL                0x44
  73
  74 #define ACPIBASE_GCS_OFF        0x3410
  75 #define ACPIBASE_GCS_END        0x3414
  76
  77 #define GPIOBASE                0x48
  78 #define GPIOCTRL                0x4C
  79
  80 #define RCBABASE                0xf0
  81
  82 #define wdt_io_res(i) wdt_res(0, i)
  83 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
  84 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
  85
  86 static int lpc_ich_acpi_save = -1;
  87 static int lpc_ich_gpio_save = -1;
  88
  89 static struct resource wdt_ich_res[] = {
  90         /* ACPI - TCO */
  91         {
  92                 .flags = IORESOURCE_IO,
  93         },
  94         /* ACPI - SMI */
  95         {
  96                 .flags = IORESOURCE_IO,
  97         },
  98         /* GCS */
  99         {
 100                 .flags = IORESOURCE_MEM,
 101         },
 102 };
 103
 104 static struct resource gpio_ich_res[] = {
 105         /* GPIO */
 106         {
 107                 .flags = IORESOURCE_IO,
 108         },
 109         /* ACPI - GPE0 */
 110         {
 111                 .flags = IORESOURCE_IO,
 112         },
 113 };
 114
 115 enum lpc_cells {
 116         LPC_WDT = 0,
 117         LPC_GPIO,
 118 };
 119
 120 static struct mfd_cell lpc_ich_cells[] = {
 121         [LPC_WDT] = {
 122                 .name = "iTCO_wdt",
 123                 .num_resources = ARRAY_SIZE(wdt_ich_res),
 124                 .resources = wdt_ich_res,
 125                 .ignore_resource_conflicts = true,
 126         },
 127         [LPC_GPIO] = {
 128                 .name = "gpio_ich",
 129                 .num_resources = ARRAY_SIZE(gpio_ich_res),
 130                 .resources = gpio_ich_res,
 131                 .ignore_resource_conflicts = true,
 132         },
 133 };
 134
 135 /* chipset related info */
 136 enum lpc_chipsets {
 137         LPC_ICH = 0,    /* ICH */
 138         LPC_ICH0,       /* ICH0 */
 139         LPC_ICH2,       /* ICH2 */
 140         LPC_ICH2M,      /* ICH2-M */
 141         LPC_ICH3,       /* ICH3-S */
 142         LPC_ICH3M,      /* ICH3-M */
 143         LPC_ICH4,       /* ICH4 */
 144         LPC_ICH4M,      /* ICH4-M */
 145         LPC_CICH,       /* C-ICH */
 146         LPC_ICH5,       /* ICH5 & ICH5R */
 147         LPC_6300ESB,    /* 6300ESB */
 148         LPC_ICH6,       /* ICH6 & ICH6R */
 149         LPC_ICH6M,      /* ICH6-M */
 150         LPC_ICH6W,      /* ICH6W & ICH6RW */
 151         LPC_631XESB,    /* 631xESB/632xESB */
 152         LPC_ICH7,       /* ICH7 & ICH7R */
 153         LPC_ICH7DH,     /* ICH7DH */
 154         LPC_ICH7M,      /* ICH7-M & ICH7-U */
 155         LPC_ICH7MDH,    /* ICH7-M DH */
 156         LPC_NM10,       /* NM10 */
 157         LPC_ICH8,       /* ICH8 & ICH8R */
 158         LPC_ICH8DH,     /* ICH8DH */
 159         LPC_ICH8DO,     /* ICH8DO */
 160         LPC_ICH8M,      /* ICH8M */
 161         LPC_ICH8ME,     /* ICH8M-E */
 162         LPC_ICH9,       /* ICH9 */
 163         LPC_ICH9R,      /* ICH9R */
 164         LPC_ICH9DH,     /* ICH9DH */
 165         LPC_ICH9DO,     /* ICH9DO */
 166         LPC_ICH9M,      /* ICH9M */
 167         LPC_ICH9ME,     /* ICH9M-E */
 168         LPC_ICH10,      /* ICH10 */
 169         LPC_ICH10R,     /* ICH10R */
 170         LPC_ICH10D,     /* ICH10D */
 171         LPC_ICH10DO,    /* ICH10DO */
 172         LPC_PCH,        /* PCH Desktop Full Featured */
 173         LPC_PCHM,       /* PCH Mobile Full Featured */
 174         LPC_P55,        /* P55 */
 175         LPC_PM55,       /* PM55 */
 176         LPC_H55,        /* H55 */
 177         LPC_QM57,       /* QM57 */
 178         LPC_H57,        /* H57 */
 179         LPC_HM55,       /* HM55 */
 180         LPC_Q57,        /* Q57 */
 181         LPC_HM57,       /* HM57 */
 182         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
 183         LPC_QS57,       /* QS57 */
 184         LPC_3400,       /* 3400 */
 185         LPC_3420,       /* 3420 */
 186         LPC_3450,       /* 3450 */
 187         LPC_EP80579,    /* EP80579 */
 188         LPC_CPT,        /* Cougar Point */
 189         LPC_CPTD,       /* Cougar Point Desktop */
 190         LPC_CPTM,       /* Cougar Point Mobile */
 191         LPC_PBG,        /* Patsburg */
 192         LPC_DH89XXCC,   /* DH89xxCC */
 193         LPC_PPT,        /* Panther Point */
 194         LPC_LPT,        /* Lynx Point */
 195 };
 196
 197 struct lpc_ich_info lpc_chipset_info[] __devinitdata = {
 198         [LPC_ICH] = {
 199                 .name = "ICH",
 200                 .iTCO_version = 1,
 201         },
 202         [LPC_ICH0] = {
 203                 .name = "ICH0",
 204                 .iTCO_version = 1,
 205         },
 206         [LPC_ICH2] = {
 207                 .name = "ICH2",
 208                 .iTCO_version = 1,
 209         },
 210         [LPC_ICH2M] = {
 211                 .name = "ICH2-M",
 212                 .iTCO_version = 1,
 213         },
 214         [LPC_ICH3] = {
 215                 .name = "ICH3-S",
 216                 .iTCO_version = 1,
 217         },
 218         [LPC_ICH3M] = {
 219                 .name = "ICH3-M",
 220                 .iTCO_version = 1,
 221         },
 222         [LPC_ICH4] = {
 223                 .name = "ICH4",
 224                 .iTCO_version = 1,
 225         },
 226         [LPC_ICH4M] = {
 227                 .name = "ICH4-M",
 228                 .iTCO_version = 1,
 229         },
 230         [LPC_CICH] = {
 231                 .name = "C-ICH",
 232                 .iTCO_version = 1,
 233         },
 234         [LPC_ICH5] = {
 235                 .name = "ICH5 or ICH5R",
 236                 .iTCO_version = 1,
 237         },
 238         [LPC_6300ESB] = {
 239                 .name = "6300ESB",
 240                 .iTCO_version = 1,
 241         },
 242         [LPC_ICH6] = {
 243                 .name = "ICH6 or ICH6R",
 244                 .iTCO_version = 2,
 245                 .gpio_version = ICH_V6_GPIO,
 246         },
 247         [LPC_ICH6M] = {
 248                 .name = "ICH6-M",
 249                 .iTCO_version = 2,
 250                 .gpio_version = ICH_V6_GPIO,
 251         },
 252         [LPC_ICH6W] = {
 253                 .name = "ICH6W or ICH6RW",
 254                 .iTCO_version = 2,
 255                 .gpio_version = ICH_V6_GPIO,
 256         },
 257         [LPC_631XESB] = {
 258                 .name = "631xESB/632xESB",
 259                 .iTCO_version = 2,
 260                 .gpio_version = ICH_V6_GPIO,
 261         },
 262         [LPC_ICH7] = {
 263                 .name = "ICH7 or ICH7R",
 264                 .iTCO_version = 2,
 265                 .gpio_version = ICH_V7_GPIO,
 266         },
 267         [LPC_ICH7DH] = {
 268                 .name = "ICH7DH",
 269                 .iTCO_version = 2,
 270                 .gpio_version = ICH_V7_GPIO,
 271         },
 272         [LPC_ICH7M] = {
 273                 .name = "ICH7-M or ICH7-U",
 274                 .iTCO_version = 2,
 275                 .gpio_version = ICH_V7_GPIO,
 276         },
 277         [LPC_ICH7MDH] = {
 278                 .name = "ICH7-M DH",
 279                 .iTCO_version = 2,
 280                 .gpio_version = ICH_V7_GPIO,
 281         },
 282         [LPC_NM10] = {
 283                 .name = "NM10",
 284                 .iTCO_version = 2,
 285         },
 286         [LPC_ICH8] = {
 287                 .name = "ICH8 or ICH8R",
 288                 .iTCO_version = 2,
 289                 .gpio_version = ICH_V7_GPIO,
 290         },
 291         [LPC_ICH8DH] = {
 292                 .name = "ICH8DH",
 293                 .iTCO_version = 2,
 294                 .gpio_version = ICH_V7_GPIO,
 295         },
 296         [LPC_ICH8DO] = {
 297                 .name = "ICH8DO",
 298                 .iTCO_version = 2,
 299                 .gpio_version = ICH_V7_GPIO,
 300         },
 301         [LPC_ICH8M] = {
 302                 .name = "ICH8M",
 303                 .iTCO_version = 2,
 304                 .gpio_version = ICH_V7_GPIO,
 305         },
 306         [LPC_ICH8ME] = {
 307                 .name = "ICH8M-E",
 308                 .iTCO_version = 2,
 309                 .gpio_version = ICH_V7_GPIO,
 310         },
 311         [LPC_ICH9] = {
 312                 .name = "ICH9",
 313                 .iTCO_version = 2,
 314                 .gpio_version = ICH_V9_GPIO,
 315         },
 316         [LPC_ICH9R] = {
 317                 .name = "ICH9R",
 318                 .iTCO_version = 2,
 319                 .gpio_version = ICH_V9_GPIO,
 320         },
 321         [LPC_ICH9DH] = {
 322                 .name = "ICH9DH",
 323                 .iTCO_version = 2,
 324                 .gpio_version = ICH_V9_GPIO,
 325         },
 326         [LPC_ICH9DO] = {
 327                 .name = "ICH9DO",
 328                 .iTCO_version = 2,
 329                 .gpio_version = ICH_V9_GPIO,
 330         },
 331         [LPC_ICH9M] = {
 332                 .name = "ICH9M",
 333                 .iTCO_version = 2,
 334                 .gpio_version = ICH_V9_GPIO,
 335         },
 336         [LPC_ICH9ME] = {
 337                 .name = "ICH9M-E",
 338                 .iTCO_version = 2,
 339                 .gpio_version = ICH_V9_GPIO,
 340         },
 341         [LPC_ICH10] = {
 342                 .name = "ICH10",
 343                 .iTCO_version = 2,
 344                 .gpio_version = ICH_V10CONS_GPIO,
 345         },
 346         [LPC_ICH10R] = {
 347                 .name = "ICH10R",
 348                 .iTCO_version = 2,
 349                 .gpio_version = ICH_V10CONS_GPIO,
 350         },
 351         [LPC_ICH10D] = {
 352                 .name = "ICH10D",
 353                 .iTCO_version = 2,
 354                 .gpio_version = ICH_V10CORP_GPIO,
 355         },
 356         [LPC_ICH10DO] = {
 357                 .name = "ICH10DO",
 358                 .iTCO_version = 2,
 359                 .gpio_version = ICH_V10CORP_GPIO,
 360         },
 361         [LPC_PCH] = {
 362                 .name = "PCH Desktop Full Featured",
 363                 .iTCO_version = 2,
 364                 .gpio_version = ICH_V5_GPIO,
 365         },
 366         [LPC_PCHM] = {
 367                 .name = "PCH Mobile Full Featured",
 368                 .iTCO_version = 2,
 369                 .gpio_version = ICH_V5_GPIO,
 370         },
 371         [LPC_P55] = {
 372                 .name = "P55",
 373                 .iTCO_version = 2,
 374                 .gpio_version = ICH_V5_GPIO,
 375         },
 376         [LPC_PM55] = {
 377                 .name = "PM55",
 378                 .iTCO_version = 2,
 379                 .gpio_version = ICH_V5_GPIO,
 380         },
 381         [LPC_H55] = {
 382                 .name = "H55",
 383                 .iTCO_version = 2,
 384                 .gpio_version = ICH_V5_GPIO,
 385         },
 386         [LPC_QM57] = {
 387                 .name = "QM57",
 388                 .iTCO_version = 2,
 389                 .gpio_version = ICH_V5_GPIO,
 390         },
 391         [LPC_H57] = {
 392                 .name = "H57",
 393                 .iTCO_version = 2,
 394                 .gpio_version = ICH_V5_GPIO,
 395         },
 396         [LPC_HM55] = {
 397                 .name = "HM55",
 398                 .iTCO_version = 2,
 399                 .gpio_version = ICH_V5_GPIO,
 400         },
 401         [LPC_Q57] = {
 402                 .name = "Q57",
 403                 .iTCO_version = 2,
 404                 .gpio_version = ICH_V5_GPIO,
 405         },
 406         [LPC_HM57] = {
 407                 .name = "HM57",
 408                 .iTCO_version = 2,
 409                 .gpio_version = ICH_V5_GPIO,
 410         },
 411         [LPC_PCHMSFF] = {
 412                 .name = "PCH Mobile SFF Full Featured",
 413                 .iTCO_version = 2,
 414                 .gpio_version = ICH_V5_GPIO,
 415         },
 416         [LPC_QS57] = {
 417                 .name = "QS57",
 418                 .iTCO_version = 2,
 419                 .gpio_version = ICH_V5_GPIO,
 420         },
 421         [LPC_3400] = {
 422                 .name = "3400",
 423                 .iTCO_version = 2,
 424                 .gpio_version = ICH_V5_GPIO,
 425         },
 426         [LPC_3420] = {
 427                 .name = "3420",
 428                 .iTCO_version = 2,
 429                 .gpio_version = ICH_V5_GPIO,
 430         },
 431         [LPC_3450] = {
 432                 .name = "3450",
 433                 .iTCO_version = 2,
 434                 .gpio_version = ICH_V5_GPIO,
 435         },
 436         [LPC_EP80579] = {
 437                 .name = "EP80579",
 438                 .iTCO_version = 2,
 439         },
 440         [LPC_CPT] = {
 441                 .name = "Cougar Point",
 442                 .iTCO_version = 2,
 443                 .gpio_version = ICH_V5_GPIO,
 444         },
 445         [LPC_CPTD] = {
 446                 .name = "Cougar Point Desktop",
 447                 .iTCO_version = 2,
 448                 .gpio_version = ICH_V5_GPIO,
 449         },
 450         [LPC_CPTM] = {
 451                 .name = "Cougar Point Mobile",
 452                 .iTCO_version = 2,
 453                 .gpio_version = ICH_V5_GPIO,
 454         },
 455         [LPC_PBG] = {
 456                 .name = "Patsburg",
 457                 .iTCO_version = 2,
 458         },
 459         [LPC_DH89XXCC] = {
 460                 .name = "DH89xxCC",
 461                 .iTCO_version = 2,
 462         },
 463         [LPC_PPT] = {
 464                 .name = "Panther Point",
 465                 .iTCO_version = 2,
 466         },
 467         [LPC_LPT] = {
 468                 .name = "Lynx Point",
 469                 .iTCO_version = 2,
 470         },
 471 };
 472
 473 /*
 474  * This data only exists for exporting the supported PCI ids
 475  * via MODULE_DEVICE_TABLE.  We do not actually register a
 476  * pci_driver, because the I/O Controller Hub has also other
 477  * functions that probably will be registered by other drivers.
 478  */
 479 static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids) = {
 480         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
 481         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
 482         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
 483         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
 484         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
 485         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
 486         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
 487         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
 488         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
 489         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
 490         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
 491         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
 492         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
 493         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
 494         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
 495         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
 496         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
 497         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
 498         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
 499         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
 500         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
 501         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
 502         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
 503         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
 504         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
 505         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
 506         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
 507         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
 508         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
 509         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
 510         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
 511         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
 512         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
 513         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
 514         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
 515         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
 516         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
 517         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
 518         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
 519         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
 520         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
 521         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
 522         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
 523         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
 524         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
 525         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
 526         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
 527         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
 528         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
 529         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
 530         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
 531         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
 532         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
 533         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
 534         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
 535         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
 536         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
 537         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
 538         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
 539         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
 540         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
 541         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
 542         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
 543         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
 544         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
 545         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
 546         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
 547         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
 548         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
 549         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
 550         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
 551         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
 552         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
 553         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
 554         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
 555         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
 556         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
 557         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
 558         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
 559         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
 560         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
 561         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
 562         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
 563         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
 564         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
 565         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
 566         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
 567         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
 568         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
 569         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
 570         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
 571         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
 572         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
 573         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
 574         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
 575         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
 576         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
 577         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
 578         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
 579         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
 580         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
 581         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
 582         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
 583         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
 584         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
 585         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
 586         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
 587         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
 588         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
 589         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
 590         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
 591         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
 592         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
 593         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
 594         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
 595         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
 596         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
 597         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
 598         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
 599         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
 600         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
 601         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
 602         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
 603         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
 604         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
 605         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
 606         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
 607         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
 608         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
 609         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
 610         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
 611         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
 612         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
 613         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
 614         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
 615         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
 616         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
 617         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
 618         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
 619         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
 620         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
 621         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
 622         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
 623         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
 624         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
 625         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
 626         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
 627         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
 628         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
 629         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
 630         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
 631         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
 632         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
 633         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
 634         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
 635         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
 636         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
 637         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
 638         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
 639         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
 640         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
 641         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
 642         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
 643         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
 644         { 0, },                 /* End of list */
 645 };
 646 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
 647
 648 static void lpc_ich_restore_config_space(struct pci_dev *dev)
 649 {
 650         if (lpc_ich_acpi_save >= 0) {
 651                 pci_write_config_byte(dev, ACPICTRL, lpc_ich_acpi_save);
 652                 lpc_ich_acpi_save = -1;
 653         }
 654
 655         if (lpc_ich_gpio_save >= 0) {
 656                 pci_write_config_byte(dev, GPIOCTRL, lpc_ich_gpio_save);
 657                 lpc_ich_gpio_save = -1;
 658         }
 659 }
 660
 661 static void __devinit lpc_ich_enable_acpi_space(struct pci_dev *dev)
 662 {
 663         u8 reg_save;
 664
 665         pci_read_config_byte(dev, ACPICTRL, &reg_save);
 666         pci_write_config_byte(dev, ACPICTRL, reg_save | 0x10);
 667         lpc_ich_acpi_save = reg_save;
 668 }
 669
 670 static void __devinit lpc_ich_enable_gpio_space(struct pci_dev *dev)
 671 {
 672         u8 reg_save;
 673
 674         pci_read_config_byte(dev, GPIOCTRL, &reg_save);
 675         pci_write_config_byte(dev, GPIOCTRL, reg_save | 0x10);
 676         lpc_ich_gpio_save = reg_save;
 677 }
 678
 679 static void __devinit lpc_ich_finalize_cell(struct mfd_cell *cell,
 680                                         const struct pci_device_id *id)
 681 {
 682         cell->platform_data = &lpc_chipset_info[id->driver_data];
 683         cell->pdata_size = sizeof(struct lpc_ich_info);
 684 }
 685
 686 static int __devinit lpc_ich_init_gpio(struct pci_dev *dev,
 687                                 const struct pci_device_id *id)
 688 {
 689         u32 base_addr_cfg;
 690         u32 base_addr;
 691         int ret;
 692         bool acpi_conflict = false;
 693         struct resource *res;
 694
 695         /* Setup power management base register */
 696         pci_read_config_dword(dev, ACPIBASE, &base_addr_cfg);
 697         base_addr = base_addr_cfg & 0x0000ff80;
 698         if (!base_addr) {
 699                 dev_err(&dev->dev, "I/O space for ACPI uninitialized\n");
 700                 lpc_ich_cells[LPC_GPIO].num_resources--;
 701                 goto gpe0_done;
 702         }
 703
 704         res = &gpio_ich_res[ICH_RES_GPE0];
 705         res->start = base_addr + ACPIBASE_GPE_OFF;
 706         res->end = base_addr + ACPIBASE_GPE_END;
 707         ret = acpi_check_resource_conflict(res);
 708         if (ret) {
 709                 /*
 710                  * This isn't fatal for the GPIO, but we have to make sure that
 711                  * the platform_device subsystem doesn't see this resource
 712                  * or it will register an invalid region.
 713                  */
 714                 lpc_ich_cells[LPC_GPIO].num_resources--;
 715                 acpi_conflict = true;
 716         } else {
 717                 lpc_ich_enable_acpi_space(dev);
 718         }
 719
 720 gpe0_done:
 721         /* Setup GPIO base register */
 722         pci_read_config_dword(dev, GPIOBASE, &base_addr_cfg);
 723         base_addr = base_addr_cfg & 0x0000ff80;
 724         if (!base_addr) {
 725                 dev_err(&dev->dev, "I/O space for GPIO uninitialized\n");
 726                 ret = -ENODEV;
 727                 goto gpio_done;
 728         }
 729
 730         /* Older devices provide fewer GPIO and have a smaller resource size. */
 731         res = &gpio_ich_res[ICH_RES_GPIO];
 732         res->start = base_addr;
 733         switch (lpc_chipset_info[id->driver_data].gpio_version) {
 734         case ICH_V5_GPIO:
 735         case ICH_V10CORP_GPIO:
 736                 res->end = res->start + 128 - 1;
 737                 break;
 738         default:
 739                 res->end = res->start + 64 - 1;
 740                 break;
 741         }
 742
 743         ret = acpi_check_resource_conflict(res);
 744         if (ret) {
 745                 /* this isn't necessarily fatal for the GPIO */
 746                 acpi_conflict = true;
 747                 goto gpio_done;
 748         }
 749         lpc_ich_enable_gpio_space(dev);
 750
 751         lpc_ich_finalize_cell(&lpc_ich_cells[LPC_GPIO], id);
 752         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
 753                               1, NULL, 0, NULL);
 754
 755 gpio_done:
 756         if (acpi_conflict)
 757                 pr_warn("Resource conflict(s) found affecting %s\n",
 758                                 lpc_ich_cells[LPC_GPIO].name);
 759         return ret;
 760 }
 761
 762 static int __devinit lpc_ich_init_wdt(struct pci_dev *dev,
 763                                 const struct pci_device_id *id)
 764 {
 765         u32 base_addr_cfg;
 766         u32 base_addr;
 767         int ret;
 768         struct resource *res;
 769
 770         /* Setup power management base register */
 771         pci_read_config_dword(dev, ACPIBASE, &base_addr_cfg);
 772         base_addr = base_addr_cfg & 0x0000ff80;
 773         if (!base_addr) {
 774                 dev_err(&dev->dev, "I/O space for ACPI uninitialized\n");
 775                 ret = -ENODEV;
 776                 goto wdt_done;
 777         }
 778
 779         res = wdt_io_res(ICH_RES_IO_TCO);
 780         res->start = base_addr + ACPIBASE_TCO_OFF;
 781         res->end = base_addr + ACPIBASE_TCO_END;
 782
 783         res = wdt_io_res(ICH_RES_IO_SMI);
 784         res->start = base_addr + ACPIBASE_SMI_OFF;
 785         res->end = base_addr + ACPIBASE_SMI_END;
 786
 787         lpc_ich_enable_acpi_space(dev);
 788
 789         /*
 790          * Get the Memory-Mapped GCS register. To get access to it
 791          * we have to read RCBA from PCI Config space 0xf0 and use
 792          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
 793          */
 794         if (lpc_chipset_info[id->driver_data].iTCO_version == 2) {
 795                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
 796                 base_addr = base_addr_cfg & 0xffffc000;
 797                 if (!(base_addr_cfg & 1)) {
 798                         pr_err("RCBA is disabled by hardware/BIOS, "
 799                                         "device disabled\n");
 800                         ret = -ENODEV;
 801                         goto wdt_done;
 802                 }
 803                 res = wdt_mem_res(ICH_RES_MEM_GCS);
 804                 res->start = base_addr + ACPIBASE_GCS_OFF;
 805                 res->end = base_addr + ACPIBASE_GCS_END;
 806         }
 807
 808         lpc_ich_finalize_cell(&lpc_ich_cells[LPC_WDT], id);
 809         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
 810                               1, NULL, 0, NULL);
 811
 812 wdt_done:
 813         return ret;
 814 }
 815
 816 static int __devinit lpc_ich_probe(struct pci_dev *dev,
 817                                 const struct pci_device_id *id)
 818 {
 819         int ret;
 820         bool cell_added = false;
 821
 822         ret = lpc_ich_init_wdt(dev, id);
 823         if (!ret)
 824                 cell_added = true;
 825
 826         ret = lpc_ich_init_gpio(dev, id);
 827         if (!ret)
 828                 cell_added = true;
 829
 830         /*
 831          * We only care if at least one or none of the cells registered
 832          * successfully.
 833          */
 834         if (!cell_added) {
 835                 lpc_ich_restore_config_space(dev);
 836                 return -ENODEV;
 837         }
 838
 839         return 0;
 840 }
 841
 842 static void __devexit lpc_ich_remove(struct pci_dev *dev)
 843 {
 844         mfd_remove_devices(&dev->dev);
 845         lpc_ich_restore_config_space(dev);
 846 }
 847
 848 static struct pci_driver lpc_ich_driver = {
 849         .name           = "lpc_ich",
 850         .id_table       = lpc_ich_ids,
 851         .probe          = lpc_ich_probe,
 852         .remove         = __devexit_p(lpc_ich_remove),
 853 };
 854
 855 static int __init lpc_ich_init(void)
 856 {
 857         return pci_register_driver(&lpc_ich_driver);
 858 }
 859
 860 static void __exit lpc_ich_exit(void)
 861 {
 862         pci_unregister_driver(&lpc_ich_driver);
 863 }
 864
 865 module_init(lpc_ich_init);
 866 module_exit(lpc_ich_exit);
 867
 868 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
 869 MODULE_DESCRIPTION("LPC interface for Intel ICH");
 870 MODULE_LICENSE("GPL");