drivers/mfd/mc13xxx-core.c

   1 /*
   2  * Copyright 2009-2010 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mutex.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/mfd/mc13xxx.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/regmap.h>
  25 #include <linux/err.h>
  26
  27 enum mc13xxx_id {
  28         MC13XXX_ID_MC13783,
  29         MC13XXX_ID_MC13892,
  30         MC13XXX_ID_INVALID,
  31 };
  32
  33 struct mc13xxx {
  34         struct regmap *regmap;
  35
  36         struct device *dev;
  37         enum mc13xxx_id ictype;
  38
  39         struct mutex lock;
  40         int irq;
  41         int flags;
  42
  43         irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
  44         void *irqdata[MC13XXX_NUM_IRQ];
  45
  46         int adcflags;
  47 };
  48
  49 #define MC13XXX_IRQSTAT0        0
  50 #define MC13XXX_IRQSTAT0_ADCDONEI       (1 << 0)
  51 #define MC13XXX_IRQSTAT0_ADCBISDONEI    (1 << 1)
  52 #define MC13XXX_IRQSTAT0_TSI            (1 << 2)
  53 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  54 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  55 #define MC13XXX_IRQSTAT0_CHGDETI        (1 << 6)
  56 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  57 #define MC13XXX_IRQSTAT0_CHGREVI        (1 << 8)
  58 #define MC13XXX_IRQSTAT0_CHGSHORTI      (1 << 9)
  59 #define MC13XXX_IRQSTAT0_CCCVI          (1 << 10)
  60 #define MC13XXX_IRQSTAT0_CHGCURRI       (1 << 11)
  61 #define MC13XXX_IRQSTAT0_BPONI          (1 << 12)
  62 #define MC13XXX_IRQSTAT0_LOBATLI        (1 << 13)
  63 #define MC13XXX_IRQSTAT0_LOBATHI        (1 << 14)
  64 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  65 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  66 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  67 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  68 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  69 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  70
  71 #define MC13XXX_IRQMASK0        1
  72 #define MC13XXX_IRQMASK0_ADCDONEM       MC13XXX_IRQSTAT0_ADCDONEI
  73 #define MC13XXX_IRQMASK0_ADCBISDONEM    MC13XXX_IRQSTAT0_ADCBISDONEI
  74 #define MC13XXX_IRQMASK0_TSM            MC13XXX_IRQSTAT0_TSI
  75 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  76 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  77 #define MC13XXX_IRQMASK0_CHGDETM        MC13XXX_IRQSTAT0_CHGDETI
  78 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  79 #define MC13XXX_IRQMASK0_CHGREVM        MC13XXX_IRQSTAT0_CHGREVI
  80 #define MC13XXX_IRQMASK0_CHGSHORTM      MC13XXX_IRQSTAT0_CHGSHORTI
  81 #define MC13XXX_IRQMASK0_CCCVM          MC13XXX_IRQSTAT0_CCCVI
  82 #define MC13XXX_IRQMASK0_CHGCURRM       MC13XXX_IRQSTAT0_CHGCURRI
  83 #define MC13XXX_IRQMASK0_BPONM          MC13XXX_IRQSTAT0_BPONI
  84 #define MC13XXX_IRQMASK0_LOBATLM        MC13XXX_IRQSTAT0_LOBATLI
  85 #define MC13XXX_IRQMASK0_LOBATHM        MC13XXX_IRQSTAT0_LOBATHI
  86 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  87 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  88 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  89 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  90 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  91 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  92
  93 #define MC13XXX_IRQSTAT1        3
  94 #define MC13XXX_IRQSTAT1_1HZI           (1 << 0)
  95 #define MC13XXX_IRQSTAT1_TODAI          (1 << 1)
  96 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  97 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  98 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  99 #define MC13XXX_IRQSTAT1_SYSRSTI        (1 << 6)
 100 #define MC13XXX_IRQSTAT1_RTCRSTI        (1 << 7)
 101 #define MC13XXX_IRQSTAT1_PCI            (1 << 8)
 102 #define MC13XXX_IRQSTAT1_WARMI          (1 << 9)
 103 #define MC13XXX_IRQSTAT1_MEMHLDI        (1 << 10)
 104 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
 105 #define MC13XXX_IRQSTAT1_THWARNLI       (1 << 12)
 106 #define MC13XXX_IRQSTAT1_THWARNHI       (1 << 13)
 107 #define MC13XXX_IRQSTAT1_CLKI           (1 << 14)
 108 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
 109 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
 110 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
 111 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
 112 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
 113 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
 114
 115 #define MC13XXX_IRQMASK1        4
 116 #define MC13XXX_IRQMASK1_1HZM           MC13XXX_IRQSTAT1_1HZI
 117 #define MC13XXX_IRQMASK1_TODAM          MC13XXX_IRQSTAT1_TODAI
 118 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
 119 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
 120 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
 121 #define MC13XXX_IRQMASK1_SYSRSTM        MC13XXX_IRQSTAT1_SYSRSTI
 122 #define MC13XXX_IRQMASK1_RTCRSTM        MC13XXX_IRQSTAT1_RTCRSTI
 123 #define MC13XXX_IRQMASK1_PCM            MC13XXX_IRQSTAT1_PCI
 124 #define MC13XXX_IRQMASK1_WARMM          MC13XXX_IRQSTAT1_WARMI
 125 #define MC13XXX_IRQMASK1_MEMHLDM        MC13XXX_IRQSTAT1_MEMHLDI
 126 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
 127 #define MC13XXX_IRQMASK1_THWARNLM       MC13XXX_IRQSTAT1_THWARNLI
 128 #define MC13XXX_IRQMASK1_THWARNHM       MC13XXX_IRQSTAT1_THWARNHI
 129 #define MC13XXX_IRQMASK1_CLKM           MC13XXX_IRQSTAT1_CLKI
 130 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
 131 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 132 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 133 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 134 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 135 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 136
 137 #define MC13XXX_REVISION        7
 138 #define MC13XXX_REVISION_REVMETAL       (0x07 <<  0)
 139 #define MC13XXX_REVISION_REVFULL        (0x03 <<  3)
 140 #define MC13XXX_REVISION_ICID           (0x07 <<  6)
 141 #define MC13XXX_REVISION_FIN            (0x03 <<  9)
 142 #define MC13XXX_REVISION_FAB            (0x03 << 11)
 143 #define MC13XXX_REVISION_ICIDCODE       (0x3f << 13)
 144
 145 #define MC13XXX_ADC1            44
 146 #define MC13XXX_ADC1_ADEN               (1 << 0)
 147 #define MC13XXX_ADC1_RAND               (1 << 1)
 148 #define MC13XXX_ADC1_ADSEL              (1 << 3)
 149 #define MC13XXX_ADC1_ASC                (1 << 20)
 150 #define MC13XXX_ADC1_ADTRIGIGN          (1 << 21)
 151
 152 #define MC13XXX_ADC2            45
 153
 154 #define MC13XXX_NUMREGS 0x3f
 155
 156 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 157 {
 158         if (!mutex_trylock(&mc13xxx->lock)) {
 159                 dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 160                                 __func__, __builtin_return_address(0));
 161
 162                 mutex_lock(&mc13xxx->lock);
 163         }
 164         dev_dbg(mc13xxx->dev, "%s from %pf\n",
 165                         __func__, __builtin_return_address(0));
 166 }
 167 EXPORT_SYMBOL(mc13xxx_lock);
 168
 169 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 170 {
 171         dev_dbg(mc13xxx->dev, "%s from %pf\n",
 172                         __func__, __builtin_return_address(0));
 173         mutex_unlock(&mc13xxx->lock);
 174 }
 175 EXPORT_SYMBOL(mc13xxx_unlock);
 176
 177 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 178 {
 179         int ret;
 180
 181         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 182
 183         if (offset > MC13XXX_NUMREGS)
 184                 return -EINVAL;
 185
 186         ret = regmap_read(mc13xxx->regmap, offset, val);
 187         dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 188
 189         return ret;
 190 }
 191 EXPORT_SYMBOL(mc13xxx_reg_read);
 192
 193 int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 194 {
 195         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 196
 197         dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 198
 199         if (offset > MC13XXX_NUMREGS || val > 0xffffff)
 200                 return -EINVAL;
 201
 202         return regmap_write(mc13xxx->regmap, offset, val);
 203 }
 204 EXPORT_SYMBOL(mc13xxx_reg_write);
 205
 206 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 207                 u32 mask, u32 val)
 208 {
 209         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 210         BUG_ON(val & ~mask);
 211         dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
 212                         offset, val, mask);
 213
 214         return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
 215 }
 216 EXPORT_SYMBOL(mc13xxx_reg_rmw);
 217
 218 int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
 219 {
 220         int ret;
 221         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 222         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 223         u32 mask;
 224
 225         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 226                 return -EINVAL;
 227
 228         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 229         if (ret)
 230                 return ret;
 231
 232         if (mask & irqbit)
 233                 /* already masked */
 234                 return 0;
 235
 236         return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
 237 }
 238 EXPORT_SYMBOL(mc13xxx_irq_mask);
 239
 240 int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
 241 {
 242         int ret;
 243         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 244         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 245         u32 mask;
 246
 247         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 248                 return -EINVAL;
 249
 250         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 251         if (ret)
 252                 return ret;
 253
 254         if (!(mask & irqbit))
 255                 /* already unmasked */
 256                 return 0;
 257
 258         return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
 259 }
 260 EXPORT_SYMBOL(mc13xxx_irq_unmask);
 261
 262 int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
 263                 int *enabled, int *pending)
 264 {
 265         int ret;
 266         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 267         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 268         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 269
 270         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 271                 return -EINVAL;
 272
 273         if (enabled) {
 274                 u32 mask;
 275
 276                 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 277                 if (ret)
 278                         return ret;
 279
 280                 *enabled = mask & irqbit;
 281         }
 282
 283         if (pending) {
 284                 u32 stat;
 285
 286                 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 287                 if (ret)
 288                         return ret;
 289
 290                 *pending = stat & irqbit;
 291         }
 292
 293         return 0;
 294 }
 295 EXPORT_SYMBOL(mc13xxx_irq_status);
 296
 297 int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
 298 {
 299         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 300         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 301
 302         BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
 303
 304         return mc13xxx_reg_write(mc13xxx, offstat, val);
 305 }
 306 EXPORT_SYMBOL(mc13xxx_irq_ack);
 307
 308 int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
 309                 irq_handler_t handler, const char *name, void *dev)
 310 {
 311         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 312         BUG_ON(!handler);
 313
 314         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 315                 return -EINVAL;
 316
 317         if (mc13xxx->irqhandler[irq])
 318                 return -EBUSY;
 319
 320         mc13xxx->irqhandler[irq] = handler;
 321         mc13xxx->irqdata[irq] = dev;
 322
 323         return 0;
 324 }
 325 EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
 326
 327 int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
 328                 irq_handler_t handler, const char *name, void *dev)
 329 {
 330         int ret;
 331
 332         ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
 333         if (ret)
 334                 return ret;
 335
 336         ret = mc13xxx_irq_unmask(mc13xxx, irq);
 337         if (ret) {
 338                 mc13xxx->irqhandler[irq] = NULL;
 339                 mc13xxx->irqdata[irq] = NULL;
 340                 return ret;
 341         }
 342
 343         return 0;
 344 }
 345 EXPORT_SYMBOL(mc13xxx_irq_request);
 346
 347 int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
 348 {
 349         int ret;
 350         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 351
 352         if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
 353                         mc13xxx->irqdata[irq] != dev)
 354                 return -EINVAL;
 355
 356         ret = mc13xxx_irq_mask(mc13xxx, irq);
 357         if (ret)
 358                 return ret;
 359
 360         mc13xxx->irqhandler[irq] = NULL;
 361         mc13xxx->irqdata[irq] = NULL;
 362
 363         return 0;
 364 }
 365 EXPORT_SYMBOL(mc13xxx_irq_free);
 366
 367 static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
 368 {
 369         return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
 370 }
 371
 372 /*
 373  * returns: number of handled irqs or negative error
 374  * locking: holds mc13xxx->lock
 375  */
 376 static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 377                 unsigned int offstat, unsigned int offmask, int baseirq)
 378 {
 379         u32 stat, mask;
 380         int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 381         int num_handled = 0;
 382
 383         if (ret)
 384                 return ret;
 385
 386         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 387         if (ret)
 388                 return ret;
 389
 390         while (stat & ~mask) {
 391                 int irq = __ffs(stat & ~mask);
 392
 393                 stat &= ~(1 << irq);
 394
 395                 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
 396                         irqreturn_t handled;
 397
 398                         handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
 399                         if (handled == IRQ_HANDLED)
 400                                 num_handled++;
 401                 } else {
 402                         dev_err(mc13xxx->dev,
 403                                         "BUG: irq %u but no handler\n",
 404                                         baseirq + irq);
 405
 406                         mask |= 1 << irq;
 407
 408                         ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
 409                 }
 410         }
 411
 412         return num_handled;
 413 }
 414
 415 static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 416 {
 417         struct mc13xxx *mc13xxx = data;
 418         irqreturn_t ret;
 419         int handled = 0;
 420
 421         mc13xxx_lock(mc13xxx);
 422
 423         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
 424                         MC13XXX_IRQMASK0, 0);
 425         if (ret > 0)
 426                 handled = 1;
 427
 428         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
 429                         MC13XXX_IRQMASK1, 24);
 430         if (ret > 0)
 431                 handled = 1;
 432
 433         mc13xxx_unlock(mc13xxx);
 434
 435         return IRQ_RETVAL(handled);
 436 }
 437
 438 static const char *mc13xxx_chipname[] = {
 439         [MC13XXX_ID_MC13783] = "mc13783",
 440         [MC13XXX_ID_MC13892] = "mc13892",
 441 };
 442
 443 #define maskval(reg, mask)      (((reg) & (mask)) >> __ffs(mask))
 444 static int mc13xxx_identify(struct mc13xxx *mc13xxx)
 445 {
 446         u32 icid;
 447         u32 revision;
 448         int ret;
 449
 450         /*
 451          * Get the generation ID from register 46, as apparently some older
 452          * IC revisions only have this info at this location. Newer ICs seem to
 453          * have both.
 454          */
 455         ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
 456         if (ret)
 457                 return ret;
 458
 459         icid = (icid >> 6) & 0x7;
 460
 461         switch (icid) {
 462         case 2:
 463                 mc13xxx->ictype = MC13XXX_ID_MC13783;
 464                 break;
 465         case 7:
 466                 mc13xxx->ictype = MC13XXX_ID_MC13892;
 467                 break;
 468         default:
 469                 mc13xxx->ictype = MC13XXX_ID_INVALID;
 470                 break;
 471         }
 472
 473         if (mc13xxx->ictype == MC13XXX_ID_MC13783 ||
 474                         mc13xxx->ictype == MC13XXX_ID_MC13892) {
 475                 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
 476
 477                 dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 478                                 "fin: %d, fab: %d, icid: %d/%d\n",
 479                                 mc13xxx_chipname[mc13xxx->ictype],
 480                                 maskval(revision, MC13XXX_REVISION_REVFULL),
 481                                 maskval(revision, MC13XXX_REVISION_REVMETAL),
 482                                 maskval(revision, MC13XXX_REVISION_FIN),
 483                                 maskval(revision, MC13XXX_REVISION_FAB),
 484                                 maskval(revision, MC13XXX_REVISION_ICID),
 485                                 maskval(revision, MC13XXX_REVISION_ICIDCODE));
 486         }
 487
 488         return (mc13xxx->ictype == MC13XXX_ID_INVALID) ? -ENODEV : 0;
 489 }
 490
 491 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 492 {
 493         return mc13xxx_chipname[mc13xxx->ictype];
 494 }
 495
 496 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
 497 {
 498         return mc13xxx->flags;
 499 }
 500 EXPORT_SYMBOL(mc13xxx_get_flags);
 501
 502 #define MC13XXX_ADC1_CHAN0_SHIFT        5
 503 #define MC13XXX_ADC1_CHAN1_SHIFT        8
 504 #define MC13783_ADC1_ATO_SHIFT          11
 505 #define MC13783_ADC1_ATOX               (1 << 19)
 506
 507 struct mc13xxx_adcdone_data {
 508         struct mc13xxx *mc13xxx;
 509         struct completion done;
 510 };
 511
 512 static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
 513 {
 514         struct mc13xxx_adcdone_data *adcdone_data = data;
 515
 516         mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
 517
 518         complete_all(&adcdone_data->done);
 519
 520         return IRQ_HANDLED;
 521 }
 522
 523 #define MC13XXX_ADC_WORKING (1 << 0)
 524
 525 int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 526                 unsigned int channel, u8 ato, bool atox,
 527                 unsigned int *sample)
 528 {
 529         u32 adc0, adc1, old_adc0;
 530         int i, ret;
 531         struct mc13xxx_adcdone_data adcdone_data = {
 532                 .mc13xxx = mc13xxx,
 533         };
 534         init_completion(&adcdone_data.done);
 535
 536         dev_dbg(mc13xxx->dev, "%s\n", __func__);
 537
 538         mc13xxx_lock(mc13xxx);
 539
 540         if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
 541                 ret = -EBUSY;
 542                 goto out;
 543         }
 544
 545         mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
 546
 547         mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
 548
 549         adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
 550         adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
 551
 552         if (channel > 7)
 553                 adc1 |= MC13XXX_ADC1_ADSEL;
 554
 555         switch (mode) {
 556         case MC13XXX_ADC_MODE_TS:
 557                 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
 558                         MC13XXX_ADC0_TSMOD1;
 559                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 560                 break;
 561
 562         case MC13XXX_ADC_MODE_SINGLE_CHAN:
 563                 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 564                 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
 565                 adc1 |= MC13XXX_ADC1_RAND;
 566                 break;
 567
 568         case MC13XXX_ADC_MODE_MULT_CHAN:
 569                 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 570                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 571                 break;
 572
 573         default:
 574                 mc13xxx_unlock(mc13xxx);
 575                 return -EINVAL;
 576         }
 577
 578         adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
 579         if (atox)
 580                 adc1 |= MC13783_ADC1_ATOX;
 581
 582         dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 583         mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 584                         mc13xxx_handler_adcdone, __func__, &adcdone_data);
 585         mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
 586
 587         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
 588         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
 589
 590         mc13xxx_unlock(mc13xxx);
 591
 592         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 593
 594         if (!ret)
 595                 ret = -ETIMEDOUT;
 596
 597         mc13xxx_lock(mc13xxx);
 598
 599         mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
 600
 601         if (ret > 0)
 602                 for (i = 0; i < 4; ++i) {
 603                         ret = mc13xxx_reg_read(mc13xxx,
 604                                         MC13XXX_ADC2, &sample[i]);
 605                         if (ret)
 606                                 break;
 607                 }
 608
 609         if (mode == MC13XXX_ADC_MODE_TS)
 610                 /* restore TSMOD */
 611                 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
 612
 613         mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
 614 out:
 615         mc13xxx_unlock(mc13xxx);
 616
 617         return ret;
 618 }
 619 EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
 620
 621 static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 622                 const char *format, void *pdata, size_t pdata_size)
 623 {
 624         char buf[30];
 625         const char *name = mc13xxx_get_chipname(mc13xxx);
 626
 627         struct mfd_cell cell = {
 628                 .platform_data = pdata,
 629                 .pdata_size = pdata_size,
 630         };
 631
 632         /* there is no asnprintf in the kernel :-( */
 633         if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
 634                 return -E2BIG;
 635
 636         cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
 637         if (!cell.name)
 638                 return -ENOMEM;
 639
 640         return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0);
 641 }
 642
 643 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 644 {
 645         return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
 646 }
 647
 648 #ifdef CONFIG_OF
 649 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 650 {
 651         struct device_node *np = mc13xxx->dev->of_node;
 652
 653         if (!np)
 654                 return -ENODEV;
 655
 656         if (of_get_property(np, "fsl,mc13xxx-uses-adc", NULL))
 657                 mc13xxx->flags |= MC13XXX_USE_ADC;
 658
 659         if (of_get_property(np, "fsl,mc13xxx-uses-codec", NULL))
 660                 mc13xxx->flags |= MC13XXX_USE_CODEC;
 661
 662         if (of_get_property(np, "fsl,mc13xxx-uses-rtc", NULL))
 663                 mc13xxx->flags |= MC13XXX_USE_RTC;
 664
 665         if (of_get_property(np, "fsl,mc13xxx-uses-touch", NULL))
 666                 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
 667
 668         return 0;
 669 }
 670 #else
 671 static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 672 {
 673         return -ENODEV;
 674 }
 675 #endif
 676
 677 static const struct spi_device_id mc13xxx_device_id[] = {
 678         {
 679                 .name = "mc13783",
 680                 .driver_data = MC13XXX_ID_MC13783,
 681         }, {
 682                 .name = "mc13892",
 683                 .driver_data = MC13XXX_ID_MC13892,
 684         }, {
 685                 /* sentinel */
 686         }
 687 };
 688 MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
 689
 690 static const struct of_device_id mc13xxx_dt_ids[] = {
 691         { .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
 692         { .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
 693         { /* sentinel */ }
 694 };
 695 MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
 696
 697 static struct regmap_config mc13xxx_regmap_spi_config = {
 698         .reg_bits = 7,
 699         .pad_bits = 1,
 700         .val_bits = 24,
 701
 702         .max_register = MC13XXX_NUMREGS,
 703
 704         .cache_type = REGCACHE_NONE,
 705 };
 706
 707 static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 708                 struct mc13xxx_platform_data *pdata, int irq);
 709
 710 static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
 711
 712 static int mc13xxx_spi_probe(struct spi_device *spi)
 713 {
 714         const struct of_device_id *of_id;
 715         struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
 716         struct mc13xxx *mc13xxx;
 717         struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
 718         int ret;
 719
 720         of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
 721         if (of_id)
 722                 sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
 723
 724         mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
 725         if (!mc13xxx)
 726                 return -ENOMEM;
 727
 728         dev_set_drvdata(&spi->dev, mc13xxx);
 729         spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 730         spi->bits_per_word = 32;
 731
 732         mc13xxx->dev = &spi->dev;
 733         mutex_init(&mc13xxx->lock);
 734
 735         mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
 736         if (IS_ERR(mc13xxx->regmap)) {
 737                 ret = PTR_ERR(mc13xxx->regmap);
 738                 dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
 739                                 ret);
 740                 dev_set_drvdata(&spi->dev, NULL);
 741                 kfree(mc13xxx);
 742                 return ret;
 743         }
 744
 745         ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
 746
 747         if (ret) {
 748                 dev_set_drvdata(&spi->dev, NULL);
 749         } else {
 750                 const struct spi_device_id *devid =
 751                         spi_get_device_id(spi);
 752                 if (!devid || devid->driver_data != mc13xxx->ictype)
 753                         dev_warn(mc13xxx->dev,
 754                                 "device id doesn't match auto detection!\n");
 755         }
 756
 757         return ret;
 758 }
 759
 760 static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 761                 struct mc13xxx_platform_data *pdata, int irq)
 762 {
 763         int ret;
 764
 765         mc13xxx_lock(mc13xxx);
 766
 767         ret = mc13xxx_identify(mc13xxx);
 768         if (ret)
 769                 goto err_revision;
 770
 771         /* mask all irqs */
 772         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
 773         if (ret)
 774                 goto err_mask;
 775
 776         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
 777         if (ret)
 778                 goto err_mask;
 779
 780         ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
 781                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 782
 783         if (ret) {
 784 err_mask:
 785 err_revision:
 786                 mc13xxx_unlock(mc13xxx);
 787                 kfree(mc13xxx);
 788                 return ret;
 789         }
 790
 791         mc13xxx->irq = irq;
 792
 793         mc13xxx_unlock(mc13xxx);
 794
 795         if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
 796                 mc13xxx->flags = pdata->flags;
 797
 798         if (mc13xxx->flags & MC13XXX_USE_ADC)
 799                 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
 800
 801         if (mc13xxx->flags & MC13XXX_USE_CODEC)
 802                 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
 803
 804         if (mc13xxx->flags & MC13XXX_USE_RTC)
 805                 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
 806
 807         if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
 808                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
 809                                 &pdata->touch, sizeof(pdata->touch));
 810
 811         if (pdata) {
 812                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
 813                         &pdata->regulators, sizeof(pdata->regulators));
 814                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
 815                                 pdata->leds, sizeof(*pdata->leds));
 816                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
 817                                 pdata->buttons, sizeof(*pdata->buttons));
 818         } else {
 819                 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
 820                 mc13xxx_add_subdevice(mc13xxx, "%s-led");
 821                 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
 822         }
 823
 824         return 0;
 825 }
 826
 827 static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
 828 {
 829         struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
 830
 831         mc13xxx_common_cleanup(mc13xxx);
 832
 833         return 0;
 834 }
 835
 836 static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 837 {
 838         free_irq(mc13xxx->irq, mc13xxx);
 839
 840         mfd_remove_devices(mc13xxx->dev);
 841
 842         regmap_exit(mc13xxx->regmap);
 843
 844         kfree(mc13xxx);
 845 }
 846
 847 static struct spi_driver mc13xxx_spi_driver = {
 848         .id_table = mc13xxx_device_id,
 849         .driver = {
 850                 .name = "mc13xxx",
 851                 .owner = THIS_MODULE,
 852                 .of_match_table = mc13xxx_dt_ids,
 853         },
 854         .probe = mc13xxx_spi_probe,
 855         .remove = __devexit_p(mc13xxx_spi_remove),
 856 };
 857
 858 static int __init mc13xxx_init(void)
 859 {
 860         return spi_register_driver(&mc13xxx_spi_driver);
 861 }
 862 subsys_initcall(mc13xxx_init);
 863
 864 static void __exit mc13xxx_exit(void)
 865 {
 866         spi_unregister_driver(&mc13xxx_spi_driver);
 867 }
 868 module_exit(mc13xxx_exit);
 869
 870 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 871 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 872 MODULE_LICENSE("GPL v2");