drivers/mfd/mc13xxx-core.c

   1 /*
   2  * Copyright 2009-2010 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mutex.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/mfd/mc13xxx.h>
  21
  22 struct mc13xxx {
  23         struct spi_device *spidev;
  24         struct mutex lock;
  25         int irq;
  26
  27         irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
  28         void *irqdata[MC13XXX_NUM_IRQ];
  29
  30         int adcflags;
  31 };
  32
  33 #define MC13XXX_IRQSTAT0        0
  34 #define MC13XXX_IRQSTAT0_ADCDONEI       (1 << 0)
  35 #define MC13XXX_IRQSTAT0_ADCBISDONEI    (1 << 1)
  36 #define MC13XXX_IRQSTAT0_TSI            (1 << 2)
  37 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  38 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  39 #define MC13XXX_IRQSTAT0_CHGDETI        (1 << 6)
  40 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  41 #define MC13XXX_IRQSTAT0_CHGREVI        (1 << 8)
  42 #define MC13XXX_IRQSTAT0_CHGSHORTI      (1 << 9)
  43 #define MC13XXX_IRQSTAT0_CCCVI          (1 << 10)
  44 #define MC13XXX_IRQSTAT0_CHGCURRI       (1 << 11)
  45 #define MC13XXX_IRQSTAT0_BPONI          (1 << 12)
  46 #define MC13XXX_IRQSTAT0_LOBATLI        (1 << 13)
  47 #define MC13XXX_IRQSTAT0_LOBATHI        (1 << 14)
  48 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  49 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  50 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  51 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  52 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  53 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  54
  55 #define MC13XXX_IRQMASK0        1
  56 #define MC13XXX_IRQMASK0_ADCDONEM       MC13XXX_IRQSTAT0_ADCDONEI
  57 #define MC13XXX_IRQMASK0_ADCBISDONEM    MC13XXX_IRQSTAT0_ADCBISDONEI
  58 #define MC13XXX_IRQMASK0_TSM            MC13XXX_IRQSTAT0_TSI
  59 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  60 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  61 #define MC13XXX_IRQMASK0_CHGDETM        MC13XXX_IRQSTAT0_CHGDETI
  62 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  63 #define MC13XXX_IRQMASK0_CHGREVM        MC13XXX_IRQSTAT0_CHGREVI
  64 #define MC13XXX_IRQMASK0_CHGSHORTM      MC13XXX_IRQSTAT0_CHGSHORTI
  65 #define MC13XXX_IRQMASK0_CCCVM          MC13XXX_IRQSTAT0_CCCVI
  66 #define MC13XXX_IRQMASK0_CHGCURRM       MC13XXX_IRQSTAT0_CHGCURRI
  67 #define MC13XXX_IRQMASK0_BPONM          MC13XXX_IRQSTAT0_BPONI
  68 #define MC13XXX_IRQMASK0_LOBATLM        MC13XXX_IRQSTAT0_LOBATLI
  69 #define MC13XXX_IRQMASK0_LOBATHM        MC13XXX_IRQSTAT0_LOBATHI
  70 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  71 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  72 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  73 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  74 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  75 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  76
  77 #define MC13XXX_IRQSTAT1        3
  78 #define MC13XXX_IRQSTAT1_1HZI           (1 << 0)
  79 #define MC13XXX_IRQSTAT1_TODAI          (1 << 1)
  80 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  81 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  82 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  83 #define MC13XXX_IRQSTAT1_SYSRSTI        (1 << 6)
  84 #define MC13XXX_IRQSTAT1_RTCRSTI        (1 << 7)
  85 #define MC13XXX_IRQSTAT1_PCI            (1 << 8)
  86 #define MC13XXX_IRQSTAT1_WARMI          (1 << 9)
  87 #define MC13XXX_IRQSTAT1_MEMHLDI        (1 << 10)
  88 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  89 #define MC13XXX_IRQSTAT1_THWARNLI       (1 << 12)
  90 #define MC13XXX_IRQSTAT1_THWARNHI       (1 << 13)
  91 #define MC13XXX_IRQSTAT1_CLKI           (1 << 14)
  92 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
  93 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
  94 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
  95 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
  96 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
  97 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
  98
  99 #define MC13XXX_IRQMASK1        4
 100 #define MC13XXX_IRQMASK1_1HZM           MC13XXX_IRQSTAT1_1HZI
 101 #define MC13XXX_IRQMASK1_TODAM          MC13XXX_IRQSTAT1_TODAI
 102 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
 103 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
 104 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
 105 #define MC13XXX_IRQMASK1_SYSRSTM        MC13XXX_IRQSTAT1_SYSRSTI
 106 #define MC13XXX_IRQMASK1_RTCRSTM        MC13XXX_IRQSTAT1_RTCRSTI
 107 #define MC13XXX_IRQMASK1_PCM            MC13XXX_IRQSTAT1_PCI
 108 #define MC13XXX_IRQMASK1_WARMM          MC13XXX_IRQSTAT1_WARMI
 109 #define MC13XXX_IRQMASK1_MEMHLDM        MC13XXX_IRQSTAT1_MEMHLDI
 110 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
 111 #define MC13XXX_IRQMASK1_THWARNLM       MC13XXX_IRQSTAT1_THWARNLI
 112 #define MC13XXX_IRQMASK1_THWARNHM       MC13XXX_IRQSTAT1_THWARNHI
 113 #define MC13XXX_IRQMASK1_CLKM           MC13XXX_IRQSTAT1_CLKI
 114 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
 115 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 116 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 117 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 118 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 119 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 120
 121 #define MC13XXX_REVISION        7
 122 #define MC13XXX_REVISION_REVMETAL       (0x07 <<  0)
 123 #define MC13XXX_REVISION_REVFULL        (0x03 <<  3)
 124 #define MC13XXX_REVISION_ICID           (0x07 <<  6)
 125 #define MC13XXX_REVISION_FIN            (0x03 <<  9)
 126 #define MC13XXX_REVISION_FAB            (0x03 << 11)
 127 #define MC13XXX_REVISION_ICIDCODE       (0x3f << 13)
 128
 129 #define MC13XXX_ADC1            44
 130 #define MC13XXX_ADC1_ADEN               (1 << 0)
 131 #define MC13XXX_ADC1_RAND               (1 << 1)
 132 #define MC13XXX_ADC1_ADSEL              (1 << 3)
 133 #define MC13XXX_ADC1_ASC                (1 << 20)
 134 #define MC13XXX_ADC1_ADTRIGIGN          (1 << 21)
 135
 136 #define MC13XXX_ADC2            45
 137
 138 #define MC13XXX_NUMREGS 0x3f
 139
 140 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 141 {
 142         if (!mutex_trylock(&mc13xxx->lock)) {
 143                 dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
 144                                 __func__, __builtin_return_address(0));
 145
 146                 mutex_lock(&mc13xxx->lock);
 147         }
 148         dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
 149                         __func__, __builtin_return_address(0));
 150 }
 151 EXPORT_SYMBOL(mc13xxx_lock);
 152
 153 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 154 {
 155         dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
 156                         __func__, __builtin_return_address(0));
 157         mutex_unlock(&mc13xxx->lock);
 158 }
 159 EXPORT_SYMBOL(mc13xxx_unlock);
 160
 161 #define MC13XXX_REGOFFSET_SHIFT 25
 162 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 163 {
 164         struct spi_transfer t;
 165         struct spi_message m;
 166         int ret;
 167
 168         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 169
 170         if (offset > MC13XXX_NUMREGS)
 171                 return -EINVAL;
 172
 173         *val = offset << MC13XXX_REGOFFSET_SHIFT;
 174
 175         memset(&t, 0, sizeof(t));
 176
 177         t.tx_buf = val;
 178         t.rx_buf = val;
 179         t.len = sizeof(u32);
 180
 181         spi_message_init(&m);
 182         spi_message_add_tail(&t, &m);
 183
 184         ret = spi_sync(mc13xxx->spidev, &m);
 185
 186         /* error in message.status implies error return from spi_sync */
 187         BUG_ON(!ret && m.status);
 188
 189         if (ret)
 190                 return ret;
 191
 192         *val &= 0xffffff;
 193
 194         dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 195
 196         return 0;
 197 }
 198 EXPORT_SYMBOL(mc13xxx_reg_read);
 199
 200 int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 201 {
 202         u32 buf;
 203         struct spi_transfer t;
 204         struct spi_message m;
 205         int ret;
 206
 207         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 208
 209         dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 210
 211         if (offset > MC13XXX_NUMREGS || val > 0xffffff)
 212                 return -EINVAL;
 213
 214         buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
 215
 216         memset(&t, 0, sizeof(t));
 217
 218         t.tx_buf = &buf;
 219         t.rx_buf = &buf;
 220         t.len = sizeof(u32);
 221
 222         spi_message_init(&m);
 223         spi_message_add_tail(&t, &m);
 224
 225         ret = spi_sync(mc13xxx->spidev, &m);
 226
 227         BUG_ON(!ret && m.status);
 228
 229         if (ret)
 230                 return ret;
 231
 232         return 0;
 233 }
 234 EXPORT_SYMBOL(mc13xxx_reg_write);
 235
 236 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 237                 u32 mask, u32 val)
 238 {
 239         int ret;
 240         u32 valread;
 241
 242         BUG_ON(val & ~mask);
 243
 244         ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
 245         if (ret)
 246                 return ret;
 247
 248         valread = (valread & ~mask) | val;
 249
 250         return mc13xxx_reg_write(mc13xxx, offset, valread);
 251 }
 252 EXPORT_SYMBOL(mc13xxx_reg_rmw);
 253
 254 int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
 255 {
 256         int ret;
 257         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 258         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 259         u32 mask;
 260
 261         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 262                 return -EINVAL;
 263
 264         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 265         if (ret)
 266                 return ret;
 267
 268         if (mask & irqbit)
 269                 /* already masked */
 270                 return 0;
 271
 272         return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
 273 }
 274 EXPORT_SYMBOL(mc13xxx_irq_mask);
 275
 276 int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
 277 {
 278         int ret;
 279         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 280         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 281         u32 mask;
 282
 283         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 284                 return -EINVAL;
 285
 286         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 287         if (ret)
 288                 return ret;
 289
 290         if (!(mask & irqbit))
 291                 /* already unmasked */
 292                 return 0;
 293
 294         return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
 295 }
 296 EXPORT_SYMBOL(mc13xxx_irq_unmask);
 297
 298 int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
 299                 int *enabled, int *pending)
 300 {
 301         int ret;
 302         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 303         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 304         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 305
 306         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 307                 return -EINVAL;
 308
 309         if (enabled) {
 310                 u32 mask;
 311
 312                 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 313                 if (ret)
 314                         return ret;
 315
 316                 *enabled = mask & irqbit;
 317         }
 318
 319         if (pending) {
 320                 u32 stat;
 321
 322                 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 323                 if (ret)
 324                         return ret;
 325
 326                 *pending = stat & irqbit;
 327         }
 328
 329         return 0;
 330 }
 331 EXPORT_SYMBOL(mc13xxx_irq_status);
 332
 333 int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
 334 {
 335         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 336         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 337
 338         BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
 339
 340         return mc13xxx_reg_write(mc13xxx, offstat, val);
 341 }
 342 EXPORT_SYMBOL(mc13xxx_irq_ack);
 343
 344 int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
 345                 irq_handler_t handler, const char *name, void *dev)
 346 {
 347         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 348         BUG_ON(!handler);
 349
 350         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 351                 return -EINVAL;
 352
 353         if (mc13xxx->irqhandler[irq])
 354                 return -EBUSY;
 355
 356         mc13xxx->irqhandler[irq] = handler;
 357         mc13xxx->irqdata[irq] = dev;
 358
 359         return 0;
 360 }
 361 EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
 362
 363 int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
 364                 irq_handler_t handler, const char *name, void *dev)
 365 {
 366         int ret;
 367
 368         ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
 369         if (ret)
 370                 return ret;
 371
 372         ret = mc13xxx_irq_unmask(mc13xxx, irq);
 373         if (ret) {
 374                 mc13xxx->irqhandler[irq] = NULL;
 375                 mc13xxx->irqdata[irq] = NULL;
 376                 return ret;
 377         }
 378
 379         return 0;
 380 }
 381 EXPORT_SYMBOL(mc13xxx_irq_request);
 382
 383 int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
 384 {
 385         int ret;
 386         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 387
 388         if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
 389                         mc13xxx->irqdata[irq] != dev)
 390                 return -EINVAL;
 391
 392         ret = mc13xxx_irq_mask(mc13xxx, irq);
 393         if (ret)
 394                 return ret;
 395
 396         mc13xxx->irqhandler[irq] = NULL;
 397         mc13xxx->irqdata[irq] = NULL;
 398
 399         return 0;
 400 }
 401 EXPORT_SYMBOL(mc13xxx_irq_free);
 402
 403 static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
 404 {
 405         return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
 406 }
 407
 408 /*
 409  * returns: number of handled irqs or negative error
 410  * locking: holds mc13xxx->lock
 411  */
 412 static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 413                 unsigned int offstat, unsigned int offmask, int baseirq)
 414 {
 415         u32 stat, mask;
 416         int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 417         int num_handled = 0;
 418
 419         if (ret)
 420                 return ret;
 421
 422         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 423         if (ret)
 424                 return ret;
 425
 426         while (stat & ~mask) {
 427                 int irq = __ffs(stat & ~mask);
 428
 429                 stat &= ~(1 << irq);
 430
 431                 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
 432                         irqreturn_t handled;
 433
 434                         handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
 435                         if (handled == IRQ_HANDLED)
 436                                 num_handled++;
 437                 } else {
 438                         dev_err(&mc13xxx->spidev->dev,
 439                                         "BUG: irq %u but no handler\n",
 440                                         baseirq + irq);
 441
 442                         mask |= 1 << irq;
 443
 444                         ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
 445                 }
 446         }
 447
 448         return num_handled;
 449 }
 450
 451 static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 452 {
 453         struct mc13xxx *mc13xxx = data;
 454         irqreturn_t ret;
 455         int handled = 0;
 456
 457         mc13xxx_lock(mc13xxx);
 458
 459         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
 460                         MC13XXX_IRQMASK0, 0);
 461         if (ret > 0)
 462                 handled = 1;
 463
 464         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
 465                         MC13XXX_IRQMASK1, 24);
 466         if (ret > 0)
 467                 handled = 1;
 468
 469         mc13xxx_unlock(mc13xxx);
 470
 471         return IRQ_RETVAL(handled);
 472 }
 473
 474 enum mc13xxx_id {
 475         MC13XXX_ID_MC13783,
 476         MC13XXX_ID_MC13892,
 477         MC13XXX_ID_INVALID,
 478 };
 479
 480 static const char *mc13xxx_chipname[] = {
 481         [MC13XXX_ID_MC13783] = "mc13783",
 482         [MC13XXX_ID_MC13892] = "mc13892",
 483 };
 484
 485 #define maskval(reg, mask)      (((reg) & (mask)) >> __ffs(mask))
 486 static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 487 {
 488         u32 icid;
 489         u32 revision;
 490         const char *name;
 491         int ret;
 492
 493         ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
 494         if (ret)
 495                 return ret;
 496
 497         icid = (icid >> 6) & 0x7;
 498
 499         switch (icid) {
 500         case 2:
 501                 *id = MC13XXX_ID_MC13783;
 502                 name = "mc13783";
 503                 break;
 504         case 7:
 505                 *id = MC13XXX_ID_MC13892;
 506                 name = "mc13892";
 507                 break;
 508         default:
 509                 *id = MC13XXX_ID_INVALID;
 510                 break;
 511         }
 512
 513         if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
 514                 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
 515                 if (ret)
 516                         return ret;
 517
 518                 dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
 519                                 "fin: %d, fab: %d, icid: %d/%d\n",
 520                                 mc13xxx_chipname[*id],
 521                                 maskval(revision, MC13XXX_REVISION_REVFULL),
 522                                 maskval(revision, MC13XXX_REVISION_REVMETAL),
 523                                 maskval(revision, MC13XXX_REVISION_FIN),
 524                                 maskval(revision, MC13XXX_REVISION_FAB),
 525                                 maskval(revision, MC13XXX_REVISION_ICID),
 526                                 maskval(revision, MC13XXX_REVISION_ICIDCODE));
 527         }
 528
 529         if (*id != MC13XXX_ID_INVALID) {
 530                 const struct spi_device_id *devid =
 531                         spi_get_device_id(mc13xxx->spidev);
 532                 if (!devid || devid->driver_data != *id)
 533                         dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
 534                                         "match auto detection!\n");
 535         }
 536
 537         return 0;
 538 }
 539
 540 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 541 {
 542         const struct spi_device_id *devid =
 543                 spi_get_device_id(mc13xxx->spidev);
 544
 545         if (!devid)
 546                 return NULL;
 547
 548         return mc13xxx_chipname[devid->driver_data];
 549 }
 550
 551 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
 552 {
 553         struct mc13xxx_platform_data *pdata =
 554                 dev_get_platdata(&mc13xxx->spidev->dev);
 555
 556         return pdata->flags;
 557 }
 558 EXPORT_SYMBOL(mc13xxx_get_flags);
 559
 560 #define MC13XXX_ADC1_CHAN0_SHIFT        5
 561 #define MC13XXX_ADC1_CHAN1_SHIFT        8
 562
 563 struct mc13xxx_adcdone_data {
 564         struct mc13xxx *mc13xxx;
 565         struct completion done;
 566 };
 567
 568 static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
 569 {
 570         struct mc13xxx_adcdone_data *adcdone_data = data;
 571
 572         mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
 573
 574         complete_all(&adcdone_data->done);
 575
 576         return IRQ_HANDLED;
 577 }
 578
 579 #define MC13XXX_ADC_WORKING (1 << 0)
 580
 581 int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 582                 unsigned int channel, unsigned int *sample)
 583 {
 584         u32 adc0, adc1, old_adc0;
 585         int i, ret;
 586         struct mc13xxx_adcdone_data adcdone_data = {
 587                 .mc13xxx = mc13xxx,
 588         };
 589         init_completion(&adcdone_data.done);
 590
 591         dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
 592
 593         mc13xxx_lock(mc13xxx);
 594
 595         if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
 596                 ret = -EBUSY;
 597                 goto out;
 598         }
 599
 600         mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
 601
 602         mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
 603
 604         adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
 605         adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
 606
 607         if (channel > 7)
 608                 adc1 |= MC13XXX_ADC1_ADSEL;
 609
 610         switch (mode) {
 611         case MC13XXX_ADC_MODE_TS:
 612                 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
 613                         MC13XXX_ADC0_TSMOD1;
 614                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 615                 break;
 616
 617         case MC13XXX_ADC_MODE_SINGLE_CHAN:
 618                 adc0 |= old_adc0 & MC13XXX_ADC0_TSMOD_MASK;
 619                 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
 620                 adc1 |= MC13XXX_ADC1_RAND;
 621                 break;
 622
 623         case MC13XXX_ADC_MODE_MULT_CHAN:
 624                 adc0 |= old_adc0 & MC13XXX_ADC0_TSMOD_MASK;
 625                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 626                 break;
 627
 628         default:
 629                 mc13xxx_unlock(mc13xxx);
 630                 return -EINVAL;
 631         }
 632
 633         dev_dbg(&mc13xxx->spidev->dev, "%s: request irq\n", __func__);
 634         mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 635                         mc13xxx_handler_adcdone, __func__, &adcdone_data);
 636         mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
 637
 638         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
 639         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
 640
 641         mc13xxx_unlock(mc13xxx);
 642
 643         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 644
 645         if (!ret)
 646                 ret = -ETIMEDOUT;
 647
 648         mc13xxx_lock(mc13xxx);
 649
 650         mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
 651
 652         if (ret > 0)
 653                 for (i = 0; i < 4; ++i) {
 654                         ret = mc13xxx_reg_read(mc13xxx,
 655                                         MC13XXX_ADC2, &sample[i]);
 656                         if (ret)
 657                                 break;
 658                 }
 659
 660         if (mode == MC13XXX_ADC_MODE_TS)
 661                 /* restore TSMOD */
 662                 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
 663
 664         mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
 665 out:
 666         mc13xxx_unlock(mc13xxx);
 667
 668         return ret;
 669 }
 670 EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
 671
 672 static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 673                 const char *format, void *pdata, size_t pdata_size)
 674 {
 675         char buf[30];
 676         const char *name = mc13xxx_get_chipname(mc13xxx);
 677
 678         struct mfd_cell cell = {
 679                 .platform_data = pdata,
 680                 .pdata_size = pdata_size,
 681         };
 682
 683         /* there is no asnprintf in the kernel :-( */
 684         if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
 685                 return -E2BIG;
 686
 687         cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
 688         if (!cell.name)
 689                 return -ENOMEM;
 690
 691         return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
 692 }
 693
 694 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 695 {
 696         return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
 697 }
 698
 699 static int mc13xxx_probe(struct spi_device *spi)
 700 {
 701         struct mc13xxx *mc13xxx;
 702         struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
 703         enum mc13xxx_id id;
 704         int ret;
 705
 706         if (!pdata) {
 707                 dev_err(&spi->dev, "invalid platform data\n");
 708                 return -EINVAL;
 709         }
 710
 711         mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
 712         if (!mc13xxx)
 713                 return -ENOMEM;
 714
 715         dev_set_drvdata(&spi->dev, mc13xxx);
 716         spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 717         spi->bits_per_word = 32;
 718         spi_setup(spi);
 719
 720         mc13xxx->spidev = spi;
 721
 722         mutex_init(&mc13xxx->lock);
 723         mc13xxx_lock(mc13xxx);
 724
 725         ret = mc13xxx_identify(mc13xxx, &id);
 726         if (ret || id == MC13XXX_ID_INVALID)
 727                 goto err_revision;
 728
 729         /* mask all irqs */
 730         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
 731         if (ret)
 732                 goto err_mask;
 733
 734         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
 735         if (ret)
 736                 goto err_mask;
 737
 738         ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
 739                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 740
 741         if (ret) {
 742 err_mask:
 743 err_revision:
 744                 mc13xxx_unlock(mc13xxx);
 745                 dev_set_drvdata(&spi->dev, NULL);
 746                 kfree(mc13xxx);
 747                 return ret;
 748         }
 749
 750         mc13xxx_unlock(mc13xxx);
 751
 752         if (pdata->flags & MC13XXX_USE_ADC)
 753                 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
 754
 755         if (pdata->flags & MC13XXX_USE_CODEC)
 756                 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
 757
 758         mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
 759                 &pdata->regulators, sizeof(pdata->regulators));
 760
 761         if (pdata->flags & MC13XXX_USE_RTC)
 762                 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
 763
 764         if (pdata->flags & MC13XXX_USE_TOUCHSCREEN)
 765                 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
 766
 767         if (pdata->leds)
 768                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
 769                                 pdata->leds, sizeof(*pdata->leds));
 770
 771         if (pdata->buttons)
 772                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
 773                                 pdata->buttons, sizeof(*pdata->buttons));
 774
 775         return 0;
 776 }
 777
 778 static int __devexit mc13xxx_remove(struct spi_device *spi)
 779 {
 780         struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
 781
 782         free_irq(mc13xxx->spidev->irq, mc13xxx);
 783
 784         mfd_remove_devices(&spi->dev);
 785
 786         kfree(mc13xxx);
 787
 788         return 0;
 789 }
 790
 791 static const struct spi_device_id mc13xxx_device_id[] = {
 792         {
 793                 .name = "mc13783",
 794                 .driver_data = MC13XXX_ID_MC13783,
 795         }, {
 796                 .name = "mc13892",
 797                 .driver_data = MC13XXX_ID_MC13892,
 798         }, {
 799                 /* sentinel */
 800         }
 801 };
 802 MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
 803
 804 static struct spi_driver mc13xxx_driver = {
 805         .id_table = mc13xxx_device_id,
 806         .driver = {
 807                 .name = "mc13xxx",
 808                 .bus = &spi_bus_type,
 809                 .owner = THIS_MODULE,
 810         },
 811         .probe = mc13xxx_probe,
 812         .remove = __devexit_p(mc13xxx_remove),
 813 };
 814
 815 static int __init mc13xxx_init(void)
 816 {
 817         return spi_register_driver(&mc13xxx_driver);
 818 }
 819 subsys_initcall(mc13xxx_init);
 820
 821 static void __exit mc13xxx_exit(void)
 822 {
 823         spi_unregister_driver(&mc13xxx_driver);
 824 }
 825 module_exit(mc13xxx_exit);
 826
 827 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 828 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 829 MODULE_LICENSE("GPL v2");