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Merge tag 'clk-bulk-get-prep-enable' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / mfd / rtsx_pcr.c
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <linux/mmc/card.h>
34 #include <asm/unaligned.h>
35
36 #include "rtsx_pcr.h"
37
38 static bool msi_en = true;
39 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(msi_en, "Enable MSI");
41
42 static DEFINE_IDR(rtsx_pci_idr);
43 static DEFINE_SPINLOCK(rtsx_pci_lock);
44
45 static struct mfd_cell rtsx_pcr_cells[] = {
46 [RTSX_SD_CARD] = {
47 .name = DRV_NAME_RTSX_PCI_SDMMC,
48 },
49 [RTSX_MS_CARD] = {
50 .name = DRV_NAME_RTSX_PCI_MS,
51 },
52 };
53
54 static const struct pci_device_id rtsx_pci_ids[] = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
61 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
62 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
63 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
64 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
65 { 0, }
66 };
67
68 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
69
70 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
71 {
72 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
73 0xFC, pcr->aspm_en);
74 }
75
76 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
77 {
78 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
79 0xFC, 0);
80 }
81
82 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
83 {
84 /* If pci device removed, don't queue idle work any more */
85 if (pcr->remove_pci)
86 return;
87
88 if (pcr->state != PDEV_STAT_RUN) {
89 pcr->state = PDEV_STAT_RUN;
90 if (pcr->ops->enable_auto_blink)
91 pcr->ops->enable_auto_blink(pcr);
92
93 if (pcr->aspm_en)
94 rtsx_pci_disable_aspm(pcr);
95 }
96
97 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
98 }
99 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
100
101 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
102 {
103 int i;
104 u32 val = HAIMR_WRITE_START;
105
106 val |= (u32)(addr & 0x3FFF) << 16;
107 val |= (u32)mask << 8;
108 val |= (u32)data;
109
110 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
111
112 for (i = 0; i < MAX_RW_REG_CNT; i++) {
113 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
114 if ((val & HAIMR_TRANS_END) == 0) {
115 if (data != (u8)val)
116 return -EIO;
117 return 0;
118 }
119 }
120
121 return -ETIMEDOUT;
122 }
123 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
124
125 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
126 {
127 u32 val = HAIMR_READ_START;
128 int i;
129
130 val |= (u32)(addr & 0x3FFF) << 16;
131 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
132
133 for (i = 0; i < MAX_RW_REG_CNT; i++) {
134 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
135 if ((val & HAIMR_TRANS_END) == 0)
136 break;
137 }
138
139 if (i >= MAX_RW_REG_CNT)
140 return -ETIMEDOUT;
141
142 if (data)
143 *data = (u8)(val & 0xFF);
144
145 return 0;
146 }
147 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
148
149 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
150 {
151 int err, i, finished = 0;
152 u8 tmp;
153
154 rtsx_pci_init_cmd(pcr);
155
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
158 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
159 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
160
161 err = rtsx_pci_send_cmd(pcr, 100);
162 if (err < 0)
163 return err;
164
165 for (i = 0; i < 100000; i++) {
166 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
167 if (err < 0)
168 return err;
169
170 if (!(tmp & 0x80)) {
171 finished = 1;
172 break;
173 }
174 }
175
176 if (!finished)
177 return -ETIMEDOUT;
178
179 return 0;
180 }
181
182 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
183 {
184 if (pcr->ops->write_phy)
185 return pcr->ops->write_phy(pcr, addr, val);
186
187 return __rtsx_pci_write_phy_register(pcr, addr, val);
188 }
189 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
190
191 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
192 {
193 int err, i, finished = 0;
194 u16 data;
195 u8 *ptr, tmp;
196
197 rtsx_pci_init_cmd(pcr);
198
199 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
200 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
201
202 err = rtsx_pci_send_cmd(pcr, 100);
203 if (err < 0)
204 return err;
205
206 for (i = 0; i < 100000; i++) {
207 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
208 if (err < 0)
209 return err;
210
211 if (!(tmp & 0x80)) {
212 finished = 1;
213 break;
214 }
215 }
216
217 if (!finished)
218 return -ETIMEDOUT;
219
220 rtsx_pci_init_cmd(pcr);
221
222 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
223 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
224
225 err = rtsx_pci_send_cmd(pcr, 100);
226 if (err < 0)
227 return err;
228
229 ptr = rtsx_pci_get_cmd_data(pcr);
230 data = ((u16)ptr[1] << 8) | ptr[0];
231
232 if (val)
233 *val = data;
234
235 return 0;
236 }
237
238 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
239 {
240 if (pcr->ops->read_phy)
241 return pcr->ops->read_phy(pcr, addr, val);
242
243 return __rtsx_pci_read_phy_register(pcr, addr, val);
244 }
245 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
246
247 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
248 {
249 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
250 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
251
252 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
253 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
254 }
255 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
256
257 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
258 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
259 {
260 unsigned long flags;
261 u32 val = 0;
262 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
263
264 val |= (u32)(cmd_type & 0x03) << 30;
265 val |= (u32)(reg_addr & 0x3FFF) << 16;
266 val |= (u32)mask << 8;
267 val |= (u32)data;
268
269 spin_lock_irqsave(&pcr->lock, flags);
270 ptr += pcr->ci;
271 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
272 put_unaligned_le32(val, ptr);
273 ptr++;
274 pcr->ci++;
275 }
276 spin_unlock_irqrestore(&pcr->lock, flags);
277 }
278 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
279
280 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
281 {
282 u32 val = 1 << 31;
283
284 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
285
286 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
287 /* Hardware Auto Response */
288 val |= 0x40000000;
289 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
290 }
291 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
292
293 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
294 {
295 struct completion trans_done;
296 u32 val = 1 << 31;
297 long timeleft;
298 unsigned long flags;
299 int err = 0;
300
301 spin_lock_irqsave(&pcr->lock, flags);
302
303 /* set up data structures for the wakeup system */
304 pcr->done = &trans_done;
305 pcr->trans_result = TRANS_NOT_READY;
306 init_completion(&trans_done);
307
308 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
309
310 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
311 /* Hardware Auto Response */
312 val |= 0x40000000;
313 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
314
315 spin_unlock_irqrestore(&pcr->lock, flags);
316
317 /* Wait for TRANS_OK_INT */
318 timeleft = wait_for_completion_interruptible_timeout(
319 &trans_done, msecs_to_jiffies(timeout));
320 if (timeleft <= 0) {
321 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
322 err = -ETIMEDOUT;
323 goto finish_send_cmd;
324 }
325
326 spin_lock_irqsave(&pcr->lock, flags);
327 if (pcr->trans_result == TRANS_RESULT_FAIL)
328 err = -EINVAL;
329 else if (pcr->trans_result == TRANS_RESULT_OK)
330 err = 0;
331 else if (pcr->trans_result == TRANS_NO_DEVICE)
332 err = -ENODEV;
333 spin_unlock_irqrestore(&pcr->lock, flags);
334
335 finish_send_cmd:
336 spin_lock_irqsave(&pcr->lock, flags);
337 pcr->done = NULL;
338 spin_unlock_irqrestore(&pcr->lock, flags);
339
340 if ((err < 0) && (err != -ENODEV))
341 rtsx_pci_stop_cmd(pcr);
342
343 if (pcr->finish_me)
344 complete(pcr->finish_me);
345
346 return err;
347 }
348 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
349
350 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
351 dma_addr_t addr, unsigned int len, int end)
352 {
353 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
354 u64 val;
355 u8 option = SG_VALID | SG_TRANS_DATA;
356
357 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
358
359 if (end)
360 option |= SG_END;
361 val = ((u64)addr << 32) | ((u64)len << 12) | option;
362
363 put_unaligned_le64(val, ptr);
364 pcr->sgi++;
365 }
366
367 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
368 int num_sg, bool read, int timeout)
369 {
370 int err = 0, count;
371
372 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
373 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
374 if (count < 1)
375 return -EINVAL;
376 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
377
378 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
379
380 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
381
382 return err;
383 }
384 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
385
386 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
387 int num_sg, bool read)
388 {
389 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
390
391 if (pcr->remove_pci)
392 return -EINVAL;
393
394 if ((sglist == NULL) || (num_sg <= 0))
395 return -EINVAL;
396
397 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
398 }
399 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
400
401 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
402 int num_sg, bool read)
403 {
404 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
405
406 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
407 }
408 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
409
410 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
411 int count, bool read, int timeout)
412 {
413 struct completion trans_done;
414 struct scatterlist *sg;
415 dma_addr_t addr;
416 long timeleft;
417 unsigned long flags;
418 unsigned int len;
419 int i, err = 0;
420 u32 val;
421 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
422
423 if (pcr->remove_pci)
424 return -ENODEV;
425
426 if ((sglist == NULL) || (count < 1))
427 return -EINVAL;
428
429 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
430 pcr->sgi = 0;
431 for_each_sg(sglist, sg, count, i) {
432 addr = sg_dma_address(sg);
433 len = sg_dma_len(sg);
434 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
435 }
436
437 spin_lock_irqsave(&pcr->lock, flags);
438
439 pcr->done = &trans_done;
440 pcr->trans_result = TRANS_NOT_READY;
441 init_completion(&trans_done);
442 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
443 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
444
445 spin_unlock_irqrestore(&pcr->lock, flags);
446
447 timeleft = wait_for_completion_interruptible_timeout(
448 &trans_done, msecs_to_jiffies(timeout));
449 if (timeleft <= 0) {
450 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
451 err = -ETIMEDOUT;
452 goto out;
453 }
454
455 spin_lock_irqsave(&pcr->lock, flags);
456 if (pcr->trans_result == TRANS_RESULT_FAIL) {
457 err = -EILSEQ;
458 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
459 pcr->dma_error_count++;
460 }
461
462 else if (pcr->trans_result == TRANS_NO_DEVICE)
463 err = -ENODEV;
464 spin_unlock_irqrestore(&pcr->lock, flags);
465
466 out:
467 spin_lock_irqsave(&pcr->lock, flags);
468 pcr->done = NULL;
469 spin_unlock_irqrestore(&pcr->lock, flags);
470
471 if ((err < 0) && (err != -ENODEV))
472 rtsx_pci_stop_cmd(pcr);
473
474 if (pcr->finish_me)
475 complete(pcr->finish_me);
476
477 return err;
478 }
479 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
480
481 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
482 {
483 int err;
484 int i, j;
485 u16 reg;
486 u8 *ptr;
487
488 if (buf_len > 512)
489 buf_len = 512;
490
491 ptr = buf;
492 reg = PPBUF_BASE2;
493 for (i = 0; i < buf_len / 256; i++) {
494 rtsx_pci_init_cmd(pcr);
495
496 for (j = 0; j < 256; j++)
497 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
498
499 err = rtsx_pci_send_cmd(pcr, 250);
500 if (err < 0)
501 return err;
502
503 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
504 ptr += 256;
505 }
506
507 if (buf_len % 256) {
508 rtsx_pci_init_cmd(pcr);
509
510 for (j = 0; j < buf_len % 256; j++)
511 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
512
513 err = rtsx_pci_send_cmd(pcr, 250);
514 if (err < 0)
515 return err;
516 }
517
518 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
519
520 return 0;
521 }
522 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
523
524 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
525 {
526 int err;
527 int i, j;
528 u16 reg;
529 u8 *ptr;
530
531 if (buf_len > 512)
532 buf_len = 512;
533
534 ptr = buf;
535 reg = PPBUF_BASE2;
536 for (i = 0; i < buf_len / 256; i++) {
537 rtsx_pci_init_cmd(pcr);
538
539 for (j = 0; j < 256; j++) {
540 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
541 reg++, 0xFF, *ptr);
542 ptr++;
543 }
544
545 err = rtsx_pci_send_cmd(pcr, 250);
546 if (err < 0)
547 return err;
548 }
549
550 if (buf_len % 256) {
551 rtsx_pci_init_cmd(pcr);
552
553 for (j = 0; j < buf_len % 256; j++) {
554 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
555 reg++, 0xFF, *ptr);
556 ptr++;
557 }
558
559 err = rtsx_pci_send_cmd(pcr, 250);
560 if (err < 0)
561 return err;
562 }
563
564 return 0;
565 }
566 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
567
568 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
569 {
570 rtsx_pci_init_cmd(pcr);
571
572 while (*tbl & 0xFFFF0000) {
573 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
574 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
575 tbl++;
576 }
577
578 return rtsx_pci_send_cmd(pcr, 100);
579 }
580
581 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
582 {
583 const u32 *tbl;
584
585 if (card == RTSX_SD_CARD)
586 tbl = pcr->sd_pull_ctl_enable_tbl;
587 else if (card == RTSX_MS_CARD)
588 tbl = pcr->ms_pull_ctl_enable_tbl;
589 else
590 return -EINVAL;
591
592 return rtsx_pci_set_pull_ctl(pcr, tbl);
593 }
594 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
595
596 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
597 {
598 const u32 *tbl;
599
600 if (card == RTSX_SD_CARD)
601 tbl = pcr->sd_pull_ctl_disable_tbl;
602 else if (card == RTSX_MS_CARD)
603 tbl = pcr->ms_pull_ctl_disable_tbl;
604 else
605 return -EINVAL;
606
607
608 return rtsx_pci_set_pull_ctl(pcr, tbl);
609 }
610 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
611
612 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
613 {
614 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
615
616 if (pcr->num_slots > 1)
617 pcr->bier |= MS_INT_EN;
618
619 /* Enable Bus Interrupt */
620 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
621
622 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
623 }
624
625 static inline u8 double_ssc_depth(u8 depth)
626 {
627 return ((depth > 1) ? (depth - 1) : depth);
628 }
629
630 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
631 {
632 if (div > CLK_DIV_1) {
633 if (ssc_depth > (div - 1))
634 ssc_depth -= (div - 1);
635 else
636 ssc_depth = SSC_DEPTH_4M;
637 }
638
639 return ssc_depth;
640 }
641
642 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
643 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
644 {
645 int err, clk;
646 u8 n, clk_divider, mcu_cnt, div;
647 u8 depth[] = {
648 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
649 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
650 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
651 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
652 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
653 };
654
655 if (initial_mode) {
656 /* We use 250k(around) here, in initial stage */
657 clk_divider = SD_CLK_DIVIDE_128;
658 card_clock = 30000000;
659 } else {
660 clk_divider = SD_CLK_DIVIDE_0;
661 }
662 err = rtsx_pci_write_register(pcr, SD_CFG1,
663 SD_CLK_DIVIDE_MASK, clk_divider);
664 if (err < 0)
665 return err;
666
667 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
668 if (card_clock == UHS_SDR104_MAX_DTR &&
669 pcr->dma_error_count &&
670 PCI_PID(pcr) == RTS5227_DEVICE_ID)
671 card_clock = UHS_SDR104_MAX_DTR -
672 (pcr->dma_error_count * 20000000);
673
674 card_clock /= 1000000;
675 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
676
677 clk = card_clock;
678 if (!initial_mode && double_clk)
679 clk = card_clock * 2;
680 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
681 clk, pcr->cur_clock);
682
683 if (clk == pcr->cur_clock)
684 return 0;
685
686 if (pcr->ops->conv_clk_and_div_n)
687 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
688 else
689 n = (u8)(clk - 2);
690 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
691 return -EINVAL;
692
693 mcu_cnt = (u8)(125/clk + 3);
694 if (mcu_cnt > 15)
695 mcu_cnt = 15;
696
697 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
698 div = CLK_DIV_1;
699 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
700 if (pcr->ops->conv_clk_and_div_n) {
701 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
702 DIV_N_TO_CLK) * 2;
703 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
704 CLK_TO_DIV_N);
705 } else {
706 n = (n + 2) * 2 - 2;
707 }
708 div++;
709 }
710 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
711
712 ssc_depth = depth[ssc_depth];
713 if (double_clk)
714 ssc_depth = double_ssc_depth(ssc_depth);
715
716 ssc_depth = revise_ssc_depth(ssc_depth, div);
717 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
718
719 rtsx_pci_init_cmd(pcr);
720 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
721 CLK_LOW_FREQ, CLK_LOW_FREQ);
722 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
723 0xFF, (div << 4) | mcu_cnt);
724 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
725 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
726 SSC_DEPTH_MASK, ssc_depth);
727 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
728 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
729 if (vpclk) {
730 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
731 PHASE_NOT_RESET, 0);
732 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
733 PHASE_NOT_RESET, PHASE_NOT_RESET);
734 }
735
736 err = rtsx_pci_send_cmd(pcr, 2000);
737 if (err < 0)
738 return err;
739
740 /* Wait SSC clock stable */
741 udelay(10);
742 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
743 if (err < 0)
744 return err;
745
746 pcr->cur_clock = clk;
747 return 0;
748 }
749 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
750
751 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
752 {
753 if (pcr->ops->card_power_on)
754 return pcr->ops->card_power_on(pcr, card);
755
756 return 0;
757 }
758 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
759
760 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
761 {
762 if (pcr->ops->card_power_off)
763 return pcr->ops->card_power_off(pcr, card);
764
765 return 0;
766 }
767 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
768
769 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
770 {
771 unsigned int cd_mask[] = {
772 [RTSX_SD_CARD] = SD_EXIST,
773 [RTSX_MS_CARD] = MS_EXIST
774 };
775
776 if (!(pcr->flags & PCR_MS_PMOS)) {
777 /* When using single PMOS, accessing card is not permitted
778 * if the existing card is not the designated one.
779 */
780 if (pcr->card_exist & (~cd_mask[card]))
781 return -EIO;
782 }
783
784 return 0;
785 }
786 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
787
788 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
789 {
790 if (pcr->ops->switch_output_voltage)
791 return pcr->ops->switch_output_voltage(pcr, voltage);
792
793 return 0;
794 }
795 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
796
797 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
798 {
799 unsigned int val;
800
801 val = rtsx_pci_readl(pcr, RTSX_BIPR);
802 if (pcr->ops->cd_deglitch)
803 val = pcr->ops->cd_deglitch(pcr);
804
805 return val;
806 }
807 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
808
809 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
810 {
811 struct completion finish;
812
813 pcr->finish_me = &finish;
814 init_completion(&finish);
815
816 if (pcr->done)
817 complete(pcr->done);
818
819 if (!pcr->remove_pci)
820 rtsx_pci_stop_cmd(pcr);
821
822 wait_for_completion_interruptible_timeout(&finish,
823 msecs_to_jiffies(2));
824 pcr->finish_me = NULL;
825 }
826 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
827
828 static void rtsx_pci_card_detect(struct work_struct *work)
829 {
830 struct delayed_work *dwork;
831 struct rtsx_pcr *pcr;
832 unsigned long flags;
833 unsigned int card_detect = 0, card_inserted, card_removed;
834 u32 irq_status;
835
836 dwork = to_delayed_work(work);
837 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
838
839 pcr_dbg(pcr, "--> %s\n", __func__);
840
841 mutex_lock(&pcr->pcr_mutex);
842 spin_lock_irqsave(&pcr->lock, flags);
843
844 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
845 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
846
847 irq_status &= CARD_EXIST;
848 card_inserted = pcr->card_inserted & irq_status;
849 card_removed = pcr->card_removed;
850 pcr->card_inserted = 0;
851 pcr->card_removed = 0;
852
853 spin_unlock_irqrestore(&pcr->lock, flags);
854
855 if (card_inserted || card_removed) {
856 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
857 card_inserted, card_removed);
858
859 if (pcr->ops->cd_deglitch)
860 card_inserted = pcr->ops->cd_deglitch(pcr);
861
862 card_detect = card_inserted | card_removed;
863
864 pcr->card_exist |= card_inserted;
865 pcr->card_exist &= ~card_removed;
866 }
867
868 mutex_unlock(&pcr->pcr_mutex);
869
870 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
871 pcr->slots[RTSX_SD_CARD].card_event(
872 pcr->slots[RTSX_SD_CARD].p_dev);
873 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
874 pcr->slots[RTSX_MS_CARD].card_event(
875 pcr->slots[RTSX_MS_CARD].p_dev);
876 }
877
878 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
879 {
880 struct rtsx_pcr *pcr = dev_id;
881 u32 int_reg;
882
883 if (!pcr)
884 return IRQ_NONE;
885
886 spin_lock(&pcr->lock);
887
888 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
889 /* Clear interrupt flag */
890 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
891 if ((int_reg & pcr->bier) == 0) {
892 spin_unlock(&pcr->lock);
893 return IRQ_NONE;
894 }
895 if (int_reg == 0xFFFFFFFF) {
896 spin_unlock(&pcr->lock);
897 return IRQ_HANDLED;
898 }
899
900 int_reg &= (pcr->bier | 0x7FFFFF);
901
902 if (int_reg & SD_INT) {
903 if (int_reg & SD_EXIST) {
904 pcr->card_inserted |= SD_EXIST;
905 } else {
906 pcr->card_removed |= SD_EXIST;
907 pcr->card_inserted &= ~SD_EXIST;
908 }
909 pcr->dma_error_count = 0;
910 }
911
912 if (int_reg & MS_INT) {
913 if (int_reg & MS_EXIST) {
914 pcr->card_inserted |= MS_EXIST;
915 } else {
916 pcr->card_removed |= MS_EXIST;
917 pcr->card_inserted &= ~MS_EXIST;
918 }
919 }
920
921 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
922 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
923 pcr->trans_result = TRANS_RESULT_FAIL;
924 if (pcr->done)
925 complete(pcr->done);
926 } else if (int_reg & TRANS_OK_INT) {
927 pcr->trans_result = TRANS_RESULT_OK;
928 if (pcr->done)
929 complete(pcr->done);
930 }
931 }
932
933 if (pcr->card_inserted || pcr->card_removed)
934 schedule_delayed_work(&pcr->carddet_work,
935 msecs_to_jiffies(200));
936
937 spin_unlock(&pcr->lock);
938 return IRQ_HANDLED;
939 }
940
941 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
942 {
943 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
944 __func__, pcr->msi_en, pcr->pci->irq);
945
946 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
947 pcr->msi_en ? 0 : IRQF_SHARED,
948 DRV_NAME_RTSX_PCI, pcr)) {
949 dev_err(&(pcr->pci->dev),
950 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
951 pcr->pci->irq);
952 return -1;
953 }
954
955 pcr->irq = pcr->pci->irq;
956 pci_intx(pcr->pci, !pcr->msi_en);
957
958 return 0;
959 }
960
961 static void rtsx_pci_idle_work(struct work_struct *work)
962 {
963 struct delayed_work *dwork = to_delayed_work(work);
964 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
965
966 pcr_dbg(pcr, "--> %s\n", __func__);
967
968 mutex_lock(&pcr->pcr_mutex);
969
970 pcr->state = PDEV_STAT_IDLE;
971
972 if (pcr->ops->disable_auto_blink)
973 pcr->ops->disable_auto_blink(pcr);
974 if (pcr->ops->turn_off_led)
975 pcr->ops->turn_off_led(pcr);
976
977 if (pcr->aspm_en)
978 rtsx_pci_enable_aspm(pcr);
979
980 mutex_unlock(&pcr->pcr_mutex);
981 }
982
983 #ifdef CONFIG_PM
984 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
985 {
986 if (pcr->ops->turn_off_led)
987 pcr->ops->turn_off_led(pcr);
988
989 rtsx_pci_writel(pcr, RTSX_BIER, 0);
990 pcr->bier = 0;
991
992 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
993 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
994
995 if (pcr->ops->force_power_down)
996 pcr->ops->force_power_down(pcr, pm_state);
997 }
998 #endif
999
1000 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1001 {
1002 int err;
1003
1004 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
1005 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1006
1007 rtsx_pci_enable_bus_int(pcr);
1008
1009 /* Power on SSC */
1010 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1011 if (err < 0)
1012 return err;
1013
1014 /* Wait SSC power stable */
1015 udelay(200);
1016
1017 rtsx_pci_disable_aspm(pcr);
1018 if (pcr->ops->optimize_phy) {
1019 err = pcr->ops->optimize_phy(pcr);
1020 if (err < 0)
1021 return err;
1022 }
1023
1024 rtsx_pci_init_cmd(pcr);
1025
1026 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1028
1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1030 /* Disable card clock */
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1032 /* Reset delink mode */
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1034 /* Card driving select */
1035 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1036 0xFF, pcr->card_drive_sel);
1037 /* Enable SSC Clock */
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1039 0xFF, SSC_8X_EN | SSC_SEL_4M);
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1041 /* Disable cd_pwr_save */
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1043 /* Clear Link Ready Interrupt */
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1045 LINK_RDY_INT, LINK_RDY_INT);
1046 /* Enlarge the estimation window of PERST# glitch
1047 * to reduce the chance of invalid card interrupt
1048 */
1049 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1050 /* Update RC oscillator to 400k
1051 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1052 * 1: 2M 0: 400k
1053 */
1054 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1055 /* Set interrupt write clear
1056 * bit 1: U_elbi_if_rd_clr_en
1057 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1058 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1059 */
1060 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1061
1062 err = rtsx_pci_send_cmd(pcr, 100);
1063 if (err < 0)
1064 return err;
1065
1066 /* Enable clk_request_n to enable clock power management */
1067 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1068 /* Enter L1 when host tx idle */
1069 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1070
1071 if (pcr->ops->extra_init_hw) {
1072 err = pcr->ops->extra_init_hw(pcr);
1073 if (err < 0)
1074 return err;
1075 }
1076
1077 /* No CD interrupt if probing driver with card inserted.
1078 * So we need to initialize pcr->card_exist here.
1079 */
1080 if (pcr->ops->cd_deglitch)
1081 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1082 else
1083 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1084
1085 return 0;
1086 }
1087
1088 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1089 {
1090 int err;
1091
1092 spin_lock_init(&pcr->lock);
1093 mutex_init(&pcr->pcr_mutex);
1094
1095 switch (PCI_PID(pcr)) {
1096 default:
1097 case 0x5209:
1098 rts5209_init_params(pcr);
1099 break;
1100
1101 case 0x5229:
1102 rts5229_init_params(pcr);
1103 break;
1104
1105 case 0x5289:
1106 rtl8411_init_params(pcr);
1107 break;
1108
1109 case 0x5227:
1110 rts5227_init_params(pcr);
1111 break;
1112
1113 case 0x522A:
1114 rts522a_init_params(pcr);
1115 break;
1116
1117 case 0x5249:
1118 rts5249_init_params(pcr);
1119 break;
1120
1121 case 0x524A:
1122 rts524a_init_params(pcr);
1123 break;
1124
1125 case 0x525A:
1126 rts525a_init_params(pcr);
1127 break;
1128
1129 case 0x5287:
1130 rtl8411b_init_params(pcr);
1131 break;
1132
1133 case 0x5286:
1134 rtl8402_init_params(pcr);
1135 break;
1136 }
1137
1138 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1139 PCI_PID(pcr), pcr->ic_version);
1140
1141 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1142 GFP_KERNEL);
1143 if (!pcr->slots)
1144 return -ENOMEM;
1145
1146 if (pcr->ops->fetch_vendor_settings)
1147 pcr->ops->fetch_vendor_settings(pcr);
1148
1149 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1150 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1151 pcr->sd30_drive_sel_1v8);
1152 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1153 pcr->sd30_drive_sel_3v3);
1154 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1155 pcr->card_drive_sel);
1156 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1157
1158 pcr->state = PDEV_STAT_IDLE;
1159 err = rtsx_pci_init_hw(pcr);
1160 if (err < 0) {
1161 kfree(pcr->slots);
1162 return err;
1163 }
1164
1165 return 0;
1166 }
1167
1168 static int rtsx_pci_probe(struct pci_dev *pcidev,
1169 const struct pci_device_id *id)
1170 {
1171 struct rtsx_pcr *pcr;
1172 struct pcr_handle *handle;
1173 u32 base, len;
1174 int ret, i, bar = 0;
1175
1176 dev_dbg(&(pcidev->dev),
1177 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1178 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1179 (int)pcidev->revision);
1180
1181 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1182 if (ret < 0)
1183 return ret;
1184
1185 ret = pci_enable_device(pcidev);
1186 if (ret)
1187 return ret;
1188
1189 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1190 if (ret)
1191 goto disable;
1192
1193 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1194 if (!pcr) {
1195 ret = -ENOMEM;
1196 goto release_pci;
1197 }
1198
1199 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1200 if (!handle) {
1201 ret = -ENOMEM;
1202 goto free_pcr;
1203 }
1204 handle->pcr = pcr;
1205
1206 idr_preload(GFP_KERNEL);
1207 spin_lock(&rtsx_pci_lock);
1208 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1209 if (ret >= 0)
1210 pcr->id = ret;
1211 spin_unlock(&rtsx_pci_lock);
1212 idr_preload_end();
1213 if (ret < 0)
1214 goto free_handle;
1215
1216 pcr->pci = pcidev;
1217 dev_set_drvdata(&pcidev->dev, handle);
1218
1219 if (CHK_PCI_PID(pcr, 0x525A))
1220 bar = 1;
1221 len = pci_resource_len(pcidev, bar);
1222 base = pci_resource_start(pcidev, bar);
1223 pcr->remap_addr = ioremap_nocache(base, len);
1224 if (!pcr->remap_addr) {
1225 ret = -ENOMEM;
1226 goto free_handle;
1227 }
1228
1229 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1230 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1231 GFP_KERNEL);
1232 if (pcr->rtsx_resv_buf == NULL) {
1233 ret = -ENXIO;
1234 goto unmap;
1235 }
1236 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1237 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1238 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1239 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1240
1241 pcr->card_inserted = 0;
1242 pcr->card_removed = 0;
1243 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1244 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1245
1246 pcr->msi_en = msi_en;
1247 if (pcr->msi_en) {
1248 ret = pci_enable_msi(pcidev);
1249 if (ret)
1250 pcr->msi_en = false;
1251 }
1252
1253 ret = rtsx_pci_acquire_irq(pcr);
1254 if (ret < 0)
1255 goto disable_msi;
1256
1257 pci_set_master(pcidev);
1258 synchronize_irq(pcr->irq);
1259
1260 ret = rtsx_pci_init_chip(pcr);
1261 if (ret < 0)
1262 goto disable_irq;
1263
1264 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1265 rtsx_pcr_cells[i].platform_data = handle;
1266 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1267 }
1268 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1269 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1270 if (ret < 0)
1271 goto disable_irq;
1272
1273 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1274
1275 return 0;
1276
1277 disable_irq:
1278 free_irq(pcr->irq, (void *)pcr);
1279 disable_msi:
1280 if (pcr->msi_en)
1281 pci_disable_msi(pcr->pci);
1282 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1283 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1284 unmap:
1285 iounmap(pcr->remap_addr);
1286 free_handle:
1287 kfree(handle);
1288 free_pcr:
1289 kfree(pcr);
1290 release_pci:
1291 pci_release_regions(pcidev);
1292 disable:
1293 pci_disable_device(pcidev);
1294
1295 return ret;
1296 }
1297
1298 static void rtsx_pci_remove(struct pci_dev *pcidev)
1299 {
1300 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1301 struct rtsx_pcr *pcr = handle->pcr;
1302
1303 pcr->remove_pci = true;
1304
1305 /* Disable interrupts at the pcr level */
1306 spin_lock_irq(&pcr->lock);
1307 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1308 pcr->bier = 0;
1309 spin_unlock_irq(&pcr->lock);
1310
1311 cancel_delayed_work_sync(&pcr->carddet_work);
1312 cancel_delayed_work_sync(&pcr->idle_work);
1313
1314 mfd_remove_devices(&pcidev->dev);
1315
1316 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1317 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1318 free_irq(pcr->irq, (void *)pcr);
1319 if (pcr->msi_en)
1320 pci_disable_msi(pcr->pci);
1321 iounmap(pcr->remap_addr);
1322
1323 pci_release_regions(pcidev);
1324 pci_disable_device(pcidev);
1325
1326 spin_lock(&rtsx_pci_lock);
1327 idr_remove(&rtsx_pci_idr, pcr->id);
1328 spin_unlock(&rtsx_pci_lock);
1329
1330 kfree(pcr->slots);
1331 kfree(pcr);
1332 kfree(handle);
1333
1334 dev_dbg(&(pcidev->dev),
1335 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1336 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1337 }
1338
1339 #ifdef CONFIG_PM
1340
1341 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1342 {
1343 struct pcr_handle *handle;
1344 struct rtsx_pcr *pcr;
1345
1346 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1347
1348 handle = pci_get_drvdata(pcidev);
1349 pcr = handle->pcr;
1350
1351 cancel_delayed_work(&pcr->carddet_work);
1352 cancel_delayed_work(&pcr->idle_work);
1353
1354 mutex_lock(&pcr->pcr_mutex);
1355
1356 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1357
1358 pci_save_state(pcidev);
1359 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1360 pci_disable_device(pcidev);
1361 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1362
1363 mutex_unlock(&pcr->pcr_mutex);
1364 return 0;
1365 }
1366
1367 static int rtsx_pci_resume(struct pci_dev *pcidev)
1368 {
1369 struct pcr_handle *handle;
1370 struct rtsx_pcr *pcr;
1371 int ret = 0;
1372
1373 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1374
1375 handle = pci_get_drvdata(pcidev);
1376 pcr = handle->pcr;
1377
1378 mutex_lock(&pcr->pcr_mutex);
1379
1380 pci_set_power_state(pcidev, PCI_D0);
1381 pci_restore_state(pcidev);
1382 ret = pci_enable_device(pcidev);
1383 if (ret)
1384 goto out;
1385 pci_set_master(pcidev);
1386
1387 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1388 if (ret)
1389 goto out;
1390
1391 ret = rtsx_pci_init_hw(pcr);
1392 if (ret)
1393 goto out;
1394
1395 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1396
1397 out:
1398 mutex_unlock(&pcr->pcr_mutex);
1399 return ret;
1400 }
1401
1402 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1403 {
1404 struct pcr_handle *handle;
1405 struct rtsx_pcr *pcr;
1406
1407 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1408
1409 handle = pci_get_drvdata(pcidev);
1410 pcr = handle->pcr;
1411 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1412
1413 pci_disable_device(pcidev);
1414 }
1415
1416 #else /* CONFIG_PM */
1417
1418 #define rtsx_pci_suspend NULL
1419 #define rtsx_pci_resume NULL
1420 #define rtsx_pci_shutdown NULL
1421
1422 #endif /* CONFIG_PM */
1423
1424 static struct pci_driver rtsx_pci_driver = {
1425 .name = DRV_NAME_RTSX_PCI,
1426 .id_table = rtsx_pci_ids,
1427 .probe = rtsx_pci_probe,
1428 .remove = rtsx_pci_remove,
1429 .suspend = rtsx_pci_suspend,
1430 .resume = rtsx_pci_resume,
1431 .shutdown = rtsx_pci_shutdown,
1432 };
1433 module_pci_driver(rtsx_pci_driver);
1434
1435 MODULE_LICENSE("GPL");
1436 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1437 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
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