1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <linux/mmc/card.h>
34 #include <asm/unaligned.h>
38 static bool msi_en
= true;
39 module_param(msi_en
, bool, S_IRUGO
| S_IWUSR
);
40 MODULE_PARM_DESC(msi_en
, "Enable MSI");
42 static DEFINE_IDR(rtsx_pci_idr
);
43 static DEFINE_SPINLOCK(rtsx_pci_lock
);
45 static struct mfd_cell rtsx_pcr_cells
[] = {
47 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
50 .name
= DRV_NAME_RTSX_PCI_MS
,
54 static const struct pci_device_id rtsx_pci_ids
[] = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
61 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
62 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
63 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
64 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
68 MODULE_DEVICE_TABLE(pci
, rtsx_pci_ids
);
70 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr
*pcr
)
72 rtsx_pci_update_cfg_byte(pcr
, pcr
->pcie_cap
+ PCI_EXP_LNKCTL
,
76 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr
*pcr
)
78 rtsx_pci_update_cfg_byte(pcr
, pcr
->pcie_cap
+ PCI_EXP_LNKCTL
,
82 void rtsx_pci_start_run(struct rtsx_pcr
*pcr
)
84 /* If pci device removed, don't queue idle work any more */
88 if (pcr
->state
!= PDEV_STAT_RUN
) {
89 pcr
->state
= PDEV_STAT_RUN
;
90 if (pcr
->ops
->enable_auto_blink
)
91 pcr
->ops
->enable_auto_blink(pcr
);
94 rtsx_pci_disable_aspm(pcr
);
97 mod_delayed_work(system_wq
, &pcr
->idle_work
, msecs_to_jiffies(200));
99 EXPORT_SYMBOL_GPL(rtsx_pci_start_run
);
101 int rtsx_pci_write_register(struct rtsx_pcr
*pcr
, u16 addr
, u8 mask
, u8 data
)
104 u32 val
= HAIMR_WRITE_START
;
106 val
|= (u32
)(addr
& 0x3FFF) << 16;
107 val
|= (u32
)mask
<< 8;
110 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
112 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
113 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
114 if ((val
& HAIMR_TRANS_END
) == 0) {
123 EXPORT_SYMBOL_GPL(rtsx_pci_write_register
);
125 int rtsx_pci_read_register(struct rtsx_pcr
*pcr
, u16 addr
, u8
*data
)
127 u32 val
= HAIMR_READ_START
;
130 val
|= (u32
)(addr
& 0x3FFF) << 16;
131 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
133 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
134 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
135 if ((val
& HAIMR_TRANS_END
) == 0)
139 if (i
>= MAX_RW_REG_CNT
)
143 *data
= (u8
)(val
& 0xFF);
147 EXPORT_SYMBOL_GPL(rtsx_pci_read_register
);
149 int __rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
151 int err
, i
, finished
= 0;
154 rtsx_pci_init_cmd(pcr
);
156 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA0
, 0xFF, (u8
)val
);
157 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA1
, 0xFF, (u8
)(val
>> 8));
158 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
159 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x81);
161 err
= rtsx_pci_send_cmd(pcr
, 100);
165 for (i
= 0; i
< 100000; i
++) {
166 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
182 int rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
184 if (pcr
->ops
->write_phy
)
185 return pcr
->ops
->write_phy(pcr
, addr
, val
);
187 return __rtsx_pci_write_phy_register(pcr
, addr
, val
);
189 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register
);
191 int __rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
193 int err
, i
, finished
= 0;
197 rtsx_pci_init_cmd(pcr
);
199 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
200 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x80);
202 err
= rtsx_pci_send_cmd(pcr
, 100);
206 for (i
= 0; i
< 100000; i
++) {
207 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
220 rtsx_pci_init_cmd(pcr
);
222 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA0
, 0, 0);
223 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA1
, 0, 0);
225 err
= rtsx_pci_send_cmd(pcr
, 100);
229 ptr
= rtsx_pci_get_cmd_data(pcr
);
230 data
= ((u16
)ptr
[1] << 8) | ptr
[0];
238 int rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
240 if (pcr
->ops
->read_phy
)
241 return pcr
->ops
->read_phy(pcr
, addr
, val
);
243 return __rtsx_pci_read_phy_register(pcr
, addr
, val
);
245 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register
);
247 void rtsx_pci_stop_cmd(struct rtsx_pcr
*pcr
)
249 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, STOP_CMD
);
250 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, STOP_DMA
);
252 rtsx_pci_write_register(pcr
, DMACTL
, 0x80, 0x80);
253 rtsx_pci_write_register(pcr
, RBCTL
, 0x80, 0x80);
255 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd
);
257 void rtsx_pci_add_cmd(struct rtsx_pcr
*pcr
,
258 u8 cmd_type
, u16 reg_addr
, u8 mask
, u8 data
)
262 u32
*ptr
= (u32
*)(pcr
->host_cmds_ptr
);
264 val
|= (u32
)(cmd_type
& 0x03) << 30;
265 val
|= (u32
)(reg_addr
& 0x3FFF) << 16;
266 val
|= (u32
)mask
<< 8;
269 spin_lock_irqsave(&pcr
->lock
, flags
);
271 if (pcr
->ci
< (HOST_CMDS_BUF_LEN
/ 4)) {
272 put_unaligned_le32(val
, ptr
);
276 spin_unlock_irqrestore(&pcr
->lock
, flags
);
278 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd
);
280 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr
*pcr
)
284 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
286 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
287 /* Hardware Auto Response */
289 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
291 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait
);
293 int rtsx_pci_send_cmd(struct rtsx_pcr
*pcr
, int timeout
)
295 struct completion trans_done
;
301 spin_lock_irqsave(&pcr
->lock
, flags
);
303 /* set up data structures for the wakeup system */
304 pcr
->done
= &trans_done
;
305 pcr
->trans_result
= TRANS_NOT_READY
;
306 init_completion(&trans_done
);
308 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
310 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
311 /* Hardware Auto Response */
313 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
315 spin_unlock_irqrestore(&pcr
->lock
, flags
);
317 /* Wait for TRANS_OK_INT */
318 timeleft
= wait_for_completion_interruptible_timeout(
319 &trans_done
, msecs_to_jiffies(timeout
));
321 pcr_dbg(pcr
, "Timeout (%s %d)\n", __func__
, __LINE__
);
323 goto finish_send_cmd
;
326 spin_lock_irqsave(&pcr
->lock
, flags
);
327 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
329 else if (pcr
->trans_result
== TRANS_RESULT_OK
)
331 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
333 spin_unlock_irqrestore(&pcr
->lock
, flags
);
336 spin_lock_irqsave(&pcr
->lock
, flags
);
338 spin_unlock_irqrestore(&pcr
->lock
, flags
);
340 if ((err
< 0) && (err
!= -ENODEV
))
341 rtsx_pci_stop_cmd(pcr
);
344 complete(pcr
->finish_me
);
348 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd
);
350 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr
*pcr
,
351 dma_addr_t addr
, unsigned int len
, int end
)
353 u64
*ptr
= (u64
*)(pcr
->host_sg_tbl_ptr
) + pcr
->sgi
;
355 u8 option
= SG_VALID
| SG_TRANS_DATA
;
357 pcr_dbg(pcr
, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr
, len
);
361 val
= ((u64
)addr
<< 32) | ((u64
)len
<< 12) | option
;
363 put_unaligned_le64(val
, ptr
);
367 int rtsx_pci_transfer_data(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
368 int num_sg
, bool read
, int timeout
)
372 pcr_dbg(pcr
, "--> %s: num_sg = %d\n", __func__
, num_sg
);
373 count
= rtsx_pci_dma_map_sg(pcr
, sglist
, num_sg
, read
);
376 pcr_dbg(pcr
, "DMA mapping count: %d\n", count
);
378 err
= rtsx_pci_dma_transfer(pcr
, sglist
, count
, read
, timeout
);
380 rtsx_pci_dma_unmap_sg(pcr
, sglist
, num_sg
, read
);
384 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data
);
386 int rtsx_pci_dma_map_sg(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
387 int num_sg
, bool read
)
389 enum dma_data_direction dir
= read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
394 if ((sglist
== NULL
) || (num_sg
<= 0))
397 return dma_map_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dir
);
399 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg
);
401 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
402 int num_sg
, bool read
)
404 enum dma_data_direction dir
= read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
406 dma_unmap_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dir
);
408 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg
);
410 int rtsx_pci_dma_transfer(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
411 int count
, bool read
, int timeout
)
413 struct completion trans_done
;
414 struct scatterlist
*sg
;
421 u8 dir
= read
? DEVICE_TO_HOST
: HOST_TO_DEVICE
;
426 if ((sglist
== NULL
) || (count
< 1))
429 val
= ((u32
)(dir
& 0x01) << 29) | TRIG_DMA
| ADMA_MODE
;
431 for_each_sg(sglist
, sg
, count
, i
) {
432 addr
= sg_dma_address(sg
);
433 len
= sg_dma_len(sg
);
434 rtsx_pci_add_sg_tbl(pcr
, addr
, len
, i
== count
- 1);
437 spin_lock_irqsave(&pcr
->lock
, flags
);
439 pcr
->done
= &trans_done
;
440 pcr
->trans_result
= TRANS_NOT_READY
;
441 init_completion(&trans_done
);
442 rtsx_pci_writel(pcr
, RTSX_HDBAR
, pcr
->host_sg_tbl_addr
);
443 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, val
);
445 spin_unlock_irqrestore(&pcr
->lock
, flags
);
447 timeleft
= wait_for_completion_interruptible_timeout(
448 &trans_done
, msecs_to_jiffies(timeout
));
450 pcr_dbg(pcr
, "Timeout (%s %d)\n", __func__
, __LINE__
);
455 spin_lock_irqsave(&pcr
->lock
, flags
);
456 if (pcr
->trans_result
== TRANS_RESULT_FAIL
) {
458 if (pcr
->dma_error_count
< RTS_MAX_TIMES_FREQ_REDUCTION
)
459 pcr
->dma_error_count
++;
462 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
464 spin_unlock_irqrestore(&pcr
->lock
, flags
);
467 spin_lock_irqsave(&pcr
->lock
, flags
);
469 spin_unlock_irqrestore(&pcr
->lock
, flags
);
471 if ((err
< 0) && (err
!= -ENODEV
))
472 rtsx_pci_stop_cmd(pcr
);
475 complete(pcr
->finish_me
);
479 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer
);
481 int rtsx_pci_read_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
493 for (i
= 0; i
< buf_len
/ 256; i
++) {
494 rtsx_pci_init_cmd(pcr
);
496 for (j
= 0; j
< 256; j
++)
497 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
499 err
= rtsx_pci_send_cmd(pcr
, 250);
503 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), 256);
508 rtsx_pci_init_cmd(pcr
);
510 for (j
= 0; j
< buf_len
% 256; j
++)
511 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
513 err
= rtsx_pci_send_cmd(pcr
, 250);
518 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), buf_len
% 256);
522 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf
);
524 int rtsx_pci_write_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
536 for (i
= 0; i
< buf_len
/ 256; i
++) {
537 rtsx_pci_init_cmd(pcr
);
539 for (j
= 0; j
< 256; j
++) {
540 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
545 err
= rtsx_pci_send_cmd(pcr
, 250);
551 rtsx_pci_init_cmd(pcr
);
553 for (j
= 0; j
< buf_len
% 256; j
++) {
554 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
559 err
= rtsx_pci_send_cmd(pcr
, 250);
566 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf
);
568 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr
*pcr
, const u32
*tbl
)
570 rtsx_pci_init_cmd(pcr
);
572 while (*tbl
& 0xFFFF0000) {
573 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
574 (u16
)(*tbl
>> 16), 0xFF, (u8
)(*tbl
));
578 return rtsx_pci_send_cmd(pcr
, 100);
581 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr
*pcr
, int card
)
585 if (card
== RTSX_SD_CARD
)
586 tbl
= pcr
->sd_pull_ctl_enable_tbl
;
587 else if (card
== RTSX_MS_CARD
)
588 tbl
= pcr
->ms_pull_ctl_enable_tbl
;
592 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
594 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable
);
596 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr
*pcr
, int card
)
600 if (card
== RTSX_SD_CARD
)
601 tbl
= pcr
->sd_pull_ctl_disable_tbl
;
602 else if (card
== RTSX_MS_CARD
)
603 tbl
= pcr
->ms_pull_ctl_disable_tbl
;
608 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
610 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable
);
612 static void rtsx_pci_enable_bus_int(struct rtsx_pcr
*pcr
)
614 pcr
->bier
= TRANS_OK_INT_EN
| TRANS_FAIL_INT_EN
| SD_INT_EN
;
616 if (pcr
->num_slots
> 1)
617 pcr
->bier
|= MS_INT_EN
;
619 /* Enable Bus Interrupt */
620 rtsx_pci_writel(pcr
, RTSX_BIER
, pcr
->bier
);
622 pcr_dbg(pcr
, "RTSX_BIER: 0x%08x\n", pcr
->bier
);
625 static inline u8
double_ssc_depth(u8 depth
)
627 return ((depth
> 1) ? (depth
- 1) : depth
);
630 static u8
revise_ssc_depth(u8 ssc_depth
, u8 div
)
632 if (div
> CLK_DIV_1
) {
633 if (ssc_depth
> (div
- 1))
634 ssc_depth
-= (div
- 1);
636 ssc_depth
= SSC_DEPTH_4M
;
642 int rtsx_pci_switch_clock(struct rtsx_pcr
*pcr
, unsigned int card_clock
,
643 u8 ssc_depth
, bool initial_mode
, bool double_clk
, bool vpclk
)
646 u8 n
, clk_divider
, mcu_cnt
, div
;
648 [RTSX_SSC_DEPTH_4M
] = SSC_DEPTH_4M
,
649 [RTSX_SSC_DEPTH_2M
] = SSC_DEPTH_2M
,
650 [RTSX_SSC_DEPTH_1M
] = SSC_DEPTH_1M
,
651 [RTSX_SSC_DEPTH_500K
] = SSC_DEPTH_500K
,
652 [RTSX_SSC_DEPTH_250K
] = SSC_DEPTH_250K
,
656 /* We use 250k(around) here, in initial stage */
657 clk_divider
= SD_CLK_DIVIDE_128
;
658 card_clock
= 30000000;
660 clk_divider
= SD_CLK_DIVIDE_0
;
662 err
= rtsx_pci_write_register(pcr
, SD_CFG1
,
663 SD_CLK_DIVIDE_MASK
, clk_divider
);
667 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
668 if (card_clock
== UHS_SDR104_MAX_DTR
&&
669 pcr
->dma_error_count
&&
670 PCI_PID(pcr
) == RTS5227_DEVICE_ID
)
671 card_clock
= UHS_SDR104_MAX_DTR
-
672 (pcr
->dma_error_count
* 20000000);
674 card_clock
/= 1000000;
675 pcr_dbg(pcr
, "Switch card clock to %dMHz\n", card_clock
);
678 if (!initial_mode
&& double_clk
)
679 clk
= card_clock
* 2;
680 pcr_dbg(pcr
, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
681 clk
, pcr
->cur_clock
);
683 if (clk
== pcr
->cur_clock
)
686 if (pcr
->ops
->conv_clk_and_div_n
)
687 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(clk
, CLK_TO_DIV_N
);
690 if ((clk
<= 2) || (n
> MAX_DIV_N_PCR
))
693 mcu_cnt
= (u8
)(125/clk
+ 3);
697 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
699 while ((n
< MIN_DIV_N_PCR
) && (div
< CLK_DIV_8
)) {
700 if (pcr
->ops
->conv_clk_and_div_n
) {
701 int dbl_clk
= pcr
->ops
->conv_clk_and_div_n(n
,
703 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(dbl_clk
,
710 pcr_dbg(pcr
, "n = %d, div = %d\n", n
, div
);
712 ssc_depth
= depth
[ssc_depth
];
714 ssc_depth
= double_ssc_depth(ssc_depth
);
716 ssc_depth
= revise_ssc_depth(ssc_depth
, div
);
717 pcr_dbg(pcr
, "ssc_depth = %d\n", ssc_depth
);
719 rtsx_pci_init_cmd(pcr
);
720 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
721 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
722 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
,
723 0xFF, (div
<< 4) | mcu_cnt
);
724 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
725 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
,
726 SSC_DEPTH_MASK
, ssc_depth
);
727 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, n
);
728 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, SSC_RSTB
);
730 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
732 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
733 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
736 err
= rtsx_pci_send_cmd(pcr
, 2000);
740 /* Wait SSC clock stable */
742 err
= rtsx_pci_write_register(pcr
, CLK_CTL
, CLK_LOW_FREQ
, 0);
746 pcr
->cur_clock
= clk
;
749 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock
);
751 int rtsx_pci_card_power_on(struct rtsx_pcr
*pcr
, int card
)
753 if (pcr
->ops
->card_power_on
)
754 return pcr
->ops
->card_power_on(pcr
, card
);
758 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on
);
760 int rtsx_pci_card_power_off(struct rtsx_pcr
*pcr
, int card
)
762 if (pcr
->ops
->card_power_off
)
763 return pcr
->ops
->card_power_off(pcr
, card
);
767 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off
);
769 int rtsx_pci_card_exclusive_check(struct rtsx_pcr
*pcr
, int card
)
771 unsigned int cd_mask
[] = {
772 [RTSX_SD_CARD
] = SD_EXIST
,
773 [RTSX_MS_CARD
] = MS_EXIST
776 if (!(pcr
->flags
& PCR_MS_PMOS
)) {
777 /* When using single PMOS, accessing card is not permitted
778 * if the existing card is not the designated one.
780 if (pcr
->card_exist
& (~cd_mask
[card
]))
786 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check
);
788 int rtsx_pci_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
790 if (pcr
->ops
->switch_output_voltage
)
791 return pcr
->ops
->switch_output_voltage(pcr
, voltage
);
795 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage
);
797 unsigned int rtsx_pci_card_exist(struct rtsx_pcr
*pcr
)
801 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
802 if (pcr
->ops
->cd_deglitch
)
803 val
= pcr
->ops
->cd_deglitch(pcr
);
807 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist
);
809 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr
*pcr
)
811 struct completion finish
;
813 pcr
->finish_me
= &finish
;
814 init_completion(&finish
);
819 if (!pcr
->remove_pci
)
820 rtsx_pci_stop_cmd(pcr
);
822 wait_for_completion_interruptible_timeout(&finish
,
823 msecs_to_jiffies(2));
824 pcr
->finish_me
= NULL
;
826 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer
);
828 static void rtsx_pci_card_detect(struct work_struct
*work
)
830 struct delayed_work
*dwork
;
831 struct rtsx_pcr
*pcr
;
833 unsigned int card_detect
= 0, card_inserted
, card_removed
;
836 dwork
= to_delayed_work(work
);
837 pcr
= container_of(dwork
, struct rtsx_pcr
, carddet_work
);
839 pcr_dbg(pcr
, "--> %s\n", __func__
);
841 mutex_lock(&pcr
->pcr_mutex
);
842 spin_lock_irqsave(&pcr
->lock
, flags
);
844 irq_status
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
845 pcr_dbg(pcr
, "irq_status: 0x%08x\n", irq_status
);
847 irq_status
&= CARD_EXIST
;
848 card_inserted
= pcr
->card_inserted
& irq_status
;
849 card_removed
= pcr
->card_removed
;
850 pcr
->card_inserted
= 0;
851 pcr
->card_removed
= 0;
853 spin_unlock_irqrestore(&pcr
->lock
, flags
);
855 if (card_inserted
|| card_removed
) {
856 pcr_dbg(pcr
, "card_inserted: 0x%x, card_removed: 0x%x\n",
857 card_inserted
, card_removed
);
859 if (pcr
->ops
->cd_deglitch
)
860 card_inserted
= pcr
->ops
->cd_deglitch(pcr
);
862 card_detect
= card_inserted
| card_removed
;
864 pcr
->card_exist
|= card_inserted
;
865 pcr
->card_exist
&= ~card_removed
;
868 mutex_unlock(&pcr
->pcr_mutex
);
870 if ((card_detect
& SD_EXIST
) && pcr
->slots
[RTSX_SD_CARD
].card_event
)
871 pcr
->slots
[RTSX_SD_CARD
].card_event(
872 pcr
->slots
[RTSX_SD_CARD
].p_dev
);
873 if ((card_detect
& MS_EXIST
) && pcr
->slots
[RTSX_MS_CARD
].card_event
)
874 pcr
->slots
[RTSX_MS_CARD
].card_event(
875 pcr
->slots
[RTSX_MS_CARD
].p_dev
);
878 static irqreturn_t
rtsx_pci_isr(int irq
, void *dev_id
)
880 struct rtsx_pcr
*pcr
= dev_id
;
886 spin_lock(&pcr
->lock
);
888 int_reg
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
889 /* Clear interrupt flag */
890 rtsx_pci_writel(pcr
, RTSX_BIPR
, int_reg
);
891 if ((int_reg
& pcr
->bier
) == 0) {
892 spin_unlock(&pcr
->lock
);
895 if (int_reg
== 0xFFFFFFFF) {
896 spin_unlock(&pcr
->lock
);
900 int_reg
&= (pcr
->bier
| 0x7FFFFF);
902 if (int_reg
& SD_INT
) {
903 if (int_reg
& SD_EXIST
) {
904 pcr
->card_inserted
|= SD_EXIST
;
906 pcr
->card_removed
|= SD_EXIST
;
907 pcr
->card_inserted
&= ~SD_EXIST
;
909 pcr
->dma_error_count
= 0;
912 if (int_reg
& MS_INT
) {
913 if (int_reg
& MS_EXIST
) {
914 pcr
->card_inserted
|= MS_EXIST
;
916 pcr
->card_removed
|= MS_EXIST
;
917 pcr
->card_inserted
&= ~MS_EXIST
;
921 if (int_reg
& (NEED_COMPLETE_INT
| DELINK_INT
)) {
922 if (int_reg
& (TRANS_FAIL_INT
| DELINK_INT
)) {
923 pcr
->trans_result
= TRANS_RESULT_FAIL
;
926 } else if (int_reg
& TRANS_OK_INT
) {
927 pcr
->trans_result
= TRANS_RESULT_OK
;
933 if (pcr
->card_inserted
|| pcr
->card_removed
)
934 schedule_delayed_work(&pcr
->carddet_work
,
935 msecs_to_jiffies(200));
937 spin_unlock(&pcr
->lock
);
941 static int rtsx_pci_acquire_irq(struct rtsx_pcr
*pcr
)
943 pcr_dbg(pcr
, "%s: pcr->msi_en = %d, pci->irq = %d\n",
944 __func__
, pcr
->msi_en
, pcr
->pci
->irq
);
946 if (request_irq(pcr
->pci
->irq
, rtsx_pci_isr
,
947 pcr
->msi_en
? 0 : IRQF_SHARED
,
948 DRV_NAME_RTSX_PCI
, pcr
)) {
949 dev_err(&(pcr
->pci
->dev
),
950 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
955 pcr
->irq
= pcr
->pci
->irq
;
956 pci_intx(pcr
->pci
, !pcr
->msi_en
);
961 static void rtsx_pci_idle_work(struct work_struct
*work
)
963 struct delayed_work
*dwork
= to_delayed_work(work
);
964 struct rtsx_pcr
*pcr
= container_of(dwork
, struct rtsx_pcr
, idle_work
);
966 pcr_dbg(pcr
, "--> %s\n", __func__
);
968 mutex_lock(&pcr
->pcr_mutex
);
970 pcr
->state
= PDEV_STAT_IDLE
;
972 if (pcr
->ops
->disable_auto_blink
)
973 pcr
->ops
->disable_auto_blink(pcr
);
974 if (pcr
->ops
->turn_off_led
)
975 pcr
->ops
->turn_off_led(pcr
);
978 rtsx_pci_enable_aspm(pcr
);
980 mutex_unlock(&pcr
->pcr_mutex
);
984 static void rtsx_pci_power_off(struct rtsx_pcr
*pcr
, u8 pm_state
)
986 if (pcr
->ops
->turn_off_led
)
987 pcr
->ops
->turn_off_led(pcr
);
989 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
992 rtsx_pci_write_register(pcr
, PETXCFG
, 0x08, 0x08);
993 rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, pm_state
);
995 if (pcr
->ops
->force_power_down
)
996 pcr
->ops
->force_power_down(pcr
, pm_state
);
1000 static int rtsx_pci_init_hw(struct rtsx_pcr
*pcr
)
1004 pcr
->pcie_cap
= pci_find_capability(pcr
->pci
, PCI_CAP_ID_EXP
);
1005 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
1007 rtsx_pci_enable_bus_int(pcr
);
1010 err
= rtsx_pci_write_register(pcr
, FPDCTL
, SSC_POWER_DOWN
, 0);
1014 /* Wait SSC power stable */
1017 rtsx_pci_disable_aspm(pcr
);
1018 if (pcr
->ops
->optimize_phy
) {
1019 err
= pcr
->ops
->optimize_phy(pcr
);
1024 rtsx_pci_init_cmd(pcr
);
1026 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1027 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
, 0x07, 0x07);
1029 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, HOST_SLEEP_STATE
, 0x03, 0x00);
1030 /* Disable card clock */
1031 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, 0x1E, 0);
1032 /* Reset delink mode */
1033 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x0A, 0);
1034 /* Card driving select */
1035 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_DRIVE_SEL
,
1036 0xFF, pcr
->card_drive_sel
);
1037 /* Enable SSC Clock */
1038 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
,
1039 0xFF, SSC_8X_EN
| SSC_SEL_4M
);
1040 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
, 0xFF, 0x12);
1041 /* Disable cd_pwr_save */
1042 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x16, 0x10);
1043 /* Clear Link Ready Interrupt */
1044 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
1045 LINK_RDY_INT
, LINK_RDY_INT
);
1046 /* Enlarge the estimation window of PERST# glitch
1047 * to reduce the chance of invalid card interrupt
1049 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PERST_GLITCH_WIDTH
, 0xFF, 0x80);
1050 /* Update RC oscillator to 400k
1051 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1054 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, RCCTL
, 0x01, 0x00);
1055 /* Set interrupt write clear
1056 * bit 1: U_elbi_if_rd_clr_en
1057 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1058 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1060 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, NFTS_TX_CTRL
, 0x02, 0);
1062 err
= rtsx_pci_send_cmd(pcr
, 100);
1066 /* Enable clk_request_n to enable clock power management */
1067 rtsx_pci_write_config_byte(pcr
, pcr
->pcie_cap
+ PCI_EXP_LNKCTL
+ 1, 1);
1068 /* Enter L1 when host tx idle */
1069 rtsx_pci_write_config_byte(pcr
, 0x70F, 0x5B);
1071 if (pcr
->ops
->extra_init_hw
) {
1072 err
= pcr
->ops
->extra_init_hw(pcr
);
1077 /* No CD interrupt if probing driver with card inserted.
1078 * So we need to initialize pcr->card_exist here.
1080 if (pcr
->ops
->cd_deglitch
)
1081 pcr
->card_exist
= pcr
->ops
->cd_deglitch(pcr
);
1083 pcr
->card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
) & CARD_EXIST
;
1088 static int rtsx_pci_init_chip(struct rtsx_pcr
*pcr
)
1092 spin_lock_init(&pcr
->lock
);
1093 mutex_init(&pcr
->pcr_mutex
);
1095 switch (PCI_PID(pcr
)) {
1098 rts5209_init_params(pcr
);
1102 rts5229_init_params(pcr
);
1106 rtl8411_init_params(pcr
);
1110 rts5227_init_params(pcr
);
1114 rts522a_init_params(pcr
);
1118 rts5249_init_params(pcr
);
1122 rts524a_init_params(pcr
);
1126 rts525a_init_params(pcr
);
1130 rtl8411b_init_params(pcr
);
1134 rtl8402_init_params(pcr
);
1138 pcr_dbg(pcr
, "PID: 0x%04x, IC version: 0x%02x\n",
1139 PCI_PID(pcr
), pcr
->ic_version
);
1141 pcr
->slots
= kcalloc(pcr
->num_slots
, sizeof(struct rtsx_slot
),
1146 if (pcr
->ops
->fetch_vendor_settings
)
1147 pcr
->ops
->fetch_vendor_settings(pcr
);
1149 pcr_dbg(pcr
, "pcr->aspm_en = 0x%x\n", pcr
->aspm_en
);
1150 pcr_dbg(pcr
, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1151 pcr
->sd30_drive_sel_1v8
);
1152 pcr_dbg(pcr
, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1153 pcr
->sd30_drive_sel_3v3
);
1154 pcr_dbg(pcr
, "pcr->card_drive_sel = 0x%x\n",
1155 pcr
->card_drive_sel
);
1156 pcr_dbg(pcr
, "pcr->flags = 0x%x\n", pcr
->flags
);
1158 pcr
->state
= PDEV_STAT_IDLE
;
1159 err
= rtsx_pci_init_hw(pcr
);
1168 static int rtsx_pci_probe(struct pci_dev
*pcidev
,
1169 const struct pci_device_id
*id
)
1171 struct rtsx_pcr
*pcr
;
1172 struct pcr_handle
*handle
;
1174 int ret
, i
, bar
= 0;
1176 dev_dbg(&(pcidev
->dev
),
1177 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1178 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1179 (int)pcidev
->revision
);
1181 ret
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(32));
1185 ret
= pci_enable_device(pcidev
);
1189 ret
= pci_request_regions(pcidev
, DRV_NAME_RTSX_PCI
);
1193 pcr
= kzalloc(sizeof(*pcr
), GFP_KERNEL
);
1199 handle
= kzalloc(sizeof(*handle
), GFP_KERNEL
);
1206 idr_preload(GFP_KERNEL
);
1207 spin_lock(&rtsx_pci_lock
);
1208 ret
= idr_alloc(&rtsx_pci_idr
, pcr
, 0, 0, GFP_NOWAIT
);
1211 spin_unlock(&rtsx_pci_lock
);
1217 dev_set_drvdata(&pcidev
->dev
, handle
);
1219 if (CHK_PCI_PID(pcr
, 0x525A))
1221 len
= pci_resource_len(pcidev
, bar
);
1222 base
= pci_resource_start(pcidev
, bar
);
1223 pcr
->remap_addr
= ioremap_nocache(base
, len
);
1224 if (!pcr
->remap_addr
) {
1229 pcr
->rtsx_resv_buf
= dma_alloc_coherent(&(pcidev
->dev
),
1230 RTSX_RESV_BUF_LEN
, &(pcr
->rtsx_resv_buf_addr
),
1232 if (pcr
->rtsx_resv_buf
== NULL
) {
1236 pcr
->host_cmds_ptr
= pcr
->rtsx_resv_buf
;
1237 pcr
->host_cmds_addr
= pcr
->rtsx_resv_buf_addr
;
1238 pcr
->host_sg_tbl_ptr
= pcr
->rtsx_resv_buf
+ HOST_CMDS_BUF_LEN
;
1239 pcr
->host_sg_tbl_addr
= pcr
->rtsx_resv_buf_addr
+ HOST_CMDS_BUF_LEN
;
1241 pcr
->card_inserted
= 0;
1242 pcr
->card_removed
= 0;
1243 INIT_DELAYED_WORK(&pcr
->carddet_work
, rtsx_pci_card_detect
);
1244 INIT_DELAYED_WORK(&pcr
->idle_work
, rtsx_pci_idle_work
);
1246 pcr
->msi_en
= msi_en
;
1248 ret
= pci_enable_msi(pcidev
);
1250 pcr
->msi_en
= false;
1253 ret
= rtsx_pci_acquire_irq(pcr
);
1257 pci_set_master(pcidev
);
1258 synchronize_irq(pcr
->irq
);
1260 ret
= rtsx_pci_init_chip(pcr
);
1264 for (i
= 0; i
< ARRAY_SIZE(rtsx_pcr_cells
); i
++) {
1265 rtsx_pcr_cells
[i
].platform_data
= handle
;
1266 rtsx_pcr_cells
[i
].pdata_size
= sizeof(*handle
);
1268 ret
= mfd_add_devices(&pcidev
->dev
, pcr
->id
, rtsx_pcr_cells
,
1269 ARRAY_SIZE(rtsx_pcr_cells
), NULL
, 0, NULL
);
1273 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1278 free_irq(pcr
->irq
, (void *)pcr
);
1281 pci_disable_msi(pcr
->pci
);
1282 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1283 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1285 iounmap(pcr
->remap_addr
);
1291 pci_release_regions(pcidev
);
1293 pci_disable_device(pcidev
);
1298 static void rtsx_pci_remove(struct pci_dev
*pcidev
)
1300 struct pcr_handle
*handle
= pci_get_drvdata(pcidev
);
1301 struct rtsx_pcr
*pcr
= handle
->pcr
;
1303 pcr
->remove_pci
= true;
1305 /* Disable interrupts at the pcr level */
1306 spin_lock_irq(&pcr
->lock
);
1307 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
1309 spin_unlock_irq(&pcr
->lock
);
1311 cancel_delayed_work_sync(&pcr
->carddet_work
);
1312 cancel_delayed_work_sync(&pcr
->idle_work
);
1314 mfd_remove_devices(&pcidev
->dev
);
1316 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1317 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1318 free_irq(pcr
->irq
, (void *)pcr
);
1320 pci_disable_msi(pcr
->pci
);
1321 iounmap(pcr
->remap_addr
);
1323 pci_release_regions(pcidev
);
1324 pci_disable_device(pcidev
);
1326 spin_lock(&rtsx_pci_lock
);
1327 idr_remove(&rtsx_pci_idr
, pcr
->id
);
1328 spin_unlock(&rtsx_pci_lock
);
1334 dev_dbg(&(pcidev
->dev
),
1335 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1336 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1341 static int rtsx_pci_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1343 struct pcr_handle
*handle
;
1344 struct rtsx_pcr
*pcr
;
1346 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1348 handle
= pci_get_drvdata(pcidev
);
1351 cancel_delayed_work(&pcr
->carddet_work
);
1352 cancel_delayed_work(&pcr
->idle_work
);
1354 mutex_lock(&pcr
->pcr_mutex
);
1356 rtsx_pci_power_off(pcr
, HOST_ENTER_S3
);
1358 pci_save_state(pcidev
);
1359 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1360 pci_disable_device(pcidev
);
1361 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1363 mutex_unlock(&pcr
->pcr_mutex
);
1367 static int rtsx_pci_resume(struct pci_dev
*pcidev
)
1369 struct pcr_handle
*handle
;
1370 struct rtsx_pcr
*pcr
;
1373 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1375 handle
= pci_get_drvdata(pcidev
);
1378 mutex_lock(&pcr
->pcr_mutex
);
1380 pci_set_power_state(pcidev
, PCI_D0
);
1381 pci_restore_state(pcidev
);
1382 ret
= pci_enable_device(pcidev
);
1385 pci_set_master(pcidev
);
1387 ret
= rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x00);
1391 ret
= rtsx_pci_init_hw(pcr
);
1395 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1398 mutex_unlock(&pcr
->pcr_mutex
);
1402 static void rtsx_pci_shutdown(struct pci_dev
*pcidev
)
1404 struct pcr_handle
*handle
;
1405 struct rtsx_pcr
*pcr
;
1407 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1409 handle
= pci_get_drvdata(pcidev
);
1411 rtsx_pci_power_off(pcr
, HOST_ENTER_S1
);
1413 pci_disable_device(pcidev
);
1416 #else /* CONFIG_PM */
1418 #define rtsx_pci_suspend NULL
1419 #define rtsx_pci_resume NULL
1420 #define rtsx_pci_shutdown NULL
1422 #endif /* CONFIG_PM */
1424 static struct pci_driver rtsx_pci_driver
= {
1425 .name
= DRV_NAME_RTSX_PCI
,
1426 .id_table
= rtsx_pci_ids
,
1427 .probe
= rtsx_pci_probe
,
1428 .remove
= rtsx_pci_remove
,
1429 .suspend
= rtsx_pci_suspend
,
1430 .resume
= rtsx_pci_resume
,
1431 .shutdown
= rtsx_pci_shutdown
,
1433 module_pci_driver(rtsx_pci_driver
);
1435 MODULE_LICENSE("GPL");
1436 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1437 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");