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misc: rtsx: judge ASPM Mode to set PETXCFG Reg
[mirror_ubuntu-kernels.git] / drivers / misc / cardreader / rtsx_pcr.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10 #include <linux/pci.h>
11 #include <linux/module.h>
12 #include <linux/slab.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/highmem.h>
15 #include <linux/interrupt.h>
16 #include <linux/delay.h>
17 #include <linux/idr.h>
18 #include <linux/platform_device.h>
19 #include <linux/mfd/core.h>
20 #include <linux/rtsx_pci.h>
21 #include <linux/mmc/card.h>
22 #include <asm/unaligned.h>
23 #include <linux/pm.h>
24 #include <linux/pm_runtime.h>
25
26 #include "rtsx_pcr.h"
27 #include "rts5261.h"
28 #include "rts5228.h"
29
30 static bool msi_en = true;
31 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
32 MODULE_PARM_DESC(msi_en, "Enable MSI");
33
34 static DEFINE_IDR(rtsx_pci_idr);
35 static DEFINE_SPINLOCK(rtsx_pci_lock);
36
37 static struct mfd_cell rtsx_pcr_cells[] = {
38 [RTSX_SD_CARD] = {
39 .name = DRV_NAME_RTSX_PCI_SDMMC,
40 },
41 };
42
43 static const struct pci_device_id rtsx_pci_ids[] = {
44 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
45 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
46 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
47 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
48 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
49 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
50 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
51 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
52 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
53 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
54 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { 0, }
58 };
59
60 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
61
62 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
63 {
64 rtsx_pci_write_register(pcr, MSGTXDATA0,
65 MASK_8_BIT_DEF, (u8) (latency & 0xFF));
66 rtsx_pci_write_register(pcr, MSGTXDATA1,
67 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
68 rtsx_pci_write_register(pcr, MSGTXDATA2,
69 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
70 rtsx_pci_write_register(pcr, MSGTXDATA3,
71 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
72 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
73 LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
74
75 return 0;
76 }
77
78 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
79 {
80 return rtsx_comm_set_ltr_latency(pcr, latency);
81 }
82
83 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
84 {
85 if (pcr->aspm_enabled == enable)
86 return;
87
88 if (pcr->aspm_mode == ASPM_MODE_CFG) {
89 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
90 PCI_EXP_LNKCTL_ASPMC,
91 enable ? pcr->aspm_en : 0);
92 } else if (pcr->aspm_mode == ASPM_MODE_REG) {
93 if (pcr->aspm_en & 0x02)
94 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
95 FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1);
96 else
97 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
98 FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1);
99 }
100
101 if (!enable && (pcr->aspm_en & 0x02))
102 mdelay(10);
103
104 pcr->aspm_enabled = enable;
105 }
106
107 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
108 {
109 if (pcr->ops->set_aspm)
110 pcr->ops->set_aspm(pcr, false);
111 else
112 rtsx_comm_set_aspm(pcr, false);
113 }
114
115 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
116 {
117 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
118
119 return 0;
120 }
121
122 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
123 {
124 if (pcr->ops->set_l1off_cfg_sub_d0)
125 pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
126 }
127
128 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
129 {
130 struct rtsx_cr_option *option = &pcr->option;
131
132 rtsx_disable_aspm(pcr);
133
134 /* Fixes DMA transfer timeout issue after disabling ASPM on RTS5260 */
135 msleep(1);
136
137 if (option->ltr_enabled)
138 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
139
140 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
141 rtsx_set_l1off_sub_cfg_d0(pcr, 1);
142 }
143
144 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
145 {
146 rtsx_comm_pm_full_on(pcr);
147 }
148
149 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
150 {
151 /* If pci device removed, don't queue idle work any more */
152 if (pcr->remove_pci)
153 return;
154
155 if (pcr->state != PDEV_STAT_RUN) {
156 pcr->state = PDEV_STAT_RUN;
157 if (pcr->ops->enable_auto_blink)
158 pcr->ops->enable_auto_blink(pcr);
159 rtsx_pm_full_on(pcr);
160 }
161 }
162 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
163
164 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
165 {
166 int i;
167 u32 val = HAIMR_WRITE_START;
168
169 val |= (u32)(addr & 0x3FFF) << 16;
170 val |= (u32)mask << 8;
171 val |= (u32)data;
172
173 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
174
175 for (i = 0; i < MAX_RW_REG_CNT; i++) {
176 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
177 if ((val & HAIMR_TRANS_END) == 0) {
178 if (data != (u8)val)
179 return -EIO;
180 return 0;
181 }
182 }
183
184 return -ETIMEDOUT;
185 }
186 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
187
188 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
189 {
190 u32 val = HAIMR_READ_START;
191 int i;
192
193 val |= (u32)(addr & 0x3FFF) << 16;
194 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
195
196 for (i = 0; i < MAX_RW_REG_CNT; i++) {
197 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
198 if ((val & HAIMR_TRANS_END) == 0)
199 break;
200 }
201
202 if (i >= MAX_RW_REG_CNT)
203 return -ETIMEDOUT;
204
205 if (data)
206 *data = (u8)(val & 0xFF);
207
208 return 0;
209 }
210 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
211
212 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
213 {
214 int err, i, finished = 0;
215 u8 tmp;
216
217 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
218 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
219 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
220 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
221
222 for (i = 0; i < 100000; i++) {
223 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
224 if (err < 0)
225 return err;
226
227 if (!(tmp & 0x80)) {
228 finished = 1;
229 break;
230 }
231 }
232
233 if (!finished)
234 return -ETIMEDOUT;
235
236 return 0;
237 }
238
239 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
240 {
241 if (pcr->ops->write_phy)
242 return pcr->ops->write_phy(pcr, addr, val);
243
244 return __rtsx_pci_write_phy_register(pcr, addr, val);
245 }
246 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
247
248 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
249 {
250 int err, i, finished = 0;
251 u16 data;
252 u8 tmp, val1, val2;
253
254 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
255 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
256
257 for (i = 0; i < 100000; i++) {
258 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
259 if (err < 0)
260 return err;
261
262 if (!(tmp & 0x80)) {
263 finished = 1;
264 break;
265 }
266 }
267
268 if (!finished)
269 return -ETIMEDOUT;
270
271 rtsx_pci_read_register(pcr, PHYDATA0, &val1);
272 rtsx_pci_read_register(pcr, PHYDATA1, &val2);
273 data = val1 | (val2 << 8);
274
275 if (val)
276 *val = data;
277
278 return 0;
279 }
280
281 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
282 {
283 if (pcr->ops->read_phy)
284 return pcr->ops->read_phy(pcr, addr, val);
285
286 return __rtsx_pci_read_phy_register(pcr, addr, val);
287 }
288 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
289
290 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
291 {
292 if (pcr->ops->stop_cmd)
293 return pcr->ops->stop_cmd(pcr);
294
295 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
296 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
297
298 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
299 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
300 }
301 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
302
303 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
304 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
305 {
306 unsigned long flags;
307 u32 val = 0;
308 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
309
310 val |= (u32)(cmd_type & 0x03) << 30;
311 val |= (u32)(reg_addr & 0x3FFF) << 16;
312 val |= (u32)mask << 8;
313 val |= (u32)data;
314
315 spin_lock_irqsave(&pcr->lock, flags);
316 ptr += pcr->ci;
317 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
318 put_unaligned_le32(val, ptr);
319 ptr++;
320 pcr->ci++;
321 }
322 spin_unlock_irqrestore(&pcr->lock, flags);
323 }
324 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
325
326 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
327 {
328 u32 val = 1 << 31;
329
330 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
331
332 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
333 /* Hardware Auto Response */
334 val |= 0x40000000;
335 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
336 }
337 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
338
339 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
340 {
341 struct completion trans_done;
342 u32 val = 1 << 31;
343 long timeleft;
344 unsigned long flags;
345 int err = 0;
346
347 spin_lock_irqsave(&pcr->lock, flags);
348
349 /* set up data structures for the wakeup system */
350 pcr->done = &trans_done;
351 pcr->trans_result = TRANS_NOT_READY;
352 init_completion(&trans_done);
353
354 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
355
356 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
357 /* Hardware Auto Response */
358 val |= 0x40000000;
359 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
360
361 spin_unlock_irqrestore(&pcr->lock, flags);
362
363 /* Wait for TRANS_OK_INT */
364 timeleft = wait_for_completion_interruptible_timeout(
365 &trans_done, msecs_to_jiffies(timeout));
366 if (timeleft <= 0) {
367 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
368 err = -ETIMEDOUT;
369 goto finish_send_cmd;
370 }
371
372 spin_lock_irqsave(&pcr->lock, flags);
373 if (pcr->trans_result == TRANS_RESULT_FAIL)
374 err = -EINVAL;
375 else if (pcr->trans_result == TRANS_RESULT_OK)
376 err = 0;
377 else if (pcr->trans_result == TRANS_NO_DEVICE)
378 err = -ENODEV;
379 spin_unlock_irqrestore(&pcr->lock, flags);
380
381 finish_send_cmd:
382 spin_lock_irqsave(&pcr->lock, flags);
383 pcr->done = NULL;
384 spin_unlock_irqrestore(&pcr->lock, flags);
385
386 if ((err < 0) && (err != -ENODEV))
387 rtsx_pci_stop_cmd(pcr);
388
389 if (pcr->finish_me)
390 complete(pcr->finish_me);
391
392 return err;
393 }
394 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
395
396 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
397 dma_addr_t addr, unsigned int len, int end)
398 {
399 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
400 u64 val;
401 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
402
403 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
404
405 if (end)
406 option |= RTSX_SG_END;
407
408 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
409 if (len > 0xFFFF)
410 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
411 | (((u64)len >> 16) << 6) | option;
412 else
413 val = ((u64)addr << 32) | ((u64)len << 16) | option;
414 } else {
415 val = ((u64)addr << 32) | ((u64)len << 12) | option;
416 }
417 put_unaligned_le64(val, ptr);
418 pcr->sgi++;
419 }
420
421 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
422 int num_sg, bool read, int timeout)
423 {
424 int err = 0, count;
425
426 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
427 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
428 if (count < 1)
429 return -EINVAL;
430 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
431
432 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
433
434 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
435
436 return err;
437 }
438 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
439
440 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
441 int num_sg, bool read)
442 {
443 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
444
445 if (pcr->remove_pci)
446 return -EINVAL;
447
448 if ((sglist == NULL) || (num_sg <= 0))
449 return -EINVAL;
450
451 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
452 }
453 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
454
455 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
456 int num_sg, bool read)
457 {
458 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
459
460 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
461 }
462 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
463
464 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
465 int count, bool read, int timeout)
466 {
467 struct completion trans_done;
468 struct scatterlist *sg;
469 dma_addr_t addr;
470 long timeleft;
471 unsigned long flags;
472 unsigned int len;
473 int i, err = 0;
474 u32 val;
475 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
476
477 if (pcr->remove_pci)
478 return -ENODEV;
479
480 if ((sglist == NULL) || (count < 1))
481 return -EINVAL;
482
483 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
484 pcr->sgi = 0;
485 for_each_sg(sglist, sg, count, i) {
486 addr = sg_dma_address(sg);
487 len = sg_dma_len(sg);
488 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
489 }
490
491 spin_lock_irqsave(&pcr->lock, flags);
492
493 pcr->done = &trans_done;
494 pcr->trans_result = TRANS_NOT_READY;
495 init_completion(&trans_done);
496 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
497 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
498
499 spin_unlock_irqrestore(&pcr->lock, flags);
500
501 timeleft = wait_for_completion_interruptible_timeout(
502 &trans_done, msecs_to_jiffies(timeout));
503 if (timeleft <= 0) {
504 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
505 err = -ETIMEDOUT;
506 goto out;
507 }
508
509 spin_lock_irqsave(&pcr->lock, flags);
510 if (pcr->trans_result == TRANS_RESULT_FAIL) {
511 err = -EILSEQ;
512 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
513 pcr->dma_error_count++;
514 }
515
516 else if (pcr->trans_result == TRANS_NO_DEVICE)
517 err = -ENODEV;
518 spin_unlock_irqrestore(&pcr->lock, flags);
519
520 out:
521 spin_lock_irqsave(&pcr->lock, flags);
522 pcr->done = NULL;
523 spin_unlock_irqrestore(&pcr->lock, flags);
524
525 if ((err < 0) && (err != -ENODEV))
526 rtsx_pci_stop_cmd(pcr);
527
528 if (pcr->finish_me)
529 complete(pcr->finish_me);
530
531 return err;
532 }
533 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
534
535 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
536 {
537 int err;
538 int i, j;
539 u16 reg;
540 u8 *ptr;
541
542 if (buf_len > 512)
543 buf_len = 512;
544
545 ptr = buf;
546 reg = PPBUF_BASE2;
547 for (i = 0; i < buf_len / 256; i++) {
548 rtsx_pci_init_cmd(pcr);
549
550 for (j = 0; j < 256; j++)
551 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
552
553 err = rtsx_pci_send_cmd(pcr, 250);
554 if (err < 0)
555 return err;
556
557 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
558 ptr += 256;
559 }
560
561 if (buf_len % 256) {
562 rtsx_pci_init_cmd(pcr);
563
564 for (j = 0; j < buf_len % 256; j++)
565 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
566
567 err = rtsx_pci_send_cmd(pcr, 250);
568 if (err < 0)
569 return err;
570 }
571
572 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
573
574 return 0;
575 }
576 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
577
578 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
579 {
580 int err;
581 int i, j;
582 u16 reg;
583 u8 *ptr;
584
585 if (buf_len > 512)
586 buf_len = 512;
587
588 ptr = buf;
589 reg = PPBUF_BASE2;
590 for (i = 0; i < buf_len / 256; i++) {
591 rtsx_pci_init_cmd(pcr);
592
593 for (j = 0; j < 256; j++) {
594 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
595 reg++, 0xFF, *ptr);
596 ptr++;
597 }
598
599 err = rtsx_pci_send_cmd(pcr, 250);
600 if (err < 0)
601 return err;
602 }
603
604 if (buf_len % 256) {
605 rtsx_pci_init_cmd(pcr);
606
607 for (j = 0; j < buf_len % 256; j++) {
608 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
609 reg++, 0xFF, *ptr);
610 ptr++;
611 }
612
613 err = rtsx_pci_send_cmd(pcr, 250);
614 if (err < 0)
615 return err;
616 }
617
618 return 0;
619 }
620 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
621
622 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
623 {
624 rtsx_pci_init_cmd(pcr);
625
626 while (*tbl & 0xFFFF0000) {
627 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
628 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
629 tbl++;
630 }
631
632 return rtsx_pci_send_cmd(pcr, 100);
633 }
634
635 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
636 {
637 const u32 *tbl;
638
639 if (card == RTSX_SD_CARD)
640 tbl = pcr->sd_pull_ctl_enable_tbl;
641 else if (card == RTSX_MS_CARD)
642 tbl = pcr->ms_pull_ctl_enable_tbl;
643 else
644 return -EINVAL;
645
646 return rtsx_pci_set_pull_ctl(pcr, tbl);
647 }
648 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
649
650 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
651 {
652 const u32 *tbl;
653
654 if (card == RTSX_SD_CARD)
655 tbl = pcr->sd_pull_ctl_disable_tbl;
656 else if (card == RTSX_MS_CARD)
657 tbl = pcr->ms_pull_ctl_disable_tbl;
658 else
659 return -EINVAL;
660
661 return rtsx_pci_set_pull_ctl(pcr, tbl);
662 }
663 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
664
665 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
666 {
667 struct rtsx_hw_param *hw_param = &pcr->hw_param;
668
669 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
670 | hw_param->interrupt_en;
671
672 if (pcr->num_slots > 1)
673 pcr->bier |= MS_INT_EN;
674
675 /* Enable Bus Interrupt */
676 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
677
678 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
679 }
680
681 static inline u8 double_ssc_depth(u8 depth)
682 {
683 return ((depth > 1) ? (depth - 1) : depth);
684 }
685
686 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
687 {
688 if (div > CLK_DIV_1) {
689 if (ssc_depth > (div - 1))
690 ssc_depth -= (div - 1);
691 else
692 ssc_depth = SSC_DEPTH_4M;
693 }
694
695 return ssc_depth;
696 }
697
698 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
699 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
700 {
701 int err, clk;
702 u8 n, clk_divider, mcu_cnt, div;
703 static const u8 depth[] = {
704 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
705 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
706 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
707 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
708 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
709 };
710
711 if (PCI_PID(pcr) == PID_5261)
712 return rts5261_pci_switch_clock(pcr, card_clock,
713 ssc_depth, initial_mode, double_clk, vpclk);
714 if (PCI_PID(pcr) == PID_5228)
715 return rts5228_pci_switch_clock(pcr, card_clock,
716 ssc_depth, initial_mode, double_clk, vpclk);
717
718 if (initial_mode) {
719 /* We use 250k(around) here, in initial stage */
720 clk_divider = SD_CLK_DIVIDE_128;
721 card_clock = 30000000;
722 } else {
723 clk_divider = SD_CLK_DIVIDE_0;
724 }
725 err = rtsx_pci_write_register(pcr, SD_CFG1,
726 SD_CLK_DIVIDE_MASK, clk_divider);
727 if (err < 0)
728 return err;
729
730 /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
731 if (card_clock == UHS_SDR104_MAX_DTR &&
732 pcr->dma_error_count &&
733 PCI_PID(pcr) == RTS5227_DEVICE_ID)
734 card_clock = UHS_SDR104_MAX_DTR -
735 (pcr->dma_error_count * 20000000);
736
737 card_clock /= 1000000;
738 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
739
740 clk = card_clock;
741 if (!initial_mode && double_clk)
742 clk = card_clock * 2;
743 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
744 clk, pcr->cur_clock);
745
746 if (clk == pcr->cur_clock)
747 return 0;
748
749 if (pcr->ops->conv_clk_and_div_n)
750 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
751 else
752 n = (u8)(clk - 2);
753 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
754 return -EINVAL;
755
756 mcu_cnt = (u8)(125/clk + 3);
757 if (mcu_cnt > 15)
758 mcu_cnt = 15;
759
760 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
761 div = CLK_DIV_1;
762 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
763 if (pcr->ops->conv_clk_and_div_n) {
764 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
765 DIV_N_TO_CLK) * 2;
766 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
767 CLK_TO_DIV_N);
768 } else {
769 n = (n + 2) * 2 - 2;
770 }
771 div++;
772 }
773 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
774
775 ssc_depth = depth[ssc_depth];
776 if (double_clk)
777 ssc_depth = double_ssc_depth(ssc_depth);
778
779 ssc_depth = revise_ssc_depth(ssc_depth, div);
780 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
781
782 rtsx_pci_init_cmd(pcr);
783 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
784 CLK_LOW_FREQ, CLK_LOW_FREQ);
785 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
786 0xFF, (div << 4) | mcu_cnt);
787 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
788 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
789 SSC_DEPTH_MASK, ssc_depth);
790 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
791 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
792 if (vpclk) {
793 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
794 PHASE_NOT_RESET, 0);
795 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
796 PHASE_NOT_RESET, PHASE_NOT_RESET);
797 }
798
799 err = rtsx_pci_send_cmd(pcr, 2000);
800 if (err < 0)
801 return err;
802
803 /* Wait SSC clock stable */
804 udelay(SSC_CLOCK_STABLE_WAIT);
805 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
806 if (err < 0)
807 return err;
808
809 pcr->cur_clock = clk;
810 return 0;
811 }
812 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
813
814 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
815 {
816 if (pcr->ops->card_power_on)
817 return pcr->ops->card_power_on(pcr, card);
818
819 return 0;
820 }
821 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
822
823 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
824 {
825 if (pcr->ops->card_power_off)
826 return pcr->ops->card_power_off(pcr, card);
827
828 return 0;
829 }
830 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
831
832 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
833 {
834 static const unsigned int cd_mask[] = {
835 [RTSX_SD_CARD] = SD_EXIST,
836 [RTSX_MS_CARD] = MS_EXIST
837 };
838
839 if (!(pcr->flags & PCR_MS_PMOS)) {
840 /* When using single PMOS, accessing card is not permitted
841 * if the existing card is not the designated one.
842 */
843 if (pcr->card_exist & (~cd_mask[card]))
844 return -EIO;
845 }
846
847 return 0;
848 }
849 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
850
851 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
852 {
853 if (pcr->ops->switch_output_voltage)
854 return pcr->ops->switch_output_voltage(pcr, voltage);
855
856 return 0;
857 }
858 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
859
860 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
861 {
862 unsigned int val;
863
864 val = rtsx_pci_readl(pcr, RTSX_BIPR);
865 if (pcr->ops->cd_deglitch)
866 val = pcr->ops->cd_deglitch(pcr);
867
868 return val;
869 }
870 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
871
872 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
873 {
874 struct completion finish;
875
876 pcr->finish_me = &finish;
877 init_completion(&finish);
878
879 if (pcr->done)
880 complete(pcr->done);
881
882 if (!pcr->remove_pci)
883 rtsx_pci_stop_cmd(pcr);
884
885 wait_for_completion_interruptible_timeout(&finish,
886 msecs_to_jiffies(2));
887 pcr->finish_me = NULL;
888 }
889 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
890
891 static void rtsx_pci_card_detect(struct work_struct *work)
892 {
893 struct delayed_work *dwork;
894 struct rtsx_pcr *pcr;
895 unsigned long flags;
896 unsigned int card_detect = 0, card_inserted, card_removed;
897 u32 irq_status;
898
899 dwork = to_delayed_work(work);
900 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
901
902 pcr_dbg(pcr, "--> %s\n", __func__);
903
904 mutex_lock(&pcr->pcr_mutex);
905 spin_lock_irqsave(&pcr->lock, flags);
906
907 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
908 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
909
910 irq_status &= CARD_EXIST;
911 card_inserted = pcr->card_inserted & irq_status;
912 card_removed = pcr->card_removed;
913 pcr->card_inserted = 0;
914 pcr->card_removed = 0;
915
916 spin_unlock_irqrestore(&pcr->lock, flags);
917
918 if (card_inserted || card_removed) {
919 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
920 card_inserted, card_removed);
921
922 if (pcr->ops->cd_deglitch)
923 card_inserted = pcr->ops->cd_deglitch(pcr);
924
925 card_detect = card_inserted | card_removed;
926
927 pcr->card_exist |= card_inserted;
928 pcr->card_exist &= ~card_removed;
929 }
930
931 mutex_unlock(&pcr->pcr_mutex);
932
933 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
934 pcr->slots[RTSX_SD_CARD].card_event(
935 pcr->slots[RTSX_SD_CARD].p_dev);
936 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
937 pcr->slots[RTSX_MS_CARD].card_event(
938 pcr->slots[RTSX_MS_CARD].p_dev);
939 }
940
941 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
942 {
943 if (pcr->ops->process_ocp) {
944 pcr->ops->process_ocp(pcr);
945 } else {
946 if (!pcr->option.ocp_en)
947 return;
948 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
949 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
950 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
951 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
952 rtsx_pci_clear_ocpstat(pcr);
953 pcr->ocp_stat = 0;
954 }
955 }
956 }
957
958 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
959 {
960 if (pcr->option.ocp_en)
961 rtsx_pci_process_ocp(pcr);
962
963 return 0;
964 }
965
966 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
967 {
968 struct rtsx_pcr *pcr = dev_id;
969 u32 int_reg;
970
971 if (!pcr)
972 return IRQ_NONE;
973
974 spin_lock(&pcr->lock);
975
976 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
977 /* Clear interrupt flag */
978 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
979 if ((int_reg & pcr->bier) == 0) {
980 spin_unlock(&pcr->lock);
981 return IRQ_NONE;
982 }
983 if (int_reg == 0xFFFFFFFF) {
984 spin_unlock(&pcr->lock);
985 return IRQ_HANDLED;
986 }
987
988 int_reg &= (pcr->bier | 0x7FFFFF);
989
990 if (int_reg & SD_OC_INT)
991 rtsx_pci_process_ocp_interrupt(pcr);
992
993 if (int_reg & SD_INT) {
994 if (int_reg & SD_EXIST) {
995 pcr->card_inserted |= SD_EXIST;
996 } else {
997 pcr->card_removed |= SD_EXIST;
998 pcr->card_inserted &= ~SD_EXIST;
999 if (PCI_PID(pcr) == PID_5261) {
1000 rtsx_pci_write_register(pcr, RTS5261_FW_STATUS,
1001 RTS5261_EXPRESS_LINK_FAIL_MASK, 0);
1002 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
1003 }
1004 }
1005 pcr->dma_error_count = 0;
1006 }
1007
1008 if (int_reg & MS_INT) {
1009 if (int_reg & MS_EXIST) {
1010 pcr->card_inserted |= MS_EXIST;
1011 } else {
1012 pcr->card_removed |= MS_EXIST;
1013 pcr->card_inserted &= ~MS_EXIST;
1014 }
1015 }
1016
1017 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
1018 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
1019 pcr->trans_result = TRANS_RESULT_FAIL;
1020 if (pcr->done)
1021 complete(pcr->done);
1022 } else if (int_reg & TRANS_OK_INT) {
1023 pcr->trans_result = TRANS_RESULT_OK;
1024 if (pcr->done)
1025 complete(pcr->done);
1026 }
1027 }
1028
1029 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1030 schedule_delayed_work(&pcr->carddet_work,
1031 msecs_to_jiffies(200));
1032
1033 spin_unlock(&pcr->lock);
1034 return IRQ_HANDLED;
1035 }
1036
1037 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1038 {
1039 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1040 __func__, pcr->msi_en, pcr->pci->irq);
1041
1042 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1043 pcr->msi_en ? 0 : IRQF_SHARED,
1044 DRV_NAME_RTSX_PCI, pcr)) {
1045 dev_err(&(pcr->pci->dev),
1046 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
1047 pcr->pci->irq);
1048 return -1;
1049 }
1050
1051 pcr->irq = pcr->pci->irq;
1052 pci_intx(pcr->pci, !pcr->msi_en);
1053
1054 return 0;
1055 }
1056
1057 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr)
1058 {
1059 /* Set relink_time to 0 */
1060 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1061 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1062 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1063 RELINK_TIME_MASK, 0);
1064
1065 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1066 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
1067
1068 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1069 }
1070
1071 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
1072 {
1073 if (pcr->ops->turn_off_led)
1074 pcr->ops->turn_off_led(pcr);
1075
1076 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1077 pcr->bier = 0;
1078
1079 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1080 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1081
1082 if (pcr->ops->force_power_down)
1083 pcr->ops->force_power_down(pcr, pm_state, runtime);
1084 else
1085 rtsx_base_force_power_down(pcr);
1086 }
1087
1088 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1089 {
1090 u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
1091
1092 if (pcr->ops->enable_ocp) {
1093 pcr->ops->enable_ocp(pcr);
1094 } else {
1095 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1096 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1097 }
1098
1099 }
1100
1101 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1102 {
1103 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
1104
1105 if (pcr->ops->disable_ocp) {
1106 pcr->ops->disable_ocp(pcr);
1107 } else {
1108 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1109 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1110 OC_POWER_DOWN);
1111 }
1112 }
1113
1114 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1115 {
1116 if (pcr->ops->init_ocp) {
1117 pcr->ops->init_ocp(pcr);
1118 } else {
1119 struct rtsx_cr_option *option = &(pcr->option);
1120
1121 if (option->ocp_en) {
1122 u8 val = option->sd_800mA_ocp_thd;
1123
1124 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1125 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1126 SD_OCP_TIME_MASK, SD_OCP_TIME_800);
1127 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1128 SD_OCP_THD_MASK, val);
1129 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1130 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1131 rtsx_pci_enable_ocp(pcr);
1132 }
1133 }
1134 }
1135
1136 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1137 {
1138 if (pcr->ops->get_ocpstat)
1139 return pcr->ops->get_ocpstat(pcr, val);
1140 else
1141 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1142 }
1143
1144 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1145 {
1146 if (pcr->ops->clear_ocpstat) {
1147 pcr->ops->clear_ocpstat(pcr);
1148 } else {
1149 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
1150 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1151
1152 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1153 udelay(100);
1154 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1155 }
1156 }
1157
1158 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1159 {
1160 u16 val;
1161
1162 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1163 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1164 val |= 1<<9;
1165 rtsx_pci_write_phy_register(pcr, 0x01, val);
1166 }
1167 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1168 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1169 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1170 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1171
1172 }
1173
1174 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1175 {
1176 u16 val;
1177
1178 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1179 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1180 val &= ~(1<<9);
1181 rtsx_pci_write_phy_register(pcr, 0x01, val);
1182 }
1183 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1184 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1185
1186 }
1187
1188 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1189 {
1190 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1191 MS_CLK_EN | SD40_CLK_EN, 0);
1192 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1193 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1194
1195 msleep(50);
1196
1197 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1198
1199 return 0;
1200 }
1201
1202 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1203 {
1204 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1205 MS_CLK_EN | SD40_CLK_EN, 0);
1206
1207 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1208
1209 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1210 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1211
1212 return 0;
1213 }
1214
1215 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1216 {
1217 struct pci_dev *pdev = pcr->pci;
1218 int err;
1219
1220 if (PCI_PID(pcr) == PID_5228)
1221 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1222 RTS5228_LDO1_SR_0_5);
1223
1224 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1225
1226 rtsx_pci_enable_bus_int(pcr);
1227
1228 /* Power on SSC */
1229 if (PCI_PID(pcr) == PID_5261) {
1230 /* Gating real mcu clock */
1231 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1232 RTS5261_MCU_CLOCK_GATING, 0);
1233 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1234 SSC_POWER_DOWN, 0);
1235 } else {
1236 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1237 }
1238 if (err < 0)
1239 return err;
1240
1241 /* Wait SSC power stable */
1242 udelay(200);
1243
1244 rtsx_disable_aspm(pcr);
1245 if (pcr->ops->optimize_phy) {
1246 err = pcr->ops->optimize_phy(pcr);
1247 if (err < 0)
1248 return err;
1249 }
1250
1251 rtsx_pci_init_cmd(pcr);
1252
1253 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1254 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1255
1256 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1257 /* Disable card clock */
1258 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1259 /* Reset delink mode */
1260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1261 /* Card driving select */
1262 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1263 0xFF, pcr->card_drive_sel);
1264 /* Enable SSC Clock */
1265 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1266 0xFF, SSC_8X_EN | SSC_SEL_4M);
1267 if (PCI_PID(pcr) == PID_5261)
1268 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1269 RTS5261_SSC_DEPTH_2M);
1270 else if (PCI_PID(pcr) == PID_5228)
1271 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1272 RTS5228_SSC_DEPTH_2M);
1273 else
1274 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1275
1276 /* Disable cd_pwr_save */
1277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1278 /* Clear Link Ready Interrupt */
1279 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1280 LINK_RDY_INT, LINK_RDY_INT);
1281 /* Enlarge the estimation window of PERST# glitch
1282 * to reduce the chance of invalid card interrupt
1283 */
1284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1285 /* Update RC oscillator to 400k
1286 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1287 * 1: 2M 0: 400k
1288 */
1289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1290 /* Set interrupt write clear
1291 * bit 1: U_elbi_if_rd_clr_en
1292 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1293 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1294 */
1295 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1296
1297 err = rtsx_pci_send_cmd(pcr, 100);
1298 if (err < 0)
1299 return err;
1300
1301 switch (PCI_PID(pcr)) {
1302 case PID_5250:
1303 case PID_524A:
1304 case PID_525A:
1305 case PID_5260:
1306 case PID_5261:
1307 case PID_5228:
1308 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1309 break;
1310 default:
1311 break;
1312 }
1313
1314 /*init ocp*/
1315 rtsx_pci_init_ocp(pcr);
1316
1317 /* Enable clk_request_n to enable clock power management */
1318 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
1319 0, PCI_EXP_LNKCTL_CLKREQ_EN);
1320 /* Enter L1 when host tx idle */
1321 pci_write_config_byte(pdev, 0x70F, 0x5B);
1322
1323 if (pcr->ops->extra_init_hw) {
1324 err = pcr->ops->extra_init_hw(pcr);
1325 if (err < 0)
1326 return err;
1327 }
1328
1329 if (pcr->aspm_mode == ASPM_MODE_REG) {
1330 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
1331 rtsx_pci_write_register(pcr, PETXCFG,
1332 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
1333 }
1334
1335 /* No CD interrupt if probing driver with card inserted.
1336 * So we need to initialize pcr->card_exist here.
1337 */
1338 if (pcr->ops->cd_deglitch)
1339 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1340 else
1341 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1342
1343 return 0;
1344 }
1345
1346 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1347 {
1348 int err;
1349 u16 cfg_val;
1350 u8 val;
1351
1352 spin_lock_init(&pcr->lock);
1353 mutex_init(&pcr->pcr_mutex);
1354
1355 switch (PCI_PID(pcr)) {
1356 default:
1357 case 0x5209:
1358 rts5209_init_params(pcr);
1359 break;
1360
1361 case 0x5229:
1362 rts5229_init_params(pcr);
1363 break;
1364
1365 case 0x5289:
1366 rtl8411_init_params(pcr);
1367 break;
1368
1369 case 0x5227:
1370 rts5227_init_params(pcr);
1371 break;
1372
1373 case 0x522A:
1374 rts522a_init_params(pcr);
1375 break;
1376
1377 case 0x5249:
1378 rts5249_init_params(pcr);
1379 break;
1380
1381 case 0x524A:
1382 rts524a_init_params(pcr);
1383 break;
1384
1385 case 0x525A:
1386 rts525a_init_params(pcr);
1387 break;
1388
1389 case 0x5287:
1390 rtl8411b_init_params(pcr);
1391 break;
1392
1393 case 0x5286:
1394 rtl8402_init_params(pcr);
1395 break;
1396
1397 case 0x5260:
1398 rts5260_init_params(pcr);
1399 break;
1400
1401 case 0x5261:
1402 rts5261_init_params(pcr);
1403 break;
1404
1405 case 0x5228:
1406 rts5228_init_params(pcr);
1407 break;
1408 }
1409
1410 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1411 PCI_PID(pcr), pcr->ic_version);
1412
1413 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1414 GFP_KERNEL);
1415 if (!pcr->slots)
1416 return -ENOMEM;
1417
1418 if (pcr->aspm_mode == ASPM_MODE_CFG) {
1419 pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val);
1420 if (cfg_val & PCI_EXP_LNKCTL_ASPM_L1)
1421 pcr->aspm_enabled = true;
1422 else
1423 pcr->aspm_enabled = false;
1424
1425 } else if (pcr->aspm_mode == ASPM_MODE_REG) {
1426 rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
1427 if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1)
1428 pcr->aspm_enabled = false;
1429 else
1430 pcr->aspm_enabled = true;
1431 }
1432
1433 if (pcr->ops->fetch_vendor_settings)
1434 pcr->ops->fetch_vendor_settings(pcr);
1435
1436 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1437 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1438 pcr->sd30_drive_sel_1v8);
1439 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1440 pcr->sd30_drive_sel_3v3);
1441 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1442 pcr->card_drive_sel);
1443 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1444
1445 pcr->state = PDEV_STAT_IDLE;
1446 err = rtsx_pci_init_hw(pcr);
1447 if (err < 0) {
1448 kfree(pcr->slots);
1449 return err;
1450 }
1451
1452 return 0;
1453 }
1454
1455 static int rtsx_pci_probe(struct pci_dev *pcidev,
1456 const struct pci_device_id *id)
1457 {
1458 struct rtsx_pcr *pcr;
1459 struct pcr_handle *handle;
1460 u32 base, len;
1461 int ret, i, bar = 0;
1462
1463 dev_dbg(&(pcidev->dev),
1464 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1465 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1466 (int)pcidev->revision);
1467
1468 ret = dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32));
1469 if (ret < 0)
1470 return ret;
1471
1472 ret = pci_enable_device(pcidev);
1473 if (ret)
1474 return ret;
1475
1476 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1477 if (ret)
1478 goto disable;
1479
1480 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1481 if (!pcr) {
1482 ret = -ENOMEM;
1483 goto release_pci;
1484 }
1485
1486 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1487 if (!handle) {
1488 ret = -ENOMEM;
1489 goto free_pcr;
1490 }
1491 handle->pcr = pcr;
1492
1493 idr_preload(GFP_KERNEL);
1494 spin_lock(&rtsx_pci_lock);
1495 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1496 if (ret >= 0)
1497 pcr->id = ret;
1498 spin_unlock(&rtsx_pci_lock);
1499 idr_preload_end();
1500 if (ret < 0)
1501 goto free_handle;
1502
1503 pcr->pci = pcidev;
1504 dev_set_drvdata(&pcidev->dev, handle);
1505
1506 if (CHK_PCI_PID(pcr, 0x525A))
1507 bar = 1;
1508 len = pci_resource_len(pcidev, bar);
1509 base = pci_resource_start(pcidev, bar);
1510 pcr->remap_addr = ioremap(base, len);
1511 if (!pcr->remap_addr) {
1512 ret = -ENOMEM;
1513 goto free_idr;
1514 }
1515
1516 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1517 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1518 GFP_KERNEL);
1519 if (pcr->rtsx_resv_buf == NULL) {
1520 ret = -ENXIO;
1521 goto unmap;
1522 }
1523 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1524 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1525 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1526 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1527 pcr->card_inserted = 0;
1528 pcr->card_removed = 0;
1529 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1530
1531 pcr->msi_en = msi_en;
1532 if (pcr->msi_en) {
1533 ret = pci_enable_msi(pcidev);
1534 if (ret)
1535 pcr->msi_en = false;
1536 }
1537
1538 ret = rtsx_pci_acquire_irq(pcr);
1539 if (ret < 0)
1540 goto disable_msi;
1541
1542 pci_set_master(pcidev);
1543 synchronize_irq(pcr->irq);
1544
1545 ret = rtsx_pci_init_chip(pcr);
1546 if (ret < 0)
1547 goto disable_irq;
1548
1549 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1550 rtsx_pcr_cells[i].platform_data = handle;
1551 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1552 }
1553
1554
1555 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1556 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1557 if (ret < 0)
1558 goto free_slots;
1559
1560 pm_runtime_allow(&pcidev->dev);
1561 pm_runtime_put(&pcidev->dev);
1562
1563 return 0;
1564
1565 free_slots:
1566 kfree(pcr->slots);
1567 disable_irq:
1568 free_irq(pcr->irq, (void *)pcr);
1569 disable_msi:
1570 if (pcr->msi_en)
1571 pci_disable_msi(pcr->pci);
1572 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1573 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1574 unmap:
1575 iounmap(pcr->remap_addr);
1576 free_idr:
1577 spin_lock(&rtsx_pci_lock);
1578 idr_remove(&rtsx_pci_idr, pcr->id);
1579 spin_unlock(&rtsx_pci_lock);
1580 free_handle:
1581 kfree(handle);
1582 free_pcr:
1583 kfree(pcr);
1584 release_pci:
1585 pci_release_regions(pcidev);
1586 disable:
1587 pci_disable_device(pcidev);
1588
1589 return ret;
1590 }
1591
1592 static void rtsx_pci_remove(struct pci_dev *pcidev)
1593 {
1594 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1595 struct rtsx_pcr *pcr = handle->pcr;
1596
1597 pcr->remove_pci = true;
1598
1599 pm_runtime_get_sync(&pcidev->dev);
1600 pm_runtime_forbid(&pcidev->dev);
1601
1602 /* Disable interrupts at the pcr level */
1603 spin_lock_irq(&pcr->lock);
1604 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1605 pcr->bier = 0;
1606 spin_unlock_irq(&pcr->lock);
1607
1608 cancel_delayed_work_sync(&pcr->carddet_work);
1609
1610 mfd_remove_devices(&pcidev->dev);
1611
1612 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1613 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1614 free_irq(pcr->irq, (void *)pcr);
1615 if (pcr->msi_en)
1616 pci_disable_msi(pcr->pci);
1617 iounmap(pcr->remap_addr);
1618
1619 pci_release_regions(pcidev);
1620 pci_disable_device(pcidev);
1621
1622 spin_lock(&rtsx_pci_lock);
1623 idr_remove(&rtsx_pci_idr, pcr->id);
1624 spin_unlock(&rtsx_pci_lock);
1625
1626 kfree(pcr->slots);
1627 kfree(pcr);
1628 kfree(handle);
1629
1630 dev_dbg(&(pcidev->dev),
1631 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1632 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1633 }
1634
1635 static int __maybe_unused rtsx_pci_suspend(struct device *dev_d)
1636 {
1637 struct pci_dev *pcidev = to_pci_dev(dev_d);
1638 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1639 struct rtsx_pcr *pcr = handle->pcr;
1640
1641 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1642
1643 cancel_delayed_work_sync(&pcr->carddet_work);
1644
1645 mutex_lock(&pcr->pcr_mutex);
1646
1647 rtsx_pci_power_off(pcr, HOST_ENTER_S3, false);
1648
1649 mutex_unlock(&pcr->pcr_mutex);
1650 return 0;
1651 }
1652
1653 static int __maybe_unused rtsx_pci_resume(struct device *dev_d)
1654 {
1655 struct pci_dev *pcidev = to_pci_dev(dev_d);
1656 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1657 struct rtsx_pcr *pcr = handle->pcr;
1658 int ret = 0;
1659
1660 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1661
1662 mutex_lock(&pcr->pcr_mutex);
1663
1664 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1665 if (ret)
1666 goto out;
1667
1668 ret = rtsx_pci_init_hw(pcr);
1669 if (ret)
1670 goto out;
1671
1672 out:
1673 mutex_unlock(&pcr->pcr_mutex);
1674 return ret;
1675 }
1676
1677 #ifdef CONFIG_PM
1678
1679 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1680 {
1681 if (pcr->ops->set_aspm)
1682 pcr->ops->set_aspm(pcr, true);
1683 else
1684 rtsx_comm_set_aspm(pcr, true);
1685 }
1686
1687 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1688 {
1689 struct rtsx_cr_option *option = &pcr->option;
1690
1691 if (option->ltr_enabled) {
1692 u32 latency = option->ltr_l1off_latency;
1693
1694 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1695 mdelay(option->l1_snooze_delay);
1696
1697 rtsx_set_ltr_latency(pcr, latency);
1698 }
1699
1700 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1701 rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1702
1703 rtsx_enable_aspm(pcr);
1704 }
1705
1706 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1707 {
1708 rtsx_comm_pm_power_saving(pcr);
1709 }
1710
1711 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1712 {
1713 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1714 struct rtsx_pcr *pcr = handle->pcr;
1715
1716 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1717
1718 rtsx_pci_power_off(pcr, HOST_ENTER_S1, false);
1719
1720 pci_disable_device(pcidev);
1721 free_irq(pcr->irq, (void *)pcr);
1722 if (pcr->msi_en)
1723 pci_disable_msi(pcr->pci);
1724 }
1725
1726 static int rtsx_pci_runtime_idle(struct device *device)
1727 {
1728 struct pci_dev *pcidev = to_pci_dev(device);
1729 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1730 struct rtsx_pcr *pcr = handle->pcr;
1731
1732 dev_dbg(device, "--> %s\n", __func__);
1733
1734 mutex_lock(&pcr->pcr_mutex);
1735
1736 pcr->state = PDEV_STAT_IDLE;
1737
1738 if (pcr->ops->disable_auto_blink)
1739 pcr->ops->disable_auto_blink(pcr);
1740 if (pcr->ops->turn_off_led)
1741 pcr->ops->turn_off_led(pcr);
1742
1743 rtsx_pm_power_saving(pcr);
1744
1745 mutex_unlock(&pcr->pcr_mutex);
1746
1747 if (pcr->rtd3_en)
1748 pm_schedule_suspend(device, 10000);
1749
1750 return -EBUSY;
1751 }
1752
1753 static int rtsx_pci_runtime_suspend(struct device *device)
1754 {
1755 struct pci_dev *pcidev = to_pci_dev(device);
1756 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1757 struct rtsx_pcr *pcr = handle->pcr;
1758
1759 dev_dbg(device, "--> %s\n", __func__);
1760
1761 cancel_delayed_work_sync(&pcr->carddet_work);
1762
1763 mutex_lock(&pcr->pcr_mutex);
1764 rtsx_pci_power_off(pcr, HOST_ENTER_S3, true);
1765
1766 mutex_unlock(&pcr->pcr_mutex);
1767
1768 return 0;
1769 }
1770
1771 static int rtsx_pci_runtime_resume(struct device *device)
1772 {
1773 struct pci_dev *pcidev = to_pci_dev(device);
1774 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1775 struct rtsx_pcr *pcr = handle->pcr;
1776
1777 dev_dbg(device, "--> %s\n", __func__);
1778
1779 mutex_lock(&pcr->pcr_mutex);
1780
1781 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1782
1783 rtsx_pci_init_hw(pcr);
1784
1785 if (pcr->slots[RTSX_SD_CARD].p_dev != NULL) {
1786 pcr->slots[RTSX_SD_CARD].card_event(
1787 pcr->slots[RTSX_SD_CARD].p_dev);
1788 }
1789
1790 mutex_unlock(&pcr->pcr_mutex);
1791 return 0;
1792 }
1793
1794 #else /* CONFIG_PM */
1795
1796 #define rtsx_pci_shutdown NULL
1797 #define rtsx_pci_runtime_suspend NULL
1798 #define rtsx_pic_runtime_resume NULL
1799
1800 #endif /* CONFIG_PM */
1801
1802 static const struct dev_pm_ops rtsx_pci_pm_ops = {
1803 SET_SYSTEM_SLEEP_PM_OPS(rtsx_pci_suspend, rtsx_pci_resume)
1804 SET_RUNTIME_PM_OPS(rtsx_pci_runtime_suspend, rtsx_pci_runtime_resume, rtsx_pci_runtime_idle)
1805 };
1806
1807 static struct pci_driver rtsx_pci_driver = {
1808 .name = DRV_NAME_RTSX_PCI,
1809 .id_table = rtsx_pci_ids,
1810 .probe = rtsx_pci_probe,
1811 .remove = rtsx_pci_remove,
1812 .driver.pm = &rtsx_pci_pm_ops,
1813 .shutdown = rtsx_pci_shutdown,
1814 };
1815 module_pci_driver(rtsx_pci_driver);
1816
1817 MODULE_LICENSE("GPL");
1818 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1819 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Ubuntu combined Linux kernel mirror