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MAINTAINERS: Update MAX77802 PMIC entry
[mirror_ubuntu-artful-kernel.git] / drivers / misc / cxl / pci.c
1 /*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10 #include <linux/pci_regs.h>
11 #include <linux/pci_ids.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17 #include <linux/pci.h>
18 #include <linux/of.h>
19 #include <linux/delay.h>
20 #include <asm/opal.h>
21 #include <asm/msi_bitmap.h>
22 #include <asm/pnv-pci.h>
23 #include <asm/io.h>
24 #include <asm/reg.h>
25
26 #include "cxl.h"
27 #include <misc/cxl.h>
28
29
30 #define CXL_PCI_VSEC_ID 0x1280
31 #define CXL_VSEC_MIN_SIZE 0x80
32
33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43 #define CXL_STATUS_SECOND_PORT 0x80
44 #define CXL_STATUS_MSI_X_FULL 0x40
45 #define CXL_STATUS_MSI_X_SINGLE 0x20
46 #define CXL_STATUS_FLASH_RW 0x08
47 #define CXL_STATUS_FLASH_RO 0x04
48 #define CXL_STATUS_LOADABLE_AFU 0x02
49 #define CXL_STATUS_LOADABLE_PSL 0x01
50 /* If we see these features we won't try to use the card */
51 #define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
60 #define CXL_VSEC_PROTOCOL_MASK 0xe0
61 #define CXL_VSEC_PROTOCOL_1024TB 0x80
62 #define CXL_VSEC_PROTOCOL_512TB 0x40
63 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
65
66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0xc, dest)
68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xe, dest)
70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71 pci_read_config_byte(dev, vsec + 0xf, dest)
72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73 pci_read_config_word(dev, vsec + 0x10, dest)
74
75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76 pci_read_config_byte(dev, vsec + 0x13, dest)
77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78 pci_write_config_byte(dev, vsec + 0x13, val)
79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
82
83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x20, dest)
85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x24, dest)
87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x28, dest)
89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90 pci_read_config_dword(dev, vsec + 0x2c, dest)
91
92
93 /* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
95 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
96 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
97 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
98 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
99
100 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
101 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
102 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
103 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
104 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
105 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
107 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
108 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
109 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
110 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
112 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
113 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
114 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
115 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
116 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
117 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
118 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
119 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
120
121 static const struct pci_device_id cxl_pci_tbl[] = {
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
126 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
127 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
128 { PCI_DEVICE_CLASS(0x120000, ~0), },
129
130 { }
131 };
132 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
133
134
135 /*
136 * Mostly using these wrappers to avoid confusion:
137 * priv 1 is BAR2, while priv 2 is BAR0
138 */
139 static inline resource_size_t p1_base(struct pci_dev *dev)
140 {
141 return pci_resource_start(dev, 2);
142 }
143
144 static inline resource_size_t p1_size(struct pci_dev *dev)
145 {
146 return pci_resource_len(dev, 2);
147 }
148
149 static inline resource_size_t p2_base(struct pci_dev *dev)
150 {
151 return pci_resource_start(dev, 0);
152 }
153
154 static inline resource_size_t p2_size(struct pci_dev *dev)
155 {
156 return pci_resource_len(dev, 0);
157 }
158
159 static int find_cxl_vsec(struct pci_dev *dev)
160 {
161 int vsec = 0;
162 u16 val;
163
164 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
165 pci_read_config_word(dev, vsec + 0x4, &val);
166 if (val == CXL_PCI_VSEC_ID)
167 return vsec;
168 }
169 return 0;
170
171 }
172
173 static void dump_cxl_config_space(struct pci_dev *dev)
174 {
175 int vsec;
176 u32 val;
177
178 dev_info(&dev->dev, "dump_cxl_config_space\n");
179
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
181 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
183 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
185 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
187 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
189 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
190 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
191 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
192
193 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
194 p1_base(dev), p1_size(dev));
195 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
196 p2_base(dev), p2_size(dev));
197 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
198 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
199
200 if (!(vsec = find_cxl_vsec(dev)))
201 return;
202
203 #define show_reg(name, what) \
204 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
205
206 pci_read_config_dword(dev, vsec + 0x0, &val);
207 show_reg("Cap ID", (val >> 0) & 0xffff);
208 show_reg("Cap Ver", (val >> 16) & 0xf);
209 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
210 pci_read_config_dword(dev, vsec + 0x4, &val);
211 show_reg("VSEC ID", (val >> 0) & 0xffff);
212 show_reg("VSEC Rev", (val >> 16) & 0xf);
213 show_reg("VSEC Length", (val >> 20) & 0xfff);
214 pci_read_config_dword(dev, vsec + 0x8, &val);
215 show_reg("Num AFUs", (val >> 0) & 0xff);
216 show_reg("Status", (val >> 8) & 0xff);
217 show_reg("Mode Control", (val >> 16) & 0xff);
218 show_reg("Reserved", (val >> 24) & 0xff);
219 pci_read_config_dword(dev, vsec + 0xc, &val);
220 show_reg("PSL Rev", (val >> 0) & 0xffff);
221 show_reg("CAIA Ver", (val >> 16) & 0xffff);
222 pci_read_config_dword(dev, vsec + 0x10, &val);
223 show_reg("Base Image Rev", (val >> 0) & 0xffff);
224 show_reg("Reserved", (val >> 16) & 0x0fff);
225 show_reg("Image Control", (val >> 28) & 0x3);
226 show_reg("Reserved", (val >> 30) & 0x1);
227 show_reg("Image Loaded", (val >> 31) & 0x1);
228
229 pci_read_config_dword(dev, vsec + 0x14, &val);
230 show_reg("Reserved", val);
231 pci_read_config_dword(dev, vsec + 0x18, &val);
232 show_reg("Reserved", val);
233 pci_read_config_dword(dev, vsec + 0x1c, &val);
234 show_reg("Reserved", val);
235
236 pci_read_config_dword(dev, vsec + 0x20, &val);
237 show_reg("AFU Descriptor Offset", val);
238 pci_read_config_dword(dev, vsec + 0x24, &val);
239 show_reg("AFU Descriptor Size", val);
240 pci_read_config_dword(dev, vsec + 0x28, &val);
241 show_reg("Problem State Offset", val);
242 pci_read_config_dword(dev, vsec + 0x2c, &val);
243 show_reg("Problem State Size", val);
244
245 pci_read_config_dword(dev, vsec + 0x30, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x34, &val);
248 show_reg("Reserved", val);
249 pci_read_config_dword(dev, vsec + 0x38, &val);
250 show_reg("Reserved", val);
251 pci_read_config_dword(dev, vsec + 0x3c, &val);
252 show_reg("Reserved", val);
253
254 pci_read_config_dword(dev, vsec + 0x40, &val);
255 show_reg("PSL Programming Port", val);
256 pci_read_config_dword(dev, vsec + 0x44, &val);
257 show_reg("PSL Programming Control", val);
258
259 pci_read_config_dword(dev, vsec + 0x48, &val);
260 show_reg("Reserved", val);
261 pci_read_config_dword(dev, vsec + 0x4c, &val);
262 show_reg("Reserved", val);
263
264 pci_read_config_dword(dev, vsec + 0x50, &val);
265 show_reg("Flash Address Register", val);
266 pci_read_config_dword(dev, vsec + 0x54, &val);
267 show_reg("Flash Size Register", val);
268 pci_read_config_dword(dev, vsec + 0x58, &val);
269 show_reg("Flash Status/Control Register", val);
270 pci_read_config_dword(dev, vsec + 0x58, &val);
271 show_reg("Flash Data Port", val);
272
273 #undef show_reg
274 }
275
276 static void dump_afu_descriptor(struct cxl_afu *afu)
277 {
278 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
279 int i;
280
281 #define show_reg(name, what) \
282 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
283
284 val = AFUD_READ_INFO(afu);
285 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
286 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
287 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
288 show_reg("req_prog_mode", val & 0xffffULL);
289 afu_cr_num = AFUD_NUM_CRS(val);
290
291 val = AFUD_READ(afu, 0x8);
292 show_reg("Reserved", val);
293 val = AFUD_READ(afu, 0x10);
294 show_reg("Reserved", val);
295 val = AFUD_READ(afu, 0x18);
296 show_reg("Reserved", val);
297
298 val = AFUD_READ_CR(afu);
299 show_reg("Reserved", (val >> (63-7)) & 0xff);
300 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
301 afu_cr_len = AFUD_CR_LEN(val) * 256;
302
303 val = AFUD_READ_CR_OFF(afu);
304 afu_cr_off = val;
305 show_reg("AFU_CR_offset", val);
306
307 val = AFUD_READ_PPPSA(afu);
308 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
309 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
310
311 val = AFUD_READ_PPPSA_OFF(afu);
312 show_reg("PerProcessPSA_offset", val);
313
314 val = AFUD_READ_EB(afu);
315 show_reg("Reserved", (val >> (63-7)) & 0xff);
316 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
317
318 val = AFUD_READ_EB_OFF(afu);
319 show_reg("AFU_EB_offset", val);
320
321 for (i = 0; i < afu_cr_num; i++) {
322 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
323 show_reg("CR Vendor", val & 0xffff);
324 show_reg("CR Device", (val >> 16) & 0xffff);
325 }
326 #undef show_reg
327 }
328
329 #define P8_CAPP_UNIT0_ID 0xBA
330 #define P8_CAPP_UNIT1_ID 0XBE
331 #define P9_CAPP_UNIT0_ID 0xC0
332 #define P9_CAPP_UNIT1_ID 0xE0
333
334 static int get_phb_index(struct device_node *np, u32 *phb_index)
335 {
336 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
337 return -ENODEV;
338 return 0;
339 }
340
341 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
342 {
343 /*
344 * POWER 8:
345 * - For chips other than POWER8NVL, we only have CAPP 0,
346 * irrespective of which PHB is used.
347 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
348 * CAPP 1 is attached to PHB1.
349 */
350 if (cxl_is_power8()) {
351 if (!pvr_version_is(PVR_POWER8NVL))
352 return P8_CAPP_UNIT0_ID;
353
354 if (phb_index == 0)
355 return P8_CAPP_UNIT0_ID;
356
357 if (phb_index == 1)
358 return P8_CAPP_UNIT1_ID;
359 }
360
361 /*
362 * POWER 9:
363 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
364 * PEC1 (PHB1 - PHB2). No capi mode
365 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
366 */
367 if (cxl_is_power9()) {
368 if (phb_index == 0)
369 return P9_CAPP_UNIT0_ID;
370
371 if (phb_index == 3)
372 return P9_CAPP_UNIT1_ID;
373 }
374
375 return 0;
376 }
377
378 static int calc_capp_routing(struct pci_dev *dev, u64 *chipid,
379 u32 *phb_index, u64 *capp_unit_id)
380 {
381 int rc;
382 struct device_node *np;
383 const __be32 *prop;
384
385 if (!(np = pnv_pci_get_phb_node(dev)))
386 return -ENODEV;
387
388 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
389 np = of_get_next_parent(np);
390 if (!np)
391 return -ENODEV;
392
393 *chipid = be32_to_cpup(prop);
394
395 rc = get_phb_index(np, phb_index);
396 if (rc) {
397 pr_err("cxl: invalid phb index\n");
398 return rc;
399 }
400
401 *capp_unit_id = get_capp_unit_id(np, *phb_index);
402 of_node_put(np);
403 if (!*capp_unit_id) {
404 pr_err("cxl: invalid capp unit id\n");
405 return -ENODEV;
406 }
407
408 return 0;
409 }
410
411 static int init_implementation_adapter_regs_psl9(struct cxl *adapter, struct pci_dev *dev)
412 {
413 u64 xsl_dsnctl, psl_fircntl;
414 u64 chipid;
415 u32 phb_index;
416 u64 capp_unit_id;
417 int rc;
418
419 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
420 if (rc)
421 return rc;
422
423 /*
424 * CAPI Identifier bits [0:7]
425 * bit 61:60 MSI bits --> 0
426 * bit 59 TVT selector --> 0
427 */
428
429 /*
430 * Tell XSL where to route data to.
431 * The field chipid should match the PHB CAPI_CMPM register
432 */
433 xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
434 xsl_dsnctl |= (capp_unit_id << (63-15));
435
436 /* nMMU_ID Defaults to: b’000001001’*/
437 xsl_dsnctl |= ((u64)0x09 << (63-28));
438
439 if (cxl_is_power9() && !cpu_has_feature(CPU_FTR_POWER9_DD1)) {
440 /*
441 * Used to identify CAPI packets which should be sorted into
442 * the Non-Blocking queues by the PHB. This field should match
443 * the PHB PBL_NBW_CMPM register
444 * nbwind=0x03, bits [57:58], must include capi indicator.
445 * Not supported on P9 DD1.
446 */
447 xsl_dsnctl |= ((u64)0x03 << (63-47));
448
449 /*
450 * Upper 16b address bits of ASB_Notify messages sent to the
451 * system. Need to match the PHB’s ASN Compare/Mask Register.
452 * Not supported on P9 DD1.
453 */
454 xsl_dsnctl |= ((u64)0x04 << (63-55));
455 }
456
457 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
458
459 /* Set fir_cntl to recommended value for production env */
460 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
461 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
462 psl_fircntl |= 0x1ULL; /* ce_thresh */
463 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
464
465 /* vccredits=0x1 pcklat=0x4 */
466 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
467
468 /*
469 * For debugging with trace arrays.
470 * Configure RX trace 0 segmented mode.
471 * Configure CT trace 0 segmented mode.
472 * Configure LA0 trace 0 segmented mode.
473 * Configure LA1 trace 0 segmented mode.
474 */
475 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
476 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
477 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
478 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
479
480 /*
481 * A response to an ASB_Notify request is returned by the
482 * system as an MMIO write to the address defined in
483 * the PSL_TNR_ADDR register
484 */
485 /* PSL_TNR_ADDR */
486
487 /* NORST */
488 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
489
490 /* allocate the apc machines */
491 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
492
493 /* Disable vc dd1 fix */
494 if ((cxl_is_power9() && cpu_has_feature(CPU_FTR_POWER9_DD1)))
495 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
496
497 return 0;
498 }
499
500 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
501 {
502 u64 psl_dsnctl, psl_fircntl;
503 u64 chipid;
504 u32 phb_index;
505 u64 capp_unit_id;
506 int rc;
507
508 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
509 if (rc)
510 return rc;
511
512 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
513 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
514 /* Tell PSL where to route data to */
515 psl_dsnctl |= (chipid << (63-5));
516 psl_dsnctl |= (capp_unit_id << (63-13));
517
518 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
519 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
520 /* snoop write mask */
521 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
522 /* set fir_cntl to recommended value for production env */
523 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
524 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
525 psl_fircntl |= 0x1ULL; /* ce_thresh */
526 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
527 /* for debugging with trace arrays */
528 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
529
530 return 0;
531 }
532
533 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
534 {
535 u64 xsl_dsnctl;
536 u64 chipid;
537 u32 phb_index;
538 u64 capp_unit_id;
539 int rc;
540
541 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
542 if (rc)
543 return rc;
544
545 /* Tell XSL where to route data to */
546 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
547 xsl_dsnctl |= (capp_unit_id << (63-13));
548 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
549
550 return 0;
551 }
552
553 /* PSL & XSL */
554 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
555 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
556 /* For the PSL this is a multiple for 0 < n <= 7: */
557 #define PSL_2048_250MHZ_CYCLES 1
558
559 static void write_timebase_ctrl_psl9(struct cxl *adapter)
560 {
561 cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
562 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
563 }
564
565 static void write_timebase_ctrl_psl8(struct cxl *adapter)
566 {
567 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
568 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
569 }
570
571 /* XSL */
572 #define TBSYNC_ENA (1ULL << 63)
573 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
574 #define XSL_2000_CLOCKS 1
575 #define XSL_4000_CLOCKS 2
576 #define XSL_8000_CLOCKS 3
577
578 static void write_timebase_ctrl_xsl(struct cxl *adapter)
579 {
580 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
581 TBSYNC_ENA |
582 TBSYNC_CAL(3) |
583 TBSYNC_CNT(XSL_4000_CLOCKS));
584 }
585
586 static u64 timebase_read_psl9(struct cxl *adapter)
587 {
588 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
589 }
590
591 static u64 timebase_read_psl8(struct cxl *adapter)
592 {
593 return cxl_p1_read(adapter, CXL_PSL_Timebase);
594 }
595
596 static u64 timebase_read_xsl(struct cxl *adapter)
597 {
598 return cxl_p1_read(adapter, CXL_XSL_Timebase);
599 }
600
601 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
602 {
603 u64 psl_tb;
604 int delta;
605 unsigned int retry = 0;
606 struct device_node *np;
607
608 adapter->psl_timebase_synced = false;
609
610 if (!(np = pnv_pci_get_phb_node(dev)))
611 return;
612
613 /* Do not fail when CAPP timebase sync is not supported by OPAL */
614 of_node_get(np);
615 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
616 of_node_put(np);
617 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
618 return;
619 }
620 of_node_put(np);
621
622 /*
623 * Setup PSL Timebase Control and Status register
624 * with the recommended Timebase Sync Count value
625 */
626 adapter->native->sl_ops->write_timebase_ctrl(adapter);
627
628 /* Enable PSL Timebase */
629 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
630 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
631
632 /* Wait until CORE TB and PSL TB difference <= 16usecs */
633 do {
634 msleep(1);
635 if (retry++ > 5) {
636 dev_info(&dev->dev, "PSL timebase can't synchronize\n");
637 return;
638 }
639 psl_tb = adapter->native->sl_ops->timebase_read(adapter);
640 delta = mftb() - psl_tb;
641 if (delta < 0)
642 delta = -delta;
643 } while (tb_to_ns(delta) > 16000);
644
645 adapter->psl_timebase_synced = true;
646 return;
647 }
648
649 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
650 {
651 return 0;
652 }
653
654 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
655 {
656 /* read/write masks for this slice */
657 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
658 /* APC read/write masks for this slice */
659 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
660 /* for debugging with trace arrays */
661 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
662 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
663
664 return 0;
665 }
666
667 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
668 unsigned int virq)
669 {
670 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
671
672 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
673 }
674
675 int cxl_update_image_control(struct cxl *adapter)
676 {
677 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
678 int rc;
679 int vsec;
680 u8 image_state;
681
682 if (!(vsec = find_cxl_vsec(dev))) {
683 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
684 return -ENODEV;
685 }
686
687 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
688 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
689 return rc;
690 }
691
692 if (adapter->perst_loads_image)
693 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
694 else
695 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
696
697 if (adapter->perst_select_user)
698 image_state |= CXL_VSEC_PERST_SELECT_USER;
699 else
700 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
701
702 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
703 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
704 return rc;
705 }
706
707 return 0;
708 }
709
710 int cxl_pci_alloc_one_irq(struct cxl *adapter)
711 {
712 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
713
714 return pnv_cxl_alloc_hwirqs(dev, 1);
715 }
716
717 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
718 {
719 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
720
721 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
722 }
723
724 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
725 struct cxl *adapter, unsigned int num)
726 {
727 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
728
729 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
730 }
731
732 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
733 struct cxl *adapter)
734 {
735 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
736
737 pnv_cxl_release_hwirq_ranges(irqs, dev);
738 }
739
740 static int setup_cxl_bars(struct pci_dev *dev)
741 {
742 /* Safety check in case we get backported to < 3.17 without M64 */
743 if ((p1_base(dev) < 0x100000000ULL) ||
744 (p2_base(dev) < 0x100000000ULL)) {
745 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
746 return -ENODEV;
747 }
748
749 /*
750 * BAR 4/5 has a special meaning for CXL and must be programmed with a
751 * special value corresponding to the CXL protocol address range.
752 * For POWER 8/9 that means bits 48:49 must be set to 10
753 */
754 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
755 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
756
757 return 0;
758 }
759
760 #ifdef CONFIG_CXL_BIMODAL
761
762 struct cxl_switch_work {
763 struct pci_dev *dev;
764 struct work_struct work;
765 int vsec;
766 int mode;
767 };
768
769 static void switch_card_to_cxl(struct work_struct *work)
770 {
771 struct cxl_switch_work *switch_work =
772 container_of(work, struct cxl_switch_work, work);
773 struct pci_dev *dev = switch_work->dev;
774 struct pci_bus *bus = dev->bus;
775 struct pci_controller *hose = pci_bus_to_host(bus);
776 struct pci_dev *bridge;
777 struct pnv_php_slot *php_slot;
778 unsigned int devfn;
779 u8 val;
780 int rc;
781
782 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
783 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
784 bus_list);
785 if (!bridge) {
786 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
787 goto err_dev_put;
788 }
789
790 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
791 if (!php_slot) {
792 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
793 "information. You may need to upgrade "
794 "skiboot. Aborting.\n");
795 goto err_dev_put;
796 }
797
798 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
799 if (rc) {
800 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
801 goto err_dev_put;
802 }
803 devfn = dev->devfn;
804
805 /* Release the reference obtained in cxl_check_and_switch_mode() */
806 pci_dev_put(dev);
807
808 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
809 pci_lock_rescan_remove();
810 pci_hp_remove_devices(bridge->subordinate);
811 pci_unlock_rescan_remove();
812
813 /* Switch the CXL protocol on the card */
814 if (switch_work->mode == CXL_BIMODE_CXL) {
815 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
816 val &= ~CXL_VSEC_PROTOCOL_MASK;
817 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
818 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
819 if (rc) {
820 dev_err(&bus->dev, "cxl: Failed to enable kernel API"
821 " on real PHB, aborting\n");
822 goto err_free_work;
823 }
824 } else {
825 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
826 goto err_free_work;
827 }
828
829 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
830 if (rc) {
831 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
832 goto err_free_work;
833 }
834
835 /*
836 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
837 * we must wait 100ms after this mode switch before touching PCIe config
838 * space.
839 */
840 msleep(100);
841
842 /*
843 * Hot reset to cause the card to come back in cxl mode. A
844 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
845 * in skiboot, so we use a hot reset instead.
846 *
847 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
848 * guaranteed to sit directly under the root port, and setting the reset
849 * state on a device directly under the root port is equivalent to doing
850 * it on the root port iself.
851 */
852 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
853 pci_set_pcie_reset_state(bridge, pcie_hot_reset);
854 pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
855
856 dev_dbg(&bus->dev, "cxl: Offlining slot\n");
857 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
858 if (rc) {
859 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
860 goto err_free_work;
861 }
862
863 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
864 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
865 if (rc) {
866 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
867 goto err_free_work;
868 }
869
870 pci_lock_rescan_remove();
871 pci_hp_add_devices(bridge->subordinate);
872 pci_unlock_rescan_remove();
873
874 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
875 kfree(switch_work);
876 return;
877
878 err_dev_put:
879 /* Release the reference obtained in cxl_check_and_switch_mode() */
880 pci_dev_put(dev);
881 err_free_work:
882 kfree(switch_work);
883 }
884
885 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
886 {
887 struct cxl_switch_work *work;
888 u8 val;
889 int rc;
890
891 if (!cpu_has_feature(CPU_FTR_HVMODE))
892 return -ENODEV;
893
894 if (!vsec) {
895 vsec = find_cxl_vsec(dev);
896 if (!vsec) {
897 dev_info(&dev->dev, "CXL VSEC not found\n");
898 return -ENODEV;
899 }
900 }
901
902 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
903 if (rc) {
904 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
905 return rc;
906 }
907
908 if (mode == CXL_BIMODE_PCI) {
909 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
910 dev_info(&dev->dev, "Card is already in PCI mode\n");
911 return 0;
912 }
913 /*
914 * TODO: Before it's safe to switch the card back to PCI mode
915 * we need to disable the CAPP and make sure any cachelines the
916 * card holds have been flushed out. Needs skiboot support.
917 */
918 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
919 return -EIO;
920 }
921
922 if (val & CXL_VSEC_PROTOCOL_ENABLE) {
923 dev_info(&dev->dev, "Card is already in CXL mode\n");
924 return 0;
925 }
926
927 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
928 "to switch to CXL mode\n");
929
930 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
931 if (!work)
932 return -ENOMEM;
933
934 pci_dev_get(dev);
935 work->dev = dev;
936 work->vsec = vsec;
937 work->mode = mode;
938 INIT_WORK(&work->work, switch_card_to_cxl);
939
940 schedule_work(&work->work);
941
942 /*
943 * We return a failure now to abort the driver init. Once the
944 * link has been cycled and the card is in cxl mode we will
945 * come back (possibly using the generic cxl driver), but
946 * return success as the card should then be in cxl mode.
947 *
948 * TODO: What if the card comes back in PCI mode even after
949 * the switch? Don't want to spin endlessly.
950 */
951 return -EBUSY;
952 }
953 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
954
955 #endif /* CONFIG_CXL_BIMODAL */
956
957 static int setup_cxl_protocol_area(struct pci_dev *dev)
958 {
959 u8 val;
960 int rc;
961 int vsec = find_cxl_vsec(dev);
962
963 if (!vsec) {
964 dev_info(&dev->dev, "CXL VSEC not found\n");
965 return -ENODEV;
966 }
967
968 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
969 if (rc) {
970 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
971 return rc;
972 }
973
974 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
975 dev_err(&dev->dev, "Card not in CAPI mode!\n");
976 return -EIO;
977 }
978
979 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
980 val &= ~CXL_VSEC_PROTOCOL_MASK;
981 val |= CXL_VSEC_PROTOCOL_256TB;
982 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
983 if (rc) {
984 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
985 return rc;
986 }
987 }
988
989 return 0;
990 }
991
992 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
993 {
994 u64 p1n_base, p2n_base, afu_desc;
995 const u64 p1n_size = 0x100;
996 const u64 p2n_size = 0x1000;
997
998 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
999 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
1000 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
1001 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1002
1003 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
1004 goto err;
1005 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1006 goto err1;
1007 if (afu_desc) {
1008 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
1009 goto err2;
1010 }
1011
1012 return 0;
1013 err2:
1014 iounmap(afu->p2n_mmio);
1015 err1:
1016 iounmap(afu->native->p1n_mmio);
1017 err:
1018 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1019 return -ENOMEM;
1020 }
1021
1022 static void pci_unmap_slice_regs(struct cxl_afu *afu)
1023 {
1024 if (afu->p2n_mmio) {
1025 iounmap(afu->p2n_mmio);
1026 afu->p2n_mmio = NULL;
1027 }
1028 if (afu->native->p1n_mmio) {
1029 iounmap(afu->native->p1n_mmio);
1030 afu->native->p1n_mmio = NULL;
1031 }
1032 if (afu->native->afu_desc_mmio) {
1033 iounmap(afu->native->afu_desc_mmio);
1034 afu->native->afu_desc_mmio = NULL;
1035 }
1036 }
1037
1038 void cxl_pci_release_afu(struct device *dev)
1039 {
1040 struct cxl_afu *afu = to_cxl_afu(dev);
1041
1042 pr_devel("%s\n", __func__);
1043
1044 idr_destroy(&afu->contexts_idr);
1045 cxl_release_spa(afu);
1046
1047 kfree(afu->native);
1048 kfree(afu);
1049 }
1050
1051 /* Expects AFU struct to have recently been zeroed out */
1052 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1053 {
1054 u64 val;
1055
1056 val = AFUD_READ_INFO(afu);
1057 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1058 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
1059 afu->crs_num = AFUD_NUM_CRS(val);
1060
1061 if (AFUD_AFU_DIRECTED(val))
1062 afu->modes_supported |= CXL_MODE_DIRECTED;
1063 if (AFUD_DEDICATED_PROCESS(val))
1064 afu->modes_supported |= CXL_MODE_DEDICATED;
1065 if (AFUD_TIME_SLICED(val))
1066 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1067
1068 val = AFUD_READ_PPPSA(afu);
1069 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1070 afu->psa = AFUD_PPPSA_PSA(val);
1071 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
1072 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
1073
1074 val = AFUD_READ_CR(afu);
1075 afu->crs_len = AFUD_CR_LEN(val) * 256;
1076 afu->crs_offset = AFUD_READ_CR_OFF(afu);
1077
1078
1079 /* eb_len is in multiple of 4K */
1080 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1081 afu->eb_offset = AFUD_READ_EB_OFF(afu);
1082
1083 /* eb_off is 4K aligned so lower 12 bits are always zero */
1084 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1085 dev_warn(&afu->dev,
1086 "Invalid AFU error buffer offset %Lx\n",
1087 afu->eb_offset);
1088 dev_info(&afu->dev,
1089 "Ignoring AFU error buffer in the descriptor\n");
1090 /* indicate that no afu buffer exists */
1091 afu->eb_len = 0;
1092 }
1093
1094 return 0;
1095 }
1096
1097 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1098 {
1099 int i, rc;
1100 u32 val;
1101
1102 if (afu->psa && afu->adapter->ps_size <
1103 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
1104 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1105 return -ENODEV;
1106 }
1107
1108 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
1109 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
1110
1111 for (i = 0; i < afu->crs_num; i++) {
1112 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1113 if (rc || val == 0) {
1114 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1115 return -EINVAL;
1116 }
1117 }
1118
1119 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1120 /*
1121 * We could also check this for the dedicated process model
1122 * since the architecture indicates it should be set to 1, but
1123 * in that case we ignore the value and I'd rather not risk
1124 * breaking any existing dedicated process AFUs that left it as
1125 * 0 (not that I'm aware of any). It is clearly an error for an
1126 * AFU directed AFU to set this to 0, and would have previously
1127 * triggered a bug resulting in the maximum not being enforced
1128 * at all since idr_alloc treats 0 as no maximum.
1129 */
1130 dev_err(&afu->dev, "AFU does not support any processes\n");
1131 return -EINVAL;
1132 }
1133
1134 return 0;
1135 }
1136
1137 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1138 {
1139 u64 reg;
1140
1141 /*
1142 * Clear out any regs that contain either an IVTE or address or may be
1143 * waiting on an acknowledgment to try to be a bit safer as we bring
1144 * it online
1145 */
1146 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1147 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1148 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1149 if (cxl_ops->afu_reset(afu))
1150 return -EIO;
1151 if (cxl_afu_disable(afu))
1152 return -EIO;
1153 if (cxl_psl_purge(afu))
1154 return -EIO;
1155 }
1156 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1157 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1158 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1159 if (reg) {
1160 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1161 if (reg & CXL_PSL9_DSISR_An_TF)
1162 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1163 else
1164 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1165 }
1166 if (afu->adapter->native->sl_ops->register_serr_irq) {
1167 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1168 if (reg) {
1169 if (reg & ~0x000000007fffffff)
1170 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1171 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1172 }
1173 }
1174 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1175 if (reg) {
1176 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1177 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1178 }
1179
1180 return 0;
1181 }
1182
1183 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
1184 {
1185 u64 reg;
1186
1187 /*
1188 * Clear out any regs that contain either an IVTE or address or may be
1189 * waiting on an acknowledgement to try to be a bit safer as we bring
1190 * it online
1191 */
1192 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1193 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1194 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1195 if (cxl_ops->afu_reset(afu))
1196 return -EIO;
1197 if (cxl_afu_disable(afu))
1198 return -EIO;
1199 if (cxl_psl_purge(afu))
1200 return -EIO;
1201 }
1202 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1203 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1204 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1205 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1206 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1207 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1208 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1209 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1210 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1211 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1212 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1213 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1214 if (reg) {
1215 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1216 if (reg & CXL_PSL_DSISR_TRANS)
1217 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1218 else
1219 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1220 }
1221 if (afu->adapter->native->sl_ops->register_serr_irq) {
1222 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1223 if (reg) {
1224 if (reg & ~0xffff)
1225 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1226 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1227 }
1228 }
1229 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1230 if (reg) {
1231 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1232 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1233 }
1234
1235 return 0;
1236 }
1237
1238 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1239 /*
1240 * afu_eb_read:
1241 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1242 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1243 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1244 */
1245 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1246 loff_t off, size_t count)
1247 {
1248 loff_t aligned_start, aligned_end;
1249 size_t aligned_length;
1250 void *tbuf;
1251 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1252
1253 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1254 return 0;
1255
1256 /* calculate aligned read window */
1257 count = min((size_t)(afu->eb_len - off), count);
1258 aligned_start = round_down(off, 8);
1259 aligned_end = round_up(off + count, 8);
1260 aligned_length = aligned_end - aligned_start;
1261
1262 /* max we can copy in one read is PAGE_SIZE */
1263 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1264 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1265 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1266 }
1267
1268 /* use bounce buffer for copy */
1269 tbuf = (void *)__get_free_page(GFP_TEMPORARY);
1270 if (!tbuf)
1271 return -ENOMEM;
1272
1273 /* perform aligned read from the mmio region */
1274 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1275 memcpy(buf, tbuf + (off & 0x7), count);
1276
1277 free_page((unsigned long)tbuf);
1278
1279 return count;
1280 }
1281
1282 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1283 {
1284 int rc;
1285
1286 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1287 return rc;
1288
1289 if (adapter->native->sl_ops->sanitise_afu_regs) {
1290 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1291 if (rc)
1292 goto err1;
1293 }
1294
1295 /* We need to reset the AFU before we can read the AFU descriptor */
1296 if ((rc = cxl_ops->afu_reset(afu)))
1297 goto err1;
1298
1299 if (cxl_verbose)
1300 dump_afu_descriptor(afu);
1301
1302 if ((rc = cxl_read_afu_descriptor(afu)))
1303 goto err1;
1304
1305 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1306 goto err1;
1307
1308 if (adapter->native->sl_ops->afu_regs_init)
1309 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1310 goto err1;
1311
1312 if (adapter->native->sl_ops->register_serr_irq)
1313 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1314 goto err1;
1315
1316 if ((rc = cxl_native_register_psl_irq(afu)))
1317 goto err2;
1318
1319 atomic_set(&afu->configured_state, 0);
1320 return 0;
1321
1322 err2:
1323 if (adapter->native->sl_ops->release_serr_irq)
1324 adapter->native->sl_ops->release_serr_irq(afu);
1325 err1:
1326 pci_unmap_slice_regs(afu);
1327 return rc;
1328 }
1329
1330 static void pci_deconfigure_afu(struct cxl_afu *afu)
1331 {
1332 /*
1333 * It's okay to deconfigure when AFU is already locked, otherwise wait
1334 * until there are no readers
1335 */
1336 if (atomic_read(&afu->configured_state) != -1) {
1337 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1338 schedule();
1339 }
1340 cxl_native_release_psl_irq(afu);
1341 if (afu->adapter->native->sl_ops->release_serr_irq)
1342 afu->adapter->native->sl_ops->release_serr_irq(afu);
1343 pci_unmap_slice_regs(afu);
1344 }
1345
1346 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1347 {
1348 struct cxl_afu *afu;
1349 int rc = -ENOMEM;
1350
1351 afu = cxl_alloc_afu(adapter, slice);
1352 if (!afu)
1353 return -ENOMEM;
1354
1355 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1356 if (!afu->native)
1357 goto err_free_afu;
1358
1359 mutex_init(&afu->native->spa_mutex);
1360
1361 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1362 if (rc)
1363 goto err_free_native;
1364
1365 rc = pci_configure_afu(afu, adapter, dev);
1366 if (rc)
1367 goto err_free_native;
1368
1369 /* Don't care if this fails */
1370 cxl_debugfs_afu_add(afu);
1371
1372 /*
1373 * After we call this function we must not free the afu directly, even
1374 * if it returns an error!
1375 */
1376 if ((rc = cxl_register_afu(afu)))
1377 goto err_put1;
1378
1379 if ((rc = cxl_sysfs_afu_add(afu)))
1380 goto err_put1;
1381
1382 adapter->afu[afu->slice] = afu;
1383
1384 if ((rc = cxl_pci_vphb_add(afu)))
1385 dev_info(&afu->dev, "Can't register vPHB\n");
1386
1387 return 0;
1388
1389 err_put1:
1390 pci_deconfigure_afu(afu);
1391 cxl_debugfs_afu_remove(afu);
1392 device_unregister(&afu->dev);
1393 return rc;
1394
1395 err_free_native:
1396 kfree(afu->native);
1397 err_free_afu:
1398 kfree(afu);
1399 return rc;
1400
1401 }
1402
1403 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1404 {
1405 pr_devel("%s\n", __func__);
1406
1407 if (!afu)
1408 return;
1409
1410 cxl_pci_vphb_remove(afu);
1411 cxl_sysfs_afu_remove(afu);
1412 cxl_debugfs_afu_remove(afu);
1413
1414 spin_lock(&afu->adapter->afu_list_lock);
1415 afu->adapter->afu[afu->slice] = NULL;
1416 spin_unlock(&afu->adapter->afu_list_lock);
1417
1418 cxl_context_detach_all(afu);
1419 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1420
1421 pci_deconfigure_afu(afu);
1422 device_unregister(&afu->dev);
1423 }
1424
1425 int cxl_pci_reset(struct cxl *adapter)
1426 {
1427 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1428 int rc;
1429
1430 if (adapter->perst_same_image) {
1431 dev_warn(&dev->dev,
1432 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1433 return -EINVAL;
1434 }
1435
1436 dev_info(&dev->dev, "CXL reset\n");
1437
1438 /*
1439 * The adapter is about to be reset, so ignore errors.
1440 * Not supported on P9 DD1
1441 */
1442 if ((cxl_is_power8()) ||
1443 ((cxl_is_power9() && !cpu_has_feature(CPU_FTR_POWER9_DD1))))
1444 cxl_data_cache_flush(adapter);
1445
1446 /* pcie_warm_reset requests a fundamental pci reset which includes a
1447 * PERST assert/deassert. PERST triggers a loading of the image
1448 * if "user" or "factory" is selected in sysfs */
1449 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1450 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1451 return rc;
1452 }
1453
1454 return rc;
1455 }
1456
1457 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1458 {
1459 if (pci_request_region(dev, 2, "priv 2 regs"))
1460 goto err1;
1461 if (pci_request_region(dev, 0, "priv 1 regs"))
1462 goto err2;
1463
1464 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1465 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1466
1467 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1468 goto err3;
1469
1470 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1471 goto err4;
1472
1473 return 0;
1474
1475 err4:
1476 iounmap(adapter->native->p1_mmio);
1477 adapter->native->p1_mmio = NULL;
1478 err3:
1479 pci_release_region(dev, 0);
1480 err2:
1481 pci_release_region(dev, 2);
1482 err1:
1483 return -ENOMEM;
1484 }
1485
1486 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1487 {
1488 if (adapter->native->p1_mmio) {
1489 iounmap(adapter->native->p1_mmio);
1490 adapter->native->p1_mmio = NULL;
1491 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1492 }
1493 if (adapter->native->p2_mmio) {
1494 iounmap(adapter->native->p2_mmio);
1495 adapter->native->p2_mmio = NULL;
1496 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1497 }
1498 }
1499
1500 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1501 {
1502 int vsec;
1503 u32 afu_desc_off, afu_desc_size;
1504 u32 ps_off, ps_size;
1505 u16 vseclen;
1506 u8 image_state;
1507
1508 if (!(vsec = find_cxl_vsec(dev))) {
1509 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1510 return -ENODEV;
1511 }
1512
1513 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1514 if (vseclen < CXL_VSEC_MIN_SIZE) {
1515 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1516 return -EINVAL;
1517 }
1518
1519 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1520 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1521 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1522 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1523 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1524 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1525 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1526 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1527 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1528
1529 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1530 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1531 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1532 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1533 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1534
1535 /* Convert everything to bytes, because there is NO WAY I'd look at the
1536 * code a month later and forget what units these are in ;-) */
1537 adapter->native->ps_off = ps_off * 64 * 1024;
1538 adapter->ps_size = ps_size * 64 * 1024;
1539 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1540 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1541
1542 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1543 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1544
1545 return 0;
1546 }
1547
1548 /*
1549 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1550 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1551 * reported. Mask this error in the Uncorrectable Error Mask Register.
1552 *
1553 * The upper nibble of the PSL revision is used to distinguish between
1554 * different cards. The affected ones have it set to 0.
1555 */
1556 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1557 {
1558 int aer;
1559 u32 data;
1560
1561 if (adapter->psl_rev & 0xf000)
1562 return;
1563 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1564 return;
1565 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1566 if (data & PCI_ERR_UNC_MALF_TLP)
1567 if (data & PCI_ERR_UNC_INTN)
1568 return;
1569 data |= PCI_ERR_UNC_MALF_TLP;
1570 data |= PCI_ERR_UNC_INTN;
1571 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1572 }
1573
1574 static bool cxl_compatible_caia_version(struct cxl *adapter)
1575 {
1576 if (cxl_is_power8() && (adapter->caia_major == 1))
1577 return true;
1578
1579 if (cxl_is_power9() && (adapter->caia_major == 2))
1580 return true;
1581
1582 return false;
1583 }
1584
1585 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1586 {
1587 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1588 return -EBUSY;
1589
1590 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1591 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1592 return -EINVAL;
1593 }
1594
1595 if (!cxl_compatible_caia_version(adapter)) {
1596 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1597 adapter->caia_major);
1598 return -ENODEV;
1599 }
1600
1601 if (!adapter->slices) {
1602 /* Once we support dynamic reprogramming we can use the card if
1603 * it supports loadable AFUs */
1604 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1605 return -EINVAL;
1606 }
1607
1608 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1609 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1610 return -EINVAL;
1611 }
1612
1613 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1614 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1615 "available in BAR2: 0x%llx > 0x%llx\n",
1616 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1617 return -EINVAL;
1618 }
1619
1620 return 0;
1621 }
1622
1623 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1624 {
1625 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1626 }
1627
1628 static void cxl_release_adapter(struct device *dev)
1629 {
1630 struct cxl *adapter = to_cxl_adapter(dev);
1631
1632 pr_devel("cxl_release_adapter\n");
1633
1634 cxl_remove_adapter_nr(adapter);
1635
1636 kfree(adapter->native);
1637 kfree(adapter);
1638 }
1639
1640 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1641
1642 static int sanitise_adapter_regs(struct cxl *adapter)
1643 {
1644 int rc = 0;
1645
1646 /* Clear PSL tberror bit by writing 1 to it */
1647 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1648
1649 if (adapter->native->sl_ops->invalidate_all) {
1650 /* do not invalidate ERAT entries when not reloading on PERST */
1651 if (cxl_is_power9() && (adapter->perst_loads_image))
1652 return 0;
1653 rc = adapter->native->sl_ops->invalidate_all(adapter);
1654 }
1655
1656 return rc;
1657 }
1658
1659 /* This should contain *only* operations that can safely be done in
1660 * both creation and recovery.
1661 */
1662 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1663 {
1664 int rc;
1665
1666 adapter->dev.parent = &dev->dev;
1667 adapter->dev.release = cxl_release_adapter;
1668 pci_set_drvdata(dev, adapter);
1669
1670 rc = pci_enable_device(dev);
1671 if (rc) {
1672 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1673 return rc;
1674 }
1675
1676 if ((rc = cxl_read_vsec(adapter, dev)))
1677 return rc;
1678
1679 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1680 return rc;
1681
1682 cxl_fixup_malformed_tlp(adapter, dev);
1683
1684 if ((rc = setup_cxl_bars(dev)))
1685 return rc;
1686
1687 if ((rc = setup_cxl_protocol_area(dev)))
1688 return rc;
1689
1690 if ((rc = cxl_update_image_control(adapter)))
1691 return rc;
1692
1693 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1694 return rc;
1695
1696 if ((rc = sanitise_adapter_regs(adapter)))
1697 goto err;
1698
1699 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1700 goto err;
1701
1702 /* Required for devices using CAPP DMA mode, harmless for others */
1703 pci_set_master(dev);
1704
1705 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1706 goto err;
1707
1708 /* If recovery happened, the last step is to turn on snooping.
1709 * In the non-recovery case this has no effect */
1710 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1711 goto err;
1712
1713 /* Ignore error, adapter init is not dependant on timebase sync */
1714 cxl_setup_psl_timebase(adapter, dev);
1715
1716 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1717 goto err;
1718
1719 return 0;
1720
1721 err:
1722 cxl_unmap_adapter_regs(adapter);
1723 return rc;
1724
1725 }
1726
1727 static void cxl_deconfigure_adapter(struct cxl *adapter)
1728 {
1729 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1730
1731 cxl_native_release_psl_err_irq(adapter);
1732 cxl_unmap_adapter_regs(adapter);
1733
1734 pci_disable_device(pdev);
1735 }
1736
1737 static const struct cxl_service_layer_ops psl9_ops = {
1738 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1739 .invalidate_all = cxl_invalidate_all_psl9,
1740 .afu_regs_init = init_implementation_afu_regs_psl9,
1741 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1742 .register_serr_irq = cxl_native_register_serr_irq,
1743 .release_serr_irq = cxl_native_release_serr_irq,
1744 .handle_interrupt = cxl_irq_psl9,
1745 .fail_irq = cxl_fail_irq_psl,
1746 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1747 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1748 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1749 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1750 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1751 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1752 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1753 .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1754 .debugfs_stop_trace = cxl_stop_trace_psl9,
1755 .write_timebase_ctrl = write_timebase_ctrl_psl9,
1756 .timebase_read = timebase_read_psl9,
1757 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1758 .needs_reset_before_disable = true,
1759 };
1760
1761 static const struct cxl_service_layer_ops psl8_ops = {
1762 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1763 .invalidate_all = cxl_invalidate_all_psl8,
1764 .afu_regs_init = init_implementation_afu_regs_psl8,
1765 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1766 .register_serr_irq = cxl_native_register_serr_irq,
1767 .release_serr_irq = cxl_native_release_serr_irq,
1768 .handle_interrupt = cxl_irq_psl8,
1769 .fail_irq = cxl_fail_irq_psl,
1770 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1771 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1772 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1773 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1774 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1775 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1776 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1777 .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1778 .debugfs_stop_trace = cxl_stop_trace_psl8,
1779 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1780 .timebase_read = timebase_read_psl8,
1781 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1782 .needs_reset_before_disable = true,
1783 };
1784
1785 static const struct cxl_service_layer_ops xsl_ops = {
1786 .adapter_regs_init = init_implementation_adapter_regs_xsl,
1787 .invalidate_all = cxl_invalidate_all_psl8,
1788 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1789 .handle_interrupt = cxl_irq_psl8,
1790 .fail_irq = cxl_fail_irq_psl,
1791 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1792 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1793 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1794 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1795 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
1796 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1797 .timebase_read = timebase_read_xsl,
1798 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1799 };
1800
1801 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1802 {
1803 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1804 /* Mellanox CX-4 */
1805 dev_info(&dev->dev, "Device uses an XSL\n");
1806 adapter->native->sl_ops = &xsl_ops;
1807 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1808 } else {
1809 if (cxl_is_power8()) {
1810 dev_info(&dev->dev, "Device uses a PSL8\n");
1811 adapter->native->sl_ops = &psl8_ops;
1812 } else {
1813 dev_info(&dev->dev, "Device uses a PSL9\n");
1814 adapter->native->sl_ops = &psl9_ops;
1815 }
1816 }
1817 }
1818
1819
1820 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1821 {
1822 struct cxl *adapter;
1823 int rc;
1824
1825 adapter = cxl_alloc_adapter();
1826 if (!adapter)
1827 return ERR_PTR(-ENOMEM);
1828
1829 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1830 if (!adapter->native) {
1831 rc = -ENOMEM;
1832 goto err_release;
1833 }
1834
1835 set_sl_ops(adapter, dev);
1836
1837 /* Set defaults for parameters which need to persist over
1838 * configure/reconfigure
1839 */
1840 adapter->perst_loads_image = true;
1841 adapter->perst_same_image = false;
1842
1843 rc = cxl_configure_adapter(adapter, dev);
1844 if (rc) {
1845 pci_disable_device(dev);
1846 goto err_release;
1847 }
1848
1849 /* Don't care if this one fails: */
1850 cxl_debugfs_adapter_add(adapter);
1851
1852 /*
1853 * After we call this function we must not free the adapter directly,
1854 * even if it returns an error!
1855 */
1856 if ((rc = cxl_register_adapter(adapter)))
1857 goto err_put1;
1858
1859 if ((rc = cxl_sysfs_adapter_add(adapter)))
1860 goto err_put1;
1861
1862 /* Release the context lock as adapter is configured */
1863 cxl_adapter_context_unlock(adapter);
1864
1865 return adapter;
1866
1867 err_put1:
1868 /* This should mirror cxl_remove_adapter, except without the
1869 * sysfs parts
1870 */
1871 cxl_debugfs_adapter_remove(adapter);
1872 cxl_deconfigure_adapter(adapter);
1873 device_unregister(&adapter->dev);
1874 return ERR_PTR(rc);
1875
1876 err_release:
1877 cxl_release_adapter(&adapter->dev);
1878 return ERR_PTR(rc);
1879 }
1880
1881 static void cxl_pci_remove_adapter(struct cxl *adapter)
1882 {
1883 pr_devel("cxl_remove_adapter\n");
1884
1885 cxl_sysfs_adapter_remove(adapter);
1886 cxl_debugfs_adapter_remove(adapter);
1887
1888 /*
1889 * Flush adapter datacache as its about to be removed.
1890 * Not supported on P9 DD1.
1891 */
1892 if ((cxl_is_power8()) ||
1893 ((cxl_is_power9() && !cpu_has_feature(CPU_FTR_POWER9_DD1))))
1894 cxl_data_cache_flush(adapter);
1895
1896 cxl_deconfigure_adapter(adapter);
1897
1898 device_unregister(&adapter->dev);
1899 }
1900
1901 #define CXL_MAX_PCIEX_PARENT 2
1902
1903 static int cxl_slot_is_switched(struct pci_dev *dev)
1904 {
1905 struct device_node *np;
1906 int depth = 0;
1907 const __be32 *prop;
1908
1909 if (!(np = pci_device_to_OF_node(dev))) {
1910 pr_err("cxl: np = NULL\n");
1911 return -ENODEV;
1912 }
1913 of_node_get(np);
1914 while (np) {
1915 np = of_get_next_parent(np);
1916 prop = of_get_property(np, "device_type", NULL);
1917 if (!prop || strcmp((char *)prop, "pciex"))
1918 break;
1919 depth++;
1920 }
1921 of_node_put(np);
1922 return (depth > CXL_MAX_PCIEX_PARENT);
1923 }
1924
1925 bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1926 {
1927 if (!cpu_has_feature(CPU_FTR_HVMODE))
1928 return false;
1929
1930 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1931 /*
1932 * CAPP DMA mode is technically supported on regular P8, but
1933 * will EEH if the card attempts to access memory < 4GB, which
1934 * we cannot realistically avoid. We might be able to work
1935 * around the issue, but until then return unsupported:
1936 */
1937 return false;
1938 }
1939
1940 if (cxl_slot_is_switched(dev))
1941 return false;
1942
1943 /*
1944 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1945 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1946 * served basis, which is racy to check from here. If we need to
1947 * support this in future we might need to consider having this
1948 * function effectively reserve it ahead of time.
1949 *
1950 * Currently, the only user of this API is the Mellanox CX4, which is
1951 * only supported on P8NVL due to the above mentioned limitation of
1952 * CAPP DMA mode and therefore does not need to worry about this. If the
1953 * issue with CAPP DMA mode is later worked around on P8 we might need
1954 * to revisit this.
1955 */
1956
1957 return true;
1958 }
1959 EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
1960
1961
1962 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1963 {
1964 struct cxl *adapter;
1965 int slice;
1966 int rc;
1967
1968 if (cxl_pci_is_vphb_device(dev)) {
1969 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1970 return -ENODEV;
1971 }
1972
1973 if (cxl_slot_is_switched(dev)) {
1974 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1975 return -ENODEV;
1976 }
1977
1978 if (cxl_is_power9() && !radix_enabled()) {
1979 dev_info(&dev->dev, "Only Radix mode supported\n");
1980 return -ENODEV;
1981 }
1982
1983 if (cxl_verbose)
1984 dump_cxl_config_space(dev);
1985
1986 adapter = cxl_pci_init_adapter(dev);
1987 if (IS_ERR(adapter)) {
1988 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1989 return PTR_ERR(adapter);
1990 }
1991
1992 for (slice = 0; slice < adapter->slices; slice++) {
1993 if ((rc = pci_init_afu(adapter, slice, dev))) {
1994 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1995 continue;
1996 }
1997
1998 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1999 if (rc)
2000 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
2001 }
2002
2003 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2004 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2005
2006 return 0;
2007 }
2008
2009 static void cxl_remove(struct pci_dev *dev)
2010 {
2011 struct cxl *adapter = pci_get_drvdata(dev);
2012 struct cxl_afu *afu;
2013 int i;
2014
2015 /*
2016 * Lock to prevent someone grabbing a ref through the adapter list as
2017 * we are removing it
2018 */
2019 for (i = 0; i < adapter->slices; i++) {
2020 afu = adapter->afu[i];
2021 cxl_pci_remove_afu(afu);
2022 }
2023 cxl_pci_remove_adapter(adapter);
2024 }
2025
2026 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2027 pci_channel_state_t state)
2028 {
2029 struct pci_dev *afu_dev;
2030 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2031 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2032
2033 /* There should only be one entry, but go through the list
2034 * anyway
2035 */
2036 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2037 if (!afu_dev->driver)
2038 continue;
2039
2040 afu_dev->error_state = state;
2041
2042 if (afu_dev->driver->err_handler)
2043 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2044 state);
2045 /* Disconnect trumps all, NONE trumps NEED_RESET */
2046 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2047 result = PCI_ERS_RESULT_DISCONNECT;
2048 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2049 (result == PCI_ERS_RESULT_NEED_RESET))
2050 result = PCI_ERS_RESULT_NONE;
2051 }
2052 return result;
2053 }
2054
2055 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2056 pci_channel_state_t state)
2057 {
2058 struct cxl *adapter = pci_get_drvdata(pdev);
2059 struct cxl_afu *afu;
2060 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET, afu_result;
2061 int i;
2062
2063 /* At this point, we could still have an interrupt pending.
2064 * Let's try to get them out of the way before they do
2065 * anything we don't like.
2066 */
2067 schedule();
2068
2069 /* If we're permanently dead, give up. */
2070 if (state == pci_channel_io_perm_failure) {
2071 for (i = 0; i < adapter->slices; i++) {
2072 afu = adapter->afu[i];
2073 /*
2074 * Tell the AFU drivers; but we don't care what they
2075 * say, we're going away.
2076 */
2077 if (afu->phb != NULL)
2078 cxl_vphb_error_detected(afu, state);
2079 }
2080 return PCI_ERS_RESULT_DISCONNECT;
2081 }
2082
2083 /* Are we reflashing?
2084 *
2085 * If we reflash, we could come back as something entirely
2086 * different, including a non-CAPI card. As such, by default
2087 * we don't participate in the process. We'll be unbound and
2088 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2089 * us!)
2090 *
2091 * However, this isn't the entire story: for reliablity
2092 * reasons, we usually want to reflash the FPGA on PERST in
2093 * order to get back to a more reliable known-good state.
2094 *
2095 * This causes us a bit of a problem: if we reflash we can't
2096 * trust that we'll come back the same - we could have a new
2097 * image and been PERSTed in order to load that
2098 * image. However, most of the time we actually *will* come
2099 * back the same - for example a regular EEH event.
2100 *
2101 * Therefore, we allow the user to assert that the image is
2102 * indeed the same and that we should continue on into EEH
2103 * anyway.
2104 */
2105 if (adapter->perst_loads_image && !adapter->perst_same_image) {
2106 /* TODO take the PHB out of CXL mode */
2107 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2108 return PCI_ERS_RESULT_NONE;
2109 }
2110
2111 /*
2112 * At this point, we want to try to recover. We'll always
2113 * need a complete slot reset: we don't trust any other reset.
2114 *
2115 * Now, we go through each AFU:
2116 * - We send the driver, if bound, an error_detected callback.
2117 * We expect it to clean up, but it can also tell us to give
2118 * up and permanently detach the card. To simplify things, if
2119 * any bound AFU driver doesn't support EEH, we give up on EEH.
2120 *
2121 * - We detach all contexts associated with the AFU. This
2122 * does not free them, but puts them into a CLOSED state
2123 * which causes any the associated files to return useful
2124 * errors to userland. It also unmaps, but does not free,
2125 * any IRQs.
2126 *
2127 * - We clean up our side: releasing and unmapping resources we hold
2128 * so we can wire them up again when the hardware comes back up.
2129 *
2130 * Driver authors should note:
2131 *
2132 * - Any contexts you create in your kernel driver (except
2133 * those associated with anonymous file descriptors) are
2134 * your responsibility to free and recreate. Likewise with
2135 * any attached resources.
2136 *
2137 * - We will take responsibility for re-initialising the
2138 * device context (the one set up for you in
2139 * cxl_pci_enable_device_hook and accessed through
2140 * cxl_get_context). If you've attached IRQs or other
2141 * resources to it, they remains yours to free.
2142 *
2143 * You can call the same functions to release resources as you
2144 * normally would: we make sure that these functions continue
2145 * to work when the hardware is down.
2146 *
2147 * Two examples:
2148 *
2149 * 1) If you normally free all your resources at the end of
2150 * each request, or if you use anonymous FDs, your
2151 * error_detected callback can simply set a flag to tell
2152 * your driver not to start any new calls. You can then
2153 * clear the flag in the resume callback.
2154 *
2155 * 2) If you normally allocate your resources on startup:
2156 * * Set a flag in error_detected as above.
2157 * * Let CXL detach your contexts.
2158 * * In slot_reset, free the old resources and allocate new ones.
2159 * * In resume, clear the flag to allow things to start.
2160 */
2161 for (i = 0; i < adapter->slices; i++) {
2162 afu = adapter->afu[i];
2163
2164 afu_result = cxl_vphb_error_detected(afu, state);
2165
2166 cxl_context_detach_all(afu);
2167 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2168 pci_deconfigure_afu(afu);
2169
2170 /* Disconnect trumps all, NONE trumps NEED_RESET */
2171 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2172 result = PCI_ERS_RESULT_DISCONNECT;
2173 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2174 (result == PCI_ERS_RESULT_NEED_RESET))
2175 result = PCI_ERS_RESULT_NONE;
2176 }
2177
2178 /* should take the context lock here */
2179 if (cxl_adapter_context_lock(adapter) != 0)
2180 dev_warn(&adapter->dev,
2181 "Couldn't take context lock with %d active-contexts\n",
2182 atomic_read(&adapter->contexts_num));
2183
2184 cxl_deconfigure_adapter(adapter);
2185
2186 return result;
2187 }
2188
2189 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2190 {
2191 struct cxl *adapter = pci_get_drvdata(pdev);
2192 struct cxl_afu *afu;
2193 struct cxl_context *ctx;
2194 struct pci_dev *afu_dev;
2195 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2196 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2197 int i;
2198
2199 if (cxl_configure_adapter(adapter, pdev))
2200 goto err;
2201
2202 /*
2203 * Unlock context activation for the adapter. Ideally this should be
2204 * done in cxl_pci_resume but cxlflash module tries to activate the
2205 * master context as part of slot_reset callback.
2206 */
2207 cxl_adapter_context_unlock(adapter);
2208
2209 for (i = 0; i < adapter->slices; i++) {
2210 afu = adapter->afu[i];
2211
2212 if (pci_configure_afu(afu, adapter, pdev))
2213 goto err;
2214
2215 if (cxl_afu_select_best_mode(afu))
2216 goto err;
2217
2218 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2219 /* Reset the device context.
2220 * TODO: make this less disruptive
2221 */
2222 ctx = cxl_get_context(afu_dev);
2223
2224 if (ctx && cxl_release_context(ctx))
2225 goto err;
2226
2227 ctx = cxl_dev_context_init(afu_dev);
2228 if (IS_ERR(ctx))
2229 goto err;
2230
2231 afu_dev->dev.archdata.cxl_ctx = ctx;
2232
2233 if (cxl_ops->afu_check_and_enable(afu))
2234 goto err;
2235
2236 afu_dev->error_state = pci_channel_io_normal;
2237
2238 /* If there's a driver attached, allow it to
2239 * chime in on recovery. Drivers should check
2240 * if everything has come back OK, but
2241 * shouldn't start new work until we call
2242 * their resume function.
2243 */
2244 if (!afu_dev->driver)
2245 continue;
2246
2247 if (afu_dev->driver->err_handler &&
2248 afu_dev->driver->err_handler->slot_reset)
2249 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2250
2251 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2252 result = PCI_ERS_RESULT_DISCONNECT;
2253 }
2254 }
2255 return result;
2256
2257 err:
2258 /* All the bits that happen in both error_detected and cxl_remove
2259 * should be idempotent, so we don't need to worry about leaving a mix
2260 * of unconfigured and reconfigured resources.
2261 */
2262 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2263 return PCI_ERS_RESULT_DISCONNECT;
2264 }
2265
2266 static void cxl_pci_resume(struct pci_dev *pdev)
2267 {
2268 struct cxl *adapter = pci_get_drvdata(pdev);
2269 struct cxl_afu *afu;
2270 struct pci_dev *afu_dev;
2271 int i;
2272
2273 /* Everything is back now. Drivers should restart work now.
2274 * This is not the place to be checking if everything came back up
2275 * properly, because there's no return value: do that in slot_reset.
2276 */
2277 for (i = 0; i < adapter->slices; i++) {
2278 afu = adapter->afu[i];
2279
2280 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2281 if (afu_dev->driver && afu_dev->driver->err_handler &&
2282 afu_dev->driver->err_handler->resume)
2283 afu_dev->driver->err_handler->resume(afu_dev);
2284 }
2285 }
2286 }
2287
2288 static const struct pci_error_handlers cxl_err_handler = {
2289 .error_detected = cxl_pci_error_detected,
2290 .slot_reset = cxl_pci_slot_reset,
2291 .resume = cxl_pci_resume,
2292 };
2293
2294 struct pci_driver cxl_pci_driver = {
2295 .name = "cxl-pci",
2296 .id_table = cxl_pci_tbl,
2297 .probe = cxl_probe,
2298 .remove = cxl_remove,
2299 .shutdown = cxl_remove,
2300 .err_handler = &cxl_err_handler,
2301 };
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